LMK1D1208IRHAT [TI]
具有 I²C 的 8 通道输出 1.8V、2.5V 和 3.3V LVDS 缓冲器 | RHA | 40 | -40 to 105;型号: | LMK1D1208IRHAT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 I²C 的 8 通道输出 1.8V、2.5V 和 3.3V LVDS 缓冲器 | RHA | 40 | -40 to 105 |
文件: | 总44页 (文件大小:2172K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMK1D1208I
ZHCSPZ0A –FEBRUARY 2022 –REVISED JUNE 2023
LMK1D1208I I2C 可配置低附加抖动LVDS 缓冲器
1 特性
3 说明
• 具有2 个输入和8 个输出的高性能LVDS 时钟
缓冲器系列
• 输出频率最高可达2GHz
LMK1D1208I 是一款 I2C 可编程 LVDS 时钟缓冲器。
该器件具有两个输入和八对差分 LVDS 时钟输出
(OUT0 到 OUT7),具有超小延迟,可实现时钟分
配。输入可以为 LVDS、LVPECL、LVCMOS、HCSL
或CML。
• 电源电压:1.8V/2.5V/3.3V ± 5%
• 通过I2C 编程实现器件可配置性
– 单独的输入和输出启用/禁用
– 单独的输出振幅选择(标准或增强)
– 组输入多路复用器
LMK1D1208I 专为驱动 50Ω 传输线路而设计。在单端
模式下驱动输入时,对未使用的负输入引脚施加适当的
偏置电压(请参阅图9-6)。
I2C 编程使该器件能够配置为单组缓冲区(两个输入之
一分配到八个输出对)或双组缓冲区(每个输入分配到
四个输出对) 。每个输出都可以配置为具有标准
(350mV) 或增强 (500mV) 摆幅。该器件还通过 I2C 编
程集成了单个输出通道的启用/禁用。LMK1D1208I 具
有失效防护输入,可防止在没有输入信号的情况下输出
发生振荡并允许在提供VDD 之前输入信号。
• 通过IDX 引脚实现四个可编程I2C 地址
• 低附加抖动:156.25MHz 下12kHz 至20MHz 范围
内的
RMS 最大值小于60fs
– 超低相位本底噪声:-164dBc/Hz(典型值)
• 超低传播延迟:< 575ps(最大值)
• 输出偏斜:20ps(最大值)
• 通用输入接受LVDS、LVPECL、LVCMOS、HCSL
和CML
该器件可在 1.8V、2.5V 或 3.3V 电源环境下工作,其
特点是温度范围为–40°C 至105°C(环境温度)。
• 失效防护输入
• LVDS 基准电压,VAC_REF,适用于容性耦合输入
• 工业温度范围:–40°C 至105°C
• 可用封装
封装信息
封装尺寸(标称值)
封装(1)
器件型号
(2)
– 6mm × 6mm 40 引脚VQFN (RHA)
LMK1D1208I
VQFN (40)
6.00mm × 6.00mm
2 应用
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸(长× 宽)为标称值,并包括引脚(如适用)。
• 电信及网络
• 医疗成像
• 测试和测量设备
• 无线通信
• 专业音频/视频
ADC CLOCK
100
200 MHz
156.25 MHz
Oscillator
LMK1D1208I
LVDS Buffer
SDA
SCL
IDX1
IDX0
FPGA CLOCK
100
应用示例
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS828
LMK1D1208I
ZHCSPZ0A –FEBRUARY 2022 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
9.5 Programming............................................................ 20
9.6 Register Maps...........................................................21
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Application.................................................. 25
10.3 Power Supply Recommendations...........................28
10.4 Layout..................................................................... 29
11 Device and Documentation Support..........................31
11.1 Documentation Support.......................................... 31
11.2 接收文档更新通知................................................... 31
11.3 支持资源..................................................................31
11.4 Trademarks............................................................. 31
11.5 静电放电警告...........................................................31
11.6 术语表..................................................................... 31
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................7
7.5 Electrical Characteristics.............................................7
7.6 Typical Characteristics.............................................. 11
8 Parameter Measurement Information..........................12
9 Detailed Description......................................................14
9.1 Overview...................................................................14
9.2 Functional Block Diagram.........................................14
9.3 Feature Description...................................................15
9.4 Device Functional Modes..........................................18
Information.................................................................... 31
12.1 Package Option Addendum....................................32
12.2 Tape and Reel Information......................................34
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2022) to Revision A (June 2023)
Page
• 将表标题从“器件信息”更改为“封装信息”....................................................................................................1
• Added the Device Comparison table for the LMK1Dxxxx buffer device family...................................................3
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation
section.............................................................................................................................................................. 28
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNAS828
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5 Device Comparison
DEVICE
OUTPUT
SWING
DEVICE
TYPE
FEATURES
PACKAGE
BODY SIZE
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
350 mV
500 mV
Global output enable and swing
control through pin control
LMK1D2108
LMK1D2106
LMK1D2104
LMK1D2102
LMK1D1216
LMK1D1212
LMK1D1208P
LMK1D1208I
Dual 1:8
Dual 1:6
Dual 1:4
Dual 1:2
2:16
VQFN (48)
7.00 mm × 7.00 mm
Global output enable and swing
control through pin control
VQFN (40)
VQFN (28)
VQFN (16)
VQFN (48)
VQFN (40)
VQGN (40)
VQFN (40)
6.00 mm × 6.00 mm
5.00 mm × 5.00 mm
3.00 mm × 3.00 mm
7.00 mm × 7.00 mm
6.00 mm × 6.00 mm
6.00 mm × 6.00 mm
6.00 mm × 6.00 mm
Global output enable and swing
control through pin control
Global output enable and swing
control through pin control
Global output enable control
through pin control
Global output enable control
through pin control
2:12
Individual output enable control
through pin control
2:8
Individual output enable control
through I2C
2:8
Global output enable control
through pin control
LMK1D1208
LMK1D1204P
LMK1D1204
2:8
2:4
2:4
350 mV
350 mV
350 mV
VQFN (28)
VQGN (28)
VQFN (16)
5.00 mm × 5.00 mm
5.00 mm × 5.00 mm
3.00 mm × 3.00 mm
Individual output enable control
through pin control
Global output enable control
through pin control
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English Data Sheet: SNAS828
LMK1D1208I
ZHCSPZ0A –FEBRUARY 2022 –REVISED JUNE 2023
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6 Pin Configuration and Functions
30
29
28
27
26
25
24
23
22
21
VDD
NC
OUT4_P
OUT4_N
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
OUT0_N
OUT0_P
NC
OUT5_P
OUT5_N
NC
6mm x 6mm
40 pin QFN
IDX1
IDX0
NC
OUT6_P
OUT6_N
VDD
VAC_REF0
IN0_N
IN0_P
VDD
Thermal Pad
1
2
3
4
5
6
7
8
9
10
图6-1. LMK1D1208I: RHA Package 40-Pin VQFN (Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
LMK1D1208I
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N
IN1_P, IN1_N
I2C PROGRAMMING
SDA
12, 13
8, 9
I
I
Primary: Differential input pair or single-ended input
Secondary: Differential input pair or single-ended input.
5
6
I/O
I
I2C data
I2C clock
SCL
I2C address bit[0]. This is a 2-level input that is decoded in
conjunction with pin 15 to set the I2C address. It has internal
670-kΩpullup.
IDX0
IDX1
15
16
I,S,PU
I,S, PU
I2C address bit[1]. This is a 2-level input that is decoded in
conjunction with pin 16 to set the I2C address. It has internal
670-kΩpullup.
BIAS VOLTAGE OUTPUT
Bias voltage output for capacitive coupled inputs. If used, TI
recommends using a 0.1-µF capacitor to GND on this pin.
VAC_REF0, VAC_REF1
14, 10
O
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N
OUT1_P, OUT1_N
OUT2_P, OUT2_N
OUT3_P, OUT3_N
OUT4_P, OUT4_N
OUT5_P, OUT5_N
OUT6_P, OUT6_N
OUT7_P, OUT7_N
18, 19
22, 23
24, 25
28, 29
32, 33
34, 35
38, 39
2, 3
O
O
O
O
O
O
O
O
Differential LVDS output pair number 0
Differential LVDS output pair number 1
Differential LVDS output pair number 2
Differential LVDS output pair number 3
Differential LVDS output pair number 4
Differential LVDS output pair number 5
Differential LVDS output pair number 6
Differential LVDS output pair number 7
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English Data Sheet: SNAS828
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表6-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
LMK1D1208I
SUPPLY VOLTAGE
VDD
11, 20, 40
P
Device power supply (1.8 V, 2.5 V, or 3.3 V)
GROUND
Die Attach Pad. Connect to the printed circuit board (PCB)
ground plane for heat dissipation.
DAP
NO CONNECT
NC
DAP
G
1, 4, 7, 17, 21, 26,
27, 30, 31, 36, 37
No connection. Leave floating.
—
(1) The definitions below define the I/O type for each pin.
•
•
•
•
•
•
•
I = Input
O = Output
I / O = Input / Output
PU = Internal 670-kΩPullup
S = Hardware Configuration Pin
P = Power Supply
G = Ground
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English Data Sheet: SNAS828
LMK1D1208I
ZHCSPZ0A –FEBRUARY 2022 –REVISED JUNE 2023
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–20
–50
MAX
3.6
UNIT
V
VDD
VIN
VO
IIN
Supply voltage
Input voltage
3.6
V
Output voltage
VDD + 0.3
20
V
Input current
mA
mA
°C
°C
IO
Continuous output current
Junction temperature
Storage temperature (2)
50
TJ
135
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Device unpowered
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
2.375
1.71
NOM
3.3
MAX
3.465
2.625
1.89
UNIT
3.3-V supply
VDD
Core supply voltage
Supply voltage ramp
2.5-V supply
2.5
V
1.8-V supply
1.8
Supply
Ramp
Requires monotonic ramp (10-90% of
0.1
20
ms
VDD
)
TA
TJ
Operating free-air temperature
Operating junction temperature
105
135
°C
°C
–40
–40
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English Data Sheet: SNAS828
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7.4 Thermal Information
LMK1D1208I
THERMAL METRIC(1)
VQFN
40 PINS
39.1
32.4
20.2
1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
20.2
8.3
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY CHARACTERISTICS
All-outputs enabled and
unterminated, f = 0 Hz (AMP_SEL
=1)
IDDSTAT
LMK1D1208I
55
75
mA
All-outputs enabled, RL = 100 Ω, f
=100 MHz (AMP_SEL = 0,
default)
IDD100M
IDD100M
LMK1D1208I
LMK1D1208I
95
mA
mA
All-outputs enabled, RL = 100 Ω,
f =100 MHz, AMP_SEL = 1
110
IDX INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
Minimum input voltage for a
logical "1" state
VIH
VIL
IIH
Input high voltage
Input low voltage
Input high current
0.7 × VCC
VCC + 0.3
0.3 × VCC
30
V
V
Maximum input voltage for a
logical "0" state
–0.3
VDD can be 1.8V/2.5V/3.3V with
VIH = VDD
µA
VDD can be 1.8V/2.5V/3.3V with
VIH = VDD
IIL
Input low current
µA
–30
Rpull-up(IDX)
Input pullup resistor
670
kΩ
I2C INTERFACE CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VIH
VIL
Input high voltage
Input low voltage
Input high current
Input low current
Input capacitance
Output low voltage
0.7 × VCC
VCC + 0.3
0.3 × VCC
30
V
V
–0.3
IIH
µA
µA
pF
V
IIL
–30
CIN_SE
VOL
at 25°C
2
IOL = 3 mA
0.3
100
Standard
fSCL
I2C clock rate
Fast mode
400
kHz
Ultra Fast mode
SCL high before SDA low
SCL low after SDA low
1000
tSU(START)
tH(START)
tW(SCLH)
START condition setup time
START condition hold time
SCL pulse width high
0.6
0.6
0.6
1.3
us
us
us
us
tW(SCLL)
SCL pulse width low
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VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
100
0
TYP
MAX
UNIT
ns
tSU(SDA)
tH(SDA)
tR(IN)
SDA setup time
SDA hold time
SDA valid after SCL low
0.9
300
300
300
us
SDA/SCL input rise time
SDA/SCL input fall time
SDA output fall time
ns
tF(IN)
ns
tF(OUT)
tSU(STOP)
tBUS
CBUS <= 400 pF
ns
STOP condition setup time
Bus free time between STOP and START
0.6
1.3
us
us
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
DC
0.4
250
MHz
V
Assumes a square wave input
with two levels
VIN_S-E
Single-ended Input Voltage Swing
3.465
Input Slew Rate (20% to 80% of the
amplitude)
dVIN/dt
0.05
V/ns
IIH
Input high current
Input low current
Input capacitance
VDD = 3.465 V, VIH = 3.465 V
VDD = 3.465 V, VIL = 0 V
at 25°C
50
µA
µA
pF
IIL
–30
CIN_SE
3.5
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
2
2.4
2.4
GHz
VPP
VICM = 1 V (VDD = 1.8 V)
VICM = 1.25 V (VDD = 2.5 V/3.3 V)
0.3
0.3
Differential input voltage peak-to-peak
{2*(VINP-VINN)}
VIN,DIFF(p-p)
VIN,DIFF(P-P) > 0.4 V (VDD = 1.8
V/2.5/3.3 V)
VICM
IIH
Input common mode voltage
Input high current
0.25
2.3
30
V
VDD = 3.465 V, VINP = 2.4 V, VINN
= 1.2 V
µA
VDD = 3.465 V, VINP = 0 V, VINN
1.2 V
=
IIL
Input low current
µA
pF
–30
CIN_S-E
Input capacitance (Single-ended)
at 25°C
3.5
LVDS DC OUTPUT CHARACTERISTICS
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 0
Differential output voltage magnitude |
VOUTP - VOUTN
|VOD|
|VOD|
250
400
350
500
450
650
mV
mV
|
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
Differential output voltage magnitude |
VOUTP - VOUTN
|
Change in differential output voltage
magnitude. Per output, defined as the
difference between VOD in logic hi/lo
states.
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 0
15
mV
mV
ΔVOD
ΔVOD
–15
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
Change in differential output voltage
magnitude
20
1.2
–20
1
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 1.8 V)
Steady-state common mode output
voltage
VOC(SS)
V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 2.5 V/3.3 V)
1.1
0.8
1.375
1
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 1.8 V), AMP_SEL = 1
Steady-state common mode output
voltage
VOC(SS)
V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω(VDD = 2.5 V/3.3 V), AMP_SEL
= 1
0.9
1.1
15
Change in steady-state common mode
output voltage. Per output, defined as the
difference in VOC in logic hi/lo states.
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 0
mV
ΔVOC(SS)
–15
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VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
Change in steady-state common mode
output voltage
20
mV
ΔVOC(SS)
–20
LVDS AC OUTPUT CHARACTERISTICS
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, fOUT = 491.52 MHz
Vring
VOS
Output overshoot and undershoot
Output AC common mode
0.1
VOD
–0.1
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 0
50
75
100
mVpp
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, AMP_SEL = 1
VOS
Output AC common mode
150
12
mVpp
mA
IOS
Short-circuit output current (differential)
VOUTP = VOUTN
–12
–24
Short-circuit output current (common-
mode)
IOS(cm)
VOUTP = VOUTN = 0
24
mA
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
tPD
Propagation delay
Output skew
0.3
0.575
20
ns
ps
Ω(2)
Skew between outputs with the
same load conditions (4 and 8
channel) (3)
tSK, O
Skew between outputs on
different parts subjected to the
same operating conditions with
the same input and output
loading.
tSK, PP
Part-to-part skew
250
20
ps
ps
50% duty cycle input, crossing
tSK, P
Pulse skew
point-to-crossing-point distortion
–20
(4)
fIN = 156.25 MHz with 50% duty-
cycle, Input slew rate = 1.5V/ns,
Integration range = 12 kHz –20
tRJIT(ADD)
Random additive Jitter (rms)
50
60 fs, RMS
MHz, with output load RLOAD
=
100 Ω
PN1kHz
PN10kHz
PN100kHz
PN1MHz
PNfloor
–143
–152
–157
–160
–164
Phase Noise for a carrier frequency of
156.25 MHz with 50% duty-cycle, Input
slew rate = 1.5V/ns with output load
RLOAD = 100 Ω
Phase noise
dBc/Hz
fIN = 156.25 MHz. The difference
in power level at fIN when the
selected clock is active and the
unselected clock is static versus
when the selected clock is inactive
and the unselected clock is active.
MUXISO
Mux Isolation
80
dB
ODC
tR/tF
Output duty cycle
With 50% duty cycle input
45
55
%
Output rise and fall time
300
ps
20% to 80% with RLOAD = 100 Ω
20% to 80% with RLOAD = 100 Ω
(AMP_SEL= 1)
tR/tF
Output rise and fall time
300
1
ps
us
Time taken for outputs to go from
disable state to enable state and
vice versa. (5) (6)
ten/disable
Output Enable and Disable Time
Outputs are held in high Z mode
with OUTP = OUTN (max applied
external voltage is the lesser of
VDD or 1.89V and minimum
applied external voltage is 0V
IleakZ
Output leakage current in High Z
50
uA
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VDD = 1.8 V ± 5 %, –40°C ≤TA ≤105°C. Typical values are at VDD = 1.8 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.375
UNIT
VAC_REF
Reference output voltage
VDD = 2.5 V, ILOAD = 100 µA
0.9
1.25
V
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V
10 kHz, 100 mVpp ripple injected
–70
–50
on VDD
Power Supply Noise Rejection (fcarrier
156.25 MHz)
=
PSNR
dBc
1 MHz, 100 mVpp ripple injected
on VDD
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
(3) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(4) Applies to the dual bank family.
(5) Time starts after the acknowledge bit
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7.6 Typical Characteristics
图 7-1 captures the variation of the LMK1D1208I current consumption with input frequency and supply voltage.
图7-2 shows the variation of the differential output voltage (VOD) swept across frequency.
It is important to note that 图 7-1 and 图 7-2 serve as a guidance to the users on what to expect for the range of
operating frequency supported by LMK1D1208I. These graphs were plotted for a limited number of frequencies
and load conditions which may not represent the customer system.
90
85
80
75
70
65
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V,TA = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V,TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V,TA =105
60
55
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
图7-1. LMK1D1208I Current Consumption vs. Frequency
380
370
360
350
340
330
320
310
300
290
280
270
260
250
240
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V, Ta = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V, TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V, TA = 105
100
200
300
400
500
600 700 800 9001000
2000
Frequency (MHz)
图7-2. LMK1D1208I VOD vs. Frequency
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8 Parameter Measurement Information
Oscilloscope
100 W
LVDS
图8-1. LVDS Output DC Configuration During Device Test
Phase Noise/
Spectrum Analyzer
Balun
LMK1D1208I
图8-2. LVDS Output AC Configuration During Device Test
V
IH
V
th
IN
V
IL
IN
V
th
图8-3. DC-Coupled LVCMOS Input During Device Test
V
OUTNx
OUTPx
OH
V
OD
V
OL
80%
V
(= 2 x V
)
20%
0 V
OUT,DIFF,PP
OD
t
r
t
f
图8-4. Output Voltage and Rise/Fall Time
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INNx
INPx
t
t
t
PLH0
PHL0
PHL1
OUTN0
OUTP0
t
PLH1
OUTN1
OUTP1
t
t
PLH2
PHL2
OUTN2
OUTP2
t
t
PLH7
PHL7
OUTN7
OUTP7
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
图8-5. Output Skew and Part-to-Part Skew
V
ring
OUTNx
V
OD
0 V Differential
OUTPx
图8-6. Output Overshoot and Undershoot
V
OS
GND
图8-7. Output AC Common Mode
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9 Detailed Description
9.1 Overview
The LMK1D1208I is a low-additive jitter, I2C-programmable, LVDS output clock buffer that uses CMOS
transistors to control the output current. Therefore, proper biasing and termination are required to ensure correct
operation of the device and to maximize signal integrity. The LMK1D1208I also includes status and control
registers for configuring the different modes in the device.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI
recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage
different than the output common-mode voltage of the LMK1D1208I, AC coupling must be used.If the LVDS
receiver has internal 100-Ωtermination, external termination must be omitted.
9.2 Functional Block Diagram
VDD
VDD
Rpull-up
IDX0, IDX1
2
SDA
SCL
OUTx_AMP_SEL
Output Swing
Control
I2C Logic
OUT[0:N/2-1]
OUT[N/2:N-1]
IN0
IN1
Bank Control
Reference
Voltage
VAC_REF
GND
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9.3 Feature Description
The LMK1D1208I is an I2C-programmable, low-additive jitter, LVDS fan-out buffer that can generate up to eight
copies of two selectable LVPECL, LVDS, HCSL, CML, or LVCMOS inputs. This feature-rich device allows the
user to have flexibility on the configuration based on their application use-case.
9.3.1 Fail-Safe Input
The LMK1D120x family of devices is designed to support fail-safe input operation. This feature allows the user to
drive the device inputs before VDD is applied without damaging the device. Refer to Specifications for more
information on the maximum input supported by the device. The device also incorporates an input hysteresis,
which prevents random oscillation in absence of an input signal, allowing the input pins to be left open.
9.3.2 Input Stage Configurability
The LMK1D1208I has an input stage that accepts up to two clock inputs and can be configured as either a 2:1
mux or as a dual bank. When configured as a 2:1 mux, the LMK1D1208I device can select one of the two clock
inputs and then distribute it to the eight LVDS output pairs. In the dual bank mode, the LMK1D1208I can assign
each clock input to fan out four LVDS output pairs per bank. Refer to the Device Functional Modes for how to
configure the two input stages.
Unused inputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be
used with the LMK1D1208I to provide greater system flexibility.
9.3.3 Dual Output Bank
LMK1D1208I has eight LVDS output pairs which are grouped into two banks, each with four LVDS output pairs.
The 表9-1 outlines this mapping.
表9-1. Output Bank Map
BANK
CLOCK OUTPUTS
0
1
OUT0, OUT1, OUT2, OUT3
OUT4, OUT5, OUT6, OUT7
9.3.4 I2C
The I2C control is used to configure the different features in the LMK1D1208I. These features include individual
input and output channel enable or disable, input mux select in each bank, bank muting (setting bank outputs to
logic low), and individual output amplitude control. The I2C logic is also capable of fast mode where the
frequency is 400 kHz.
9.3.4.1 I2C Address Assignment
The I2C address is assigned by the two pins, IDX0 and IDX1. Each IDX pin supports two levels allowing the
LMK1D1208I to assume four different I2C addresses. See 表9-2 for address pin assignment.
表9-2. I2C Address Assignment
I2C ADDRESS
IDX1
IDX0
0x68
L
L
L
H
L
0x69
0x6A
H
H
0x6B
H
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9.3.5 LVDS Output Termination
TI recommends that unused outputs are terminated differentially with a 100-Ωresistor for optimum performance.
Unterminated outputs are also okay, but this will result in a slight degradation in performance (Output AC
common-mode VOS) in the outputs being used.
图 9-1 and 图 9-2 show how the LMK1D1208I can be connected to LVDS receiver inputs with DC and AC
coupling, respectively.
100 W
LVDS
LMK1D12XX
Z = 50 W
图9-1. Output DC Termination
100 nF
100 W
LVDS
LMK1D12XX
Z = 50 W
100 nF
图9-2. Output AC Termination (With the Receiver Internally Biased)
9.3.6 Input Termination
The LMK1D1208I inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers.
图 9-3 and 图 9-4 show how LVDS drivers can be connected to LMK1D1208I inputs with DC coupling and AC
coupling, respectively.
100 W
LVDS
LMK1D12XX
Z = 50 W
图9-3. LVDS Clock Driver Connected to LMK1D1208I Input (DC-Coupled)
100 nF
LVDS
LMK1D12XX
Z = 50 W
100 nF
50 W
50 W
V
AC_REF
图9-4. LVDS Clock Driver Connected to LMK1D1208I Input (AC-Coupled)
图9-5 shows how to connect LVPECL inputs to the LMK1D1208I. The series resistors are required to reduce the
LVPECL signal swing if the signal swing is >1.6 VPP
.
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75 W
100 nF
LMK1D12XX
LVPECL
Z = 50 W
100 nF
50 W
75 W
150 W
150 W
50 W
V
AC_REF
图9-5. LVPECL Clock Driver Connected to LMK1D1208I Input
图9-6 shows how to couple a LVCMOS clock input to the LMK1D1208I directly.
R
S
LVCMOS
(1.8/2.5/3.3 V)
LMK1D12XX
VIH + VIL
Vth =
图9-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1208I Input
For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩresistors.
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9.4 Device Functional Modes
The outputs of Bank 0 and Bank 1 can be one of three options: logic low, buffered IN0, or buffered IN1. These
output types should only be attained by maintaining the register setting combination outlined in 表 9-3. The
LMK1D1208I registers must be programmed within these possible logic states to ensure proper device
functionality. Using the device outside the intended logic can result in degraded performance.
表9-3. Register Control Logic Table
BANKx OUTPUTS BANKx_IN_SEL
BANKx_MUTE
IN0_EN
IN1_EN
Logic low
IN0
X
1
0
1
0
0
X
1
X
X
1
IN1
X
9.4.1 Input Enable Control
The LMK1D1208I allows for individual input channel enable or disable through the INx_EN register field. The
inputs should be disabled when not in use to reduce the power consumption.
表 9-4 describes the control of this function. INx_EN is set by register 0x02 (R2). See R2 Register for more
information on this register.
表9-4. Input Control
INx_EN
ACTIVE CLOCK INPUT
0
INx_P, INx_N disabled
1
INx_P, INx_N enabled
9.4.2 Bank Input Selection
Bank 0 and Bank 1 can choose between the two inputs to fanout four LVDS output pairs each. In the 2:1 input
mux mode, each bank must select the same clock input to output eight identical clocks. With the dual bank
mode, each bank can select a different clock input to distribute both inputs separately; this is analogous to
having two 1:4 buffers. When operating in dual bank mode, TI recommends that Bank 0 not select IN1 and Bank
1 not select IN0 to avoid crosstalk and degraded performance.
The BANKx_IN_SEL register field configures this function described in 表 9-5. BANKx_IN_SEL is set by register
0x02 (R2). See R2 Register for more information on this register.
表9-5. Bank Input Selection
BANKx_IN_SEL
BANK CLOCK INPUT
BANKx selects IN1_P, IN1_N
BANKx selects IN0_P, IN0_N
0
1
9.4.3 Bank Mute Control
Each bank, Bank 0 or Bank 1, can be individually muted such that the bank outputs are set to logic low (OUTx_P
is low and OUTx_N is high).
表 9-6 describes the control of this function. The BANKx_MUTE register field is set by register 0x02 (R2). See
R2 Register for more information on this register.
表9-6. Bank Mute Control
BANKx_MUTE
BANK CLOCK OUTPUTS
0
BANKx outputs selected INx
1
BANKx outputs logic low
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9.4.4 Output Enable Control
The outputs of the LMK1D1208I can be individually enabled or disabled through the OUTx_EN register field. The
disabled state of the outputs is high impedance as this reduces the power consumption and also prevents back-
biasing of the devices connected to these outputs. Unused outputs should be disabled to eliminate the need for
a termination resistor. In the case of enabled unused outputs, TI recommends a 100-Ω termination for optimal
performance.
表 9-7 describes the control of this function. OUTx_EN is set by register 0x00 (R0). See R0 Register for more
information on this register.
表9-7. Output Control
OUTx_EN
CLOCK OUTPUTS
OUTx_P, OUTx_N disabled in
Hi-Z state
0
1
OUTx_P, OUTx_N enabled
9.4.5 Output Amplitude Selection
The amplitude of the LMK1D1208I outputs can be individually programmed through the OUTx_AMP_SEL
register field. The boosted LVDS swing mode can be used in applications which require a higher output swing for
better noise performance (higher slew rate) or for swing requirements in the receiver that the standard LVDS
swing cannot meet.
表 9-8 describes the control of this function. OUTx_AMP_SEL is set by register 0x01 (R1). See R1 Register for
more information on this register.
表9-8. Output Amplitude Selection Table
OUTx_AMP_SEL
OUTPUT AMPLITUDE (VOD)
Standard LVDS swing (350 mV)
Boosted LVDS swing (500 mV)
0
1
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9.5 Programming
The LMK1D1208I uses I2C to program the states of its eight output drivers. See I2C for more information on the
I2C features and address assignment, and Register Maps for the list of programmable registers.
表9-9. Command Code Definition
BIT
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
7
(6:0) Register address for Byte operations, or starting register address for Block, operations
1
7
1
1
8
1
1
S
Peripheral Address
A
Data Byte
A
P
R/W
MSB
LSB
MSB
LSB
S
Start Condition
Sr Repeated Start Condition
1 = Read (Rd); 0 = Write (Wr)
R/W
A
Acknowledge (ACK = 0 and NACK =1)
Stop Condition
P
Controller-to-Peripheral Transmission
Peripheral-to-Controller Transmission
图9-7. Generic Programming Sequence
1
7
1
1
8
1
8
1
1
S
Peripheral Address
Wr
A
CommandCode
A
Data Byte
A
P
图9-8. Byte Write Protocol
1
1
1
7
1
1
8
7
1
1
A
S
S
Peripheral Address
Wr
A
CommandCode
Peripheral Address
Rd
A
1
1
8
Data Byte
A
P
1
图9-9. Byte Read Protocol
1
7
1
1
8
1
8
1
S
Peripheral Address
Wr
A
CommandCode
A
Byte Count = N
A
8
1
8
1
8
1
1
Data Byte 0
A
Data Byte 1
A
…
Data Byte N-1
A
P
图9-10. Block Write Protocol
1
1
1
7
1
1
8
7
1
1
A
S
S
Peripheral Address
Wr
A
CommandCode
Peripheral Address
Rd
A
1
1
8
1
1
8
8
Data Byte N-1
A
P
Data Byte N
A
A
Data Byte 0
1
1
1
图9-11. Block Read Protocol
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9.6 Register Maps
9.6.1 LMK1D1208I Registers
表 9-10 lists the LMK1D1208I registers. All register locations not listed should be considered as reserved
locations and the register contents should not be modified.
TI highly suggests that the user only operates within the logic states listed in 表9-3 for optimum performance.
表9-10. LMK1D1208I Registers
Address
Acronym
R0
Register Fields
Section
Go
0h
1h
2h
5h
Eh
Output Enable Control
R1
Output Amplitude Control
Input Enable and Bank Setting Control
Device/Revision Identification
I2C Address Readback
Go
R2
Go
R5
Go
R14
Go
Complex bit access types are encoded to fit into small table cells. 表 9-11 shows the codes that are used for
access types in this section.
表9-11. LMK1D1208I Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Reset/default value in
hexadecimal
9.6.1.1 R0 Register (Address = 0h) [reset = 0h]
R0 is shown in 表9-12.
The R0 register contains bits that enable or disable individual output clock channels [7:0].
Return to the Summary Table.
表9-12. R0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OUT7_EN
R/W
0h
This bit controls the output enable signal for output channel
OUT7_P/OUT7_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
6
5
OUT6_EN
OUT5_EN
R/W
R/W
0h
0h
This bit controls the output enable signal for output channel
OUT6_P/OUT6_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
This bit controls the output enable signal for output channel
OUT5_P/OUT5_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
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表9-12. R0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
OUT4_EN
R/W
0h
This bit controls the output enable signal for output channel
OUT4_P/OUT4_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
3
2
1
0
OUT3_EN
OUT2_EN
OUT1_EN
OUT0_EN
R/W
R/W
R/W
R/W
0h
0h
0h
0h
This bit controls the output enable signal for output channel
OUT3_P/OUT3_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
This bit controls the output enable signal for output channel
OUT2_P/OUT2_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
This bit controls the output enable signal for output channel
OUT1_P/OUT1_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
This bit controls the output enable signal for output channel
OUT0_P/OUT0_N.
0h = Output Disabled (Hi-Z)
1h = Output Enabled
9.6.1.2 R1 Register (Address = 1h) [reset = 0h]
R1 is shown in 表9-13.
The R1 register contains bits that set the output amplitude to a standard or boosted LVDS swing.
Return to the Summary Table.
表9-13. R1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OUT7_AMP_SEL
R/W
0h
This bit sets the output amplitude for output channel OUT7_P/
OUT7_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
6
5
4
3
OUT6_AMP_SEL
OUT5_AMP_SEL
OUT4_AMP_SEL
OUT3_AMP_SEL
R/W
R/W
R/W
R/W
0h
0h
0h
0h
This bit sets the output amplitude for output channel OUT6_P/
OUT6_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
This bit sets the output amplitude for output channel OUT5_P/
OUT5_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
This bit sets the output amplitude for output channel OUT4_P/
OUT4_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
This bit sets the output amplitude for output channel OUT3_P/
OUT3_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
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表9-13. R1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
OUT2_AMP_SEL
OUT1_AMP_SEL
OUT0_AMP_SEL
R/W
0h
This bit sets the output amplitude for output channel OUT2_P/
OUT2_N.
0h = Standard LVDS swing (350 mV)
1h = Boosted LVDS swing (500 mV)
1
0
R/W
R/W
0h
0h
This bit sets the output amplitude for output channel OUT1_P/
OUT1_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
This bit sets the output amplitude for output channel OUT0_P/
OUT0_N.
0h = Standard LVDS Swing (350 mV)
1h = Boosted LVDS Swing (500 mV)
9.6.1.3 R2 Register (Address = 2h) [reset = F1h]
R2 is shown in 表9-14.
The R2 register contains bits that enable/disable the input channels and control the banks.
Return to the Summary Table.
表9-14. R2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R/W
1h
Register bit can be written to 1.
Writing a different value than 1 will affect device functionality.
6
5
Reserved
R/W
R/W
1h
1h
Register bit can be written to 1.
Writing a different value than 1 will affect device functionality.
BANK1_IN_SEL
This bit sets the input channel for Bank 1.
0h = IN1_P/IN1_N
1h = IN0_P/IN0_N
4
3
2
1
BANK0_IN_SEL
BANK1_MUTE
BANK0_MUTE
IN1_EN
R/W
R/W
R/W
R/W
1h
0h
0h
0h
This bit sets the input channel for Bank 0.
0h = IN1_P/IN1_N
1h = IN0_P/IN0_N
This bit sets the outputs in Bank 1 to logic low level.
0h = INx_P/INx_N
1h = Logic low
This bit sets the outputs in Bank 0 to logic low level.
0h = INx_P/INx_N
1h = Logic low
This bit controls the input enable signal for input channel IN1_P/
IN1_N.
0h = Input Disabled (reduces power consumption)
1h = Input Enabled
0
IN0_EN
R/W
1h
This bit controls the input enable signal for input channel IN0_P/
IN0_N.
0h = Input Disabled (reduces power consumption)
1h = Input Enabled
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9.6.1.4 R5 Register (Address = 5h) [reset = 20h]
R5 is shown in 表9-15.
The R5 register contains the silicon revision code and the device identification code.
Return to the Summary Table.
表9-15. R5 Register Field Descriptions
Bit
7:4
3:0
Field
Type
Reset
Description
REV_ID
DEV_ID
R
2h
These bits provide the silicon revision code.
These bits provide the device identification code.
R
0h
9.6.1.5 R14 Register (Address = Eh) [reset = 0h]
R14 is shown in 表9-16.
The R14 register contains the bits that report the current state of the I2C address based on the IDX0 and IDX1
input pins.
Return to the Summary Table.
表9-16. R14 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
IDX_RB
R
0h
These bits report the I2C address state.
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The LMK1D1208I is a low-additive jitter universal to LVDS fan-out buffer with two selectable inputs. The small
package, low output skew, and low additive jitter make for a flexible device in demanding applications.
10.2 Typical Application
1.8V/ 2.5V/ 3.3V
FPGA
IN0_P
156.25 MHz LVDS
100
from Backplane
IN0_N
50
50
CPU
100
156.25 MHz LVCMOS
Oscillator
IN1_P
IN1_N
PHY
100
2.5V
1 k
1 k
ASIC
100
SDA
SCL
IDX1
IDX0
图10-1. Fan-Out Buffer for Line Card Application
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10.2.1 Design Requirements
The LMK1D1208I shown in 图 10-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the
backplane at IN0, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator at IN1. The LVDS clock is AC-coupled
and biased using the integrated reference voltage generator. A resistor divider is used to set the threshold
voltage correctly for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both VAC_REF and IN1_N.
Either input signal can be then fanned out to desired devices via register control. The configuration example is
driving four LVDS receivers in a line card application with the following properties:
• The PHY device is capable of DC coupling with an LVDS driver such as the LMK1D1208I. This PHY device
features internal termination so no additional components are required for proper operation
• The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as
the LMK1D1208I. Again, no additional components are required.
• The FPGA requires external AC coupling, but has internal termination. 0.1-µF capacitors are placed to
provide AC coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling
capacitors.
• The unused outputs of the LMK1D1208I can be disabled by clearing the corresponding OUTx_EN register
through I2C. This results in a lower power consumption.
10.2.2 Detailed Design Procedure
See Input Termination for proper input terminations, dependent on single-ended or differential inputs.
See LVDS Output Termination for output termination schemes depending on the receiver application.
Unused outputs should be terminated differentially with a 100-Ω resistor or disabled through OUTx_EN register
control (see 表 9-7) for optimum performance. Outputs may be left unterminated, but will result in slight
degradation in performance (Output AC common-mode VOS ) in the outputs being used.
In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power-supply filtering and
bypassing is critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043).
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10.2.3 Application Curves
The following graphs show the low additive noise of the LMK1D1208I. The low noise 156.25-MHz source with
24-fs RMS jitter shown in 图10-2 drives the LMK1D1208I, resulting in 46.4-fs RMS when integrated from 12 kHz
to 20 MHz (图10-3). The resultant additive jitter is a low 39.7-fs RMS for this configuration.
Reference signal is low-noise Rohde and Schwarz SMA100B
图10-2. LMK1D1208I Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz)
图10-3. LMK1D1208I Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz)
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图 10-4 shows the low close-in phase noise of the LMK1D1208I device. The LMK1D1208I has excellent flicker
noise as a result of superior process technology and design. This enables their use for clock distribution in radar
systems, medical imaging systems etc which require ultra-low close-in phase noise clocks.
图10-4. LMK1D1208I Output Phase Noise, 100 MHz, 1-kHz Offset: –147 dBc/Hz
10.3 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must
be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends
adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.
TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip
power supply that isolates the high-frequency switching noises generated by the clock driver. These beads
prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC
resistance, because it is imperative to provide adequate isolation between the board supply and the chip supply,
as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper
operation.
图10-5 shows this recommended power-supply decoupling method.
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Chip
Supply
Board
Supply
Ferrite Bead
1µF
10µF
0.1µF
(x3)
图10-5. Power Supply Decoupling
10.4 Layout
10.4.1 Layout Guidelines
For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. 图 10-6 and 图 10-7 show the
LMK1D1208I top and bottom PCB layer examples.
10.4.2 Layout Example
图10-6. Recommended PCB Layout, Top Layer
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图10-7. Recommended PCB Layout Bottom Layer
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Power Consumption of LVPECL and LVDS Analog Design Journal
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application note
• Texas Instruments, Using Thermal Calculation Tools for Analog Components application note
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
Packaging Information
Orderable
Device
Package
Drawing
Lead/Ball
Finish(6)
MSL Peak
Temp(3)
Device
Status(1)
Package Type
Pins
Package Qty
Eco Plan(2)
Op Temp (°C)
Marking(4) (5)
LMK1D1208IR ACTIVE
HAR
VQFN
RHA
Green (RoHS& NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 85
YEAR
LMK1D1208I
40
2500
LMK1D1208IR ACTIVE
HAT
VQFN
RHA
250
Green (RoHS& NIPDAU
no Sb/Br)
Level-2-260C-1 -40 to 85
YEAR
40
LMK1D1208I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a
new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all
6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high
temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)
as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
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Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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12.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
LMK1D1208IRHAR
LMK1D1208IRHAT
VQFN
VQFN
RHA
RHA
330.0
180.0
16.4
16.4
6.3
6.3
1.1
1.1
12.0
12.0
13.3
13.3
Q2
Q2
40
40
2500
250
6.3
6.3
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
Package Drawing Pins
SPQ
2500
250
Length (mm) Width (mm)
Height (mm)
LMK1D1208IRHAR
LMK1D1208IRHAT
VQFN
RHA
RHA
367.0
210.0
367.0
185.0
35.0
40
40
VQFN
35.0
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK1D1208IRHAR
LMK1D1208IRHAT
ACTIVE
VQFN
VQFN
RHA
40
40
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
LMK1D
1208I
Samples
Samples
ACTIVE
RHA
NIPDAU
LMK1D
1208I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK1D1208IRHAR
LMK1D1208IRHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK1D1208IRHAR
LMK1D1208IRHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040D
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
0.5
0.3
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
(0.1) TYP
2.9 0.1
EXPOSED
THERMAL PAD
11
20
36X 0.5
10
21
2X
41
SYMM
4.5
1
30
SEE TERMINAL
DETAIL
0.3
0.2
0.1
40X
40
31
SYMM
C A
B
PIN 1 ID
(OPTIONAL)
0.5
0.3
40X
0.05
4225822/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHA0040D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.9)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
(1.2)
TYP
41
SYMM
(5.8)
36X (0.5)
(
0.2) TYP
VIA
21
10
(R0.05)
TYP
11
20
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225822/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view.
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EXAMPLE STENCIL DESIGN
RHA0040D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.05) TYP
SYMM
40
31
40X (0.6)
1
30
4X ( 1.27)
40X (0.25)
(0.735) TYP
(0.735)
TYP
41
SYMM
(5.8)
36X (0.5)
METAL
TYP
21
10
20
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
76.46% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4225822/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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