LMK1D1208 [TI]

LMK1D120x Low Additive Jitter LVDS Buffer;


型号：	LMK1D1208
厂家：	TEXAS INSTRUMENTS
描述：	LMK1D120x Low Additive Jitter LVDS Buffer
文件：	总35页 (文件大小：1981K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

LMK1D120x Low Additive Jitter LVDS Buffer

1 Features

3 Description

•

High-performance LVDS clock buffer family with 2

inputs and 4 (2:4) or 8 (2:8) outputs.

Output frequency up to 2 GHz.

Supply voltage: 1.71 V to 3.465 V

Low additive jitter: < maximum 60 fs RMS in 12-

kHz to 20-MHz at 156.25 MHz

– Very low phase noise floor: –164 dBc/Hz

(typical)

Very low propagation delay: < 575 ps maximum

Output skew: 20 ps maximum

Universal inputs accept LVDS, LVPECL, LVCMOS,

LP-HCSL, HCSL and CML inputs

LVDS reference voltage, V_{AC_REF}, available for

capacitive-coupled inputs

Industrial temperature range: –40°C to 105°C

Packages available:

– LMK1D1204: 3-mm × 3-mm, 16-pin VQFN

(RGT)

– LMK1D1208: 5-mm × 5-mm, 28-pin VQFN

(RHD)

The LMK1D120x clock buffer distributes one of two

selectable clock inputs (IN0 and IN1) to 4 or 8 pairs

of differential LVDS clock outputs (OUT0 through

OUT7) with minimum skew for clock distribution. The

LMK1D12x family can accept two clock sources into

an input multiplexer. The inputs can either be LVDS,

LVPECL, LP-HCSL, HCSL, CML or LVCMOS.

•

The LMK1D12x is specifically designed for driving 50-

Ω transmission lines. In case of driving the inputs in

single-ended mode, the appropriate bias voltage as

shown in Figure 8-6 must be applied to the unused

negative input pin.

•

The IN_SEL pin selects the input which is routed

to the outputs. If this pin is left open, it disables

the outputs (logic low). The part supports a fail-safe

function. The device further incorporates an input

hysteresis which prevents random oscillation of the

outputs in the absence of an input signal.

•

The device operates in 1.8-V or 2.5-V or 3.3-V

supply environment and is characterized from –40°C

to 105°C (ambient temperature). The LMK1D12x

package variant is shown in the table below:

2 Applications

•

Telecommunications and networking

Medical imaging

Test and measurement

Wireless infrastructure

Pro audio, video and signage

Device Information

PART NUMBER⁽¹⁾

LMK1D1204

PACKAGE

VQFN (16)

VQFN (28)

BODY SIZE (NOM)

3.00 mm × 3.00 mm

5.00 mm × 5.00 mm

LMK1D1208

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

ADC CLOCK

F1 MHz

100 Ω

156.25 MHz

Oscillator

LMK1D 12XX

LVDS Buffer

IN_SEL

FPGA CLOCK

100 Ω

Application Example

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................6

6.5 Electrical Characteristics ............................................6

6.6 Typical Characteristics................................................9

7 Parameter Measurement Information..........................10

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................13

9 Application and Implementation..................................15

9.1 Application Information............................................. 15

9.2 Typical Application.................................................... 15

10 Power Supply Recommendations..............................19

11 Layout...........................................................................20

11.1 Layout Guidelines................................................... 20

11.2 Layout Example...................................................... 20

12 Device and Documentation Support..........................22

12.1 Documentation Support.......................................... 22

12.2 Receiving Notification of Documentation Updates..22

12.3 Support Resources................................................. 22

12.4 Trademarks.............................................................22

12.5 Electrostatic Discharge Caution..............................22

12.6 Glossary..................................................................22

13 Mechanical, Packaging, and Orderable

Information.................................................................... 22

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (December 2020) to Revision A (August 2021)

Page

•

First public release..............................................................................................................................................1

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

5 Pin Configuration and Functions

V_{AC_REF0}

IN0_N

IN0_P

V_DD

OUT2_P

OUT2_N

OUT3_P

OUT3_N

3mm x 3mm

16 pin QFN

Thermal Pad

Figure 5-1. LMK1D1204: RGT Package 16-Pin VQFN Top View

OUT4_P

OUT4_N

OUT5_P

OUT5_N

OUT6_P

OUT6_N

GND

OUT0_N

OUT0_P

5mm x 5mm

28 pin QFN

AC_REF0

IN0_N

IN0_P

Thermal Pad

Figure 5-2. LMK1D1208: RHD Package 28-Pin VQFN Top View

Table 5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

LMK1D1204

LMK1D1208

DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT

IN0_P

IN0_N

IN1_P

Primary: Differential input pair or single-ended input

Secondary: Differential input pair or single-ended input.

Note that INP0, INN0 are used indistinguishably with IN0_P,

IN0_N.

IN1_N

INPUT SELECT

IN_SEL

Input Selection with an internal 500-kΩ pullup and 320-kΩ

pulldown resistor, selects input port; (See Table 8-1)

BIAS VOLTAGE OUTPUT

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

Table 5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

V_{AC_REF0}

V_{AC_REF1}

LMK1D1204

LMK1D1208

Bias voltage output for capacitive coupled inputs. If used, TI

recommends using a 0.1-µF capacitor to GND on this pin.

—

DIFFERENTIAL CLOCK OUTPUT

OUT0_P

OUT0_N

OUT1_P

OUT1_N

OUT2_P

OUT2_N

OUT3_P

OUT3_N

OUT4_P

OUT4_N

OUT5_P

OUT5_N

OUT6_P

OUT6_N

OUT7_P

OUT7_N

SUPPLY VOLTAGE

Differential LVDS output pair number 0

Differential LVDS output pair number 1

Differential LVDS output pair number 2

Differential LVDS output pair number 3

Differential LVDS output pair number 4

Differential LVDS output pair number 5

Differential LVDS output pair number 6

Differential LVDS output pair number 7

—

V_DD

Device Power Supply (1.8V or 2.5V or 3.3V)

GROUND

GND

Ground

—

MISC

DAP

—

DAP

—

GND

Die Attach Pad. Connect to the PCB ground plane for heat

dissipation.

No Connection

(1) G = Ground, I = Input, O = Output, P = Power

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–20

MAX

3.6

UNIT

V_DD

V_IN

V_O

I_IN

Supply voltage

Input voltage

3.6

Output voltage

V_DD+ 0.3

Input current

°C

I_O

Continuous output current

Junction temperature

Storage temperature ⁽²⁾

–50

T_J

135

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Device unpowered

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±3000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

2.375

1.71

NOM

3.3

MAX

3.465

2.625

1.89

UNIT

3.3-V supply

V_DD

Core supply voltage

Supply voltage ramp

2.5-V supply

2.5

1.8-V supply

1.8

Supply

Ramp

Requires monotonic ramp (10-90% of

0.1

V_DD

)

T_A

T_J

Operating free-air temperature

Operating junction temperature

–40

105

135

°C

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

www.ti.com

UNIT

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

6.4 Thermal Information

LMK1D1204

VQFN

16 PINS

48.7

LMK1D1208

VQFN

28 PINS

38.9

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

56.4

32.1

23.6

18.7

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.6

Ψ_JB

23.6

18.7

R_θJC(bot)

8.6

8.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

VDD = 1.8 V ± 5 %, –40 °C ≤T_A ≤ 105 °C. Typical values are at VDD = 1.8 V, 25 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY CHARACTERISTICS

All-outputs enabled and

unterminated, f = 0 Hz

IDD_STAT

IDD_100M

LMK1D1204

LMK1D1208

LMK1D1204

LMK1D1208

All-outputs enabled and

unterminated, f = 0 Hz

All-outputs enabled, R_L= 100 Ω, f

=100 MHz

All-outputs enabled, R_L= 100 Ω, f

=100 MHz

IN_SEL CONTROL INPUT CHARACTERISTICS (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

Vd_I3

V_IH

3-state input

Open

0.4*V_CC

Minimun input voltage for a logical

"1" state in table 1

Input high voltage

0.7*V_CC

–0.3

V_CC+ 0.3

0.3*V_CC

Maximum input voltage for a

logical "0" state in table 1

V_IL

I_IH

I_IL

Input low voltage

V_DDcan be 1.8V/2.5V/3.3V with

V_IH= V_DD

Input high current

Input low current

kΩ

V_DDcan be 1.8V/2.5V/3.3V with

V_IH= V_DD

–30

R_pull-

Input pullup resistor

Input pulldown resistor

500

320

up(IN_SEL)

R_pull-

down(IN_SEL)

SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

f_IN

Input frequency

Clock input

0.4

250

MHz

Assumes a square wave input

with two levels

V_{IN_S-E}

Single-ended Input Voltage Swing

3.465

Input Slew Rate (20% to 80% of the

amplitude)

dVIN/dt

0.05

-30

V/ns

I_IH

Input high current

Input low current

Input capacitance

V_DD= 3.465 V, V_IH= 3.465 V

V_DD= 3.465 V, V_IL= 0 V

at 25°C

I_IL

C_{IN_SE}

3.5

DIFFERENTIAL CLOCK INPUT (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

f_IN

Input frequency

Clock input

GHz

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

VDD = 1.8 V ± 5 %, –40 °C ≤T_A ≤ 105 °C. Typical values are at VDD = 1.8 V, 25 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_ICM= 1 V (V_DD= 1.8 V)

0.3

2.4

Differential input voltage peak-to-peak

{2*(V_INP-V_INN)}

V_IN,DIFF(p-p)

V_PP

V_ICM= 1.25 V (V_DD= 2.5 V/3.3 V)

0.3

2.4

V_IN,DIFF(P-P)> 0.4 V (V_DD= 1.8

V/2.5/3.3 V)

V_ICM

I_IH

Input common mode voltage

Input high current

0.25

2.3

V_DD= 3.465 V, V_INP= 2.4 V, V_INN

= 1.2 V

V_DD= 3.465 V, V_INP= 0 V, V_INN

1.2 V

I_IL

Input low current

–30

C_{IN_S-E}

Input capacitance (Single-ended)

at 25°C

3.5

LVDS DC OUTPUT CHARACTERISTICS

Differential output voltage magnitude |

V_OUTP- V_OUTN

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

|VOD|

ΔVOD

250

–15

350

450

Change in differential output voltage

magnitude. Per output, defined as the

difference between VOD in logic hi/lo

states.

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω (V_DD= 1.8 V)

1.2

Steady-state common mode output

voltage

V_OC(SS)

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω (V_DD= 2.5 V/3.3 V)

1.1

1.375

Change in steady-state common mode

output voltage. Per output, defined as the

difference in VOC in logic hi/lo states.

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Δ_VOC(SS)

–15

LVDS AC OUTPUT CHARACTERISTICS

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω, f_OUT= 491.52 MHz

V_ring

Output overshoot and undershoot

–0.1

0.1

V_OD

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

V_OS

Output AC common mode

100

mV_pp

I_OS

Short-circuit output current (differential)

V_OUTP= V_OUTN

–12

–24

Short-circuit output current (common-

mode)

I_OS(cm)

V_OUTP= V_OUTN= 0

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω ⁽¹⁾

t_PD

Propagation delay

Output skew

0.3

0.575

skew between outputs with the

same load conditions (4 and 8

channel) ⁽²⁾

t_{SK, O}

Skew between outputs on

different parts subjected to the

same operating conditions with

the same input and output

t_{SK, PP}

Part-to-part skew

250

50% duty cycle input, crossing

t_{SK, P}

Pulse skew

point-to-crossing-point distortion

–20

(3)

f_IN= 156.25 MHz with 50% duty-

cycle, Input slew rate = 1.5V/ns,

Integration range = 12kHz -

t_RJIT(ADD)

Random additive Jitter (rms)

60 fs, RMS

20MHz, with output load R_LOAD

100 Ω

PN_1kHz

PN_10kHz

PN_100kHz

PN_1MHz

PN_floor

–143

-152

-157

-160

–164

Phase Noise for a carrier frequency of

156.25 MHz with 50% duty-cycle, Input

slew rate = 1.5V/ns with output load

R_LOAD= 100 Ω

Phase noise

dBc/Hz

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

www.ti.com

UNIT

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

VDD = 1.8 V ± 5 %, –40 °C ≤T_A ≤ 105 °C. Typical values are at VDD = 1.8 V, 25 °C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

f_IN= 156.25 MHz. The difference

in power level @ f_INwhen the

selected clock is active and the

unselected clock is static versus

when the selected clock is inactive

and the unselected clock is active.

MUX_ISO

Mux Isolation

ODC

Output duty cycle

With 50% duty cycle input

300

t_R/t_F

Output rise and fall time

Reference output voltage

20% to 80% with R_LOAD= 100 Ω

VDD = 2.5 V, I_LOAD= 100 uA

V_{AC_REF}

0.9

1.25

1.375

POWER SUPPLY NOISE REJECTION (PSNR) V_DD= 2.5 V/ 3.3 V

10 kHz, 100 mVpp ripple injected

–70

–50

on V_DD

Power Supply Noise Rejection (f_carrier

156.25 MHz)

PSNR

dBc

1 MHz, 100 mVpp ripple injected

on V_DD

(1) Measured between single-ended/differential input crossing point to the differential output crossing point.

(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.

(3) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

6.6 Typical Characteristics

The Figure 6-1 captures the variation of the LMK1D1208 current consumption with input frequency and supply

voltage. The LMK1D1204 follows a similar trend. Figure 6-2 shows the variation of the differential output voltage

(VOD) swept across frequency. This result is applicable to LMK1D1204 as well.

It is important to note that Figure 6-1 and Figure 6-2 serve as a guidance to the users on what to expect for the

range of operating frequency supported by LMK1D120x. It is crucial to note that these graphs were plotted for a

limited number of frequencies and load conditions which may not represent the customer system.

130

125

120

115

110

105

100

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V, T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V, T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V, T_A= 105

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Frequency (MHz)

Figure 6-1. LMK1D1208 Current Consumption vs. Frequency

380

370

360

350

340

330

320

310

300

290

280

270

260

250

240

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V, T_a= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V, T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V, T_A= 105

100

200

300

400

500

600 700 800 9001000

2000

Frequency (MHz)

Figure 6-2. LMK1D1208 VOD vs. Frequency

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

7 Parameter Measurement Information

Oscilloscope

100 W

LVDS

Figure 7-1. LVDS Output DC Configuration During Device Test

Phase Noise/

Spectrum Analyzer

LMK1D120X

Balun

100 Ω

Figure 7-2. LVDS Output AC Configuration During Device Test

Figure 7-3. DC-Coupled LVCMOS Input During Device Test

OUTNx

OUTPx

80%

(= 2 x V

)

20%

0 V

OUT,DIFF,PP

Figure 7-4. Output Voltage and Rise/Fall Time

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

INNx

INPx

PLH0

PHL0

PHL1

OUTN0

OUTP0

PLH1

OUTN1

OUTP1

PLH2

PHL2

OUTN2

OUTP2

PLH7

PHL7

OUTN7

OUTP7

A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest t_PLHnor the difference

between the fastest and the slowest t_PHLn(n = 0, 1, 2, ..7)

B. Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest t_PLHnor the difference

between the fastest and the slowest t_PHLnacross multiple devices (n = 0, 1, 2, ..7)

Figure 7-5. Output Skew and Part-to-Part Skew

ring

OUTNx

0 V Differential

OUTPx

Figure 7-6. Output Overshoot and Undershoot

GND

Figure 7-7. Output AC Common Mode

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

8 Detailed Description

8.1 Overview

The LMK1D120x LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing

and termination are required to ensure correct operation of the device and to maximize signal integrity.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the

receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI

recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage

different than the output common-mode voltage of the LMK1D12XX, AC-coupling must be used. If the LVDS

receiver has internal 100-Ω termination, external termination must be omitted.

8.2 Functional Block Diagram

VDD

1.8 to 3.3 V

Reference

Generator

V_{AC_REF}

IN0

OUT[0:N-1]

LVDS

IN_MUX

IN1

VDD

R_pull-up

IN_SEL

R_pull-down

GND

8.3 Feature Description

The LMK1D120x is a low additive jitter LVDS fan-out buffer that can generate up to eight copies of two

selectable LVPECL, LVDS, LP-HCSL, HCSL or LVCMOS inputs. The LMK1D120x can accept reference clock

frequencies up to 2 GHz while providing low output skew.

8.3.1 Fail-Safe Input and Hysteresis

The LMK1D120x family of devices is designed to support fail-safe input operation feature. This feature allows

the user to drive the device inputs before V_DDis applied without damaging the device. Refer to Specifications

for more information on the maximum input supported by the device. User should note that incorporating the

fail-safe inputs also results in a slight increase in clock input pin capacitance.

The device also incorporates an input hysteresis which prevents random oscillation in absence of an input

signal. Furthermore, this feature allows the input pins to be left open.

8.3.2 Input Mux

The LMK1D120x family of devices has a 2:1 input mux. This feature allows the user to select between the two

clock inputs (using the IN_SEL pin) to the device and fan it out to the outputs. More information on the input

selection is provided in the next section.

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

8.4 Device Functional Modes

The two inputs of the LMK1D120x are internally muxed together and can be selected through the control pin

(see Table 8-1). Unused input can be left floating thus reducing the need for additional components. Both AC-

and DC-coupling schemes can be used with the LMK1D120x to provide greater system flexibility.

Table 8-1. Input Selection Table

IN_SEL

ACTIVE CLOCK INPUT

IN0_P, IN0_N

IN1_P, IN1_N

None ⁽¹⁾

Open

(1) The input buffers are disabled and the outputs are static logic

low.

8.4.1 LVDS Output Termination

TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,

although unterminated outputs are also okay but will result in slight degradation in performance (Output AC

common-mode V_OS) in the outputs being used.

The LMK1D120x can be connected to LVDS receiver inputs with DC- and AC-coupling as shown in Figure 8-1

and Figure 8-2 (respectively).

Z = 50 W

100 W

LVDS

LMK1D12XX

Z = 50 W

Figure 8-1. Output DC Termination

100 nF

Z = 50 W

100 W

LVDS

LMK1D12XX

Z = 50 W

100 nF

Figure 8-2. Output AC Termination (With the Receiver Internally Biased)

8.4.2 Input Termination

The LMK1D120x input stage is designed with flexibility in mind to allow the user to drive the device with a wide

variety of signal types. This device can be interfaced with LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS

drivers. Please refer to Electrical Characteristics for more details.

LVDS drivers can be connected to LMK1D120x inputs with DC- and AC-coupling as shown Figure 8-3 and

Figure 8-4 (respectively).

Z = 50 W

100 W

LVDS

LMK1D12XX

Z = 50 W

Figure 8-3. LVDS Clock Driver Connected to LMK1D120x Input (DC-Coupled)

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

100 nF

Z = 50 W

LVDS

LMK1D12XX

Z = 50 W

100 nF

50 W

AC_REF

Figure 8-4. LVDS Clock Driver Connected to LMK1D120x Input (AC-Coupled)

Figure 8-5 shows how to connect LVPECL inputs to the LMK1D120x. The series resistors are required to reduce

the LVPECL signal swing if the signal swing is >1.6 V_PP

75 W

100 nF

Z = 50 W

LMK1D12XX

LVPECL

Z = 50 W

100 nF

50 W

75 W

150 W

50 W

AC_REF

Figure 8-5. LVPECL Clock Driver Connected to LMK1D120x Input

Figure 8-6 illustrates how to couple a LVCMOS clock input to the LMK1D120x directly.

LVCMOS

(1.8/2.5/3.3 V)

Z = 50 W

LMK1D12XX

V_IH+ V_IL

V_th=

Figure 8-6. 1.8-V/2.5-V/3.3-V LVCMOS Clock Driver Connected to LMK1D120x Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LMK1D120x is a low additive jitter universal to LVDS fan-out buffer with 2 selectable inputs. The small

package, low output skew, and low additive jitter make for a flexible device in demanding applications.

9.2 Typical Application

1.8 V / 2.5 V / 3.3 V

PHY

PRIREF_P

156.25 MHz LVDS

From Backplane

100

PRIREF_N

V_{AC_REF}

ASIC

100

156.25 MHz LVCMOS

Oscillator

SECREF_P

FPGA

100

2.5 V

SECREF_N

CPU

100

Figure 9-1. Fan-Out Buffer for Line Card Application

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

9.2.1 Design Requirements

The LMK1D120x shown in Figure 9-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the

backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. The LVDS clock is AC-coupled and biased

using the integrated reference voltage generator. A resistor divider is used to set the threshold voltage correctly

for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both V_{AC_REF}and SECREF_N. Either

input signal can be then fanned out to desired devices, as shown. The configuration example is driving 4 LVDS

receivers in a line card application with the following properties:

•

The PHY device is capable of DC-coupling with an LVDS driver such as the LMK1D120x. This PHY device

features internal termination so no additional components are required for proper operation.

The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as

the LMK1D120x. Again, no additional components are required.

The FPGA requires external AC-coupling, but has internal termination. 0.1-µF capacitors are placed to

provide AC-coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling

capacitors.

•

Unused outputs of the LMK1D device are terminated differentially with a 100-Ω resistor for optimum

performance.

9.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,

although unterminated outputs are also okay but will result in slight degradation in performance (Output AC

common-mode V_OS) in the outputs being used.

In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power-supply filtering and

bypassing is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in

Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043).

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

9.2.3 Application Curves

The LMK1D1208's low additive noise is shown below. The low noise 156.25-MHz source with 24-fs RMS jitter

shown in Figure 9-2 drives the LMK1D1208, resulting in 46.4-fs RMS when integrated from 12 kHz to 20 MHz

(Figure 9-3). The resultant additive jitter is a low 39.7-fs RMS for this configuration. Note that this result applies

to the LMK1D1204 device as well.

Reference signal is low-noise Rohde and Schwarz SMA100B

Figure 9-2. LMK1D208 Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz)

Figure 9-3. LMK1D1208 Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz)

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

The Figure 9-4 captures the low close-in phase noise of the LMK1D1208 device. The LMK1D1204 and

LMK1D1208 have excellent flicker noise as a result of superior process technology and design. This enables

their use for clock distribution in radar systems, medical imaging systems etc which require ultra-low close-in

phase noise clocks.

Figure 9-4. LMK1D1208 Output Phase Noise, 100 MHz, 1 kHz offset: -147 dBc/Hz

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter or phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against

the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the

device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must

be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends

adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.

TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip

power supply that isolates the high-frequency switching noises generated by the clock driver; these beads

prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low

DC-resistance because it is imperative to provide adequate isolation between the board supply and the chip

supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for

proper operation.

Figure 10-1 shows this recommended power-supply decoupling method.

Chip

Supply

Board

Supply

Ferrite Bead

1µF

10µF

0.1µF

(x3)

Figure 10-1. Power Supply Decoupling

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

11 Layout

11.1 Layout Guidelines

For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a

ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be

soldered down to ensure adequate heat conduction to of the package. Figure 11-1 shows a recommended land

and via pattern for LMK1D1208.

11.2 Layout Example

Figure 11-1. Recommended PCB Layout, Top Layer

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

Figure 11-2. PCB Layout, GND Layer

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

LMK1D1204, LMK1D1208

SNAS815A – DECEMBER 2020 – REVISED AUGUST 2021

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043)

Power Consumption of LVPECL and LVDS (SLYT127)

Semiconductor and IC Package Thermal Metrics (SPRA953)

Using Thermal Calculation Tools for Analog Components (SLUA556)

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: LMK1D1204 LMK1D1208

PACKAGE OPTION ADDENDUM

www.ti.com

20-Aug-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMK1D1204RGTR

LMK1D1204RGTT

LMK1D1208RHDR

ACTIVE

VQFN

RGT

RHD

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

LD1204

NIPDAU

LD1204

LMK1D

1208

LMK1D1208RHDT

ACTIVE

VQFN

RHD

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

LMK1D

1208

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

20-Aug-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Aug-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMK1D1204RGTR

LMK1D1204RGTT

LMK1D1208RHDR

LMK1D1208RHDT

VQFN

RGT

RHD

3000

250

330.0

180.0

330.0

180.0

12.4

3.3

5.3

3.3

5.3

1.1

8.0

12.0

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Aug-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMK1D1204RGTR

LMK1D1204RGTT

LMK1D1208RHDR

LMK1D1208RHDT

VQFN

RGT

RHD

3000

250

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

35.0

3000

250

Pack Materials-Page 2

PACKAGE OUTLINE

RHD0028B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

PIN 1 INDEX AREA

5.15

4.85

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

3.15 0.1

2X 3

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

SYMM

2X 3

3.15 0.1

24X 0.5

PIN 1 ID

0.30

0.18

28X

0.1

C A B

0.65

0.45

28X

0.05

4226146/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHD0028B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.15)

SYMM

SEE SOLDER MASK

DETAIL

28X (0.75)

28X (0.24)

24X (0.5)

SYMM

(4.65)

(1.325)

(R0.05) TYP

(

0.2) TYP

VIA

(1.325)

(4.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226146/A 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHD0028B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.785) TYP

28X (0.75)

28X (0.24)

24X (0.5)

(0.785) TYP

(4.65)

SYMM

(R0.05) TYP

4X (1.37)

SYMM

(4.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 29

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4226146/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RGT0016C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

1.0

0.8

SEATING PLANE

0.08

0.05

0.00

1.68 0.07

(0.2) TYP

EXPOSED

THERMAL PAD

12X 0.5

SYMM

1.5

0.30

16X

0.18

0.1

C A B

PIN 1 ID

(OPTIONAL)

SYMM

0.05

0.5

0.3

16X

4222419/C 04/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGT0016C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.68)

SYMM

16X (0.6)

16X (0.24)

SYMM

(2.8)

(0.58)

TYP

12X (0.5)

(

0.2) TYP

VIA

(0.58) TYP

(R0.05)

ALL PAD CORNERS

(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222419/C 04/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGT0016C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.55)

16X (0.6)

16X (0.24)

SYMM

(2.8)

12X (0.5)

METAL

ALL AROUND

SYMM

(2.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4222419/C 04/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMK1D1208 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E