LMK1D2102RGTR [TI]
LMK1D210x Low Additive Jitter LVDS Buffer;型号: | LMK1D2102RGTR |
厂家: | TEXAS INSTRUMENTS |
描述: | LMK1D210x Low Additive Jitter LVDS Buffer |
文件: | 总33页 (文件大小:2052K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMK1D2102, LMK1D2104
SNAS822 – SEPTEMBER 2021
LMK1D210x Low Additive Jitter LVDS Buffer
1 Features
3 Description
•
High-performance LVDS clock buffer family: up to
2 GHz
– Dual 1:2 differential buffer
The LMK1D210x clock buffer distributes two clock
inputs (IN0 and IN1) to a total of up to 8 pairs of
differential LVDS clock outputs (OUT0, OUT7) with
minimum skew for clock distribution. Each buffer block
consists of one input and up to 4 LVDS outputs. The
inputs can either be LVDS, LVPECL, HCSL, CML or
LVCMOS.
– Dual 1:4 differential buffer
•
•
Supply voltage: 1.71 V to 3.465 V
Low additive jitter: < max 60 fs RMS in 12-kHz to
20-MHz @ 156.25 MHz
– Very low phase noise floor: -164 dBc/Hz
(typical)
Very low propagation delay < 575 ps max
Output skew of 20 ps max
Universal inputs accept LVDS, LVPECL, LVCMOS,
HCSL and CML signal levels.
The LMK1D210x is specifically designed for driving
50-Ω transmission lines. In case of driving the inputs
in single-ended mode, the appropriate bias voltage as
shown in Figure 8-6 must be applied to the unused
negative input pin.
•
•
•
Using the control pin (EN), output banks can either
be enabled or disabled. If this pin is left open, two
buffers with all outputs are enabled, if switched to
a logic "0", both banks with all outputs are disabled
(static logic "0"), if switched to a logic "1", one bank
and its outputs are disabled while another bank with
its outputs are enabled. The part supports a fail-safe
function. The device further incorporates an input
hysteresis which prevents random oscillation of the
outputs in the absence of an input signal.
•
LVDS reference voltage, VAC_REF, available for
capacitive coupled inputs
Industrial temperature range: –40°C to 105°C
Packaged in
– LMK1D2102: 3-mm x 3-mm, 16-Pin VQFN
– LMK1D2104: 5-mm x 5-mm, 28-Pin VQFN
•
•
2 Applications
•
•
•
•
•
Telecommunications and networking
Medical imaging
Test and measurement
Wireless infrastructure
Pro audio, video and signage
The device operates in 1.8-V or 2.5-V or 3.3-V
supply environment and is characterized from –40°C
to 105°C (ambient temperature). The LMK1D210x
package variant is shown in the table below:
Device Information
PART NUMBER(1)
LMK1D2102
PACKAGE
VQFN (16)
VQFN (28)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
5.00 mm × 5.00 mm
LMK1D2104
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
491.52 MHz
AFE DEVICE
CLOCK
EN
LMK1D21XX
LVDS Buffer
AFE
7.68 MHz
AFE SYSREF
CLOCK
Application Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK1D2102, LMK1D2104
SNAS822 – SEPTEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................8
7 Parameter Measurement Information............................9
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................18
11 Layout...........................................................................19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Documentation Support.......................................... 20
12.2 Receiving Notification of Documentation Updates..20
12.3 Support Resources................................................. 20
12.4 Trademarks.............................................................20
12.5 Electrostatic Discharge Caution..............................20
12.6 Glossary..................................................................20
13 Mechanical, Packaging, and Orderable
Information.................................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
September 2021
*
Initial Release
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5 Pin Configuration and Functions
21
20
19
18
17
16
15
12
11
10
9
GND
OUT4_P
OUT4_N
OUT5_P
OUT5_N
OUT6_P
OUT6_N
22
23
24
25
26
27
28
14
13
12
11
10
9
VAC_REF0
IN0_N
IN0_P
VDD
OUT2_P
OUT2_N
OUT3_P
OUT3_N
13
14
15
16
8
7
OUT0_N
OUT0_P
5mm x 5mm
28 pin QFN
3mm x 3mm
16 pin QFN
V
AC_REF0
6
5
IN0_N
IN0_P
Thermal Pad
Thermal Pad
1
2
3
4
V
V
8
DD
DD
1
2
3
4
5
6
7
Figure 5-1. LMK1D2102: RGT Package 16-Pin
VQFN Top View
Figure 5-2. LMK1D2104: RHD Package 28-Pin
VQFN Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
LMK1D2102
LMK1D2104
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N
6, 7
9, 10
5, 6
I
I
Primary: Differential input pair or single-ended input
Secondary: Differential input pair or single-ended input.
IN1_P, IN1_N
3, 4
Note that INP0, INN0 are used indistinguishably with IN0_P,
IN0_N.
OUTPUT BANK CONTROL
EN
Output bank enable/disable with an internal 500-kΩ pullup and
320-kΩ pulldown, selects input port; (See Table 8-1)
2
8
4
I
BIAS VOLTAGE OUTPUT
VAC_REF0,VAC_REF1
Bias voltage output for capacitive coupled inputs. If used, TI
recommends using a 0.1-µF capacitor to GND on this pin.
11, 7
O
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N
OUT1_P, OUT1_N
OUT2_P, OUT2_N
OUT3_P, OUT3_N
OUT4_P, OUT4_N
OUT5_P, OUT5_N
OUT6_P, OUT6_N
OUT7_P, OUT7_N
SUPPLY VOLTAGE
VDD
9, 10(IN0)
12, 13(IN0)
16, 17 (IN0)
18, 19 (IN0)
20, 21 (IN0)
22, 23 (IN1)
24, 25 (IN1)
26, 27 (IN1)
2, 3 (IN1)
O
O
O
O
O
O
O
O
Differential LVDS output pair number 0
Differential LVDS output pair number 1
Differential LVDS output pair number 2
Differential LVDS output pair number 3
Differential LVDS output pair number 4
Differential LVDS output pair number 5
Differential LVDS output pair number 6
Differential LVDS output pair number 7
11, 12(IN0)
13, 14 (IN1)
15, 16 (IN1)
5
1
8, 15, 28
1, 14
P
G
Device Power Supply (1.8V or 2.5V or 3.3V)
Ground
GROUND
GND
MISC
DAP
DAP
DAP
GND
Die Attach Pad. Connect to the PCB ground plane for heat
dissipation.
(1) G = Ground, I = Input, O = Output, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–20
MAX
3.6
UNIT
V
VDD
VIN
VO
IIN
Supply voltage
Input voltage
3.6
V
Output voltage
VDD + 0.3
20
V
Input current
mA
mA
°C
°C
IO
Continuous output current
Junction temperature
Storage temperature (2)
–50
50
TJ
135
Tstg
–65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Device unpowered
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
2.375
1.71
NOM
3.3
MAX
3.465
2.625
1.89
UNIT
3.3-V supply
VDD
Core supply voltage
Supply voltage ramp
2.5-V supply
2.5
V
1.8-V supply
1.8
Supply
Ramp
Requires monotonic ramp (10-90% of
0.1
20
ms
VDD
)
TA
TJ
Operating free-air temperature
Operating junction temperature
–40
–40
105
135
°C
°C
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6.4 Thermal Information
LMK1D1204
VQFN
16 PINS
48.7
LMK1D1208I
THERMAL METRIC(1)
VQFN
40 PINS
38.9
32.1
18.7
1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.4
23.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ΨJB
23.6
18.7
8.2
RθJC(bot)
8.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VDD = 1.8 V ± 5 %, –40 °C ≤T_A ≤ 105 °C. Typical values are at VDD = 1.8 V, 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY CHARACTERISTICS
All-outputs enabled and
unterminated, f = 0 Hz
IDDSTAT
IDDSTAT
IDD100M
IDD100M
LMK1D2102
LMK1D2104
LMK1D2102
LMK1D2104
50
55
70
84
mA
mA
mA
mA
All-outputs enabled and
unterminated, f = 0 Hz
All-outputs enabled, RL = 100 Ω, f
=100 MHz
80
All-outputs enabled, RL = 100 Ω, f
=100 MHz
110
OUTPUT BANK CONTROL (EN) INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
VdI3
VIH
3-state input
Open
0.4*VCC
V
V
Minimum input voltage for a
logical "1" state in table 1
Input high voltage
0.7*VCC
–0.3
VCC + 0.3
0.3*VCC
30
Maximum input voltage for a
logical "0" state in table 1
VIL
IIH
Input low voltage
Input high current
V
VDD can be 1.8V/2.5V/3.3V with
VIH = VDD
µA
µA
VDD can be 1.8V/2.5V/3.3V with
VIH = VDD
IIL
Input low current
–30
Rpull-up(EN)
Input pullup resistor
500
320
kΩ
kΩ
Rpull-down(EN) Input pulldown resistor
SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
DC
0.4
250
MHz
V
Assumes a square wave input
with two levels
VIN_S-E
Single-ended Input Voltage Swing
3.465
Input Slew Rate (20% to 80% of the
amplitude)
dVIN/dt
0.05
-30
V/ns
IIH
Input high current
Input low current
Input capacitance
VDD = 3.465 V, VIH = 3.465 V
VDD = 3.465 V, VIL = 0 V
at 25°C
50
µA
µA
pF
IIL
CIN_SE
3.5
DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)
fIN
Input frequency
Clock input
2
2.4
2.4
GHz
VPP
VICM = 1 V (VDD = 1.8 V)
VICM = 1.25 V (VDD = 2.5 V/3.3 V)
0.3
0.3
Differential input voltage peak-to-peak
{2*(VINP-VINN)}
VIN,DIFF(p-p)
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VDD = 1.8 V ± 5 %, –40 °C ≤T_A ≤ 105 °C. Typical values are at VDD = 1.8 V, 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN,DIFF(P-P) > 0.4 V (VDD = 1.8
V/2.5/3.3 V)
VICM
IIH
Input common mode voltage
0.25
2.3
V
VDD = 3.465 V, VINP = 2.4 V, VINN
= 1.2 V
Input high current
30
µA
VDD = 3.465 V, VINP = 0 V, VINN
1.2 V
=
IIL
Input low current
–30
µA
pF
CIN_S-E
Input capacitance (Single-ended)
at 25°C
3.5
LVDS DC OUTPUT CHARACTERISTICS
Differential output voltage magnitude |
VOUTP - VOUTN
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
|VOD|
ΔVOD
250
–15
350
450
15
mV
mV
|
Change in differential output voltage
magnitude. Per output, defined as the
difference between VOD in logic hi/lo
states.
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω (VDD = 1.8 V)
1
1.2
Steady-state common mode output
voltage
VOC(SS)
V
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω (VDD = 2.5 V/3.3 V)
1.1
1.375
Change in steady-state common mode
output voltage. Per output, defined as the
difference in VOC in logic hi/lo states.
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
ΔVOC(SS)
–15
15
mV
LVDS AC OUTPUT CHARACTERISTICS
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω, fOUT = 491.52 MHz
Vring
Output overshoot and undershoot
–0.1
0.1
VOD
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω
VOS
Output AC common mode
50
100
12
mVpp
mA
IOS
Short-circuit output current (differential)
VOUTP = VOUTN
–12
–24
Short-circuit output current (common-
mode)
IOS(cm)
VOUTP = VOUTN = 0
24
mA
VIN,DIFF(P-P) = 0.3 V, RLOAD = 100
Ω (1)
tPD
Propagation delay
Output skew
0.3
0.575
20
ns
ps
ps
Skew between outputs with the
same load conditions (4 and 8
channel) (2)
tSK, O
Skew between the outputs within
the same bank (2102/2104) (3)
tSK, b
Output bank skew
15
Skew between outputs on
different parts subjected to the
same operating conditions with
the same input and output
loading.
tSK, PP
Part-to-part skew
250
20
ps
ps
50% duty cycle input, crossing
tSK, P
Pulse skew
point-to-crossing-point distortion
–20
(4)
fIN = 156.25 MHz with 50% duty-
cycle, Input slew rate = 1.5V/ns,
Integration range = 12kHz -
tRJIT(ADD)
Random additive Jitter (rms)
50
60 fs, RMS
20MHz, with output load RLOAD
100 Ω
=
PN1kHz
PN10kHz
PN100kHz
PN1MHz
PNfloor
–143
-152
-157
-160
–164
Phase Noise for a carrier frequency of
156.25 MHz with 50% duty-cycle, Input
slew rate = 1.5V/ns with output load
RLOAD = 100 Ω
Phase noise
dBc/Hz
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VDD = 1.8 V ± 5 %, –40 °C ≤T_A ≤ 105 °C. Typical values are at VDD = 1.8 V, 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 156.25 MHz. The difference
in power level @ fIN when the
selected clock is active and the
unselected clock is static versus
when the selected clock is inactive
and the unselected clock is active.
MUXISO
Mux Isolation
80
dB
Differential inputs with FIN0
=
491.52 MHz, FIN1 = 61.44 MHz;
Measured between neighboring
outputs
–60
–70
Spurious suppression between dual
banks
SPUR
dB
Different inputs with FIN0
=
491.52 MHz, FIN1 = 15.36 MHz;
Measured between neighboring
outputs
ODC
Output duty cycle
With 50% duty cycle input
45
55
300
%
ps
V
tR/tF
Output rise and fall time
Reference output voltage
20% to 80% with RLOAD = 100 Ω
VDD = 2.5 V, ILOAD = 100 µA
VAC_REF
0.9
1.25
1.375
POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V
10 kHz, 100 mVpp ripple injected
–70
–50
on VDD
Power Supply Noise Rejection (fcarrier
156.25 MHz)
=
PSNR
dBc
1 MHz, 100 mVpp ripple injected
on VDD
(1) Measured between single-ended/differential input crossing point to the differential output crossing point.
(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.
(3) Applies to the dual bank family.
(4) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
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6.6 Typical Characteristics
The Figure 6-1 captures the variation of the LMK1D2104 current consumption with input frequency and supply
voltage. The LMK1D2102 follows a similar trend. Figure 6-2 shows the variation of the differential output voltage
(VOD) swept across frequency. This result is applicable to LMK1D2102 as well.
It is important to note that Figure 6-1 and Figure 6-2 serve as a guidance to the users on what to expect for the
range of operating frequency supported by LMK1D210x. It is crucial to note that these graphs were plotted for a
limited number of frequencies and load conditions which may not represent the customer system.
140
135
130
125
120
115
110
105
100
95
90
85
80
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V,TA = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V,TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V,TA =105
0
100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Frequency (MHz)
Figure 6-1. LMK1D2104 Current Consumption vs. Frequency
380
370
360
350
340
330
320
310
300
290
280
270
260
250
240
VDD = 1.8 V, TA = -40
VDD = 1.8 V, TA = 25
VDD = 1.8 V, Ta = 105
VDD = 2.5 V, TA = -40
VDD = 2.5 V, TA = 25
VDD = 2.5 V, TA = 105
VDD = 3.3 V, TA = -40
VDD = 3.3 V, TA = 25
VDD = 3.3 V, TA = 105
100
200
300
400
500
600 700 800 9001000
2000
Frequency (MHz)
Figure 6-2. LMK1D2104 VOD vs. Frequency
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7 Parameter Measurement Information
Oscilloscope
100 W
LVDS
Figure 7-1. LVDS Output DC Configuration During Device Test
Phase Noise/
Spectrum Analyzer
LMK1D210X
Balun
100 Ω
Figure 7-2. LVDS Output AC Configuration During Device Test
V
IH
V
th
IN
V
IL
IN
V
th
Figure 7-3. DC-Coupled LVCMOS Input During Device Test
V
OUTNx
OUTPx
OH
V
OD
V
OL
80%
V
(= 2 x V
)
OD
20%
0 V
OUT,DIFF,PP
t
r
t
f
Figure 7-4. Output Voltage and Rise/Fall Time
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INNx
INPx
t
t
t
PLH0
PHL0
PHL1
OUTN0
OUTP0
t
PLH1
OUTN1
OUTP1
t
t
PLH2
PHL2
OUTN2
OUTP2
t
t
PLH7
PHL7
OUTN7
OUTP7
A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn (n = 0, 1, 2, ..7)
B. Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest tPLHn or the difference
between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, ..7)
Figure 7-5. Output Skew and Part-to-Part Skew
V
ring
OUTNx
V
OD
0 V Differential
OUTPx
Figure 7-6. Output Overshoot and Undershoot
V
OS
GND
Figure 7-7. Output AC Common Mode
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8 Detailed Description
8.1 Overview
The LMK1D210x LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing
and termination are required to ensure correct operation of the device and to maximize signal integrity.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI
recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage
different than the output common-mode voltage of the LMK1D210x, AC-coupling must be used. If the LVDS
receiver has internal 100-Ω termination, external termination must be omitted.
8.2 Functional Block Diagram
VDD
1.8 to 3.3V
Reference
Generator
VAC_REF
IN0
LVDS
LVDS
OUT[0:N/2-1]
OUT[N/2:N-1]
IN1
EN
VDD
Rpull-up
Rpull-down
GND
8.3 Feature Description
The LMK1D210x is a low additive jitter LVDS fan-out buffer that can generate up to four copies of a single input
which can be either LVPECL, LVDS, or LVCMOS on each of its banks. Since the device has two banks, this
translates to a total of eight pairs of outputs (LMK1D2104). The reference clock frequencies can go up to 2 GHz.
Apart from providing a very low additive jitter and low output skew, the LMK1D210x has a control pin (EN), which
controls the enabling/disabling of the output banks.
8.4 Device Functional Modes
The output banks of the LMK1D210x can be selected through the control pin (see Table 8-1). Unused inputs and
outputs can be left floating to reduce overall component cost. Both AC- and DC-coupling schemes can be used
with the LMK1D210x to provide greater system flexibility.
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Table 8-1. Output Control Table
EN
CLOCK OUTPUTS
0
All outputs disabled (static "0")
OUT0, OUT1… OUT[(N/2)-1]
enabled and OUT[N/2]…OUT[-1]
disabled. Example: LMK1D2102
(OUT0, OUT1 enabled, OUT2,
OUT3 disabled
1
Open
All outputs enabled
8.4.1 LVDS Output Termination
TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,
although unterminated outputs are also okay but will result in slight degradation in performance (Output AC
common-mode VOS ) in the outputs being used.
The LMK1D210x can be connected to LVDS receiver inputs with DC- and AC-coupling as shown in Figure 8-1
and Figure 8-2 (respectively).
100 W
LVDS
LMK1D21XX
Z = 50 W
Figure 8-1. Output DC Termination
100 nF
100 W
LVDS
LMK1D21XX
Z = 50 W
100 nF
Figure 8-2. Output AC Termination (With the Receiver Internally Biased)
8.4.2 Input Termination
The LMK1D210x inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers.
LVDS drivers can be connected to LMK1D210x inputs with DC- and AC-coupling as shown Figure 8-3 and
Figure 8-4 (respectively).
100 W
LVDS
LMK1D21XX
Z = 50 W
Figure 8-3. LVDS Clock Driver Connected to LMK1D210x Input (DC-Coupled)
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100 nF
LVDS
LMK1D21XX
Z = 50 W
100 nF
50 W
50 W
V
AC_REF
Figure 8-4. LVDS Clock Driver Connected to LMK1D210x Input (AC-Coupled)
Figure 8-5 shows how to connect LVPECL inputs to the LMK1D210x. The series resistors are required to reduce
the LVPECL signal swing if the signal swing is >1.6 VPP
.
75 W
100 nF
LMK1D21XX
LVPECL
Z = 50 W
100 nF
50 W
75 W
150 W
150 W
50 W
V
AC_REF
Figure 8-5. LVPECL Clock Driver Connected to LMK1D210x Input
Figure 8-6 illustrates how to couple a LVCMOS clock input to the LMK1D210x directly.
RS
LVCMOS
Z = 50
(1.8/2.5/3.3 V)
LMK1D21XX
VTH = 0.5*(VIH + VIL)
Figure 8-6. 1.8-V/2.5-V/3.3-V LVCMOS Clock Driver Connected to LMK1D210x Input
Unused inputs can be left floating thus reducing the need for additional components.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMK1D210x is a low additive jitter universal to LVDS fan-out buffer with dual inputs which fan-out to dual
outputs banks. Each input can fan-out to a maximum of four outputs (LMK1D2104). The small package, 1.8 V
power supply operation, low output skew, and low additive jitter makes this device suitable for applications that
require high performance clock distribution as well as for low power and space constraint applications.
9.2 Typical Application
ADC CLOCK
JESD204B/C AFE
IN0
ADC CLOCK
100
Digital control
LMK1D21XX
LVDS Buffer
EN
SYSREF CLOCK
100
IN1
SYSREF CLOCK
Figure 9-1. Fan-Out Buffer for ADC Device clock and SYSREF distribution
9.2.1 Design Requirements
The LMK1D210x shown in Figure 9-1 is configured to fan-out an ADC clock on the first output bank and
SYSREF clock on the second output bank for a system utilizing the JESD204B/C ADC. The low output
to output skew, very low additive jitter and superior spurious suppression between dual banks makes the
LMK1D210x a simple, robust and low-cost solution for distributing various clocks to JESD204B/C AFE systems.
The configuration example can drive up to 4 ADC clocks and 4 SYSREF clocks for a JESD204B/C receiver with
the following properties:
•
The ADC clock receiver module is typically AC coupled with an LVDS driver such as the LMK1D210x due to
differences in common-mode between the driver and receiver. Depending on the receiver, there maybe an
option for internal 100-Ω differential termination in which case an external termination would not be required
for the LMK1D210x.
•
•
The SYSREF clock receiver module is typically DC coupled provided the common-mode voltage of the
LMK1D210x outputs match with the receiver. An external termination may not be needed in case of an
internal termination in the receiver.
Unused outputs of the LMK1D device are terminated differentially with a 100-Ω resistor for optimum
performance.
9.2.2 Detailed Design Procedure
See Section 8.4.2 for proper input terminations, dependent on single-ended or differential inputs.
See Section 8.4.1 for output termination schemes depending on the receiver application.
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TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,
although unterminated outputs are also okay but will result in slight degradation in performance (Output AC
common-mode VOS ) in the outputs being used.
In the application example described in the previous section Figure 9-1, the ADC clock and SYSREF clocks
require different output interfacing schemes. Power supply filtering and bypassing is critical for low-noise
applications.
In case of common-mode mismatch between the output voltage of the LMK1D210x and the receiver, one can
use AC coupling to get around this, however, in certain applications, it might not be possible to AC couple
the LMK1D210x outputs to the receiver due to the settling time associated with this AC coupling network (High-
pass filter) which can result in non-deterministic behavior during the initial transients. For such applications, it
becomes necessary to DC couple the outputs and thus requires a scheme which can overcome the inherent
mismatch between the common-mode of the driver and receiver.
The application report Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between
a LVDS driver and sub-LVDS receiver. Same concept can be applied to interface the LMK1D210x outputs to a
receiver which has lower common-mode.
1.8 V
R1
R3
R2
OUTX_P
IN_P
LMK1D21xx
SYSREF AFE
OUTX_N
IN_N
R3
R2
R1
1.8 V
Figure 9-2. Schematic for DC coupling LMK1D21xx with lower common-mode receiver
The Figure 9-2 illustrates the resistor divider network for stepping down the common mode as explained in
the above application report. The resistors R1, R2 and R3 are chosen according to the input common mode
requirements of the receiver. As highlighted before, user needs to make sure that the reduced swing is able to
meet the requirements of the receiver.
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9.2.3 Application Curves
The LMK1D2104's low additive noise is shown below. The low noise 156.25-MHz source with 24-fs RMS jitter
shown in Figure 9-3 drives the LMK1D2104, resulting in 46.4-fs RMS when integrated from 12 kHz to 20 MHz
(Figure 9-4). The resultant additive jitter is a low 39.7-fs RMS for this configuration. Note that this result applies
to the LMK1D2102 device as well.
A.
Reference signal is low-noise Rohde and Schwarz SMA100B
Figure 9-3. LMK1D2104 Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz)
Figure 9-4. LMK1D2104 Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz)
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The Figure 9-5 captures the low close-in phase noise of the LMK1D2104 device. The LMK1D2102 and
LMK1D2104 have excellent flicker noise as a result of superior process technology and design. This enables
their use for clock distribution in radar systems, medical imaging systems etc which require ultra-low close-in
phase noise clocks.
Figure 9-5. LMK1D2104 Output Phase Noise, 100 MHz, 1 kHz offset: -147 dBc/Hz
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10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter or phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must
be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends
adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.
TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip
power supply that isolates the high-frequency switching noises generated by the clock driver; these beads
prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low
DC-resistance because it is imperative to provide adequate isolation between the board supply and the chip
supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for
proper operation.
Figure 10-1 shows this recommended power-supply decoupling method.
Chip
Supply
Board
Supply
Ferrite Bead
1µF
10µF
0.1µF
(x3)
Figure 10-1. Power Supply Decoupling
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11 Layout
11.1 Layout Guidelines
For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.
The device package has an exposed pad that provides the primary heat removal path to the printed-circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must be
soldered down to ensure adequate heat conduction to of the package. Figure 11-1 shows a recommended land
and via pattern for the 16-pin package (LMK1D2102).
11.2 Layout Example
3,0 mm (min)
0,33 mm (typ)
0,75 mm (typ)
Figure 11-1. Recommended PCB Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043)
Power Consumption of LVPECL and LVDS (SLYT127)
Semiconductor and IC Package Thermal Metrics (SPRA953)
Using Thermal Calculation Tools for Analog Components (SLUA556)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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1-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK1D2102RGTR
LMK1D2102RGTT
LMK1D2104RHDR
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RGT
RGT
RHD
16
16
28
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
-40 to 105
LD2102
NIPDAU
NIPDAU
LD2102
LMK1D
2104
LMK1D2104RHDT
ACTIVE
VQFN
RHD
28
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
LMK1D
2104
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK1D2102RGTR
LMK1D2102RGTT
LMK1D2104RHDR
LMK1D2104RHDT
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RHD
RHD
16
16
28
28
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.3
3.3
5.3
5.3
3.3
3.3
5.3
5.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK1D2102RGTR
LMK1D2102RGTT
LMK1D2104RHDR
LMK1D2104RHDT
VQFN
VQFN
VQFN
VQFN
RGT
RGT
RHD
RHD
16
16
28
28
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/C 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/C 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/C 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
RHD0028B
VQFN - 1 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
3.15 0.1
2X 3
SYMM
(0.2) TYP
8
14
EXPOSED
THERMAL PAD
15
7
SYMM
29
2X 3
3.15 0.1
24X 0.5
1
21
PIN 1 ID
0.30
0.18
28X
22
28
0.1
C A B
0.65
0.45
28X
0.05
4226146/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHD0028B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.15)
SYMM
28
SEE SOLDER MASK
DETAIL
22
28X (0.75)
28X (0.24)
24X (0.5)
21
1
29
SYMM
(4.65)
(1.325)
(R0.05) TYP
7
15
(
0.2) TYP
VIA
8
14
(1.325)
(4.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226146/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHD0028B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.785) TYP
22
28
28X (0.75)
28X (0.24)
21
1
24X (0.5)
(0.785) TYP
(4.65)
29
SYMM
(R0.05) TYP
4X (1.37)
7
15
14
8
4X (1.37)
SYMM
(4.65)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 29
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4226146/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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