LMK1D2108RGZT [TI]

LMK1D210x Low Additive Jitter LVDS Buffer;


型号：	LMK1D2108RGZT
厂家：	TEXAS INSTRUMENTS
描述：	LMK1D210x Low Additive Jitter LVDS Buffer
文件：	总37页 (文件大小：3453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK1D2106, LMK1D2108

SNAS829 – OCTOBER 2021

LMK1D210x Low Additive Jitter LVDS Buffer

1 Features

3 Description

•

High-performance LVDS clock buffer family: up to

2 GHz

The LMK1D210x clock buffer distributes two clock

inputs (IN0 and IN1) to a total of 16 pairs of

differential LVDS clock outputs (OUT0 to OUT15) in

the LMK1D2108 and 12 pairs of clock outputs (OUT0

to OUT11) in the LMK1D2106 with minimum skew

for clock distribution. Each buffer block consists of

one input and a maximum of 6 (LMK1D2106) or 8

(LMK1D2108) LVDS outputs. The inputs can either be

LVDS, LVPECL, HCSL, CML, or LVCMOS.

– Dual 1:6 differential buffer

– Dual 1:8 differential buffer

Supply voltage: 1.71 V to 3.465 V

Low additive jitter: < 60 fs RMS maximum in 12-

kHz to

20-MHz at 156.25 MHz

– Very low phase noise floor: -164 dBc/Hz

(typical)

Very low propagation delay: < 575 ps maximum

Output skew: 20 ps maximum

High-swing LVDS (boosted mode): 500-mV VOD

typical when AMP_SEL = 1

Bank enable/disable using the EN pin

Universal inputs accept LVDS, LVPECL, LVCMOS,

HCSL and CML signal levels

LVDS reference voltage, V_{AC_REF}, available for

capacitive-coupled inputs

Industrial temperature range: –40°C to 105°C

Packaged in

– LMK1D2106: 6-mm × 6-mm, 40-pin VQFN

(RHA)

•

The LMK1D210x is specifically designed for driving

50-Ω transmission lines. When driving inputs in

single-ended mode, apply the appropriate bias

voltage to the unused negative input pin (see Figure

8-6).

•

Using the control pin (EN), output banks can either be

enable or disabled. If this pin is left open, both bank

outputs are enabled. If the control pin is switched to a

logic "0", both bank outputs are disabled (static logic

"0"). If the control pin is switched to a logic "1", the

outputs of one bank are disabled while the outputs of

the other bank are enabled. The part also supports a

fail-safe function. The device further incorporates an

input hysteresis which prevents random oscillation of

the outputs in the absence of an input signal.

•

– LMK1D2108: 7-mm × 7-mm, 48-pin VQFN

(RGZ)

The device operates in a 1.8-V, 2.5-V, or 3.3-V

supply environment and is characterized from –40°C

to 105°C (ambient temperature).

2 Applications

•

Telecommunications and networking

Medical imaging

Test and measurement

Wireless infrastructure

Pro audio, video and signage

Device Information

PART NUMBER⁽¹⁾

LMK1D2106

PACKAGE

VQFN (40)

VQFN (48)

BODY SIZE (NOM)

6.00 mm × 6.00 mm

7.00 mm × 7.00 mm

LMK1D2108

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

491.52 MHz

AFE DEVICE

CLOCK

LMK1D21XX

LVDS Buffer

AFE

7.68 MHz

AFE SYSREF

CLOCK

Application Example

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK1D2106, LMK1D2108

SNAS829 – OCTOBER 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................9

7 Parameter Measurement Information..........................12

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................15

9 Application and Implementation..................................18

9.1 Application Information............................................. 18

9.2 Typical Application.................................................... 18

10 Power Supply Recommendations..............................22

11 Layout...........................................................................23

11.1 Layout Guidelines................................................... 23

11.2 Layout Examples.....................................................23

12 Device and Documentation Support..........................24

12.1 Documentation Support.......................................... 24

12.2 Receiving Notification of Documentation Updates..24

12.3 Support Resources................................................. 24

12.4 Trademarks.............................................................24

12.5 Electrostatic Discharge Caution..............................24

12.6 Glossary..................................................................24

13 Mechanical, Packaging, and Orderable

Information.................................................................... 24

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

October 2021

Initial Release

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5 Pin Configuration and Functions

ꢀ

DDA

DDB

ꢀ

DDA

DDB

OUT11_P

OUT11_N

OUT12_P

OUT12_N

OUT13_P

OUT13_N

OUT14_P

OUT14_N

OUT15_P

OUT15_N

OUT4_N

OUT4_P

OUT3_N

OUT3_P

OUT2_N

OUT2_P

OUT1_N

OUT1_P

OUT0_N

OUT0_P

OUT8_P

OUT8_N

OUT9_P

OUT9_N

OUT10_P

OUT10_N

OUT11_P

OUT11_N

OUT3_N

OUT3_P

OUT2_N

OUT2_P

OUT1_N

OUT1_P

OUT0_N

OUT0_P

DAP

ꢀ

DDA

DDB

ꢀ

DDA

DDB

Not to scale

Figure 5-1. LMK1D2106: RHA Package 40-Pin

VQFN Top View

Figure 5-2. LMK1D2108: RGZ Package 48-Pin

VQFN Top View

Table 5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

LMK1D2106

LMK1D2108

DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT

IN0_P, IN0_N

8, 9

9, 10

Primary: Differential input pair or single-ended input

Secondary: Differential input pair or single-ended input

IN1_P, IN1_N

2, 3

3, 4

Note that INP0, INN0 are used indistinguishably with IN0_P,

IN0_N.

BANK ENABLE

Output bank enable/disable with an internal 500-kΩ pullup and

320-kΩ pulldown. See Table 8-2.

AMPLITUDE SELECT

AMP_SEL

Output amplitude swing select with an internal 500-kΩ pullup and

320-kΩ pulldown. See Table 8-3.

BIAS VOLTAGE OUTPUT

V_{AC_REF0},V_{AC_REF1}

Bias voltage output for capacitive coupled inputs. If used, TI

recommends using a 0.1-µF capacitor to GND on this pin.

7, 4

8, 5

DIFFERENTIAL CLOCK OUTPUT

OUT0_P, OUT0_N

OUT1_P, OUT1_N

OUT2_P, OUT2_N

OUT3_P, OUT3_N

OUT4_P, OUT4_N

OUT5_P, OUT5_N

OUT6_P, OUT6_N

OUT7_P, OUT7_N

OUT8_P, OUT8_N

12, 13

14, 15

16, 17

18, 19

20, 21

22, 23

25, 26

27, 28

29, 30

31, 32

Differential LVDS output pair number 0

Differential LVDS output pair number 1

Differential LVDS output pair number 2

Differential LVDS output pair number 3

Differential LVDS output pair number 4

Differential LVDS output pair number 5

Differential LVDS output pair number 6

Differential LVDS output pair number 7

Differential LVDS output pair number 8

14, 15

16, 17

18, 19

22, 23

24, 25

26, 27

28, 29

32, 33

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Table 5-1. Pin Functions (continued)

TYPE⁽¹⁾

DESCRIPTION

NAME

OUT9_P, OUT9_N

OUT10_P, OUT10_N

OUT11_P, OUT11_N

OUT12_P, OUT12_N

OUT13_P, OUT13_N

OUT14_P, OUT14_N

OUT15_P, OUT15_N

SUPPLY VOLTAGE

V_DDA

LMK1D2106

LMK1D2108

34, 35

36, 37

38, 39

—

33, 34

35, 36

38, 39

40, 41

42, 43

44, 45

46, 47

Differential LVDS output pair number 9

Differential LVDS output pair number 10

Differential LVDS output pair number 11

Differential LVDS output pair number 12

Differential LVDS output pair number 13

Differential LVDS output pair number 14

Differential LVDS output pair number 15

—

6, 11, 20

5, 31, 40

7, 13, 24

6, 37, 48

Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 0

Device power supply (1.8 V, 2.5 V, or 3.3 V) for Bank 1

V_DDB

GROUND

GND

21, 30

DAP

1, 12

DAP

Ground

MISC

Die Attach Pad. Connect to the printed circuit board (PCB)

ground plane for heat dissipation.

DAP

(1) G = Ground, I = Input, O = Output, P = Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–20

MAX

3.6

UNIT

V_DD

V_IN

V_O

I_IN

Supply voltage

Input voltage

3.6

Output voltage

V_DD+ 0.3

Input current

°C

I_O

Continuous output current

Junction temperature

Storage temperature ⁽²⁾

–50

T_J

135

T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Device unpowered

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±3000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

2.375

1.71

NOM

3.3

MAX

3.465

2.625

1.89

UNIT

3.3-V supply

V_DD

Core supply voltage

Supply voltage ramp

2.5-V supply

1.8-V supply

2.5

1.8

Supply

Ramp

Requires monotonic ramp (10-90 % of

VDD)

0.1

T_A

T_J

Operating free-air temperature

Operating junction temperature

–40

105

135

°C

6.4 Thermal Information

LMK1D2106

RHA (VQFN)

40 PINS

30.3

LMK1D2108

RGZ (VQFN)

48 PINS

30.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

21.6

21.2

13.1

12.9

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

Ψ_JB

12.8

R_θJC(bot)

4.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

V_DD= 1.8 V ± 5 %, –40°C ≤ T_A≤ 105°C. Typical values are at V_DD= 1.8 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY CHARACTERISTICS

All outputs enabled and

IDD_STAT

IDD_100M

IDD_STAT

Core supply current, static (LMK1D2106) unterminated, f = 0 Hz, AMP_SEL

= Open (default)

All outputs enabled and

Core supply current, static (LMK1D2108) unterminated, f = 0 Hz, AMP_SEL

= Open (default)

All outputs enabled, RL = 100 Ω,

Core supply current (LMK1D2106)

Core supply current (LMK1D2108)

f =100 MHz, AMP_SEL = Open

(default)

113

134

140

160

All outputs enabled, RL = 100 Ω,

f =100 MHz, AMP_SEL = Open

(default)

All outputs enabled and

Core supply current, static (LMK1D2106) unterminated, f = 0 Hz, AMP_SEL

= 1

All outputs enabled and

Core supply current, static (LMK1D2108) unterminated, f = 0 Hz, AMP_SEL

= 1

All outputs enabled, RL = 100 Ω, f

Core supply current (LMK1D2106)

IDD_100M

130

165

185

=100 MHz, AMP_SEL = 1

All outputs enabled, RL = 100 Ω, f

Core supply current (LMK1D2108)

=100 MHz, AMP_SEL = 1

EN/AMP_SEL CONTROL INPUT CHARACTERISTICS (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

Vd_I3

Tri-state input

Open

0.4 × V_CC

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V_DD= 1.8 V ± 5 %, –40°C ≤ T_A≤ 105°C. Typical values are at V_DD= 1.8 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimun input voltage for a logical

"1" state in table 1

V_IH

V_IL

I_IH

Input high voltage

0.7 × V_CC

V_CC+ 0.3

Maximum input voltage for a

logical "0" state in table 1

Input low voltage

Input high current

Input low current

–0.3

–30

0.3 × V_CC

V_DDcan be 1.8V, 2.5V, or 3.3V

with V_IH= V_DD

V_DDcan be 1.8V, 2.5V, or 3.3V

with V_IH= V_DD

I_IL

R_pull-up

Input pullup resistor

500

320

kΩ

R_pull-down

Input pulldown resistor

SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

f_IN

Input frequency

Clock input

0.4

250

MHz

Assumes a square wave input

with two levels

V_{IN_S-E}

Single-ended Input Voltage Swing

3.465

Input Slew Rate (20% to 80% of the

amplitude)

dVIN/dt

0.05

–30

V/ns

I_IH

Input high current

Input low current

Input capacitance

V_DD= 3.465 V, V_IH= 3.465 V

V_DD= 3.465 V, V_IL= 0 V

at 25°C

I_IL

C_{IN_SE}

3.5

DIFFERENTIAL CLOCK INPUT (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

f_IN

Input frequency

Clock input

2.4

GHz

V_PP

V_ICM= 1 V (V_DD= 1.8 V)

V_ICM= 1.25 V (V_DD= 2.5 V/3.3 V)

0.3

Differential input voltage peak-to-peak {2

× (V_INP– V_INN)}

V_IN,DIFF(p-p)

V_IN,DIFF(P-P)> 0.4 V (V_DD= 1.8

V/2.5 V/3.3 V)

V_ICM

I_IH

Input common-mode voltage

Input high current

0.25

2.3

V_DD= 3.465 V, V_INP= 2.4 V, V_INN

= 1.2 V

V_DD= 3.465 V, V_INP= 0 V, V_INN

1.2 V

I_IL

Input low current

–30

C_{IN_SE}

Input capacitance (Single-ended)

at 25°C

3.5

LVDS DC OUTPUT CHARACTERISTICS

Differential output voltage magnitude |

V_OUTP- V_OUTN

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

|VOD|

ΔVOD

250

400

–15

–20

350

500

450

650

Differential output voltage magnitude |

V_OUTP- V_OUTN

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω, AMP_SEL = 1

Change in differential output voltage

magnitude

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Change in differential output voltage

magnitude

V_{IN,DIFF(P-P) =}0.3 V, R_LOAD= 100

Ω, AMP_SEL = 1

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω (V_DD= 1.8 V)

1.2

Steady-state, common-mode output

voltage

V_OC(SS)

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω (V_DD= 2.5 V/3.3 V)

1.1

0.8

0.9

–15

–20

1.375

1.05

1.15

V_{IN,DIFF(P-P) =}0.3 V, R_LOAD= 100 Ω

(

_VDD= 1.8 V), AMP_SEL = 1

V_{IN,DIFF(P-P) =}0.3 V, R_LOAD= 100 Ω

_VDD= 2.5 V/3.3 V), AMP_SEL = 1

Steady-state, common-mode output

voltage

V_OC(SS)

(

Change in steady-state, common-mode

output voltage

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Δ_VOC(SS)

Change in steady-state, common-mode

output voltage

V_{IN,DIFF(P-P) =}0.3 V, R_LOAD= 100

Ω, AMP_SEL = 1

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V_DD= 1.8 V ± 5 %, –40°C ≤ T_A≤ 105°C. Typical values are at V_DD= 1.8 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVDS AC OUTPUT CHARACTERISTICS

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω, f_OUT= 491.52 MHz

V_ring

V_OS

Output overshoot and undershoot

Output AC common-mode voltage

–0.1

0.1

V_OD

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

100

mV_pp

V_{IN,DIFF(P-P) =}0.3 V, R_LOAD= 100

Ω, AMP_SEL = 1

V_OS

Output AC common-mode voltage

150

mV_pp

I_OS

Short-circuit output current (differential)

V_OUTP= V_OUTN

–12

–24

Short-circuit output current (common-

mode)

I_OS(cm)

V_OUTP= V_OUTN= 0

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω ⁽¹⁾

t_PD

Propagation delay

Output skew

0.3

0.575

Skew between outputs with the

same load conditions (12 and 16

channels) ⁽²⁾

t_{SK, O}

Skew between the outputs within

the same bank (2106/2108) ⁽³⁾

t_{SK, b}

Output bank skew

17.5

Skew between outputs on

different parts subjected to the

same operating conditions with

the same input and output

t_{SK, PP}

Part-to-part skew

200

50% duty cycle input, crossing

t_{SK, P}

Pulse skew

point-to-crossing-point distortion

–20

(4)

f_IN= 156.25 MHz with 50% duty-

cycle, Input slew rate = 1.5V/ns,

Integration range = 12 kHz to 20

t_RJIT(ADD)

Random additive Jitter (rms)

60 fs, RMS

MHz, with output load R_LOAD

100 Ω

PN_1kHz

PN_10kHz

PN_100kHz

PN_1MHz

PN_floor

–143

–150

–157

–160

–164

Phase Noise for a carrier frequency of

156.25 MHz with 50% duty-cycle, Input

slew rate = 1.5V/ns with output load

R_LOAD= 100 Ω

Phase noise

dBc/Hz

F_IN0= 491.52 MHz, F_IN1

61.44 MHz; Measured between

neighboring outputs

–60

–70

Spurious suppression between dual

banks

SPUR

F_IN0= 491.52 MHz, F_IN1

15.36 MHz; Measured between

neighboring outputs

ODC

t_R/t_F

Output duty cycle

With 50% duty cycle input

Output rise and fall time

20% to 80% with R_LOAD= 100 Ω

300

20% to 80% with RLOAD = 100 Ω

(AMP_SEL= 1)

t_R/t_F

Output rise and fall time

Reference output voltage

300

V_{AC_REF}

VDD = 2.5 V, I_LOAD= 100 μA

0.9

1.25

1.375

POWER SUPPLY NOISE REJECTION (PSNR) V_DD= 2.5 V/ 3.3 V

10 kHz, 100 mVpp ripple injected

–70

–50

on V_DD

Power Supply Noise Rejection (f_carrier

156.25 MHz)

PSNR

dBc

1 MHz, 100 mVpp ripple injected

on V_DD

(1) Measured between single-ended/differential input crossing point to the differential output crossing point.

(2) For the dual bank devices, the inputs are phase aligned and have 50% duty cycle.

(3) Applies to the dual bank family.

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(4) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.

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6.6 Typical Characteristics

Figure 6-1 (LMK1D2106) and Figure 6-3 (LMK1D2108) capture the variation of the current consumption with input frequency

and supply voltage when AMP_SEL = 0. Figure 6-2 (LMK1D2106) and Figure 6-4 (LMK1D2108) show the current

consumption variation when AMP_SEL = 1. Figure 6-5 and Figure 6-6 portray the variation of the differential output voltage

(VOD) swept across frequency.

190

185

180

175

170

165

160

155

150

145

140

135

130

125

120

115

110

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Frequency (MHz)

Figure 6-1. LMK1D2106 Current Consumption vs. Frequency, AMP_SEL = 0

210

205

200

195

190

185

180

175

170

165

160

155

150

145

140

135

130

125

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Frequency (MHz)

Figure 6-2. LMK1D2106 Current Consumption vs. Frequency, AMP_SEL = 1

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6.6 Typical Characteristics

Figure 6-1 (LMK1D2106) and Figure 6-3 (LMK1D2108) capture the variation of the current consumption with input frequency

and supply voltage when AMP_SEL = 0. Figure 6-2 (LMK1D2106) and Figure 6-4 (LMK1D2108) show the current

consumption variation when AMP_SEL = 1. Figure 6-5 and Figure 6-6 portray the variation of the differential output voltage

(VOD) swept across frequency.

235

230

225

220

215

210

205

200

195

190

185

180

175

170

165

160

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

155

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

150

145

140

135

130

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Frequency (MHz)

Figure 6-3. LMK1D2108 Current Consumption vs. Frequency, AMP_SEL = 0

260

255

250

245

240

235

230

225

220

215

210

205

200

195

190

185

180

175

170

165

160

155

150

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Frequency (MHz)

Figure 6-4. LMK1D2108 Current Consumption vs. Frequency, AMP_SEL = 1

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6.6 Typical Characteristics

Figure 6-1 (LMK1D2106) and Figure 6-3 (LMK1D2108) capture the variation of the current consumption with input frequency

and supply voltage when AMP_SEL = 0. Figure 6-2 (LMK1D2106) and Figure 6-4 (LMK1D2108) show the current

consumption variation when AMP_SEL = 1. Figure 6-5 and Figure 6-6 portray the variation of the differential output voltage

(VOD) swept across frequency.

400

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

390

380

370

360

350

340

330

320

310

300

290

280

270

260

250

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

25 30

50 60 70 80 100

200

300

400 500 600 700800 1000

2000

Frequency (MHz)

Figure 6-5. LMK1D210x VOD vs. Frequency, AMP_SEL = 0

530

520

510

500

490

480

470

460

450

440

430

420

410

400

390

380

370

360

350

340

330

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

25 30

50 60 70 80 100

200

300

400 500 600 700800 1000

2000

Frequency (MHz)

Figure 6-6. LMK1D210x VOD vs. Frequency, AMP_SEL = 1

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7 Parameter Measurement Information

Oscilloscope

100 W

LVDS

Figure 7-1. LVDS Output DC Configuration During Device Test

Phase Noise/

Spectrum Analyzer

LMK1D21XX

Balun

100 Ω

Figure 7-2. LVDS Output AC Configuration During Device Test

Figure 7-3. DC-Coupled LVCMOS Input During Device Test

OUTNx

OUTPx

80%

(= 2 x V

)

20%

0 V

OUT,DIFF,PP

Figure 7-4. Output Voltage and Rise/Fall Time

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INNx

INPx

PLH0

PHL0

PHL1

OUTN0

OUTP0

PLH1

OUTN1

OUTP1

PLH2

PHL2

OUTN2

OUTP2

PLH7

PHL7

OUTN7

OUTP7

A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest t_PLHnor the difference

between the fastest and the slowest t_PHLn(n = 0, 1, 2, ..7)

B. Part-to-part skew is calculated as the greater of the following: the difference between the fastest and the slowest t_PLHnor the difference

between the fastest and the slowest t_PHLnacross multiple devices (n = 0, 1, 2, ..7)

Figure 7-5. Output Skew and Part-to-Part Skew

ring

OUTNx

0 V Differential

OUTPx

Figure 7-6. Output Overshoot and Undershoot

GND

Figure 7-7. Output AC Common Mode

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8 Detailed Description

8.1 Overview

The LMK1D210x LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing

and termination are required to ensure correct operation of the device and to maximize signal integrity.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the

receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI

recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage

different than the output common-mode voltage of the LMK1D210x, AC coupling must be used. If the LVDS

receiver has internal 100-Ω termination, external termination must be omitted.

8.2 Functional Block Diagram

VDD

1.8 to 3.3V

V_{AC_REF0}

Reference

Generator

V_{AC_REF1}

IN0

LVDS

OUT[0:N/2-1]

OUT[N/2:N-1]

IN1

VDD

R_pull-up

R_pull-down

VDD

R_pull-up

Output Swing

Control

AMP_SEL

R_pull-down

GND

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8.3 Feature Description

The LMK1D210x is a low additive jitter LVDS fan-out buffer that can generate up to 6 (LMK1D2106) or 8

(LMK1D2108) LVDS copies of a single input that is either LVDS, LVPECL, HCSL, CML, or LVCMOS on each of

its banks. The device has two banks, therefore this translates to a total of 12 (LMK1D2106) or 16 (LMK1D2108)

pairs of outputs. Refer to the Table 8-1 for output bank mapping. The reference clock frequencies can go up to 2

GHz.

Table 8-1. Output Bank

Bank

LMK1D2106

OUT0 to OUT5

OUT6 to OUT11

LMK1D2108

OUT0 to OUT7

OUT8 to OUT15

Apart from providing a very low additive jitter and low output skew, the LMK1D210x has an output bank enable/

disable control pin (EN) and an output amplitude control pin (AMP_SEL).

8.4 Device Functional Modes

The output banks of the LMK1D210x can be selected through the control pin (see Table 8-2). Unused inputs

can be left floating to reduce overall component cost. Both AC- and DC-coupling schemes can be used with the

LMK1D210x to provide greater system flexibility.

Table 8-2. Output Control

CLOCK OUTPUTS

All bank outputs disabled (static logic "0")

Bank 0 outputs enabled and Bank 1 outputs

disabled

OPEN

All bank outputs enabled

The output amplitude of the banks of the LMK1D210x can be selected through the amplitude selection pin

(see Table 8-3). The higher output amplitude mode (boosted swing LVDS mode) can be used in applications

which require higher amplitude either for better noise performance (higher slew rate) or if the receiver has swing

requirements which the standard LVDS swing cannot meet.

Table 8-3. Amplitude Selection

AMP_SEL

OUTPUT AMPLITUDE (mV)

Bank 0: boosted LVDS swing (500 mV)

Bank 1: standard LVDS swing (350 mV)

Bank 0: standard LVDS swing (350 mV)

Bank 1: standard LVDS swing (350 mV)

OPEN

Bank 0: boosted LVDS swing (500 mV)

Bank 1: boosted LVDS swing (500 mV)

8.4.1 LVDS Output Termination

TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,

although unterminated outputs are also okay but will result in slight degradation in performance (Output AC

common-mode V_OS) in the outputs being used.

The LMK1D210x can be connected to LVDS receiver inputs with DC and AC coupling as shown in Figure 8-1

and Figure 8-2, respectively.

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Z = 50 W

100 W

LVDS

LMK1D21XX

Z = 50 W

Figure 8-1. Output DC Termination

100 nF

Z = 50 W

100 W

LVDS

LMK1D21XX

Z = 50 W

100 nF

Figure 8-2. Output AC Termination (With the Receiver Internally Biased)

8.4.2 Input Termination

The LMK1D210x inputs can be interfaced with LVDS, LVPECL, HCSL, or LVCMOS drivers.

LVDS drivers can be connected to LMK1D210x inputs with DC and AC coupling as shown Figure 8-3 and Figure

8-4, respectively.

Z = 50 W

100 W

LVDS

LMK1D21XX

Z = 50 W

Figure 8-3. LVDS Clock Driver Connected to LMK1D210x Input (DC-Coupled)

100 nF

Z = 50 W

LVDS

LMK1D21XX

Z = 50 W

100 nF

50 W

AC_REF

Figure 8-4. LVDS Clock Driver Connected to LMK1D210x Input (AC-Coupled)

Figure 8-5 shows how to connect LVPECL inputs to the LMK1D210x. The series resistors are required to reduce

the LVPECL signal swing if the signal swing is >1.6 V_PP

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75 W

100 nF

Z = 50 W

LMK1D21XX

LVPECL

Z = 50 W

100 nF

50 W

75 W

150 W

50 W

AC_REF

Figure 8-5. LVPECL Clock Driver Connected to LMK1D210x Input

Figure 8-6 shows how to couple a LVCMOS clock input to the LMK1D210x directly.

R_S

LVCMOS

Z = 50

(1.8/2.5/3.3 V)

LMK1D21XX

V_TH= 0.5*(V_IH+ V_IL)

Figure 8-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D210x Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩ resistors.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LMK1D210x is a low additive jitter universal to LVDS fan-out buffer with dual inputs which fan-out to

dual outputs banks. Each input can fan-out to six outputs in case of LMK1D2106 and eight outputs in case

of LMK1D2108. The small package size, 1.8-V power supply operation, low output skew, and low additive

jitter is desgined for applications that require high-performance clock distribution as well as for low-power and

space-constraint applications.

9.2 Typical Application

ADC CLOCK

JESD204B/C AFE

IN0

ADC CLOCK

100

Digital control

LMK1D21XX

LVDS Buffer

SYSREF CLOCK

100

IN1

SYSREF CLOCK

Figure 9-1. Fan-Out Buffer for ADC Device Clock and SYSREF Distribution

9.2.1 Design Requirements

The LMK1D210x shown in Figure 9-1 is configured to fan-out an ADC clock on the first output bank and

SYSREF clock on the second output bank for a system using the JESD204B/C ADC. The low output-to-output

skew, very low additive jitter and superior spurious suppression between dual banks makes the LMK1D210x

a simple, robust and low-cost solution for distributing various clocks to JESD204B/C AFE systems. The

configuration example can drive up to 4 ADC clocks and 4 SYSREF clocks for a JESD204B/C receiver with

the following properties:

•

The ADC clock receiver module is typically AC-coupled with an LVDS driver such as the LMK1D210x due

to differences in common-mode voltage between the driver and receiver. Depending on the receiver, there

maybe an option for internal 100-Ω differential termination in which case an external termination would not be

required for the LMK1D210x.

•

The SYSREF clock receiver module is typically DC-coupled provided the common-mode voltage of the

LMK1D210x outputs match with the receiver. An external termination may not be needed in case of an

internal termination in the receiver.

Unused outputs of the LMK1D210x device are terminated differentially with a 100-Ω resistor for optimum

performance.

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9.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

TI recommends unused outputs to be terminated differentially with a 100-Ω resistor for optimum performance,

although unterminated outputs are also okay but will result in slight degradation in performance (Output AC

common-mode V_OS) in the outputs being used.

In this application example, the ADC clock and SYSREF clocks require different output interfacing schemes.

Power-supply filtering and bypassing is critical for low-noise applications.

In case of common-mode mismatch between the output voltage of the LMK1D210x and the receiver, one can

use AC coupling to get around this. It might not be possible in certain applications, however, to AC-couple

the LMK1D210x outputs to the receiver due to the settling time associated with this AC-coupling network (High-

pass filter), which can result in non-deterministic behavior during the initial transients. For such applications,

DC-coupling the outputs is necessary and thus requires a scheme which can overcome the inherent mismatch

between the common-mode voltage of the driver and receiver.

The application report Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between a

LVDS driver and sub-LVDS receiver. The same concept can be applied to interface the LMK1D210x outputs to a

receiver which has a lower common-mode voltage.

1.8 V

OUTX_P

IN_P

LMK1D21xx

SYSREF AFE

OUTX_N

IN_N

1.8 V

Figure 9-2. Schematic for DC-Coupling LMK1D21xx With Lower Common-Mode Receiver

Figure 9-2 shows the resistor divider network for stepping down the common-mode voltage as explained in

the above application report. The resistors R1, R2 and R3 are chosen according to the input common-mode

voltage requirements of the receiver. As highlighted before, make sure that the reduced swing is able to meet

the requirements of the receiver. Higher swing mode (boosted LVDS swing mode) can be selected using the

AMP_SEL pin highlighted in Table 8-3 to compensate for the reduced swing as the result of the resistor voltage

divider.

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9.2.3 Application Curves

The low additive noise of the LMK1D2108. The low noise 156.25-MHz source with 25-fs RMS jitter, shown in

Figure 9-3, drives the LMK1D2108, resulting in 46.9-fs RMS when integrated from 12 kHz to 20 MHz (Figure

9-4). The resultant additive jitter is a low 39.7-fs RMS for this configuration. Note that this result applies to the

LMK1D2106 device as well.

Note: Reference signal is a low-noise Rhode and Schwarz SMA100B

Figure 9-3. LMK1D2108 Reference Phase Noise, 156.25 MHz, 25-fs RMS (12 kHz to 20 MHz)

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Figure 9-4. LMK1D2108 Output Phase Noise, 156.25 MHz, 46.9-fs RMS (12 kHz to 20 MHz)

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10 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter or phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against

the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the

device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must

be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends

adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.

TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip

power supply that isolates the high-frequency switching noises generated by the clock driver. These ferrite beads

prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC

resistance because it is imperative to provide adequate isolation between the board supply and the chip supply,

as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper

operation.

Figure 10-1 shows this recommended power-supply decoupling method.

Figure 10-1. Power Supply Decoupling

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11 Layout

11.1 Layout Guidelines

For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to

a ground plane must be incorporated into the PCB within the footprint of the package. The thermal pad must

be soldered down to ensure adequate heat conduction to of the package. Figure 11-1 and Figure 11-2 show the

recommended top layer and via patterns for the 40-pin package (LMK1D2106).

11.2 Layout Examples

Figure 11-1. PCB layout example for LMK1D2106, Top Layer

Figure 11-2. PCB Layout Example for LMK1D2106, GND layer

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide

Texas Instruments, Power Consumption of LVPECL and LVDS Analog design journal

Texas Instruments, Using Thermal Calculation Tools for Analog Components application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMK1D2106RHAR

LMK1D2106RHAT

LMK1D2108RGZR

LMK1D2108RGZT

ACTIVE

VQFN

RHA

2500 RoHS & Green

250 RoHS & Green

2500 RoHS & Green

250 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 105

LMK1D

2106

ACTIVE

RHA

NIPDAU

LMK1D

2106

RGZ

LMK1D

2108

RGZ

LMK1D

2108

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Oct-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMK1D2106RHAR

LMK1D2106RHAT

LMK1D2108RGZR

LMK1D2108RGZT

VQFN

RHA

RGZ

2500

250

330.0

180.0

330.0

180.0

16.4

6.3

7.3

6.3

7.3

1.1

12.0

16.0

2500

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

31-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMK1D2106RHAR

LMK1D2106RHAT

LMK1D2108RGZR

LMK1D2108RGZT

VQFN

RHA

RGZ

2500

250

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

35.0

2500

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RHA 40

6 x 6, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225870/A

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PACKAGE OUTLINE

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

PIN 1 INDEX AREA

6.1

5.9

1 MAX

SEATING PLANE

0.08

0.05

0.00

2X 4.5

4.15 0.1

(0.2) TYP

36X 0.5

EXPOSED

THERMAL PAD

4.5

SYMM

0.27

40X

0.17

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

0.5

0.3

40X

4219052/A 06/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.15)

SYMM

40X (0.6)

40X (0.22)

(0.25) TYP

36X (0.5)

SYMM

(5.8)

(0.685)

TYP

(1.14)

TYP

(

0.2) TYP

VIA

(R0.05) TYP

(0.685)

TYP

(1.14)

TYP

(5.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MIN

ALL SIDES

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219052/A 06/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RHA0040B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

9X ( 1.17)

(1.37) TYP

40X (0.6)

40X (0.22)

(1.37)

TYP

(0.25) TYP

SYMM

(5.8)

36X (0.5)

(R0.05) TYP

METAL

TYP

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 41:

72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4219052/A 06/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

PIN 1 INDEX AREA

7.15

6.85

1 MAX

SEATING PLANE

0.05

0.00

0.08 C

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

44X 0.5

SYMM

5.5

0.30

0.18

48X

0.1

0.05

C B A

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

48X (0.6)

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

48X (0.6)

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

(R0.05) TYP

(6.8)

METAL

TYP

(

1.17)

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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LMK1D2108RGZT [TI]

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