LMK61E2-156M25SIAT [TI]
156.25MHz、±50ppm、LVPECL 超低抖动标准差动振荡器 | SIA | 6 | -40 to 85;
| 型号： | LMK61E2-156M25SIAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 156.25MHz、±50ppm、LVPECL 超低抖动标准差动振荡器 | SIA | 6 | -40 to 85 振荡器 |
| 文件： | 总22页 (文件大小：733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
LMK61XX 高性能超低抖动振荡器
1 特性
3 说明
1
•
超低噪声、高性能
LMK61XX 是一款超低抖动振荡器，可生成常用的基准
时钟。该器件在出厂前进行了预编程，支持任何基准时
钟频率；支持的输出格式包括 LVPECL（最高
1GHz）、LVDS（最高 900MHz）和 HCSL（最高
400MHz）。内部电源调节功能提供出色的电源纹波抑
制 (PSRR)，降低了供电网络的成本和复杂性。该器件
由单个 3.3V ± 5% 电源供电。
–
–
抖动：Fout > 100MHz 时的典型值为 90fs RMS
PSRR：–70dBc，强大的电源抗噪性
•
支持的输出格式
–
–
–
LVPECL 高达 1 GHz
LVDS 高达 900 MHz
HSTL 高达 400 MHz
•
总频率容差：±50ppm(LMK61X2) 和 ± 25ppm
(LMK61X0)
器件信息(1)
输出频率 (MHz) 及格
式
总频率稳定性
(PPM)
器件型号
封装
•
•
•
3.3V 工作电压
LMK61A2-
100M00
工业温度范围（-40ºC 至 +85ºC）
100 LVDS
125 LVDS
± 50
± 50
± 50
± 50
± 50
± 25
± 25
± 25
± 50
± 50
± 50
± 50
± 50
7mm × 5mm 6 引脚封装，与行业标准 7050 XO 封
装引脚兼容
LMK61A2-
125M00
LMK61A2-
156M25
156.25 LVDS
312.5 LVDS
2 应用
LMK61A2-
312M50
•
晶体振荡器、SAW 振荡器或芯片振荡器的高性能
替代产品
LMK61A2-
644M53
644.53125 LVDS
50 LVPECL
•
开关、路由器、网卡、基带装置 (BBU)、服务器、
存储/SAN
LMK61E0-
050M00
6 引脚 QFM
(7.0mm x
5.0mm)
•
•
•
测试和测量
LMK61E0-
155M52
155.52 LVPECL
156.25 LVPECL
100 LVPECL
125 LVPECL
156.25 LVPECL
312.5 LVPECL
100 HCSL
医疗成像
LMK61E0-
156M25
FPGA，处理器连接
LMK61E2-
100M00
LMK61E2-
125M00
LMK61E2-
156M25
LMK61E2-
312M50
LMK61I2-
100M00
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
引脚分配
6
5
OE
NC
1
2
3
6
5
4
VDD
4
OUTN
OUTP
GND
1
2
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNAS676
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
目录
6.13 PLL Clock Output Jitter Characteristics .................. 7
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics - Power Supply ................. 5
6.6 LVPECL Output Characteristics................................ 5
6.7 LVDS Output Characteristics .................................... 5
6.8 HCSL Output Characteristics.................................... 6
6.9 OE Input Characteristics........................................... 6
6.10 Frequency Tolerance Characteristics ..................... 6
6.11 Power-On/Reset Characteristics (VDD).................. 6
6.12 PSRR Characteristics ............................................. 7
6.14 Typical 156.25-MHz Output Phase Noise
Characteristics ........................................................... 7
6.15 Additional Reliability and Qualification.................... 7
6.16 Typical Characteristics............................................ 8
Parameter Measurement Information ................ 10
7.1 Device Output Configurations ................................. 10
Power Supply Recommendations...................... 12
Layout ................................................................... 12
9.1 Layout Guidelines ................................................... 12
7
8
9
10 器件和文档支持 ..................................................... 14
10.1 相关链接................................................................ 14
10.2 接收文档更新通知 ................................................. 14
10.3 社区资源................................................................ 14
10.4 商标....................................................................... 14
10.5 静电放电警告......................................................... 14
10.6 Glossary................................................................ 14
11 机械、封装和可订购信息....................................... 15
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (September 2017) to Revision D
Page
•
•
添加了 LMK61A2-644M ......................................................................................................................................................... 1
添加了 LMK61E0-156M.......................................................................................................................................................... 1
Changes from Revision B (March 2017) to Revision C
Page
•
添加了 LMK61E0-155M.......................................................................................................................................................... 1
Changes from Revision A (November 2015) to Revision B
Page
•
•
•
•
将数据表文本更新为最新的文档和转换标准 ........................................................................................................................... 1
添加了 LMK61E0-050M.......................................................................................................................................................... 1
更新了主要图形 ...................................................................................................................................................................... 1
添加了接收文档更新通知 部分.............................................................................................................................................. 14
Changes from Original (October 2015) to Revision A
Page
•
将“产品预览”更改成了“生产数据数据表” ................................................................................................................................. 1
2
Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com.cn
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
5 Pin Configuration and Functions
SIA Package
6-Pin QFM
Top View
OE
NC
1
6
5
4
VDD
2
3
OUTN
OUTP
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
POWER
GND
NO.
3
6
Ground
Analog
Device Ground.
VDD
3.3 V Power Supply.
OUTPUT BLOCK
OUTP,
OUTN
4, 5
Universal
Differential Output Pair (LVPECL, LVDS or HCSL).
No Connect.
DIGITAL CONTROL / INTERFACES
NC
2
N/A
Output Enable (internal pullup). When set to low, output pair is disabled and set at high
impedance.
OE
1
LVCMOS
Copyright © 2015–2017, Texas Instruments Incorporated
3
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.6
UNIT
V
VDD
VIN
Device supply voltage
–0.3
–0.3
–0.3
Output voltage for logic inputs
Output voltage for clock outputs
Junction temperature
VDD + 0.3
VDD + 0.3
150
V
VOUT
TJ
V
°C
°C
TSTG
Storage temperature
–40
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
–40
NOM
3.3
MAX
3.465
85
UNIT
V
VDD
TA
Device supply voltage
Ambient temperature
25
°C
LMK61X2
LMK61X0
125
°C
TJ
Junction temperature
115
°C
tRAMP
VDD power-up ramp time
0.1
100
ms
6.4 Thermal Information
(2) (3) (4)
LMK61XX
SIA (QFM)
6 PINS
THERMAL METRIC(1)
UNIT
Airflow (LFM) 0
Airflow (LFM) 200
Airflow (LFM) 400
RθJA
Junction-to-ambient thermal resistance
55.2
34.6
37.7
11.3
37.7
n/a
46.4
n/a
43.7
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
n/a
n/a
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.6
41.5
n/a
22.5
40.1
n/a
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal resistance is calculated on a 4 layer JEDEC board.
(3) Connected to GND with 3 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations
section for more information on ensuring good system reliability and quality.
4
Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com.cn
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
6.5 Electrical Characteristics - Power Supply(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
162
152
155
136
MAX
208
196
196
UNIT
IDD
Device current consumption
LVPECL(2)
LVDS
mA
HCSL
IDD-PD
Device current consumption
when output is disabled
OE = GND
mA
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation.
6.6 LVPECL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
Output frequency(2)
TEST CONDITIONS
MIN
10
TYP
MAX
1000
1200
UNIT
MHz
mV
fOUT
VOD
Output voltage swing
700
800
2 ×
(2)
(VOH – VOL
)
VOUT, DIFF, PP Differential output peak-to-
peak swing
V
V
|VOD
|
VOS
Output common-mode voltage
VDD –
1.55
tR / tF
PN-Floor
ODC
Output rise/fall time (20% to
80%)(3)
120
200
ps
Output phase noise floor
(fOFFSET > 10 MHz)
Output duty cycle(3)
156.25 MHz
–165
dBc/Hz
45%
55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(3) Ensured by characterization.
6.7 LVDS Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
Output frequency(1)
TEST CONDITIONS
MIN
10
TYP
MAX
900
UNIT
MHz
mV
fOUT
VOD
Output voltage swing
300
390
2 ×
480
(1)
(VOH – VOL
)
VOUT, DIFF, PP Differential output peak-to-
peak swing
V
|VOD
|
VOS
Output common-mode voltage
1.2
V
tR / tF
Output rise/fall time (20% to
80%)(2)
150
250
ps
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
Output duty cycle(2)
156.25 MHz
–162
125
dBc/Hz
Ohm
ODC
ROUT
45%
55%
Differential output impedance
(1) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(2) Ensured by characterization.
Copyright © 2015–2017, Texas Instruments Incorporated
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LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
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6.8 HCSL Output Characteristics(1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX
400
850
100
475
140
2
UNIT
MHz
mV
fOUT
Output frequency
Output high voltage
Output low voltage
VOH
600
–100
250
0
VOL
mV
VCROSS
Absolute crossing voltage(2)(3)
mV
(2)(3)
VCROSS-DELTA Variation of VCROSS
mV
dV/dt
Slew rate(4)
0.8
V/ns
dBc/Hz
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
100 MHz
–164
ODC
Output duty cycle(4)
45%
55%
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential
zero crossing.
(3) Ensured by design.
(4) Ensured by characterization.
6.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IIH
Input high voltage
Input low voltage
Input high current
Input low current
Input capacitance
1.4
0.6
40
40
V
VIH = VDD
VIL = GND
–40
–40
uA
uA
pF
IIL
CIN
2
6.10 Frequency Tolerance Characteristics(1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fT
Total frequency tolerance
LMK61X2: All output formats, frequency
bands and device junction temperature up to
125°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (10 years)
–50
50
ppm
LMK61X0: All output formats, frequency
bands and device junction temperature up to
115°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (5 years at 40°C)
–25
25
ppm
(1) Ensured by characterization.
6.11 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.95
0.1
UNIT
V
VTHRESH
VDROOP
tSTARTUP
Threshold voltage(1)
Allowable voltage droop(2)
2.72
V
(1)
Start-up time
Time elapsed from VDD at 3.135 V to output
enabled
10
ms
tOE-EN
tOE-DIS
Output enable time(2)
Output disable time(2)
Time elapsed from OE at VIH to output enabled
Time elapsed from OE at VIL to output disabled
50
50
us
us
(1) Ensured by characterization.
(2) Ensured by design.
6
Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
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ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
6.12 PSRR Characteristics(1)
VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC
PARAMETER
TEST CONDITIONS
Sine wave at 50 kHz
MIN
TYP
–70
–70
–70
–70
MAX
UNIT
PSRR
Spurs induced by 50-mV
power supply ripple(2)(3) at
156.25-MHz output, all
output types
dBc
Sine wave at 100 kHz
Sine wave at 500 kHz
Sine wave at 1 MHz
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
(3) DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
6.13 PLL Clock Output Jitter Characteristics(1)(2)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RJ
RJ
RJ
RMS phase jitter(3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
RMS phase jitter(3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
RMS phase jitter(3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
fOUT < 100 MHz, all output types
200
100
150
300
200
300
fs RMS
fOUT ≥ 100 MHz (except 155.52 MHz and
fs RMS
fs RMS
644.53125 MHz), all output types
fOUT = 155.52 MHz or 644.53125 MHz, all
output types
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
(3) Ensured by characterization.
6.14 Typical 156.25-MHz Output Phase Noise Characteristics(1)(2)
VDD = 3.3 V, TA = 25°C, Output Type = LVPECL/LVDS/HCSL
PARAMETER
OUTPUT TYPE
LVDS
–143
UNITS
LVPECL
–143
–143
–144
–145
–150
–154
–165
–165
HCSL
–143
–143
–144
–145
–150
–154
–164
–164
phn10k
Phn20k
phn100k
Phn200k
phn1M
Phase noise at 10-kHz offset
Phase noise at 20-kHz offset
Phase noise at 100-kHz offset
Phase noise at 200-kHz offset
Phase noise at 1-MHz offset
Phase noise at 2-MHz offset
Phase noise at 10-MHz offset
Phase noise at 20-MHz offset
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–143
–144
–145
–150
phn2M
–154
phn10M
phn20M
–162
–162
(1) Refer to Parameter Measurement Information for relevant test conditions.
(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
6.15 Additional Reliability and Qualification
PARAMETER
CONDITION / TEST METHOD
MIL-STD-202, Method 213
MIL-STD-202, Method 204
J-STD-020, MSL3
Mechanical Shock
Mechanical Vibration
Moisture Sensitivity Level
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LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
6.16 Typical Characteristics
Figure 1. Phase Noise of 156.25-MHz LVPECL Differential
Output
Figure 2. Phase Noise of 156.25-MHz LVDS Differential
Output
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
78.125
109.375
140.625
171.875
203.125
234.375
Frequency (MHz)
D007
Figure 4. 156.25 ± 78.125-MHz LVPECL Differential Output
Spectrum
Figure 3. Phase Noise of 156.25-MHz HCSL Differential
Output
10
0
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
78.125
109.375
140.625
171.875
203.125
234.375
78.125
109.375
140.625
171.875
203.125
234.375
Frequency (MHz)
Frequency (MHz)
D008
D009
Figure 5. 156.25 ± 78.125-MHz LVDS Differential Output
Spectrum
Figure 6. 156.25 ± 78.125-MHz HCSL Differential Output
Spectrum
8
Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
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LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
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ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
Typical Characteristics (continued)
1.8
0.9
0.8
0.7
0.6
0.5
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0
200
400
600
800
1000
0
200
400
600
800
1000
Output Frequency (MHz)
Output Frequency (MHz)
D013
D014
Figure 7. LVPECL Differential Output Swing vs Frequency
Figure 8. LVDS Differential Output Swing vs Frequency
1.5
1.48
1.46
1.44
1.42
1.4
0
100
200
300
400
500
Output Frequency (MHz)
D015
Figure 9. HCSL Differential Output Swing vs Frequency
Copyright © 2015–2017, Texas Instruments Incorporated
9
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
7 Parameter Measurement Information
7.1 Device Output Configurations
High impedance differential probe
LVPECL
LMK61XX
Oscilloscope
150 ꢀ
150 ꢀ
Figure 10. LVPECL Output DC Configuration During Device Test
High impedance differential probe
LMK61XX
LVDS
Oscilloscope
Figure 11. LVDS Output DC Configuration During Device Test
High impedance differential probe
HCSL
LMK61XX
Oscilloscope
50 ꢀ
50 ꢀ
Figure 12. HCSL Output DC Configuration During Device Test
Phase Noise/
Balun/
Buffer
Spectrum
Analyzer
LMK61XX
LVPECL
150 ꢀ
150 ꢀ
Figure 13. LVPECL Output AC Configuration During Device Test
Phase Noise/
Balun/
Buffer
LMK61XX
Spectrum
Analyzer
LVDS
Figure 14. LVDS Output AC Configuration During Device Test
10
Copyright © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com.cn
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
Device Output Configurations (continued)
Phase Noise/
Spectrum
Analyzer
Balun/
Buffer
LMK61XX
HCSL
50 ꢀ
50 ꢀ
Figure 15. HCSL Output AC Configuration During Device Test
Sine wave
Modulator
Power Supply
Phase Noise/
LMK61XX
Spectrum
Analyzer
Balun
150 ꢀ (LVPECL)
Open (LVDS)
50 ꢀ (HCSL)
150 ꢀ (LVPECL)
Open (LVDS)
50 ꢀ (HCSL)
Figure 16. PSRR Test Setup
OUT_P
OUT_N
VOD
80%
VOUT,DIFF,PP = 2 x VOD
0 V
20%
tR
tF
Figure 17. Differential Output Voltage and Rise/Fall Time
Copyright © 2015–2017, Texas Instruments Incorporated
11
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
8 Power Supply Recommendations
For best electrical performance of LMK61XX, TI recommends using a combination of 10 µF, 1 µF and 0.1 µF on
its power supply bypass network. TI also recommends using component side mounting of the power supply
bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the
connections between the bypass capacitors and the power supply on the device as short as possible. Ground the
other side of the capacitor using a low impedance connection to the ground plane. Figure 18 shows the layout
recommendation for power supply decoupling of LMK61XX.
9 Layout
9.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply
bypassing when using LMK61XX to ensure good thermal / electrical performance and overall signal integrity of
entire system.
9.1.1 Ensuring Thermal Reliability
The LMK61XX is a high performance device. Therefore, pay careful attention to device configuration and printed-
circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the
ground plane of the PCB through three vias or more, as shown in Figure 18, to maximize thermal dissipation out
of the package.
Equation 1 describes the relationship between the PCB temperature around the LMK61XX and its junction
temperature.
TB = TJ – ΨJB × P
where
•
•
•
•
TB: PCB temperature around the LMK61XX
TJ: Junction temperature of LMK61XX
ΨJB: Junction-to-board thermal resistance parameter of LMK61XX (37.7°C/W without airflow)
P: On-chip power dissipation of LMK61XX
(1)
To ensure that the maximum junction temperature of LMK61X2 is below 125°C, the maximum PCB temperature
without airflow should be at 99°C or below (89°C or below for LMK61X0) when the device is optimized for best
performance resulting in maximum on-chip power dissipation of 0.68 W.
9.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK61XX, TI recommends routing vias
into decoupling capacitors and then into the LMK61XX. TI also recommends increasing the via count and width
of the traces wherever possible. These steps ensure lowest impedance and shortest path for high frequency
current flow. Figure 18 shows the layout recommendation for LMK61XX.
12
版权 © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com.cn
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
Layout Guidelines (接下页)
Figure 18. LMK61XX Layout Recommendation for Power Supply and Ground
9.1.3 Recommended Solder Reflow Profile
TI recommends following the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferrable for the LMK61XX to
be processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
版权 © 2015–2017, Texas Instruments Incorporated
13
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
10 器件和文档支持
10.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的快速访问
链接。
表 1. 相关链接
器件
产品文件夹
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样片与购买
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技术文档
工具和软件
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支持和社区
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LMK61E0-050M
LMK61E0-155M
LMK61E0-156M
LMK61E2-100M
LMK61E2-125M
LMK61E2-156M
LMK61E2-312M
LMK61A2-100M
LMK61A2-125M
LMK61A2-156M
LMK61A2-312M
LMK61A2-644M
LMK61I2-100M
请单击此处
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请单击此处
10.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
10.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14
版权 © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com.cn
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2015–2017, Texas Instruments Incorporated
15
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
PACKAGE OUTLINE
SIA0006A
QFM - 1.15 mm max height
S
C
A
L
E
2
.
2
0
0
QUAD FLAT MODULE
5.1
4.9
B
A
PIN 1 INDEX
AREA
7.1
6.9
C
1.15 MAX
0.1 C
3X 3.7
6X (0.15)
3
4
4X (0.26)
SYMM
6X
2X
5.08
1.43
1.37
4X
2.54
0.1
0.05
C A
B
C
6
1
1.03
0.97
SYMM
6X
4222361/B 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
16
版权 © 2015–2017, Texas Instruments Incorporated
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com.cn
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
EXAMPLE BOARD LAYOUT
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
6X (1)
1
6
6X (1.4)
SYMM
4X (2.54)
4
3
(R0.05) TYP
(3.7)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:8X
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222361/B 10/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
版权 © 2015–2017, Texas Instruments Incorporated
17
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
ZHCSG14D –OCTOBER 2015–REVISED OCTOBER 2017
www.ti.com.cn
EXAMPLE STENCIL DESIGN
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
12X (1)
1
6
12X (0.6)
METAL TYP
(R0.05)
SYMM
4X (2.54)
4
3
(0.4) TYP
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
ALL PADS: 86%
SCALE:10X
4222361/B 10/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
18
版权 © 2015–2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK61A2-100M00SIAR
LMK61A2-100M00SIAT
LMK61A2-125M00SIAR
LMK61A2-125M00SIAT
LMK61A2-156M25SIAR
LMK61A2-156M25SIAT
LMK61A2-312M50SIAR
LMK61A2-312M50SIAT
LMK61A2-644M53SIAR
LMK61A2-644M53SIAT
LMK61E0-050M00SIAR
LMK61E0-050M00SIAT
LMK61E0-155M52SIAR
LMK61E0-155M52SIAT
LMK61E0-156M25SIAR
LMK61E0-156M25SIAT
LMK61E2-100M00SIAR
ACTIVE
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LMK61A2
100M00
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
LMK61A2
100M00
LMK61A2
125M00
LMK61A2
125M00
LMK61A2
156M25
LMK61A2
156M25
LMK61A2
312M50
LMK61A2
312M50
LMK61A2
644M53
LMK61A2
644M53
LMK61E0
050M00
LMK61E0
050M00
LMK61E0
155M52
LMK61E0
155M52
LMK61E0
156M25
LMK61E0
156M25
LMK61E2
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
100M00
LMK61E2-100M00SIAT
LMK61E2-125M00SIAR
LMK61E2-125M00SIAT
LMK61E2-156M25SIAR
LMK61E2-156M25SIAT
LMK61E2-312M50SIAR
LMK61E2-312M50SIAT
LMK61I2-100M00SIAR
LMK61I2-100M00SIAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
QFM
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
SIA
6
6
6
6
6
6
6
6
6
250
RoHS & Green
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
LMK61E2
100M00
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
LMK61E2
125M00
LMK61E2
125M00
LMK61E2
156M25
LMK61E2
156M25
LMK61E2
312M50
LMK61E2
312M50
LMK61I2
100M00
LMK61I2
100M00
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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