LMK61E2 [TI]

156.250MHz、±50ppm、超低抖动、集成式 EEPROM、完全可编程振荡器;


型号：	LMK61E2
厂家：	TEXAS INSTRUMENTS
描述：	156.250MHz、±50ppm、超低抖动、集成式 EEPROM、完全可编程振荡器可编程只读存储器电动程控只读存储器电可擦编程只读存储器振荡器
文件：	总55页 (文件大小：1147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

具有内部 EEPROM 的 LMK61E2 超低抖动可编程振荡器

1 特性

3 说明

•

超低噪声、高性能

LMK61E2 是一款超低抖动 PLLatinum™可编程振荡

器，具有分数 N 频率合成器（带可生成常用基准时钟

的集成 VCO）。输出可配置为 LVPECL、LVDS 或

HCSL。

–

抖动：f_OUT> 100MHz 时的典型值为 90fs RMS

PSRR：–70dBc，强大的电源抗噪性

•

灵活的输出格式；用户可选择

–

低电压正射极耦合逻辑 (LVPECL) 高达 1GHz

低压差分信令 (LVDS) 高达 900MHz

该器件支持从片上 EEPROM 自启动，该片上

EEPROM 出厂时编程为生成 156.25MHz 的 LVPECL

输出。器件寄存器和 EEPROM 设置可通过 I²C 串行接

口在系统内实现完全编程。内部电源调节功能提供出色

的电源纹波抑制 (PSRR)，降低了供电网络的成本和复

杂性。该器件由单个 3.3V ± 5% 电源供电。

高速收发器逻辑 (HSTL) 高达 400MHz

•

总频率容差：±50ppm

系统级特性

–

频率裕量：精调和粗调

内部 EEPROM：用户可配置默认设置

该器件支持通过 I²C 串行接口进行频率精调和粗调，从

而支持系统设计验证测试 (DVT)，例如标准合规性和系

统时序裕量测试。

•

其他特性

–

器件控制：I²C

3.3V 工作电压

器件信息⁽¹⁾

工业温度范围（-40ºC 至 +85ºC）

默认输出频率 (MHz) 和封装和封装尺寸（标

7mm × 5mm 8 引脚封装

使用 LMK61E2 并借助 WEBENCH^®电源设计

器创建定制设计方案

器件型号

格式

称值）

LMK61E2

156.25 LVPECL

156.25 LVDS

125 LVDS

8 引脚 QFM

(SIA)，7.00mm x

5.00mm

LMK61E2BAA

LMK61E2BBA

2 应用

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

•

晶体振荡器、SAW 振荡器或芯片振荡器的高性能

替代产品

•

开关、路由器、网卡、基带装置 (BBU)、服务器、

存储/SAN

•

测试和测量

医疗成像

现场可编程门阵列 (FPGA)，处理器连接

引脚分布和简化框图

Power

Conditioning

SDA

ADD

GND

VDD

Output

Divider

Output

Buffer

Integrated

Oscillator

PLL

OUTN

OUTP

Interface

I²C/EEPROM

SCL

LMK61E2

Ultra-high performance oscillator

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNAS674

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

6.20 Typical Characteristics............................................ 9

Parameter Measurement Information ................ 12

7.1 Device Output Configurations ................................. 12

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 18

8.5 Programming........................................................... 19

8.6 EEPROM Map......................................................... 23

8.7 Register Map........................................................... 25

Application and Implementation ........................ 37

9.1 Application Information............................................ 37

9.2 Typical Applications ................................................ 37

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings ............................................................ 3

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics - Power Supply ................. 4

6.6 LVPECL Output Characteristics................................ 5

6.7 LVDS Output Characteristics .................................... 5

6.8 HCSL Output Characteristics.................................... 5

6.9 OE Input Characteristics........................................... 6

6.10 ADD Input Characteristics....................................... 6

6.11 Frequency Tolerance Characteristics ..................... 6

6.12 Power-On/Reset Characteristics (VDD).................. 6

10 Power Supply Recommendations ..................... 43

11 Layout................................................................... 44

11.1 Layout Guidelines ................................................. 44

11.2 Layout Example .................................................... 45

12 器件和文档支持 ..................................................... 46

12.1 器件支持................................................................ 46

12.2 文档支持................................................................ 46

12.3 接收文档更新通知 ................................................. 46

12.4 社区资源................................................................ 46

12.5 商标....................................................................... 46

12.6 静电放电警告......................................................... 47

12.7 Glossary................................................................ 47

13 机械、封装和可订购信息....................................... 47

6.13 I²C-Compatible Interface Characteristics (SDA,

SCL)........................................................................... 6

6.14 PSRR Characteristics ............................................. 7

6.15 Other Characteristics .............................................. 7

6.16 PLL Clock Output Jitter Characteristics .................. 7

6.17 Typical 156.25-MHz Output Phase Noise

Characteristics ........................................................... 8

6.18 Typical 161.1328125 MHz Output Phase Noise

Characteristics ........................................................... 8

6.19 Additional Reliability and Qualification.................... 8

4 修订历史记录

Changes from Revision A (September 2015) to Revision B

Page

•

添加了用于定制设计的 WEBENCH 链接和信息 ..................................................................................................................... 1

发布了新的 LMK61E2BAA、LMK61E2BBA ........................................................................................................................... 1

将数据表文本更新为最新的文档和转换标准 .......................................................................................................................... 1

Moved Figure 34 to Layout Example.................................................................................................................................... 45

Changes from Original (September 2015) to Revision A

Page

•

Moved conditions from figure title to table under each graphic.............................................................................................. 9

Updated Figure 26 ............................................................................................................................................................... 18

添加了“相关文档”部分。 ....................................................................................................................................................... 46

LMK61E2

www.ti.com.cn

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

5 Pin Configuration and Functions

SIA Package

8-Pin QFM

Top View

SDA

VDD

ADD

GND

OUTN

OUTP

SCL

Pin Functions

I/O

DESCRIPTION

NAME

POWER

GND

NO.

Ground

Analog

Device Ground.

VDD

3.3-V Power Supply.

OUTPUT BLOCK

OUTP,

OUTN

4, 5

Universal

Differential Output Pair (LVPECL, LVDS or HCSL).

DIGITAL CONTROL / INTERFACES

When left open, LSB of I²C slave address is set to 01. When tied to VDD, LSB of I²C slave

address is set to 10. When tied to GND, LSB of I²C slave address is set to 00.

ADD

LVCMOS

Output Enable (internal pullup). When set to low, output pair is disabled and set at high

impedance.

SCL

SDA

LVCMOS

I²C Serial Clock (open-drain). Requires an external pullup resistor to VDD.

I²C Serial Data (bidirectional, open-drain). Requires an external pullup resistor to VDD.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

3.6

UNIT

VDD

V_IN

Device supply voltage

Output voltage for logic inputs

Output voltage for clock outputs

Junction temperature

VDD + 0.3

150

V_OUT

T_J

°C

T_stg

Storage temperature

–40

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

–40

NOM

3.3

MAX

3.465

UNIT

VDD

T_A

Device supply voltage

Ambient temperature

Junction temperature

VDD power-up ramp time

°C

T_J

125

°C

t_RAMP

0.1

100

6.4 Thermal Information

(2) (3) (4)

LMK61E2

QFM (SIA)

8 PINS

THERMAL METRIC⁽¹⁾

UNIT

AIRFLOW (LFM)

400

AIRFLOW (LFM) 0

AIRFLOW (LFM) 200

R_θJA

Junction-to-ambient thermal resistance

n/a

41.2

n/a

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

R_θJB

ψ_JT

Junction-to-board thermal resistance

36.7

11.2

36.7

n/a

Junction-to-top characterization parameter

Junction-to-board characterization parameter

16.9

37.8

n/a

21.9

38.9

n/a

ψ_JB

R_θJC(bot)Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The package thermal resistance is calculated on a 4-layer JEDEC board.

(3) Connected to GND with 3 thermal vias (0.3-mm diameter).

(4) ψ_JB(junction-to-board) is used when the main heat flow is from the junction to the GND pad. See the Layout section for more

information on ensuring good system reliability and quality.

6.5 Electrical Characteristics - Power Supply⁽¹⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

LVPECL⁽²⁾

LVDS

MIN

TYP

162

152

155

MAX

208

196

UNIT

IDD

Device current consumption

HCSL

IDD-PD

Device current consumption

when output is disabled

OE = GND

136

(1) See Parameter Measurement Information for relevant test conditions.

(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150-Ω termination resistors, from total power dissipation.

LMK61E2

www.ti.com.cn

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

6.6 LVPECL Output Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

Output frequency⁽²⁾

TEST CONDITIONS

MIN

TYP

MAX

1000

1200

UNIT

MHz

f_OUT

V_OD

Output voltage swing

700

800

2 ×

(2)

(V_OH– V_OL

)

V_{OUT, DIFF, PP}Differential output peak-to-peak swing

|V_OD

V_OS

Output common-mode voltage

VDD –

1.55

t_R/ t_F

Output rise/fall time (20% to 80%)⁽³⁾

120

200

PN-Floor

Output phase noise floor (f_OFFSET> 10

MHz)

–165

156.25 MHz

dBc/Hz

ODC

Output duty cycle⁽³⁾

45%

55%

(1) See Parameter Measurement Information for relevant test conditions.

(2) An output frequency over f_OUTmax spec is possible, but output swing may be less than V_ODmin spec.

(3) Ensured by characterization.

6.7 LVDS Output Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

Output frequency⁽¹⁾

TEST CONDITIONS

MIN

TYP

MAX

900

UNIT

MHz

f_OUT

V_OD

Output voltage swing

300

390

2 ×

480

(1)

(V_OH– V_OL

)

V_{OUT, DIFF, PP}Differential output peak-to-peak swing

|V_OD

V_OS

Output common-mode voltage

1.2

t_R/ t_F

Output rise/fall time (20% to 80%)⁽²⁾

150

250

PN-Floor

Output phase noise floor (f_OFFSET> 10 156.25 MHz

MHz)

–162

dBc/Hz

ODC

R_OUT

Output duty cycle⁽²⁾

45%

55%

Differential output impedance

125

(1) An output frequency over f_OUTmax spec is possible, but output swing may be less than V_ODmin spec.

(2) Ensured by characterization.

6.8 HCSL Output Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

Output frequency

Output high voltage

Output low voltage

TEST CONDITIONS

MIN

TYP

MAX

400

850

100

475

140

UNIT

MHz

f_OUT

V_OH

600

–100

250

V_OL

V_CROSS

Absolute crossing voltage⁽²⁾⁽³⁾

(2)(3)

V_CROSS-DELTAVariation of V_CROSS

dV/dt

Slew rate⁽⁴⁾

0.8

V/ns

PN-Floor

Output phase noise floor (f_OFFSET> 10

MHz)

100 MHz

–164

dBc/Hz

ODC

Output duty cycle⁽⁴⁾

45%

55%

(1) See Parameter Measurement Information for relevant test conditions.

(2) Measured from –150 mV to +150 mV on the differential waveform with the 300-mVpp measurement window centered on the differential

zero crossing.

(3) Ensured by design.

(4) Ensured by characterization.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

6.9 OE Input Characteristics

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IH

V_IL

I_IH

Input high voltage

Input low voltage

Input high current

Input low current

Input capacitance

1.4

0.6

V_IH= VDD

V_IL= GND

–40

µA

I_IL

C_IN

6.10 ADD Input Characteristics

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IH

V_IL

I_IH

Input high voltage

Input low voltage

Input high current

Input low current

Input capacitance

1.4

0.4

V_IH= VDD

V_IL= GND

–40

µA

I_IL

C_IN

6.11 Frequency Tolerance Characteristics⁽¹⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

All output formats, frequency bands and

device junction temperature up to 125°C;

includes initial freq tolerance, temperature &

supply voltage variation, solder reflow and

aging (10 years)

f_T

Total frequency tolerance

–50

ppm

(1) Ensured by characterization.

6.12 Power-On/Reset Characteristics (VDD)

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

2.95

0.1

UNIT

V_THRESH

V_DROOP

Threshold voltage⁽¹⁾

Allowable voltage droop⁽²⁾

2.72

Time elapsed from VDD at 3.135 V to output

enabled

(1)

t_STARTUP

Start-up time

t_OE-EN

t_OE-DIS

Output enable time⁽²⁾

Output disable time⁽²⁾

Time elapsed from OE at V_IHto output enabled

Time elapsed from OE at V_ILto output disabled

µs

(1) Ensured by characterization.

(2) Ensured by design.

6.13 I²C-Compatible Interface Characteristics (SDA, SCL)⁽¹⁾⁽²⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IH

V_IL

Input high voltage

Input low voltage

Input leakage

1.2

0.6

I_IH

–40

µA

C_IN

C_OUT

V_OL

Input capacitance

Output low voltage

400

0.6

I_OL= 3 mA

(1) Total capacitive load for each bus line ≤ 400 pF.

(2) Ensured by design.

LMK61E2

www.ti.com.cn

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

I²C-Compatible Interface Characteristics (SDA, SCL)⁽¹⁾⁽²⁾(continued)

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

I²C clock rate

TEST CONDITIONS

MIN

100

0.6

1.3

TYP

MAX

UNIT

kHz

µs

f_SCL

400

t_{SU_STA}

t_{H_STA}

t_{PH_SCL}

t_{PL_SCL}

t_{H_SDA}

t_{SU_SDA}

START condition setup time SCL high before SDA low

START condition hold time

SCL pulse width high

SCL pulse width low

SDA hold time

SCL low after SDA low

SDA valid after SCL low

µs

0.9

µs

SDA setup time

115

SCL/SDA input rise and fall

time

t_{R_IN}/ t_{F_IN}

300

250

t_{F_OUT}

SDA output fall time

C_BUS= 10 pF to 400 pF

µs

t_{SU_STOP}

STOP condition setup time

0.6

1.3

Bus free time between STOP

and START

t_BUS

µs

6.14 PSRR Characteristics⁽¹⁾

VDD = 3.3 V, T_A= 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz (Integer-N PLL), Output Divider = 32, Output

Type = LVPECL/LVDS/HCSL

PARAMETER

TEST CONDITIONS

Sine wave at 50 kHz

MIN

TYP

–70

MAX

UNIT

Spurs induced by 50-mV

power supply ripple⁽²⁾⁽³⁾at

156.25-MHz output, all

output types

Sine wave at 100 kHz

Sine wave at 500 kHz

Sine wave at 1 MHz

PSRR

dBc

(1) See Parameter Measurement Information for relevant test conditions.

(2) Measured maximum spur level with 50-mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin

(3) DJ_SPUR(ps, pk-pk) = [2 × 10(SPUR/20) / (π × f_OUT)] × 1e6, where PSRR or SPUR in dBc and f_OUTin MHz.

6.15 Other Characteristics

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_VCO

VCO frequency range

4.6

5.6

GHz

6.16 PLL Clock Output Jitter Characteristics⁽¹⁾⁽²⁾

VDD = 3.3 V ± 5%, T_A= –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RMS phase jitter⁽³⁾

(12 kHz – 20 MHz)

(1 kHz – 5 MHz)

RMS phase jitter⁽³⁾

(12 kHz – 20 MHz)

(1 kHz – 5 MHz)

_OUT≥ 100 MHz, Integer-N PLL, All output

100

200

fs RMS

types

f_OUT≥ 100 MHz, Fractional-N PLL, All output

150

300

fs RMS

types

(1) See Parameter Measurement Information for relevant test conditions.

(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

(3) Ensured by characterization.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

6.17 Typical 156.25-MHz Output Phase Noise Characteristics⁽¹⁾⁽²⁾

VDD = 3.3 V, T_A= 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5 GHz, Integer-N PLL, Output Divider = 32, Output

Type = LVPECL/LVDS/HCSL

OUTPUT TYPE

PARAMETER

UNIT

LVPECL

–143

–144

–145

–150

–154

–165

LVDS

–143

–144

–145

–150

–154

–162

HCSL

–143

–144

–145

–150

–154

–164

phn_10k

Phn_20k

phn_100k

Phn_200k

phn_1M

Phase noise at 10-kHz offset

Phase noise at 20-kHz offset

Phase noise at 100-kHz offset

Phase noise at 200-kHz offset

Phase noise at 1-MHz offset

Phase noise at 2-MHz offset

Phase noise at 10-MHz offset

Phase noise at 20-MHz offset

dBc/Hz

phn_2M

phn_10M

phn_20M

(1) See Parameter Measurement Information for relevant test conditions.

(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

6.18 Typical 161.1328125 MHz Output Phase Noise Characteristics⁽¹⁾⁽²⁾

VDD = 3.3 V, T_A= 25°C, PLL bandwidth = 400 kHz, VCO Frequency = 5.15625 GHz, Fractional-N PLL, Output Divider = 32,

Output Type = LVPECL/LVDS/HCSL

OUTPUT TYPE

PARAMETER

UNIT

LVPECL

–136

–140

–141

–148

–156

–161

–162

LVDS

–136

–140

–141

–148

–156

–159

–160

HCSL

–136

–140

–141

–148

–156

–160

–161

phn_10k

phn_20k

phn_100k

phn_200k

phn_1M

Phase noise at 10-kHz offset

Phase noise at 20-kHz offset

Phase noise at 100-kHz offset

Phase noise at 200-kHz offset

Phase noise at 1-MHz offset

Phase noise at 2-MHz offset

Phase noise at 10-MHz offset

Phase noise at 20-MHz offset

dBc/Hz

phn_2M

phn_10M

phn_20M

(1) See Parameter Measurement Information for relevant test conditions.

(2) Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).

6.19 Additional Reliability and Qualification

PARAMETER

CONDITION / TEST METHOD

MIL-STD-202, Method 213

MIL-STD-202, Method 204

J-STD-020, MSL3

Mechanical Shock

Mechanical Vibration

Moisture Sensitivity Level

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

6.20 Typical Characteristics

PLL Bandwidth = 400 kHz

Integer-N PLL

VCO Frequency = 5 GHz

Output Divider = 32

PLL Bandwidth = 400 kHz

Integer-N PLL

VCO Frequency = 5 GHz

Output Divider = 32

Figure 1. Closed-Loop Phase Noise of LVPECL Differential

Output at 156.25 MHz

Figure 2. Closed-Loop Phase Noise of LVDS Differential

Output at 156.25 MHz

PLL Bandwidth = 400 kHz

Fractional-N PLL

VCO Frequency = 5.15625 GHz

Output Divider = 32

PLL Bandwidth = 400 kHz

Integer-N PLL

VCO Frequency = 5 GHz

Output Divider = 32

Figure 4. Closed-Loop Phase Noise of LVPECL Differential

Output at 161.1328125 MHz

Figure 3. Closed-Loop Phase Noise of HCSL Differential

Output at 156.25 MHz

PLL Bandwidth = 400 kHz

Fractional-N PLL

VCO Frequency = 5.15625 GHz

Output Divider = 32

PLL Bandwidth = 400 kHz

Fractional-N PLL

VCO Frequency = 5.15625 GHz

Output Divider = 32

Figure 6. Closed-Loop Phase Noise of HCSL Differential

Output at 161.1328125 MHz

Figure 5. Closed-Loop Phase Noise of LVDS Differential

Output at 161.1328125 MHz

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Characteristics (continued)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-10

-20

-30

-40

-50

-60

-70

-80

-90

78.125

109.375

140.625

171.875

203.125

234.375

78.125

109.375

140.625

171.875

203.125

234.375

Frequency (MHz)

D007

D008

PLL Bandwidth = 400 kHz

Integer-N PLL

VCO Frequency = 5 GHz

Output Divider = 32

PLL Bandwidth = 400 kHz

Integer-N PLL

VCO Frequency = 5 GHz

Output Divider = 32

Figure 7. 156.25 ± 78.125-MHz LVPECL Differential Output

Spectrum

Figure 8. 156.25 ± 78.125-MHz LVDS Differential Output

Spectrum

-10

-20

-30

-40

-50

-60

-70

-80

-90

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

78.125

109.375

140.625

171.875

203.125

234.375

100

120

140

160

180

200

220

240

Frequency (MHz)

D009

D010

PLL Bandwidth = 400 kHz

Integer-N PLL

VCO Frequency = 5 GHz

Output Divider = 32

PLL Bandwidth = 400 kHz

Fractional-N PLL

VCO Frequency = 5.15625 GHz

Output Divider = 32

Figure 9. 156.25 ± 78.125-MHz HCSL Differential Output

Spectrum

Figure 10. 161.1328125 ± 80.56640625-MHz LVPECL

Differential Output Spectrum

-10

-20

-30

-40

-50

-60

-70

-80

-90

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

100

120

140

160

180

200

220

240

100

120

140

160

180

200

220

240

Frequency (MHz)

D011

D012

PLL Bandwidth = 400 kHz

Fractional-N PLL

VCO Frequency = 5.15625 GHz

Output Divider = 32

PLL Bandwidth = 400 kHz

Fractional-N PLL

VCO Frequency = 5.15625 GHz

Output Divider = 32

Figure 11. 161.1328125 ± 80.56640625-MHz LVDS Output

Spectrum

Figure 12. 161.1328125 ± 80.56640625-MHz HCSL Output

Spectrum

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Typical Characteristics (continued)

1.8

0.9

0.8

0.7

0.6

0.5

1.7

1.6

1.5

1.4

1.3

1.2

1.1

200

400

600

800

1000

200

400

600

800

1000

Output Frequency (MHz)

D013

D014

Figure 13. LVPECL Differential Output Swing vs Frequency

Figure 14. LVDS Differential Output Swing vs Frequency

1.5

1.48

1.46

1.44

1.42

1.4

100

200

300

400

500

Output Frequency (MHz)

D015

Figure 15. HCSL Differential Output Swing vs Frequency

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7 Parameter Measurement Information

7.1 Device Output Configurations

High impedance differential probe

LVPECL

LMK61E2

Oscilloscope

150 ꢀ

Figure 16. LVPECL Output DC Configuration During Device Test

High impedance differential probe

LMK61E2

LVDS

Oscilloscope

Figure 17. LVDS Output DC Configuration During Device Test

High impedance differential probe

HCSL

LMK61E2

Oscilloscope

50 ꢀ

Figure 18. HCSL Output DC Configuration During Device Test

Phase Noise/

Balun/

Buffer

Spectrum

Analyzer

LMK61E2

LVPECL

150 ꢀ

Figure 19. LVPECL Output AC Configuration During Device Test

Phase Noise/

Balun/

Buffer

LMK61E2

Spectrum

Analyzer

LVDS

Figure 20. LVDS Output AC Configuration During Device Test

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Device Output Configurations (continued)

Phase Noise/

Spectrum

Analyzer

Balun/

Buffer

LMK61E2

HCSL

50 ꢀ

Figure 21. HCSL Output AC Configuration During Device Test

Sine wave

Modulator

Power Supply

Phase Noise/

LMK61E2

Spectrum

Analyzer

Balun

150 ꢀ (LVPECL)

Open (LVDS)

50 ꢀ (HCSL)

150 ꢀ (LVPECL)

Open (LVDS)

50 ꢀ (HCSL)

Figure 22. PSRR Test Setup

OUT_P

OUT_N

V_OD

80%

V_OUT,DIFF,PP= 2 x V_OD

0 V

20%

t_R

t_F

Figure 23. Differential Output Voltage and Rise/Fall Time

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8 Detailed Description

8.1 Overview

The LMK61E2 is a programmable oscillator that generates commonly used reference clocks with less than 200-

fs RMS maximum random jitter in integer PLL mode and less than 300-fs RMS maximum random jitter in

fractional PLL mode.

8.2 Functional Block Diagram

VDD

Power Conditioning

PLL

Integrated

Oscillator

10 nF

Output

LVPECL

or LVDS

or HCSL

Integer Div

/5 - /511

VCO: 4.6 GHz ~ 5.6 GHz

N Div

∑û fractional

Control

SDA

SCL

ADD

Device

Control

Registers

EEPROM

GND

od = open-drain

= tri-state

NOTE

Control blocks are compatible with 1.8, 2.5, or 3.3-V I/O voltage levels.

8.3 Feature Description

8.3.1 Device Block-Level Description

The LMK61E2 comprises of an integrated oscillator that includes a 50-MHz crystal, a fractional PLL with

integrated VCO that supports a frequency range of 4.6 GHz to 5.6 GHz. The PLL block consists of a phase

frequency detector (PFD), charge pump, integrated passive loop filter, a feedback divider that can support both

integer and fractional values and a delta-sigma engine for noise suppression in fractional PLL mode. Completing

the device is the combination of an integer output divider and a universal differential output buffer. The PLL is

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Feature Description (continued)

such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their

own LDO. The LDOs provide isolation to the PLL from any noise in the external power supply rail with a PSRR of

better than –70 dBc at 50-kHz to 1-MHz ripple frequencies at 3.3-V device supply. The device supports fine and

coarse frequency margining by changing the settings of the integrated oscillator and the output divider

respectively.

8.3.2 Device Configuration Control

The LMK61E2 supports I²C programming interface where an I²C host can update any device configuration after

the device enables the host interface and the host writes a sequence that updates the device registers. Once the

device configuration is set, the host can also write to the on-chip EEPROM for a new set of power-up defaults

based on the configuration pin settings in the soft pin configuration mode.

8.3.3 Register File Reference Convention

Figure 24 shows the method that this document employs to refer to an individual register bit or a grouping of

the bit number second. The LMK61E2 contains 38 registers that are 8 bits wide. The register addresses and the

bit positions both begin with the number zero (0). A period separates the register address and bit address. The

first bit in the register file is address ‘R0.0’ meaning that it is located in Register 0 and is bit position 0. The last

bit in the register file is address ‘R72.7’ referring to the 8th bit of register address 72 (the 73rd register in the

device). Figure 24 also lists specific bit positions as a number contained within a box. A box with the register

address encloses the group of boxes that represent the bits relevant to the specific device circuitry in context.

Reg5

Bit Number (s)

R5.2

Figure 24. LMK61E2 Register Reference Format

8.3.4 Configuring the PLL

The PLL in LMK61E2 can be configured to accommodate various output frequencies either through I²C

programming interface or in the absence of programming, the PLL defaults stored in EEPROM is loaded on

power up. The PLL can be configured by setting the Reference Doubler, Integrated PLL Loop Filter, Feedback

Divider, and Output Divider.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met.

F_VCO= F_REF× D × [(INT + NUM/DEN)]

where

•

F_VCO: PLL/VCO Frequency (4.6 GHz to 5.6 GHz)

F_REF: 50-MHz reference input

D: PLL input frequency doubler, 1=Disabled, 2=Enabled

INT: PLL feedback divider integer value (12 bits, 1 to 4095)

NUM: PLL feedback divider fractional numerator value (22 bits, 0 to 4194303)

DEN: PLL feedback divider fractional denominator value (22 bits, 1 to 4194303)

(1)

The output frequency is related to the VCO frequency as given in Equation 2.

F_OUT= F_VCO/ OUTDIV

where

•

OUTDIV: Output divider value (9 bits, 5 to 511)

(2)

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Feature Description (continued)

8.3.5 Integrated Oscillator

The integrated oscillator in LMK61E2 features programmable load capacitances that can be set to either operate

at exactly its nominal oscillation frequency or operate at a fixed frequency offset from its nominal oscillation

frequency. This is done by programming R16 and R17. More details on frequency margining are provided in Fine

Frequency Margining.

8.3.6 Reference Doubler

The reference path has a frequency doubler that can be enabled by programming R34.5 = 1. Enabling the

doubler allows a higher comparison frequency for the PLL and would result in a 3-dB reduction in the in-band

phase noise at the output of the LMK61E2. Enabling the doubler also results in higher reference and phase

detector spurs which will be minimized by enabling the higher order components (R3, C3) of the loop filter and

programmed to appropriate values. Disabling the doubler would result in higher in-band phase noise on the

device output than when the doubler is enabled but the reference and phase detector spurs would be lower on

the device output than when the doubler is enabled.

8.3.7 Phase Frequency Detector

The Phase Frequency Detector (PFD) of the PLL takes inputs from the reference path and the feedback divider

output and produces an output that is dependent on the phase and frequency difference between the two inputs.

The input frequency of the PFD is 50 MHz when reference doubler is disabled, or 100 MHz when reference

doubler is enabled.

8.3.8 Feedback Divider (N)

The N divider of the PLL includes fractional compensation and can achieve any fractional denominator (DEN)

from 1 to 4,194,303. The integer portion, INT, is the whole part of the N divider value and the fractional portion,

NUM / DEN, is the remaining fraction. INT, NUM, and DEN are programmed in R25, R26, R27, R28, R29, R30,

R31, and R32. The total programmed N divider value, N, is determined by: N = INT + NUM / DEN. The output of

the N divider sets the PFD frequency to the PLL and should equal 50 MHz, when reference doubler is disabled,

or 100 MHz, when reference doubler is enabled.

8.3.9 Fractional Circuitry

The delta signal modulator is a key component of the fractional circuitry and is involved in noise shaping for

better phase noise and spurs in the band of interest. The order of the delta sigma modulator is selectable

between integer mode and third order, for fractional PLL mode, and can be programmed in R33[1-0]. Dithering

can be programmed in R33[3-2] and should be disabled for integer PLL mode and set to weak for fractional PLL

mode.

8.3.10 Charge Pump

The PLL has charge pump slices of 1.6 mA, to be used when PLL is set to fractional mode, or 6.4 mA, to be

used when PLL is set to integer mode. These slices can be selected by programming R34[3-0]. When PLL is set

to fractional mode, a phase shift needs to be introduced to maintain a linear response and ensure consistent

performance across operating conditions and a value of 0x2 should be programmed in R35[6-4]. When PLL is

set to integer mode, a value of 0x0 should be programmed in R35[6-4].

8.3.11 Loop Filter

The LMK61E2 features a fully integrated loop filter for the PLL and supports programmable loop bandwidth from

100 kHz to 1 MHz. The loop filter components, R2, C1, R3, and C3 can be configured by programming R36,

R37, R38, and R39 respectively. The LMK61E2 features a fixed value of C2 of 10 nF. When PLL is configured in

the fractional mode, R35.2 should be set to 1. When reference doubler is disabled for integer mode PLL, R35.2

should be set to 0 and R38[6-0] should be set to 0x00. When reference doubler is enabled for integer mode PLL,

R35.2 should be set to 1 and R38 and R39 are written with the appropriate values. Figure 25 shows the loop

filter structure of the PLL. It is important to set the PLL to best possible bandwidth to minimize output jitter. TI

provides the WEBENCH^®Clock Architect Tool that makes it easy to select the right loop filter components.

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Feature Description (continued)

LMK61E2

10 nF

From PFD /

Charge Pump

To VCO

Loop Filter Control

R36 R37 R38 R39

Figure 25. Loop Filter Structure of PLL

8.3.12 VCO Calibration

The PLL in LMK61E2 is made of LC VCO that is designed using high-Q monolithic inductors to oscillate between

4.6 GHz and 5.6 GHz and has low-phase noise characteristics. The VCO must be calibrated to ensure that the

clock outputs deliver optimal phase noise performance. Fundamentally, a VCO calibration establishes an optimal

operating point within the tuning range of the VCO. Setting R72.1 to 1 causes a VCO recalibration and is

necessary after device reconfiguration. VCO calibration automatically occurs on device power up.

8.3.13 High-Speed Output Divider

The high-speed output divider supports divide values of 5 to 511 and are programmed in R22 and R23. The

output divider also supports coarse frequency margining that can initiate as low as a 5% change in the output

frequency.

8.3.14 High-Speed Clock Output

The clock output can be configured as LVPECL, LVDS, or HCSL by programming R21[1-0]. Interfacing to

LVPECL, LVDS, or HCSL receivers are done either with direct coupling or with AC-coupling capacitor as shown

in Figure 16 – Figure 21.

The LVDS output structure has integrated 125-Ω termination between each side (P and N) of the differential pair.

The HCSL output structure is open drain and can be DC or AC coupled to HCSL receivers with appropriate

termination scheme. The LVPECL output structure is an emitter follower requiring external termination.

8.3.15 Device Status

The PLL loss of lock and PLL calibration status can be monitored by reading R66[1-0]. These bits represent a

logic-high interrupt output and are self-cleared once the readback is complete.

8.3.15.1 Loss of Lock

The PLL loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle slip.

Loss of lock may occur when an incorrect PLL configuration is programmed or the VCO has not been

recalibrated.

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8.4 Device Functional Modes

8.4.1 Interface and Control

The host (DSP, Microcontroller, FPGA, and so forth) configures and monitors the LMK61E2 through the I²C port.

The host reads and writes to a collection of control and status bits called the register map. The device blocks can

be controlled and monitored through a specific grouping of bits located within the register file. The host controls

and monitors certain device Wide critical parameters directly through register control and status bits. In the

absence of the host, the LMK61E2 can be configured to operate from its on-chip EEPROM. The EEPROM array

is automatically copied to the device registers upon power up. The user has the flexibility to rewrite the contents

of EEPROM from the SRAM up to a 100 times.

Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an

attempt to write to a read-only bit does not change the state of the bit). Certain device registers and bits are

reserved, meaning that they must not be changed from their default reset state. Figure 26 shows interface and

control blocks within LMK61E2 and the arrows refer to read access from and write access to the different

embedded memories (EEPROM, SRAM).

Device Registers

Reg72

Reg66

Reg56

Reg53

Control/

Status Pins

Device

Control

And

Device

ADD

Hardware

Reg3

I2C

Port

SCL

SDA

Status

Reg2

Reg1

Reg 0

Reg35

Reg34

Reg33

Reg32

Reg3

Reg2

Reg1

Reg 0

SRAM

Figure 26. LMK61E2 Interface and Control Block

EEPROM

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8.5 Programming

8.5.1 I²C Serial Interface

The I²C port on the LMK61E2 works as a slave device and supports both the 100-kHz standard mode and 400-

kHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore,

the input receivers ignore pulses of less than 50 ns duration. The I²C timing is given in I²C-Compatible Interface

Characteristics (SDA, SCL)⁽¹⁾⁽²⁾. The timing diagram is given in Figure 27.

STOP

START

ACK

STOP

t_W(SCLL)

t_f(SM)

t_W(SCLH)

t_r(SM)

V_IH(SM)

V_IL(SM)

SCL

t_h(START)

t_SU(START)

t_BUS

t_SU(SDATA)

t_r(SM)

t_h(SDATA)

t_SU(STOP)

t_f(SM)

V_IH(SM)

V_IL(SM)

SDA

Figure 27. I²C Timing Diagram

In an I²C bus system, the LMK61E2 acts as a slave device and is connected to the serial bus (data bus SDA and

lock bus SCL). These are accessed via a 7-bit slave address transmitted as part of an I²C packet. Only the

device with a matching slave address responds to subsequent I²C commands. In soft pin mode, the LMK61E2

allows up to three unique slave devices to occupy the I²C bus based on the pin strapping of ADD (tied to VDD,

GND, or left open). The device slave address is 10110xx (the two LSBs are determined by the ADD pin).

During the data transfer through the I²C interface, one clock pulse is generated for each data bit transferred. The

data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can

change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a

high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a

low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the

master. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit

and bytes are sent MSB first. The I²C register structure of the LMK61E2 is shown in Figure 28.

I2C PROTOCOL

A6 A5 A4 A3 A2 A1 A0

I2C ADDRESS

W/R

DATA BYTE

Figure 28. I²C Register Structure

The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always

generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’

= 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA

line high during the 9th clock pulse.

(1) Total capacitive load for each bus line ≤ 400 pF.

(2) Ensured by design.

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Programming (continued)

The I²C master initiates the data transfer by asserting a start condition which initiates a response from all slave

devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line

(consisting of the 7-bit slave address (MSB first) and an R/W’ bit), the device whose address corresponds to the

transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the

selected device waits for data transfer with the master.

After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop

condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte

from the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low

during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the

slave knows the data transfer is finished and enters the idle mode. The master then takes the data line low

during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition.

A generic transaction is shown in Figure 29.

Slave Address

R/W

LSB

Data Byte

MSB

LSB

Start Condition

Sr Repeated Start Condition

R/W 1 = Read (Rd) from slave; 0 = Write (Wr) to slave

Acknowledge (ACK = 0 and NACK = 1)

Stop Condition

Master to Slave Transmission

Slave to Master Transmission

Figure 29. Generic Programming Sequence

The LMK61E2 I²C interface supports Block Register Write/Read, Read/Write SRAM, and Read/Write EEPROM

operations. For Block Register Write/Read operations, the I²C master can individually access addressed

registers that are made of an 8-bit data byte. The offset of the indexed register is encoded in the register

address, as described in Table 1.

Table 1. Slave Address Byte

DEVICE

ADD pin

R/W

LMK61E2

0x0, 0x1 or 0x3

1/0

8.5.2 Block Register Write

The I²C Block Register Write transaction is illustrated in Figure 30 and consists of the following sequence.

1. Master issues a Start Condition.

2. Master writes the 7-bit Slave Address following by a Write bit.

3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.

4. Master writes one or more data bytes each of which should be acknowledged by the slave. The slave

increments the internal register address after each byte.

5. Master issues a Stop Condition to terminate the transaction.

Slave Address

CommandCode

...

Data Byte 0

Data Byte N-1

Figure 30. Block Register Write Programming Sequence

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8.5.3 Block Register Read

The I²C Block Register Read transaction is illustrated in Figure 31 and consists of the following sequence.

1. Master issues a Start Condition.

2. Master writes the 7-bit Slave Address followed by a Write bit.

3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.

4. Master issues a Repeated Start Condition.

5. Master writes the 7-bit Slave Address following by a Read bit.

6. Slave returns one or more data bytes as long as the Master continues to acknowledge them. The slave

increments the internal register address after each byte.

7. Master issues a Stop Condition to terminate the transaction.

Slave Address

CommandCode

Slave Address

...

Data Byte 0

Data Byte N-1

Figure 31. Block Register Read Programming Sequence

8.5.4 Write SRAM

The on-chip SRAM is a volatile, shadow memory array used to temporarily store register data, and is intended

only for programming the non-Volatile EEPROM. The SRAM has the identical data format as the EEPROM map.

The register configuration data can be transferred to the SRAM array through special memory access registers in

the register map. To successfully program the SRAM, the complete base array and at least one page should be

written. The following details the programming sequence to transfer the device registers into the SRAM.

1. Program the device registers to match a desired setting.

2. Write a 1 to R49.6. This ensures that the device registers are copied to the SRAM.

The SRAM can also be written with particular values according to the following programming sequence.

1. Write the SRAM address in R51.

2. Write the desired data byte in R53 in the same I²C transaction and this data byte will be written to the

address specified in the step above. Any additional access that is part of the same transaction will cause the

SRAM address to be incremented and a write will take place to the next SRAM address. Access to SRAM

will terminate at the end of current I²C transaction.

NOTE

It is possible to increment SRAM address incorrectly when 2 successive accesses are

made to R51.

8.5.5 Write EEPROM

The on-chip EEPROM is a non-Volatile memory array used to permanently store register data for a custom

device start-up configuration setting to initialize registers upon power up or POR. The EEPROM is comprised of

bits shown in the EEPROM Map. The transfer must first happen to the SRAM and then to the EEPROM. During

EEPROM write, R49.2 is a 1 and the EEPROM contents cannot be accessed. The following details the

programming sequence to transfer the entire contents of SRAM to EEPROM.

1. Make sure the Write SRAM procedure (Write SRAM) was done to commit the register settings to the SRAM

with start-up configurations intended for programming to the EEPROM.

2. Write 0xBE to R56. This provides basic protection from inadvertent programming of EEPROM.

3. Write a 1 to R49.0. This programs the entire SRAM contents to EEPROM. Once completed, the contents in

R48 will increment by 1. R48 contains the total number of EEPROM programming cycles that are

successfully completed.

4. Write 0x00 to R56 to protect against inadvertent programming of EEPROM.

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8.5.6 Read SRAM

The contents of the SRAM can be read out, one word at a time, starting with that of the requested address.

Following details the programming sequence for an SRAM read by address.

1. Write the SRAM address in R51.

2. The SRAM data located at the address specified in the step above can be obtained by reading R53 in the

same I²C transaction. Any additional access that is part of the same transaction will cause the SRAM

address to be incremented and a read will take place of the next SRAM address. Access to SRAM will

terminate at the end of current I²C transaction.

NOTE

It is possible to increment SRAM address incorrectly when 2 successive accesses are

made to R51.

8.5.7 Read EEPROM

The contents of the EEPROM can be read out, one word at a time, starting with that of the requested address.

Following details the programming sequence for an EEPROM read by address.

1. Write the EEPROM address in R51.

2. The EEPROM data located at the address specified in the step above can be obtained by reading R52 in the

same I²C transaction. Any additional access that is part of the same transaction will cause the EEPROM

address to be incremented and a read will take place of the next EEPROM address. Access to EEPROM will

terminate at the end of current I²C transaction.

NOTE

It is possible to increment EEPROM address incorrectly when 2 successive accesses are

made to R51.

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8.6 EEPROM Map

Any bit that is labeled as RESERVED should be written with a 0.

Byte # Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

RESERVED

NVMSCRC[6]

NVMCNT[6]

RESERVED

SLAVEADR[6]

EEREV[6]

RESERVED

NVMSCRC[5]

NVMCNT[5]

RESERVED

NVMSCRC[4]

NVMCNT[4]

RESERVED

SLAVEADR[4]

EEREV[4]

RESERVED

NVMSCRC[3]

NVMCNT[3]

RESERVED

SLAVEADR[3]

EEREV[3]

RESERVED

NVMSCRC[2]

NVMCNT[2]

RESERVED

NVMSCRC[1]

NVMCNT[1]

RESERVED

EEREV[1]

RESERVED

NVMSCRC[0]

NVMCNT[0]

RESERVED

NVMSCRC[7]

NVMCNT[7]

RESERVED

SLAVEADR[7]

EEREV[7]

RESERVED

EEREV[2]

RESERVED

SLAVEADR[5]

EEREV[5]

RESERVED

EEREV[0]

RESERVED

XO_CAPCTRL[4]

RESERVED

OUT_SEL[1]

RESERVED

PLL_NDIV[11]

PLL_NDIV[3]

PLL_NUM[17]

PLL_NUM[9]

PLL_NUM[1]

PLL_DEN[15]

PLL_DEN[7]

PLL_PDN

RESERVED

XO_CAPCTRL[0]

XO_CAPCTRL[2]

RESERVED

PLL_NDIV[9]

PLL_NDIV[1]

PLL_NUM[15]

PLL_NUM[7]

PLL_DEN[21]

PLL_DEN[13]

PLL_DEN[5]

RESERVED

XO_CAPCTRL[9]

RESERVED

PLL_NDIV[8]

PLL_NDIV[0]

PLL_NUM[14]

PLL_NUM[6]

PLL_DEN[20]

PLL_DEN[12]

PLL_DEN[4]

PLL_ORDER[0]

RESERVED

XO_CAPCTRL[8]

RESERVED

PLL_NDIV[7]

PLL_NUM[21]

PLL_NUM[13]

PLL_NUM[5]

PLL_DEN[19]

PLL_DEN[11]

PLL_DEN[3]

RESERVED

AUTOSTRT

RESERVED

XO_CAPCTRL[6]

RESERVED

PLL_NDIV[5]

PLL_NUM[19]

PLL_NUM[11]

PLL_NUM[3]

PLL_DEN[17]

PLL_DEN[9]

PLL_DEN[1]

PLL_D

RESERVED

XO_CAPCTRL[1]

XO_CAPCTRL[3]

RESERVED

OUT_SEL[0]

RESERVED

PLL_NDIV[10]

PLL_NDIV[2]

PLL_NUM[16]

PLL_NUM[8]

PLL_NUM[0]

PLL_DEN[14]

PLL_DEN[6]

XO_CAPCTRL[7]

RESERVED

PLL_NDIV[6]

PLL_NUM[20]

PLL_NUM[12]

PLL_NUM[4]

PLL_DEN[18]

PLL_DEN[10]

PLL_DEN[2]

RESERVED

XO_CAPCTRL[5]

RESERVED

OUT_SEL[2]

RESERVED

PLL_NDIV[4]

PLL_NUM[18]

PLL_NUM[10]

PLL_NUM[2]

PLL_DEN[16]

PLL_DEN[8]

PLL_DEN[0]

PLL_CP[3]

PLL_

PLL_DTHRMODE[0] PLL_ORDER[1]

DTHRMODE[1]

PLL_CP[2]

PLL_CP[1]

PLL_CP[0]

PLL_CP_PHASE_

SHIFT[2]

PLL_CP_PHASE_

SHIFT[1]

PLL_CP_PHASE_

SHIFT[0]

PLL_ENABLE_

C3[2]

PLL_ENABLE_

C3[1]

PLL_ENABLE_

C3[0]

PLL_LF_R2[7]

PLL_LF_R2[6]

PLL_LF_R2[5]

PLL_LF_R2[4]

PLL_LF_R2[3]

PLL_LF_R2[2]

PLL_LF_R2[1]

PLL_LF_R2[0]

PLL_LF_R3[2]

PLL_LF_C1[2]

PLL_LF_R3[1]

PLL_LF_C1[1]

PLL_LF_R3[0]

PLL_LF_C1[0]

PLL_LF_C3[2]

PLL_LF_R3[6]

PLL_LF_C3[1]

PLL_LF_R3[5]

PLL_LF_C3[0]

PLL_LF_R3[4]

RESERVED

PLL_LF_R3[3]

RESERVED

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

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EEPROM Map (continued)

Byte # Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

RESERVED

OUT_DIV[1]

OUT_DIV[8]

OUT_DIV[0]

OUT_DIV[7]

RESERVED

OUT_DIV[6]

RESERVED

OUT_DIV[5]

RESERVED

OUT_DIV[4]

RESERVED

OUT_DIV[3]

RESERVED

OUT_DIV[2]

RESERVED

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

8.7 Register Map

The default/reset values for each register is specified for LMK61E2-I3.

Name

Addr

Reset

0x10

0x0B

0x33

0x00

0xB0

0x00

0x01

0x00

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

VNDRID_BY1

VNDRID_BY0

PRODID

VNDRID[15:8]

VNDRID[7:0]

PRODID[7:0]

REVID[7:0]

SLAVEADR[7:1]

EEREV[7:0]

RESERVED

REVID

SLAVEADR

EEREV

RESERVED

AUTOSTRT

DEV_CTL

PLL_PDN

RESERVED

ENCAL

XO_CAPCTRL_

BY1

XO_CAPCTRL[1:0]

XO_CAPCTRL_

BY0

0x00

XO_CAPCTRL[9:2]

DIFFCTL

0x01

0x00

0x20

0x00

0x64

0x00

DIFF_OUT_PD

RESERVED

OUT_DIV[7:0]

RESERVED

PLL_NDIV[7:0]

RESERVED

OUT_SEL[1:0]

OUTDIV_BY1

OUTDIV_BY0

PLL_NDIV_BY1

PLL_NDIV_BY0

OUT_DIV[8]

PLL_NDIV[11:8]

PLL_FRACNUM_

BY2

PLL_NUM[21:16]

PLL_DEN[21:16]

PLL_FRACNUM_

BY1

0x00

PLL_NUM[15:8]

PLL_NUM[7:0]

RESERVED

PLL_FRACNUM_

BY0

PLL_FRACDEN_

BY2

PLL_FRACDEN_

BY1

PLL_DEN[15:8]

PLL_DEN[7:0]

PLL_FRACDEN_

BY0

PLL_MASHCTRL

PLL_CTRL0

PLL_CTRL1

PLL_LF_R2

PLL_LF_C1

PLL_LF_R3

0x0C

0x24

0x03

0x28

0x00

RESERVED

PLL_LF_R2[7:0]

RESERVED

PLL_DTHRMODE[1:0]

PLL_CP[3:0]

PLL_ORDER[1:0]

PLL_D

RESERVED

PLL_CP_PHASE_SHIFT[2:0]

RESERVED

PLL_ENABLE_C3[2:0]

PLL_LF_C1[2:0]

PLL_LF_R3[6:0]

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

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Name

Addr

Reset

0x00

0x10

0x00

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

PLL_LF_C3[2:0]

PLL_CLSDWAIT[1:0] PLL_VCOWAIT[1:0]

Bit1

Bit0

PLL_LF_C3

PLL_CALCTRL

NVMSCRC

NVMCNT

NVMCTL

RESERVED

NVMSCRC[7:0]

NVMCNT[7:0]

RESERVED

NVMLCRC[7:0]

RESERVED

NVMDAT[7:0]

RAMDAT[7:0]

NVMUNLK[7:0]

RESERVED

REGCOMMIT

MEMADR[6:0]

NVMCRCERR

NVMAUTOCRC NVMCOMMIT

NVMBUSY NVMERASE

NVMPROG

NVMLCRC

MEMADR

NVMDAT

RAMDAT

NVMUNLK

INT_LIVE

SWRST

LOL

CAL

SWR2PLL

RESERVED

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

8.7.1 Register Descriptions

8.7.1.1 VNDRID_BY1 Register; R0

VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number

assigned to I²C vendors.

Bit #

Field

Type

Reset

EEPROM Description

N Vendor Identification Number Byte 1.

[7:0]

VNDRID[15:8]

0x10

8.7.1.2 VNDRID_BY0 Register; R1

VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number

assigned to I²C vendors.

Bit #

Field

Type

Reset

EEPROM Description

N Vendor Identification Number Byte 0.

[7:0]

VNDRID[7:0]

0x0B

8.7.1.3 PRODID Register; R2

The Product Identification Number is a unique 8-bit identification number used to identify the LMK61E2.

Bit #

Field

Type

Reset

EEPROM Description

N Product Identification Number.

[7:0]

PRODID[7:0]

0x33

8.7.1.4 REVID Register; R3

The REVID register is used to identify the LMK61E2 mask revision.

Bit #

Field

Type

Reset

EEPROM Description

N Device Revision Number. The Device Revision Number

[7:0]

REVID[7:0]

0x00

is used to identify the LMK61E2 mask-set revision used

to fabricate this device.

8.7.1.5 SLAVEADR Register; R8

The SLAVEADR register reflects the 7-bit I²C Slave Address value initialized from from on-chip EEPROM.

Bit #

Field

Type

Reset

EEPROM Description

I²C Slave Address. This field holds the 7-bit Slave

[7:1]

SLAVEADR[7:1]

0x58

Address used to identify this device during I²C

transactions. The two least significant bits of the address

can be configured using ADD pin as shown.

SLAVEADR[2:1]

0 (0x0)

ADD pin

1 (0x1)

Float

3 (0x3)

[0]

RESERVED

Reserved.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

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8.7.1.6 EEREV Register; R9

The EEREV register provides an EEPROM image revision record. EEPROM Image Revision is automatically

retrieved from EEPROM and stored in the EEREV register after a reset or after a EEPROM commit operation.

Bit #

Field

Type

Reset

EEPROM Description

Y EEPROM Image Revision ID

[7:0]

EEREV[7:0]

0x00

8.7.1.7 DEV_CTL Register; R10

The DEV_CTL register holds the control functions described in the following table.

Bit #

[7]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_PDN

Reserved.

[6]

PLL Powerdown. The PLL_PDN bit determines whether

PLL is automatically enabled and calibrated after a

hardware reset. If the PLL_PDN bit is set to 1 during

normal operation then PLL is disabled and the calibration

circuit is reset. When PLL_PDN is then cleared to 0 PLL

is re-enabled and the calibration sequence is

automatically restarted.

PLL_PDN

Value

PLL Enabled

PLL Disabled

[5:2]

[1]

RESERVED[5:2]

ENCAL

Reserved.

RWSC

Enable Frequency Calibration. Triggers PLL/VCO

calibration on both PLLs in parallel on 0 –> 1 transition

of ENCAL. This bit is self-clearing and set to a 0 after

PLL/VCO calibration is complete. In powerup or software

rest mode, AUTOSTRT takes precedence.

[0]

AUTOSTRT

Autostart. If AUTOSTRT is set to 1 the device will

automatically attempt to achieve lock and enable outputs

after a device reset. A device reset can be triggered by

the power-on-reset, RESETn pin or by writing to the

RESETN_SW bit. If AUTOSTRT is 0 then the device will

halt after the configuration phase, a subsequent write to

set the AUTOSTRT bit to 1 will trigger the PLL Lock

sequence.

8.7.1.8 XO_CAPCTRL_BY1 Register; R16

XO Margining Offset Value bits[9:8]

Bit #

[7:2]

[1:0]

Field

Type

Reset

EEPROM Description

RESERVED[5:0]

XO_CAPCTRL [1:0]

Reserved.

0x0

XO Offset Value bits [1:0]

8.7.1.9 XO_CAPCTRL_BY0 Register; R17

XO margining Offset Value bits[7:0]

Bit #

Field

Type

Reset

EEPROM Description

Y XO Offset Value bits[9:2]

[7:0]

XO_CAPCTRL [9:2]

0x80

LMK61E2

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8.7.1.10 DIFFCTL Register; R21

The DIFFCTL register provides control over Output.

Bit #

[7]

Field

Type

Reset

EEPROM Description

DIFF_OUT_PD

RESERVED

OUT_SEL[1:0]

Power down differential output buffer.

Reserved.

[6:2]

[1:0]

0x1

Channel Output Driver Format Select. The OUT_SEL

field controls the Channel Output Driver as shown below.

OUT_SEL

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

OUTPUT OPERATION

Tri-State

LVPECL

LVDS

HCSL

8.7.1.11 OUTDIV_BY1 Register; R22

The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.

Bit #

[7:1]

[0]

Field

Type

Reset

0x00

EEPROM Description

RESERVED

OUT_DIV[8]

Reserved.

Channel's Output Divider Byte 1 (Bit 8). The Channel

Divider, OUT_DIV, is a 9-bit divider. The valid values for

OUT_DIV range from 5 to 511 as shown below.

OUT_DIV

0-4

DIVIDE RATIO

RESERVED

5 (0x005)

6 (0x006)

7 (0x007)

255 (0x0FF)

256 (0x100)

257 (0x101)

...

255

256

257

...

511 (0x1FF)

511

8.7.1.12 OUTDIV_BY0 Register; R23

The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.

Bit #

Field

Type

Reset

EEPROM Description

Y Channel's Output Divider Byte 0 (Bits 7-0).

[7:0]

OUT_DIV[7:0]

0x20

LMK61E2

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8.7.1.13 PLL_NDIV_BY1 Register; R25

The 12-bit N integer divider value for PLL is set by the PLL_NDIV_BY1 and PLL_NDIV_BY0 registers.

Bit #

[7:4]

[3:0]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_NDIV[11:8]

Reserved.

0x0

PLL N Divider Byte 1. PLL Integer N Divider bits [11:8].

8.7.1.14 PLL_NDIV_BY0 Register; R26

The PLL_NDIV_BY0 register is described in the following table.

Bit #

Field

Type

Reset

EEPROM Description

Y PLL N Divider Byte 0. PLL Integer N Divider bits [7:0].

[7:0]

PLL_NDIV[7:0]

0x32

8.7.1.15 PLL_FRACNUM_BY2 Register; R27

The 22-bit Fractional Divider Numerator value for PLL is set by registers PLL_FRACNUM_BY2,

PLL_FRACNUM_BY1 and PLL_FRACNUM_BY0.

Bit #

[7:6]

[5:0]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_NUM[21:16]

Reserved.

0x00

PLL Fractional Divider Numerator Byte 2. Bits [21:16]

8.7.1.16 PLL_FRACNUM_BY1 Register; R28

The PLL_FRACNUM_BY1 register is described in the following table.

Bit #

Field

Type

Reset

EEPROM Description

Y PLL Fractional Divider Numerator Byte 1. Bits [15:8].

[7:0]

PLL_NUM[15:8]

0x00

8.7.1.17 PLL_FRACNUM_BY0 Register; R29

The PLL_FRACNUM_BY0 register is described in the following table.

Bit #

Field

Type

Reset

EEPROM Description

Y PLL Fractional Divider Numerator Byte 0. Bits [7:0].

[7:0]

PLL_NUM[7:0]

0x00

8.7.1.18 PLL_FRACDEN_BY2 Register; R30

The 22-bit Fractional Divider Denominator value for PLL is set by registers PLL_FRACDEN_BY2,

PLL_FRACDEN_BY1 and PLL_FRACDEN_BY0.

Bit #

[7:6]

[5:0]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_DEN[21:16]

Reserved.

0x00

PLL Fractional Divider Denominator Byte 2. Bits [21:16].

8.7.1.19 PLL_FRACDEN_BY1 Register; R31

The PLL_FRACDEN_BY1 register is described in the following table.

Bit #

Field

Type

Reset

EEPROM Description

Y PLL Fractional Divider Denominator Byte 1. Bits [15:8].

[7:0]

PLL_DEN[15:8]

0x00

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

8.7.1.20 PLL_FRACDEN_BY0 Register; R32

The PLL_FRACDEN_BY0 register is described in the following table.

Bit #

Field

Type

Reset

EEPROM Description

Y PLL Fractional Divider Denominator Byte 0. Bits [7:0].

[7:0]

PLL_DEN[7:0]

0x00

8.7.1.21 PLL_MASHCTRL Register; R33

The PLL_MASHCTRL register provides control of the fractional divider for PLL.

Bit #

[7:4]

[3:2]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_DTHRMODE[1:0]

Reserved.

0x3

Mash Engine dither mode control.

DITHERMODE

0 (0x0)

Dither Configuration

Weak

1 (0x1)

Reserved

Dither Disabled

2 (0x2)

3 (0x3)

[1:0]

PLL_ORDER[1:0]

0x0

Mash Engine Order.

ORDER

Order Configuration

Integer Mode Divider

Reserved

0 (0x0)

1 (0x1)

2 (0x2)

Reserved

3 (0x3)

3rd order

8.7.1.22 PLL_CTRL0 Register; R34

The PLL_CTRL1 register provides control of PLL. The PLL_CTRL1 register fields are described in the following

table.

Bit #

[7:6]

[5]

Field

Type

Reset

0x0

EEPROM Description

RESERVED

PLL_D

Reserved.

PLL R Divider Frequency Doubler Enable. If PLL_D is 1

the R Divider Frequency Doubler is enabled.

[4]

RESERVED

PLL_CP[3:0]

Reserved.

[3:0]

0x8

PLL Charge Pump Current. Other combinations of

PLL_CP[3:0] not in table below are reserved and not

supported.

PLL_CP[3:0]

4 (0x4)

PLL Charge Pump Current

1.6 mA

6.4 mA

8 (0x8)

LMK61E2

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8.7.1.23 PLL_CTRL1 Register; R35

The PLL_CTRL3 register provides control of PLL. The PLL_CTRL3 register fields are described in the following

table.

Bit #

[7]

Field

Type

Reset

EEPROM Description

RESERVED

Reserved.

[6:4]

PLL_CP_PHASE_SHIFT RW

[2:0]

0x0

Program Charge Pump Phase Shift.

PLL_CP_PHASE_SHIFT[ Phase Shift

2:0]

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

4 (0x4)

5 (0x5)

6 (0x6)

7 (0x7)

Reserved.

No delay

1.3 ns for 100 MHz f_PD

1 ns for 100 MHz f_PD

0.9 ns for 100 MHz f_PD

1.3 ns for 50 MHz f_PD

1 ns for 50 MHz f_PD

0.9 ns for 50 MHz f_PD

0.7 ns for 50 MHz f_PD

[3]

[2]

RESERVED

PLL_ENABLE_C3

Disable third order capacitor in the low pass filter.

PLL_ENABLE_C3

MODE

2nd order loop filter

recommended setting

Enables C3, 3rd order loop

filter enabled

[1:0]

RESERVED

0x3

Reserved.

8.7.1.24 PLL_LF_R2 Register; R36

The PLL_LF_R2 register controls the value of the PLL Loop Filter R2.

Bit #

Field

Type

Reset

EEPROM Description

[7:0]

PLL_LF_R2[7:0]

0x08

PLL Loop Filter R2. NOTE: Table below lists commonly

used R2 values but more selections are available.

PLL_LF_R2[7:0]

1 (0x01)

R2 (Ω)

200

4 (0x04)

500

8 (0x08)

700

32 (0x20)

48 (0x30)

64 (0x40)

1600

2400

3200

8.7.1.25 PLL_LF_C1 Register; R37

The PLL_LF_C1 register controls the value of the PLL Loop Filter C1.

Bit #

[7:3]

[2:0]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_LF_C1[2:0]

Reserved.

0x0

PLL Loop Filter C1. The value in pF is given by 5 + 50 *

PLL_LF_C1 (in decimal).

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

8.7.1.26 PLL_LF_R3 Register; R38

The PLL_LF_R3 register controls the value of the PLL Loop Filter R3.

Bit #

[7]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_LF_R3[6:0]

Reserved.

[6:0]

0x00

PLL Loop Filter R3. NOTE: Table below lists commonly

used R3 values but more selections are available.

PLL_LF_R3[6:0]

0 (0x00)

R3 (Ω)

3 (0x03)

205

8 (0x08)

854

9 (0x09)

1136

1535

1936

2335

12 (0x0C)

17 (0x11)

20 (0x14)

8.7.1.27 PLL_LF_C3 Register; R39

The PLL_LF_C3 register controls the value of the PLL Loop Filter C3.

Bit #

[7:3]

[2:0]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_LF_C3[2:0]

Reserved.

0x0

PLL Loop Filter C3. The value in pF is given by 5 *

PLL_LF_C3 (in decimal).

8.7.1.28 PLL_CALCTRL Register; R42

The PLL_CALCTRL register is described in the following table.

Bit #

[7:4]

[3:2]

Field

Type

Reset

EEPROM Description

RESERVED

PLL_CLSDWAIT[1:0]

Reserved.

0x2

Closed Loop Wait Period. The CLSDWAIT field sets the

closed loop wait period. Recommended value is 0x2.

CLSDWAIT

Anlog closed loop VCO

stabilization time

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

150 µs

300 µs

500 µs

2000 µs

[1:0]

PLL_VCOWAIT[1:0]

0x1

VCO Wait Period. Recommended value is 0x1.

VCOWAIT

0 (0x0)

VCO stabilization time

20 µs

1 (0x1)

400 µs

4000 µs

10000 µs

2 (0x2)

3 (0x3)

8.7.1.29 NVMSCRC Register; R47

The NVMSCRC register holds the Stored CRC (Cyclic Redundancy Check) byte that has been retreived from on-

chip EEPROM.

Bit #

Field

Type

Reset

EEPROM Description

Y EEPROM Stored CRC.

[7:0]

NVMSCRC[7:0]

0x00

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8.7.1.30 NVMCNT Register; R48

The NVMCNT register is intended to reflect the number of on-chip EEPROM Erase/Program cycles that have

taken place in EEPROM. The count is automatically incremented by hardware and stored in EEPROM.

Bit #

Field

Type

Reset

EEPROM Description

Y EEPROM Program Count. The NVMCNT increments

[7:0]

NVMCNT[7:0]

0x00

automatically after every EEPROM Erase/Program Cycle.

The NVMCNT value is retreived automatically after reset,

after a EEPROM Commit operation or after a Erase/Program

cycle. The NVMCNT register will increment until it reaches its

maximum value of 255 after which no further increments will

take place.

8.7.1.31 NVMCTL Register; R49

The NVMCTL register allows control of the on-chip EEPROM Memories.

Bit #

[7]

Field

Type

Reset

EEPROM Description

RESERVED

REGCOMMIT

Reserved.

[6]

RWSC

REG Commit to EEPROM SRAM Array. The REGCOMMIT bit

is used to initiate a transfer from the on-chip registers back to

the corresponding location in the EEPROM SRAM Array. The

REGCOMMIT bit is automatically cleared to 0 when the

transfer is complete.

[5]

[4]

[3]

NVMCRCERR

NVMAUTOCRC

NVMCOMMIT

EEPROM CRC Error Indication. The NVMCRCERR bit is set

to 1 if a CRC Error has been detected when reading back from

on-chip EEPROM during device configuration.

RWSC

EEPROM Automatic CRC. When NVMAUTOCRC is 1 then

the EEPROM Stored CRC byte is automatically calculated

whenever a EEPROM program takes place.

EEPROM Commit to Registers. The NVMCOMMIT bit is used

to initiate a transfer of the on-chip EEPROM contents to

internal registers. The transfer happens automatically after

reset or when NVMCOMMIT is set to 1. The NVMCOMMIT bit

is automatically cleared to 0. The I²C registers cannot be read

while a EEPROM Commit operation is taking place.

[2]

[1]

NVMBUSY

EEPROM Program Busy Indication. The NVMBUSY bit is 1

during an on-chip EEPROM Erase/Program cycle. While

NVMBUSY is 1 the on-chip EEPROM cannot be accessed.

NVMERASE

RWSC

EEPROM Erase Start. The NVMERASE bit is used to begin

an on-chip EEPROM Erase cycle. The Erase cycle is only

initiated if the immediately preceding I²C transaction was a

write to the NVMUNLK register with the appropriate code. The

NVMERASE bit is automatically cleared to 0. The EEPROM

Erase operation takes around 115ms.

[0]

NVMPROG

RWSC

EEPROM Program Start. The NVMPROG bit is used to begin

an on-chip EEPROM Program cycle. The Program cycle is

only initiated if the immediately preceding I²C transaction was

a write to the NVMUNLK register with the appropriate code.

The NVMPROG bit is automatically cleared to 0. If the

NVMERASE and NVMPROG bits are set simultaneously then

an ERASE/PROGRAM cycle will be executed The EEPROM

Program operation takes around 115ms.

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

8.7.1.32 MEMADR Register; R51

The MEMADR register holds 7-bits of the starting address for on-chip SRAM or EEPROM access.

Bit #

[7]

Field

Type

Reset

EEPROM Description

RESERVED

MEMADR[6:0]

Reserved.

[6:0]

0x00

Memory Address. The MEMADR value determines the starting

address for on-chip SRAM read/write access or on-chip

EEPROM access. The internal address to access SRAM or

EEPROM is automatically incremented; however the MEMADR

the SRAM or EEPROM arrays are accessed using the I²C

interface only bits [4:0] of MEMADR are used to form the byte

Wise address.

8.7.1.33 NVMDAT Register; R52

The NVMDAT register returns the on-chip EEPROM contents from the starting address specified by the

MEMADR register.

Bit #

Field

Type

Reset

EEPROM Description

EEPROM Read Data. The first time an I²C read transaction

[7:0]

NVMDAT[7:0]

0x00

accesses the NVMDAT register address, either because it was

explicitly targeted or because the address was auto-

incremented, the read transaction will return the EEPROM

data located at the address specified by the MEMADR

transaction will cause the EEPROM address to be

incremented and the next EEPROM data byte will be returned.

The I²C address will no longer be auto-incremented, i.e the

I²C address will be locked to the NVMDAT register after the

first access. Access to the NVMDAT register will terminate at

the end of the current I²C transaction.

8.7.1.34 RAMDAT Register; R53

The RAMDAT register provides read and write access to the SRAM that forms part of the on-chip EEPROM

module.

Bit #

Field

Type

Reset

EEPROM Description

RAM Read/Write Data. The first time an I²C read or write

[7:0]

RAMDAT[7:0]

0x00

transaction accesses the RAMDAT register address, either

because it was explicitly targeted or because the address was

auto-incremented, a read transaction will return the RAM data

located at the address specified by the MEMADR register and

a write transaction will cause the current I²C data to be written

to the address specified by the MEMADR register. Any

additional accesses which are part of the same transaction will

cause the RAM address to be incremented and a read or write

access will take place to the next SRAM address. The I²C

address will no longer be auto-incremented, i.e the I²C

address will be locked to the RAMDAT register after the first

access. Access to the RAMDAT register will terminate at the

end of the current I²C transaction.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

8.7.1.35 NVMUNLK Register; R56

The NVMUNLK register provides a rudimentary level of protection to prevent inadvertent programming of the on-

chip EEPROM.

Bit #

Field

Type

Reset

EEPROM Description

N EEPROM Prog Unlock. The NVMUNLK register must be

[7:0]

NVMUNLK[7:0]

0x00

written immediately prior to setting the NVMPROG bit of

be triggered. NVMUNLK must be written with a value of 0xBE.

8.7.1.36 INT_LIVE Register; R66

The INT_LIVE register reflects the current status of the interrupt sources.

Bit #

[7:2]

[1]

Field

Type

Reset

EEPROM Description

RESERVED

LOL

Reserved.

Loss of Lock PLL.

Calibration Active PLL.

[0]

CAL

8.7.1.37 SWRST Register; R72

The SWRST1 register provides software reset control for specific on-chip modules. Each bit in this register is

individually self cleared after a write operation. The SWRST1 register will always return 0x00 in a read

transaction.

Bit #

[7:2]

[1]

Field

Type

Reset

EEPROM Description

RESERVED

SWR2PLL

Reserved.

RWSC

Software Reset PLL. Setting SWR2PLL to 1 resets the PLL

calibrator and clock dividers. This bit is automatically cleared to

[0]

RESERVED

Reserved.

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMK61E2 is an ultra-low jitter programmable oscillator that can be used to provide reference clocks for high-

speed serial links resulting in improved system performance. The LMK61E2 also supports a variety of features

that aids the hardware designer during the system debug and validation phase.

9.2 Typical Applications

9.2.1 Jitter Considerations in Serdes Systems

Jitter-sensitive applications such as 10-Gbps or 100-Gbps Ethernet, deploy a serial link using a Serializer in the

transmit section (TX) and a De-serializer in the receive section (RX). These SERDES blocks are typically

embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of

the TX PLL bandwidth and the RX CDR bandwidth.

As can be seen in Figure 32, the pass band region between the TX low-pass cutoff and RX high-pass cutoff

frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of

the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec

or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR

bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC

or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification

that needs to be met, as related to the RX CDR bandwidth.

The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example,

IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10-Gbps Ethernet should be no more than

0.28 × UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter.

The jitter contributing elements are made up of the reference clock, generated potentially from a device like

LMK61E2, the transmit medium, transmit driver, and so forth. Only a portion of the overall allowable transmit jitter

is allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter, for a

20% clock jitter budget, is 5.43 ps, p-p.

Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or

mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other

uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout

buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern

fanout buffers have low-additive random jitter (less than 100 fs RMS) with no substantial contribution to the

deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the

primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is

to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This

amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For

serial link systems that need to meet a bit error rate (BER) of 10^–12, the allowable random jitter in root-mean-

square is 0.29 ps RMS. This is calculated by dividing the p-p jitter by 14 for a BER of 10^–12. Accounting for

random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps RMS. This is

calculated by the root-mean-square subtraction from the desired jitter at the fanout buffer's output assuming 100

fs RMS of additive jitter from the fanout buffer.

With careful frequency planning techniques, like spur optimization (covered in Spur Mitigation Techniques ) and

on-chip LDOs to suppress supply noise, the LMK61E2 is able to generate clock outputs with deterministic jitter

that is below 1 ps, p-p and random jitter that is below 0.2 ps RMS. This gives the serial link system with

additional margin on the allowable transmit jitter resulting in a BER better than 10^–12

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Applications (continued)

Parallel

Serializer

Data

Parallel

Data

Sampler

Serialized clock/data

Recovered

Clock

TX PLL

Ref Clk

CDR

Deserializer

Jitter Transfer (on clock)

Jitter Tolerance (on data)

Jitter Transfer (on clock)

F1 = TX_PLL_BWmax

F2 = RX_CDR_BWmin

Jitter Tolerance (on data)

SoC trend:

Increase stop band

Less % of jitter budget

Jitter Transfer (on clock)

SoC trend:

Decrease stop band

Improved LO design

Figure 32. Dependence of Clock Jitter in Serial Links

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

Typical Applications (continued)

9.2.2 Frequency Margining

9.2.2.1 Fine Frequency Margining

IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a

reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local

reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that

has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on

the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the

contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s

local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock

compensation.

To prevent such overflow and underflow errors from occurring, modern ASICs and FGPAs include a clock

compensation scheme that introduces elastic buffers. Such a system, shown in Figure 33, is validated thoroughly

during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3.

The LMK61E2 provides the ability to fine tune the frequency of its outputs based on changing its load

capacitance for the integrated oscillator. This fine tuning can be done through I²C as described in Integrated

Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E2

undergoes a smooth monotonic change in frequency.

9.2.2.2 Coarse Frequency Margining

Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%.

The LMK61E2 offers the ability to change its output divider for the desired change from its nominal output

frequency as explained in the High-Speed Output Divider section.

Post Processing

w/ clock

compensation

Serializer

TX PLL

Sampler

Serialized clock/data

Parallel

Data

Parallel

Data

Recovered

Clock

+/- 100 ppm

CDR

Ref Clk

+/- 100 ppm

Ref Clk

Deserializer

Elastic Buffer

(clock compensation)

FIFO

circular

Latency

Read

Pointer

Write

Pointer

Figure 33. System Implementation With Clock Compensation for Standards Compliance

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Applications (continued)

9.2.3 Design Requirements

Consider a typical wired communications application, like a top-of-rack switch, which needs to clock high data

rate 10-Gbps or 100-Gbps Ethernet PHYs. In such systems, the clock is expected to be available upon power up

without the need for any device-level programming. An example of such a clock frequency would be a 156.25

MHz in LVPECL output format.

The Detailed Design Procedure below describes the detailed design procedure to generate the required output

frequencies for the above scenario using LMK61E2.

9.2.3.1 Detailed Design Procedure

Design of all aspects of the LMK61E2 is simplified with software support that assists in part selection, part

programming, loop filter design, and phase noise simulation. This design procedure will give a quick outline of

the process.

1. Device Selection

–

The first step to calculate the specified VCO frequency given required output frequency. The device must

be able to produce the VCO frequency that can be divided down to the required output frequency.

–

The WEBENCH Clock Architect Tool from TI will aid in the selection of the right device that meets the

customer's output frequency and format requirements.

2. Device Configuration

–

There are many device configurations to achieve the desired output frequency from a device. However,

the user should consider some optimizations and trade-offs.

The WEBENCH Clock Architect Tool attempts to maximize the phase detector frequency, use smallest

dividers, and maximizes PLL charge pump current.

These guidelines below may be followed when configuring PLL related dividers or other related registers:

–

For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide

value.

For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge

pump currents often have similar performance due to diminishing returns.

For fractional divider values, keep the denominator at highest value possible in order to minimize

spurs. It is also best to use higher order modulator wherever possible for the same reason.

As a rule of thumb, keeping the phase detector frequency approximately between 10 × PLL loop

bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth

may be unstable and a phase.

3. PLL Loop Filter Design

–

It is recommended to use the WEBENCH Clock Architect Tool to design your loop filter.

Optimal loop filter design and simulation can be achieved when custom reference phase noise profiles

are loaded into the software tool.

–

While designing the loop filter, adjusting the charge pump current or N value can help with loop filter

component selection. Lower charge pump currents and larger N values result in smaller component

values but may increase impacts of leakage and reduce PLL phase noise performance.

For a more detailed understanding of loop filter design can be found in PLL Performance, Simulation, and

Design (SNAA106).

4. Device Programming

The EVM programming software tool CodeLoader can be used to program the device with the desired

configuration.

–

LMK61E2

www.ti.com.cn

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

Typical Applications (continued)

9.2.3.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMK61E2 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.3.1.2 Device Selection

Use the WEBENCH Clock Architect Tool. Enter the required output frequencies and formats into the tool. To use

this device, find a solution using the LMK61E2.

9.2.3.1.3 VCO Frequency Calculation

In this example, the VCO frequency of the LMK61E2 to generate 156.25 MHz can be calculated as 5 GHz.

9.2.3.1.4 Device Configuration

For this example, enter the desired output frequency and click on Generate Solutions. Select LMK61E2 from the

solution list. From the simulation page of the WEBENCH Clock Architect Tool, it can be seen that to maximize

phase detector frequency, PLL R divider is set to 1, doubler is enabled and N divider is set to 50 for a PFD

frequency of 100 MHz. This results in a VCO frequency of 5 GHz. At this point the design meets the output

frequency requirements and it is possible to design a loop filter for system and simulate performance on the

clock output.

9.2.3.1.5 PLL Loop Filter Design

In the WEBENCH Clock Architect Tool simulator, click on the PLL loop filter design button, then press

recommend design. For the PLL loop filter, maximum phase detector frequency and maximum charge pump

current are typically used. The tool recommends a loop filter that is designed to minimize jitter. The integrated

loop filter’s components are minimized with this recommendation as to allow maximum flexibility in achieving

wide loop bandwidths for low PLL noise. With the recommended loop filter calculated, this loop filter is ready to

be simulated.

The PLL loop filter’s bode plot can additionally be viewed and adjustments can be made to the integrated

components. The effective loop bandwidth and phase margin with the updated values is then calculated. The

integrated loop filter components are good to use when attempting to eliminate certain spurs. The recommended

procedure is to increase C3 capacitance, then R3 resistance. Large R3 resistance can result in degraded VCO

phase noise performance.

9.2.3.1.6 Spur Mitigation Techniques

The LMK61E2 offers several programmable features for optimizing fractional spurs. In order to get the best out of

these features, it makes sense to understand the different kinds of spurs as well as their behaviors, causes, and

remedies. Although optimizing spurs may involve some trial and error, there are ways to make this process more

systematic. TI offers the Clock Design Tool for more information and estimation of fractional spurs.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Applications (continued)

9.2.3.1.6.1 Phase Detection Spur

The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, f_PD. To

minimize this spur, a lower phase detector frequency should be considered. In some cases where the loop

bandwidth is very wide relative to the phase detector frequency, some benefit might be gained from using a

narrower loop bandwidth or adding poles to the loop filter by using R3 and C3 if previously unused, but otherwise

the loop filter has minimal impact. Bypassing at the supply pins and board layout can also have an impact on this

spur, especially at higher phase detector frequencies.

9.2.3.1.6.2 Integer Boundary Fractional Spur

This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel

for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency is 5003 MHz,

then the integer boundary spur would be at 3-MHz offset. This spur can be either PLL or VCO dominated. If it is

PLL dominated, decreasing the loop bandwidth and some of the programmable fractional words may impact this

spur. If the spur is VCO dominated, then reducing the loop filter will not help, but rather reducing the phase

detector and having good slew rate and signal integrity at the selected reference input will help.

9.2.3.1.6.3 Primary Fractional Spur

These spurs occur at multiples of f_PD/DEN and are not the integer boundary spur. For instance, if the phase

detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at 1 MHz, 2 MHz,

4 MHz, 5 MHz, 6 MHz, and so forth. These are impacted by the loop filter bandwidth and modulator order. If a

small frequency error is acceptable, then a larger equivalent fraction may improve these spurs. This larger

unequivalent fraction pushes the fractional spur energy to much lower frequencies that where they are not

impactful to the system performance.

9.2.3.1.6.4 Sub-Fractional Spur

These spurs appear at a fraction of f_PD/DEN and depend on modulator order. With the first order modulator, there

are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if the denominator

is even. A third order modulator can produce sub-fractional spurs at 1/2, 1/3, or 1/6 of the offset, depending if it is

divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, no sub-

fractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a second or third

order modulator would be expected. Aside from strategically choosing the fractional denominator and using a

lower order modulator, another tactic to eliminate these spurs is to use dithering and express the fraction in

larger equivalent terms. Because dithering also adds phase noise, its level needs to be managed to achieve

acceptable phase noise and spurious performance.

LMK61E2

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ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

Typical Applications (continued)

Table 2 summarizes spur and mitigation techniques.

Table 2. Spur and Mitigation Techniques

SPUR TYPE

OFFSET

WAYS TO REDUCE

TRADE-OFFS

Phase Detector

f_PD

Reduce Phase Detector

Frequency.

Although reducing the phase

detector frequency does improve

this spur, it also degrades phase

noise.

Integer Boundary

f_VCOmod f_PD

Methods for PLL Dominated

Spurs

Avoid the worst case VCO

frequencies if possible.

Reducing the loop bandwidth

may degrade the total integrated

noise if the bandwidth is too

narrow.

Ensure good slew rate and

signal integrity at reference input.

Reduce loop bandwidth or

add more filter poles to suppress

out of band spurs.

Methods for VCO Dominated

Spurs

Avoid the worst case VCO

frequencies if possible.

Reducing the phase detector

may degrade the phase noise.

Reduce Phase Detector

Frequency.

Ensure good slew rate and

signal integrity at reference input.

Primary Fractional

Sub-Fractional

f_PD/DEN

Decrease Loop Bandwidth.

Change Modulator Order.

Decreasing the loop bandwidth

may degrade in-band phase

noise. Also, larger unequivalent

fractions don’t always reduce

spurs.

Use Larger Unequivalent

Fractions.

f_PD/DEN/k k=2,3, or 6

Use Dithering.

Use Larger Equivalent

Fractions.

Use Larger Unequivalent

Fractions.

Dithering and larger fractions

may increase phase noise.

Reduce Modulator Order.

Eliminate factors of 2 or 3 in

denominator.

10 Power Supply Recommendations

For best electrical performance of the LMK61E2 device, it is preferred to use a combination of 10 µF, 1 µF, and

0.1 µF on its power supply bypass network. ITI also recommends using component side mounting of the power

supply bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep

the connections between the bypass capacitors and the power supply on the device as short as possible. Ground

the other side of the capacitor using a low impedance connection to the ground plane. Figure 34 shows the

layout recommendation for power supply decoupling of LMK61E2.

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

Ensured Thermal Reliability, Best Practices for Signal Integrity and Recommended Solder Reflow Profile provide

recommendations for board layout, solder reflow profile and power supply bypassing when using LMK61E2 to

ensure good thermal / electrical performance and overall signal integrity of entire system.

11.1.1 Ensured Thermal Reliability

The LMK61E2 is a high performance device. Therefore careful attention must be paid to device configuration and

printed circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to

the ground plane of the PCB through three vias or more, as shown in Figure 34, to maximize thermal dissipation

out of the package.

Equation 3 describes the relationship between the PCB temperature around the LMK61E2 and its junction

temperature.

T_B= T_J– Ψ_JB* P

where

•

T_B: PCB temperature around the LMK61E2

T_J: Junction temperature of LMK61E2

Ψ_JB: Junction-to-board thermal resistance parameter of LMK61E2 (36.7°C/W without airflow)

P: On-chip power dissipation of LMK61E2

(3)

In order to ensure that the maximum junction temperature of LMK61E2 is below 125°C, it can be calculated that

the maximum PCB temperature without airflow should be at 100°C or below when the device is optimized for

best performance resulting in maximum on-chip power dissipation of 0.68 W.

11.1.2 Best Practices for Signal Integrity

For best electrical performance and signal integrity of entire system with LMK61E2, it is recommended to route

vias into decoupling capacitors and then into the LMK61E2. It is also recommended to increase the via count and

width of the traces wherever possible. These steps ensure lowest impedance and shortest path for high

frequency current flow. Figure 34 shows the layout recommendation for LMK61E2.

11.1.3 Recommended Solder Reflow Profile

It is recommended to follow the solder paste supplier's recommendations to optimize flux activity and to achieve

proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the LMK61E2 to be

processed with the lowest peak temperature possible while also remaining below the components peak

temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors

including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB

material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures

recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.

LMK61E2

www.ti.com.cn

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

11.2 Layout Example

Figure 34. LMK61E2 Layout Recommendation for Power Supply and Ground

LMK61E2

ZHCSE74B –SEPTEMBER 2015–REVISED FEBRUARY 2017

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

相关开发支持，请参见以下文档：

•

WEBENCH 时钟架构工具

CodeLoader

12.1.1.1 使用 WEBENCH® 工具定制设计方案

请单击此处，使用 LMK61E2 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 在开始阶段键入输出电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键设计参数，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

12.2 文档支持

12.2.1 相关文档

LMK61E2 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E