LMP7712MM/NOPB [TI]
具有关断功能的双通道、17MHz、低噪声、低偏置电流、CMOS 输入、精密放大器 | DGS | 10 | -40 to 125;
| 型号： | LMP7712MM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断功能的双通道、17MHz、低噪声、低偏置电流、CMOS 输入、精密放大器 | DGS | 10 | -40 to 125 放大器 光电二极管 |
| 文件： | 总26页 (文件大小：1017K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP7711
www.ti.com
SNOSAP4F –SEPTEMBER 2005–REVISED MAY 2013
Single and Dual Precision, 17 MHz, Low Noise, CMOS Input Amplifiers
Check for Samples: LMP7711
1
FEATURES
DESCRIPTION
The LMP7711/LMP7712 are single and dual low
noise, low offset, CMOS input, rail-to-rail output
precision amplifiers with a high gain bandwidth
product and an enable pin. The LMP7711/LMP7712
are part of the LMP™ precision amplifier family and
are ideal for a variety of instrumentation applications.
23
•
Unless Otherwise Noted, Typical Values at VS
= 5V.
•
Input Offset Voltage ±150 μV (Max)
Input Bias Current 100 fA
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Noise 5.8 nV/√Hz
Gain Bandwidth Product 17 MHz
Supply Current (LMP7711) 1.15 mA
Supply Current (LMP7712) 1.30 mA
Supply Voltage Range 1.8V to 5.5V
THD+N @ f = 1 kHz 0.001%
Utilizing a CMOS input stage, the LMP7711/LMP7712
achieve an input bias current of 100 fA, an input
referred voltage noise of 5.8 nV/√Hz, and an input
offset voltage of less than ±150 μV. These features
make the LMP7711/LMP7712 superior choices for
precision applications.
Consuming only 1.15 mA of supply current, the
LMP7711 offers a high gain bandwidth product of 17
MHz, enabling accurate amplification at high closed
loop gains.
Operating Temperature Range −40°C to 125°C
Rail-to-rail Output Swing
Space Saving SOT Package (LMP7711)
10-pin VSSOP Package (LMP7712)
The LMP7711/LMP7712 have a supply voltage range
of 1.8V to 5.5V, which makes these ideal choices for
portable low power applications with low supply
voltage requirements. In order to reduce the already
low power consumption the LMP7711/LMP7712 have
an enable function. Once in shutdown, the
LMP7711/LMP7712 draw only 140 nA of supply
current.
APPLICATIONS
•
•
•
Active Filters and Buffers
Sensor Interface Applications
Transimpedance Amplifiers
The LMP7711/LMP7712 are built with TI's advanced
VIP50 process technology. The LMP7711 is offered
in a 6-pin SOT package and the LMP7712 is offered
in a 10-pin VSSOP.
TYPICAL PERFORMANCE
Offset Voltage Distribution
Input Referred Voltage Noise
100
25
V
V
= 5V
S
V = 5.5V
S
= V /2
S
CM
20 UNITS TESTED: 10,000
V
= 2.5V
S
15
10
5
10
1
0
-200
1k
1
10
100
10k
100k
-100
0
100
200
FREQUENCY (Hz)
OFFSET VOLTAGE (mV)
Figure 1.
Figure 2.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LMP7711
SNOSAP4F –SEPTEMBER 2005–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
ESD Tolerance(3)
Human Body Model
Machine Model
2000V
200V
Charge-Device Model
1000V
VIN Differential
±0.3V
Supply Voltage (VS = V+ – V−)
Voltage on Input/Output Pins
Storage Temperature Range
Junction Temperature(4)
Soldering Information
6.0V
V+ +0.3V, V− −0.3V
−65°C to 150°C
+150°C
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temp. (10 sec)
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state electrical specifications
under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings.
Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device
performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
OPERATING RATINGS(1)
Temperature Range(2)
Supply Voltage (VS = V+ – V−)
−40°C to 125°C
1.8V to 5.5V
2.0V to 5.5V
170°C/W
0°C ≤ TA ≤ 125°C
−40°C ≤ TA ≤ 125°C
6-Pin SOT
(2)
Package Thermal Resistance (θJA
)
10-Pin VSSOP
236°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state electrical specifications
under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings.
Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device
performance.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
2
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SNOSAP4F –SEPTEMBER 2005–REVISED MAY 2013
2.5V ELECTRICAL CHARACTERISTICS
Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2, VEN = V+. Boldface limits
apply at the temperature extremes.
Symbol
Parameter
Input Offset Voltage
Conditions
Min(1)
Typ(2)
Max(1)
Units
VOS
±20
±180
μV
±480
TC VOS Input Offset Voltage Temperature
Drift(3)(4)
LMP7711
LMP7712
–1.75
–1
±4
μV/°C
IB
Input Bias Current
VCM = 1.0V(5)(4)
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
0.05
1
25
pA
0.05
0.006
100
100
98
1
100
IOS
Input Offset Current
VCM = 1.0V(4)
0.5
50
pA
dB
CMRR Common Mode Rejection Ratio
PSRR Power Supply Rejection Ratio
0V ≤ VCM ≤ 1.4V
83
80
2.0V ≤ V+ ≤ 5.5V
85
80
V− = 0V, VCM = 0
dB
V
1.8V ≤ V+ ≤ 5.5V
85
V− = 0V, VCM = 0
CMVR Common Mode Voltage Range
CMRR ≥ 80 dB
CMRR ≥ 78 dB
−0.3
–0.3
1.5
1.5
AVOL
Open Loop Voltage Gain
LMP7711, VO = 0.15 to 2.2V
88
82
98
92
RL = 2 kΩ to V+/2
LMP7712, VO = 0.15 to 2.2V
84
80
RL = 2 kΩ to V+/2
dB
LMP7711, VO = 0.15 to 2.2V
92
88
114
95
RL = 10 kΩ to V+/2
LMP7712, VO = 0.15 to 2.2V
90
86
RL = 10 kΩ to V+/2
VOUT
Output Voltage Swing
High
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
25
70
77
20
60
66
mV from
either rail
Output Voltage Swing
Low
30
70
73
15
60
62
IOUT
Output Current
Supply Current
Sourcing to V−
VIN = 200 mV(6)
36
30
52
mA
mA
Sinking to V+
7.5
5.0
15
VIN = −200 mV(6)
IS
LMP7711
Enable Mode VEN ≥ 2.1
0.95
1.10
0.03
1.30
1.65
LMP7712 (per channel)
Enable Mode VEN ≥ 2.1
1.50
1.85
Shutdown Mode (per channel)
1
4
μA
VEN ≤ 0.4
SR
Slew Rate
AV = +1, Rising (10% to 90%)
AV = +1, Falling (90% to 10%)
8.3
V/μs
10.3
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
(6) The short circuit test is a momentary open loop test.
Copyright © 2005–2013, Texas Instruments Incorporated
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2.5V ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2, VEN = V+. Boldface limits
apply at the temperature extremes.
Symbol
GBW
en
Parameter
Gain Bandwidth
Conditions
Min(1)
Typ(2)
14
Max(1)
Units
MHz
Input Referred Voltage Noise Density
f = 400 Hz
f = 1 kHz
f = 1 kHz
6.8
nV/√Hz
5.8
in
Input Referred Current Noise Density
Turn-on Time
0.01
140
pA/√Hz
ns
ton
toff
VEN
Turn-off Time
1000
2 - 2.5
0 - 0.5
1.5
ns
Enable Pin Voltage Range
Enable Mode
2.1
V
Shutdown Mode
VEN = 2.5V(5)
VEN = 0V(5)
0.4
3.0
0.1
IEN
Enable Pin Input Current
μA
0.003
0.003
THD+N Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, RL = 100 kΩ
VO = 0.9 VPP
%
f = 1 kHz, AV = 1, RL = 600Ω
0.004
VO = 0.9 VPP
5V ELECTRICAL CHARACTERISTICS
Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VEN = V+. Boldface limits apply at
the temperature extremes.
Symbol
Parameter
Input Offset Voltage
Conditions
Min(1)
Typ(2)
Max(1)
Units
VOS
±10
±150
μV
±450
TC VOS Input Offset Voltage Temperataure
Drift(3)(4)
LMP7711
LMP7712
–1.75
–1
±4
μV/°C
IB
Input Bias Current
VCM = 2.0V(5)(4)
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
0.1
1
25
pA
0.1
0.01
100
100
98
1
100
IOS
Input Offset Current
VCM = 2.0V(4)
0.5
50
pA
dB
CMRR Common Mode Rejection Ratio
PSRR Power Supply Rejection Ratio
0V ≤ VCM ≤ 3.7V
85
82
2.0V ≤ V+ ≤ 5.5V
85
80
V− = 0V, VCM = 0
dB
V
1.8V ≤ V+ ≤ 5.5V
85
V− = 0V, VCM = 0
CMVR Common Mode Voltage Range
CMRR ≥ 80 dB
CMRR ≥ 78 dB
−0.3
–0.3
4
4
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(4) This parameter is specified by design and/or characterization and is not tested in production.
(5) Positive current corresponds to current flowing into the device.
4
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LMP7711
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SNOSAP4F –SEPTEMBER 2005–REVISED MAY 2013
5V ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VEN = V+. Boldface limits apply at
the temperature extremes.
Symbol
Parameter
Conditions
Min(1)
Typ(2)
Max(1)
Units
AVOL
Open Loop Voltage Gain
LMP7711, VO = 0.3 to 4.7V
88
82
107
RL = 2 kΩ to V+/2
LMP7712, VO = 0.3 to 4.7V
84
80
90
114
95
RL = 2 kΩ to V+/2
dB
LMP7711, VO = 0.3 to 4.7V
92
88
RL = 10 kΩ to V+/2
LMP7712, VO = 0.3 to 4.7V
90
86
RL = 10 kΩ to V+/2
VOUT
Output Voltage Swing
High
RL = 2 kΩ to V+/2
32
70
77
RL = 10 kΩ to V+/2
22
60
66
mV from
either rail
Output Voltage Swing
Low
RL = 2 kΩ to V+/2
(LMP7711)
42
70
73
RL = 2 kΩ to V+/2
50
75
(LMP7712)
78
RL = 10 kΩ to V+/2
20
60
62
IOUT
Output Current
Supply Current
Sourcing to V−
VIN = 200 mV(6)
46
38
66
mA
Sinking to V+
10.5
6.5
23
VIN = −200 mV(6)
IS
LMP7711
Enable Mode VEN ≥ 4.6
1.15
1.30
0.14
1.40
1.75
mA
LMP7712 (per channel)
Enable Mode VEN ≥ 4.6
1.70
2.05
Shutdown Mode VEN ≤ 0.4
1
4
μA
(per channel)
SR
Slew Rate
AV = +1, Rising (10% to 90%)
AV = +1, Falling (90% to 10%)
6.0
7.5
9.5
11.5
17
V/μs
MHz
GBW
en
Gain Bandwidth
Input Referred Voltage Noise Density
f = 400 Hz
f = 1 kHz
f = 1 kHz
7.0
nV/√Hz
5.8
in
Input Referred Current Noise Density
Turn-on Time
0.01
114
pA/√Hz
ns
ton
toff
VEN
Turn-off Time
800
ns
Enable Pin Voltage Range
Enable Mode
Shutdown Mode
VEN = 5V(7)
4.6
4.5 – 5
0 – 0.5
5.6
V
0.4
10
IEN
Enable Pin Input Current
μA
VEN = 0V(7)
0.005
0.001
0.2
THD+N Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, RL = 100 kΩ
VO = 4 VPP
%
f = 1 kHz, AV = 1, RL = 600Ω
0.004
VO = 4 VPP
(6) The short circuit test is a momentary open loop test.
(7) Positive current corresponds to current flowing into the device.
Copyright © 2005–2013, Texas Instruments Incorporated
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CONNECTION DIAGRAM
6
5
+
1
+
V
OUTPUT
1
2
3
10
9
V
OUT A
-IN A
OUT B
-
EN
+
2
3
-
V
-
+
+IN A
-IN B
+IN B
EN B
8
7
6
-
+
-
4
4
5
V
-IN
+IN
EN A
Figure 3. 6-Pin SOT - Top View
See Package Number DDC
Figure 4. 10-Pin VSSOP-Top View
See Package Number DGS
6
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SNOSAP4F –SEPTEMBER 2005–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Offset Voltage Distribution
TCVOS Distribution (LMP7711)
25
20
25
20
V
V
= 2.5V
S
-40°C Ç T Ç 125èC
A
= V /2
CM
S
V
V
= 2.5V, 5V
S
UNITS TESTED:10,000
= V /2
CM
S
UNITS TESTED:
10,000
15
10
5
15
10
5
0
-200
0
-100
0
100
200
-4
-3
-2
TCV
-1
0
1
2
(mV/°C)
OFFSET VOLTAGE (mV)
OS
Figure 5.
Figure 6.
Offset Voltage Distribution
TCVOS Distribution (LMP7712)
25
25
-40°C Ç T Ç 125°C
A
V
V
= 5V
S
V
= 2.5V, 5V
S
= V /2
CM
S
20
20 UNITS TESTED: 10,000
V
= V /2
CM
S
UNITS TESTED:
10,000
15
10
5
15
10
5
0
0
-200
-100
0
100
200
-4
-3
-2
(mV/°C)
-1
0
OFFSET VOLTAGE (mV)
TCV
OS
Figure 7.
Figure 8.
Offset Voltage vs. VCM
Offset Voltage vs. VCM
200
200
150
100
50
V
S
= 1.8V
V
S
= 2.5V
150
100
50
-40°C
-40°C
25°C
25°C
0
0
125°C
-50
-50
125°C
-100
-150
-200
-100
-150
-200
-0.3
0
0.3
0.9
1.2
1.5
0.6
(V)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1
(V)
-0.3
V
CM
V
CM
Figure 9.
Figure 10.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Offset Voltage vs. VCM
Offset Voltage vs. Supply Voltage
200
150
100
50
200
V
= 5V
S
150
100
-40°C
25°C
-40°C
25°C
50
0
0
125°C
125°C
-50
-50
-100
-150
-200
-100
-150
-200
1.5
2.5
3.5
4.5
5.5
6
-0.3
0.7
1.7
2.7
(V)
3.7
4.7
V
S
(V)
V
CM
Figure 11.
Figure 12.
CMRR vs. Frequency
Offset Voltage vs. Temperature
150
100
120
100
V
S
= 2.5V
50
0
V
= 2.5V
S
80
60
V
= 5V
S
LMP7711
-50
40
20
-100
-150
V
= 5V
S
LMP7712
-200
0
10
10k
100
1k
100k
1M
-40 -20
0
20 40 60 80 100 120 125
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 13.
Figure 14.
Input Bias Current Over Temperature
Input Bias Current Over Temperature
1000
50
40
30
V
S
= 5V
V
S
= 5V
25°C
500
0
20
10
125°C
-500
-1000
-1500
-2000
-2500
-3000
-40°C
0
-10
-20
85°C
-30
-40
-50
0
1
2
3
4
0
1
2
3
4
V
(V)
V
CM
(V)
CM
Figure 15.
Figure 16.
8
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SNOSAP4F –SEPTEMBER 2005–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Supply Current vs. Supply Voltage (LMP7711)
Supply Current vs. Supply Voltage (LMP7712)
2
2
125°C
1.6
1.6
125°C
25°C
25°C
1.2
1.2
-40°C
0.8
0.8
-40°C
0.4
0
0.4
0
1.5
2.5
3.5
(V)
4.5
5.5
1.5
2.5
3.5
(V)
4.5
5.5
V
V
S
S
Figure 17.
Figure 18.
Supply Current vs. Supply Voltage (Shutdown)
Crosstalk Rejection Ratio (LMP7712)
160
140
1.8
1.6
125°C
1.4
120
100
80
60
40
20
0
1.2
1
0.8
0.6
25°C
0.4
0.2
-40°C
4.5
0
1M
10M
1k
10k
100k
100M
1.5
2.5
3.5
5.5
FREQUENCY (Hz)
V
(V)
S
Figure 19.
Figure 20.
Supply Current vs. Enable Pin Voltage (LMP7711)
Supply Current vs. Enable Pin Voltage (LMP7711)
1.5
2.4
V
= 2.5V
125°C
V
= 5V
S
S
125°C
1.3
1.1
0.9
1.9
25°C
25°C
1.4
0.9
-40°C
0.7
0.5
-40°C
-40°C
0.3
0.1
0.4
125°C
-0.1
-0.1
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
ENABLE PIN VOLTAGE (V)
ENABLE PIN VOLTAGE (V)
Figure 21.
Figure 22.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Supply Current vs. Enable Pin Voltage (LMP7712)
Supply Current vs. Enable Pin Voltage (LMP7712)
1.7
2.4
125°C
V
= 2.5V
S
V
= 5V
S
1.5
1.3
1.1
125°C
1.9
25°C
1.4
0.9
25°C
0.9
0.7
0.5
0.3
0.1
-0.1
-40°C
-40°C
-40°C
25°C
125°C
0.4
-0.1
0
0.5
1
1.5
2
2.5
0
1
2
3
4
5
ENABLE PIN VOLTAGE (V)
ENABLE PIN VOLTAGE (V)
Figure 23.
Figure 24.
Sourcing Current vs. Supply Voltage
Sinking Current vs. Supply Voltage
80
35
30
25
20
15
125°C
70
125°C
60
50
25°C
-40°C
25°C
40
30
10
5
-40°C
20
10
0
0
1.5
2.5
3.5
V (V)
4.5
5.5
1.5
2.5
3.5
(V)
4.5
5.5
V
S
S
Figure 25.
Figure 26.
Sourcing Current vs. Output Voltage
Sinking Current vs. Output Voltage
30
25
70
125°C
125°C
60
50
40
30
20
20
15
10
-40°C
25°C
25°C
-40°C
5
0
10
0
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)
OUT
V
(V)
OUT
Figure 27.
Figure 28.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Output Swing High vs. Supply Voltage
Output Swing Low vs. Supply Voltage
50
50
40
30
R
L
= 10 kW
R =10 kW
L
40
30
25°C
125°C
-40°C
20
10
0
20
10
0
125°C
-40°C
25°C
1.5
2.5
3.5
(V)
4.5
5.5
1.5
2.5
3.5
(V)
4.5
5.5
V
V
S
S
Figure 29.
Figure 30.
Output Swing High vs. Supply Voltage
Output Swing Low vs. Supply Voltage
50
50
40
30
R
= 2 kW
L
-40°C
40
30
125°C
25°C
125°C
25°C
20
10
0
20
10
0
-40°C
R
= 2 kW
L
1.5
2.5
3.5
(V)
4.5
5.5
1.5
2.5
3.5
(V)
4.5
5.5
V
V
S
S
Figure 31.
Figure 32.
Output Swing High vs. Supply Voltage
Output Swing Low vs. Supply Voltage
150
120
90
150
120
90
R = 600W
L
R
= 600W
L
25°C
125°C
125°C
25°C
-40°C
60
30
0
60
30
0
-40°C
1.5
2.5
3.5
(V)
4.5
5.5
1.5
2.5
3.5
(V)
4.5
5.5
V
V
S
S
Figure 33.
Figure 34.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Open Loop Frequency Response
Open Loop Frequency Response
120
100
120
120
100
80
120
100
80
PHASE
PHASE
100
C
L
= 20 pF
80
60
80
60
C
L
= 50 pF
60
60
GAIN
C
L
= 100 pF
40
20
0
40
20
0
40
20
0
40
20
0
GAIN
C
= 20 pF
= 50 pF
L
-20
-40
-20
-40
-60
-20
-40
-60
-20
-40
C
L
C
= 100 pF
L
R
= 600W, 10 kW, 10 MW
L
-60
-60
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35.
Figure 36.
Phase Margin vs. Capacitive Load
Phase Margin vs. Capacitive Load
50
50
R
L
= 600W
40
30
40
30
R
L
= 600W
R
L
= 10 kW
R
L
= 10 kW
R
L
= 10 MW
20
20
10
0
R
L
= 10 MW
10
0
V
= 2.5V
V
= 5V
S
S
10
100
1000
10
100
1000
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 37.
Figure 38.
Overshoot and Undershoot vs. Capacitive Load
Slew Rate vs. Supply Voltage
70
12
UNDERSHOOT%
60
FALLING EDGE
11
10
50
OVERSHOOT %
40
30
20
9
8
7
RISING EDGE
10
0
0
20
40
80
100 120
60
1.5
2.5
3.5
4.5
5.5
6
CAPACITIVE LOAD (pF)
V
(V)
S
Figure 39.
Figure 40.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Small Signal Step Response
Large Signal Step Response
V
= 20 mV
PP
V
= 1 V
IN
IN
PP
f = 1 MHz, A = +1
f = 200 kHz, A = +1
V
V
V
= 2.5V, C = 10 pF
L
V
= 2.5V, C = 10 pF
L
S
S
200 ns/DIV
800 ns/DIV
Figure 41.
Figure 42.
Small Signal Step Response
Large Signal Step Response
V
= 20 mV
PP
IN
V
= 1 V
PP
IN
f = 200 kHz, A = +1
f = 1 MHz, A = +1
V
V
V
= 5V, C = 10 pF
L
V
= 5V, C = 10 pF
S
S
L
200 ns/DIV
800 ns/DIV
Figure 43.
Figure 44.
THD+N vs. Output Voltage
THD+N vs. Output Voltage
0
0
V
= 1.8V
V
= 5.5V
S
S
f = 1 kHz
f = 1 kHz
-20
-40
-20
-40
A
= +2
A
= +2
V
V
-60
-80
R
L
= 600W
-60
-80
R
L
= 600W
-100
-120
-140
-100
R
= 100 kW
L
R
= 100 kW
L
-120
0.01
0.1
1
10
0.01
0.1
1
10
OUTPUT AMPLITUDE (V
)
PP
OUTPUT AMPLITUDE (V
)
PP
Figure 45.
Figure 46.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
THD+N vs. Frequency
THD+N vs. Frequency
0.006
0.006
0.005
0.004
0.003
0.002
0.001
0
V
V
A
= 1.8V
= 0.9 V
= +2
V
V
A
= 5V
S
O
V
S
O
V
= 4 V
= +2
PP
PP
0.005
0.004
0.003
0.002
0.001
0
R
L
= 600W
R
L
= 600W
R
= 100 kW
L
R
L
= 100 kW
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47.
Figure 48.
PSRR vs. Frequency
Time Domain Voltage Noise
120
100
V
V
= ±2.5V
S
V
= 5.5V, -PSRR
S
= 0.0V
CM
V
= 1.8V, -PSRR
S
80
60
40
20
V
= 5.5V, +PSRR
S
V
= 1.8V, +PSRR
S
0
1 s/DIV
10k
1M
10
1k
100k
10M
100
FREQUENCY (Hz)
Figure 49.
Figure 50.
Input Referred Voltage Noise vs. Frequency
Closed Loop Frequency Response
100
5
225
V
= 5V
S
V
= 5.5V
S
180
4
3
2
R
= 2 kW
L
L
135
90
C
= 20 pF
V
A
= 2 V
= +1
O
V
PP
V
= 2.5V
S
1
0
45
10
0
-45
-90
-135
-1
-2
-3
-4
-5
PHASE
GAIN
-180
1
-225
1k
1
10
100
10k
100k
100 k
1M
100
1k
10k
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 51.
Figure 52.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2, VEN = V+.
Closed Loop Output Impedance vs. Frequency
100
10
1
0.1
0.01
100M
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 53.
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APPLICATION NOTES
LMP7711/LMP7712
The LMP7711/LMP7712 are single and dual, low noise, low offset, rail-to-rail output precision amplifiers with a
wide gain bandwidth product of 17 MHz and low supply current. The wide bandwidth makes the
LMP7711/LMP7712 ideal choices for wide-band amplification in portable applications. The low supply current
along with the enable feature that is built-in on the LMP7711/LMP7712 allows for even more power efficient
designs by turning the device off when not in use.
The LMP7711/LMP7712 are superior for sensor applications. The very low input referred voltage noise of only
5.8 nV/√Hz at 1 kHz and very low input referred current noise of only 10 fA/ √Hz mean more signal fidelity and
higher signal-to-noise ratio.
The LMP7711/LMP7712 have a supply voltage range of 1.8V to 5.5V over a wide temperature range of 0°C to
125°C. This is optimal for low voltage commercial applications. For applications where the ambient temperature
might be less than 0°C, the LMP7711/LMP7712 are fully operational at supply voltages of 2.0V to 5.5V over the
temperature range of −40°C to 125°C.
The outputs of the LMP7711/LMP7712 swing within 25 mV of either rail providing maximum dynamic range in
applications requiring low supply voltage. The input common mode range of the LMP7711/LMP7712 extends to
300 mV below ground. This feature enables users to utilize this device in single supply applications.
The use of a very innovative feedback topology has enhanced the current drive capability of the
LMP7711/LMP7712, resulting in sourcing currents as much as 47 mA with a supply voltage of only 1.8V.
The LMP7711 is offered in the space saving SOT package and the LMP7712 is offered in a 10-pin VSSOP.
These small packages are ideal solutions for applications requiring minimum PC board footprint.
Texas Instruments is heavily committed to precision amplifiers and the market segments they serves. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
CAPACITIVE LOAD
The unity gain follower is the most sensitive configuration to capacitive loading. The combination of a capacitive
load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a
phase lag which in turn reduces the phase margin of the amplifier. If phase margin is significantly reduced, the
response will be either underdamped or the amplifier will oscillate.
The LMP7711/LMP7712 can directly drive capacitive loads of up to 120 pF without oscillating. To drive heavier
capacitive loads, an isolation resistor, RISO in Figure 54, should be used. This resistor and CL form a pole and
hence delay the phase lag or increase the phase margin of the overall system. The larger the value of RISO, the
more stable the output voltage will be. However, larger values of RISO result in reduced output swing and
reduced output current drive.
Figure 54. Isolating Capacitive Load
INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The
LMP7711/LMP7712 enhance this performance by having the low input bias current of only 50 fA, as well as, a
very low input referred voltage noise of 5.8 nV/√Hz. In order to achieve this a larger input stage has been used.
This larger input stage increases the input capacitance of the LMP7711/LMP7712. Figure 55 shows typical input
common mode input capacitance of the LMP7711/LMP7712.
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25
20
V
S
= 5V
15
10
5
0
0
1
2
3
4
V
CM
(V)
Figure 55. Input Common Mode Capacitance
This input capacitance will interact with other impedances such as gain and feedback resistors, which are seen
on the inputs of the amplifier to form a pole. This pole will have little or no effect on the output of the amplifier at
low frequencies and under DC conditions, but will play a bigger role as the frequency increases. At higher
frequencies, the presence of this pole will decrease phase margin and also causes gain peaking. In order to
compensate for the input capacitance, care must be taken in choosing feedback resistors. In addition to being
selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase
stability.
The DC gain of the circuit shown in Figure 56 is simply −R2/R1.
C
F
R
2
R
1
-
+
C
IN
V
+
-
IN
+
V
OUT
-
R2
R1
VOUT
VIN
-
AV =
-
=
Figure 56. Compensating for Input Capacitance
For the time being, ignore CF. The AC gain of the circuit in Figure 56 can be calculated as follows:
VOUT
-R2/R1
(s) =
VIN
s2
s
«
«
∆
1 +
+
A0 R1
A0
∆
≈
≈
∆
«
≈
≈
∆
«
CIN R2
R1 + R2
(1)
This equation is rearranged to find the location of the two poles:
2
«
∆
4 A0CIN
R2
≈
1
1
-1
1
1
-
≈
P1,2
=
+
ê
+
∆
«
R1
R2
R
R2
2CIN
1
(2)
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As shown in Equation 2, as the values of R1 and R2 are increased, the magnitude of the poles are reduced,
which in turn decreases the bandwidth of the amplifier. Figure 57 shows the frequency response with different
value resistors for R1 and R2. Whenever possible, it is best to chose smaller feedback resistors.
15
A
= -1
V
10
5
0
-5
R
1,
R
2
= 30 kW
-10
-15
-20
-25
R
R
= 10 kW
1,
2
R
1,
R
2
= 1 kW
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 57. Closed Loop Frequency Response
As mentioned before, adding a capacitor to the feedback path will decrease the peaking. This is because CF will
form yet another pole in the system and will prevent pairs of poles, or complex conjugates from forming. It is the
presence of pairs of poles that cause the peaking of gain. Figure 58 shows the frequency response of the
schematic presented in Figure 56 with different values of CF. As can be seen, using a small value capacitor
significantly reduces or eliminates the peaking.
20
R , R = 30 kW
1
2
C
F
= 0 pF
A
= -1
V
10
0
C
= 5 pF
F
-10
-20
-30
-40
C
= 2 pF
F
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 58. Closed Loop Frequency Response
TRANSIMPEDANCE AMPLIFIER
In many applications, the signal of interest is a very small amount of current that needs to be detected. Current
that is transmitted through a photodiode is a good example. Barcode scanners, light meters, fiber optic receivers,
and industrial sensors are some typical applications utilizing photodiodes for current detection. This current
needs to be amplified before it can be further processed. This amplification is performed using a current-to-
voltage converter configuration or transimpedance amplifier. The signal of interest is fed to the inverting input of
an op amp with a feedback resistor in the current path. The voltage at the output of this amplifier will be equal to
the negative of the input current times the value of the feedback resistor. Figure 59 shows a transimpedance
amplifier configuration. CD represents the photodiode parasitic capacitance and CCM denotes the common-mode
capacitance of the amplifier. The presence of all of these capacitances at higher frequencies might lead to less
stable topologies at higher frequencies. Care must be taken when designing a transimpedance amplifier to
prevent the circuit from oscillating.
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With a wide gain bandwidth product, low input bias current and low input voltage and current noise, the
LMP7711/LMP7712 are ideal for wideband transimpedance applications.
C
F
R
F
I
IN
C
-
CM
+
-
+
V
OUT
C
D
V
B
CIN = CD + CCM
VOUT
- R
=
F
IIN
Figure 59. Transimpedance Amplifier
A feedback capacitance CF is usually added in parallel with RF to maintain circuit stability and to control the
frequency response. To achieve a maximally flat, 2nd order response, RF and CF should be chosen by using
Equation 3
CIN
CF =
GBWP * 2 p RF
(3)
Calculating CF from Equation 3 can sometimes result in capacitor values which are less than 2 pF. This is
especially the case for high speed applications. In these instances, its often more practical to use the circuit
shown in Figure 60 in order to allow more sensible choices for CF. The new feedback capacitor, C′F, is (1+
RB/RA) CF. This relationship holds as long as RA << RF.
R
A
R
B
C
F
R
F
-
+
IF RA < < RF
«
∆
≈
RB
≈
1 +
C Å =
F
CF
∆
RA
«
Figure 60. Modified Transimpedance Amplifier
SENSOR INTERFACE
The LMP7711/LMP7712 have low input bias current and low input referred noise, which make them ideal choices
for sensor interfaces such as thermopiles, Infra Red (IR) thermometry, thermocouple amplifiers, and pH electrode
buffers.
Thermopiles generate voltage in response to receiving radiation. These voltages are often only a few microvolts.
As a result, the operational amplifier used for this application needs to have low offset voltage, low input voltage
noise, and low input bias current. Figure 61 shows a thermopile application where the sensor detects radiation
from a distance and generates a voltage that is proportional to the intensity of the radiation. The two resistors, RA
and RB, are selected to provide high gain to amplify this signal, while CF removes the high frequency noise.
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THERMOPILE
+
-
+
V
-
+
= KI
IN
R
B
V
OUT
-
IR RADIATION
INTENSITY, I
R
A
C
F
V
R
A
OUT
I =
K(R
R )
B
A +
Figure 61. Thermopile Sensor Interface
PRECISION RECTIFIER
Rectifiers are electrical circuits used for converting AC signals to DC signals. Figure 62 shows a full-wave
precision rectifier. Each operational amplifier used in this circuit has a diode on its output. This means for the
diodes to conduct, the output of the amplifier needs to be positive with respect to ground. If VIN is in its positive
half cycle then only the output of the bottom amplifier will be positive. As a result, the diode on the output of the
bottom amplifier will conduct and the signal will show at the output of the circuit. If VIN is in its negative half cycle
then the output of the top amplifier will be positive, resulting in the diode on the output of the top amplifier
conducting and, delivering the signal on the amplifier's output to the circuits output.
For R2/ R1 ≥ 2, the resistor values can be found by using the equation shown in Figure 62. If R2/ R1 = 1, then R3
should be left open, no resistor needed, and R4 should simply be shorted.
R
2
V
IN
R
1
+
V
V
OUT
-
-
-
V
R
R
3
4
R
R
R
R
4
3
2
1
= 1 +
+
V
-
10 kW
V
Figure 62. Precision Rectifier
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REVISION HISTORY
Changes from Revision E (May 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format. ......................................................................................................... 20
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMP7711MK/NOPB
LMP7711MKE/NOPB
LMP7711MKX/NOPB
LMP7712MM/NOPB
LMP7712MME/NOPB
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DGS
DGS
6
6
1000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
AC3A
AC3A
AC3A
AD3A
AD3A
SN
SN
SN
SN
6
3000 RoHS & Green
1000 RoHS & Green
ACTIVE
ACTIVE
VSSOP
VSSOP
10
10
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP7711MK/NOPB
LMP7711MKE/NOPB
LMP7711MKX/NOPB
SOT-
23-THIN
DDC
DDC
DDC
6
6
6
1000
250
178.0
178.0
178.0
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
SOT-
23-THIN
SOT-
3000
23-THIN
LMP7712MM/NOPB
LMP7712MME/NOPB
VSSOP
VSSOP
DGS
DGS
10
10
1000
250
178.0
178.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP7711MK/NOPB
LMP7711MKE/NOPB
LMP7711MKX/NOPB
LMP7712MM/NOPB
LMP7712MME/NOPB
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
VSSOP
DDC
DDC
DDC
DGS
DGS
6
6
1000
250
208.0
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
6
3000
1000
250
10
10
VSSOP
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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