LMP92066PWPR_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

LMP92066 具有集成 EEPROM 和输出开/关控制的双路温度控制数模转换

器 (DAC)

1 特性

3 说明

1

•

内部 12 位温度传感器

精度（–40°C 至 120°C）：±3.2°C（最大值）

LMP92066 是一款高度集成的温度控制双路 DAC。这

两个 DAC 可由两个独立的、用户定义的温度至电压转

换函数（存储在内部 EEPROM 中）编程，从而可以在

无需其他外部电路的情况下校正任何温度影响。一旦

被加电，此器件自主运行，而无需系统控制器干预，以

便为控制应用中偏置电压和电流的设置和补偿提供完整

解决方案。

–

•

存储在 EEPROM 中的两个独立传输函数

双模拟输出

–

两个 12 位 DAC

输出范围为 –5V 至 0V 或 0V 至 5V

可耐受高达 10µF 的高容性负载

后置校准精度：±2.4mV（典型值）

LMP92066 具有两个支持双输出范围的模拟输出：0 至

+5V，以及 0 至 -5V。每个输出可通过专用控制引脚

单独切换为负载。输出切换被设计用于快速响应，从

而使此器件适合于射频 (RF) 功率放大器偏置应用。

•

输出开/关控制切换时间为 50ns（典型值）

–

切换时间为 50ns（典型值）

–

导通电阻 (RDSON)：5Ω（最大值）

I²C 接口：标准且快速

EEPROM 经 100 次写入操作验证，从而实现重复字段

更新。 EEPROM 编程由用户发出的 I²C 命令完成。

–

9 个可选从地址

超时功能

LMP92066 的数字端口可作为设置数字 I/O 电平的专

用 VIO 引脚与各种系统控制器相连。此器件采用耐热

增强型 PowerPAD™ 封装，从而实现高精度印刷电路

板 (PCB) 温度测量。

•

VDD 电源电压 4.75V 至 5.25V

VIO 范围 1.65V 至 3.6V

额定工作温度范围：–25°C 至 120°C

工作温度范围：–40°C 至 125°C

器件信息

2 应用范围

器件型号

LMP92066

封装

封装尺寸

•

GaN 或 LDMOS PA 偏置控制器

传感器温度补偿

HTSSOP (16)

5.00mm x 4.40mm

定时电路温度补偿

4 简化电路原理图

3.3V

5V

一点校准后的残余误差

35

30

25

20

15

10

5

VIO VDD VDDB

FETDRV1

MEAN = 0.72 mV

STDEV = 1.71 mV

Gate Bias 1

10µ

PA: LDMOS

DAC1

SDA

SCL

µC

LMP92066

DRVEN1

DRVEN0

Gate Bias 0

10µ

A1

A0

FETDRV0

DAC0

PA: LDMOS

GNDD GNDA VSSB

0

REAOPC (mV)

C009

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNAS634

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

8.5 Programming........................................................... 32

8.6 Register Map........................................................... 39

Application and Implementation ........................ 43

9.1 Application Information............................................ 43

9.2 Typical Applications ................................................ 43

9.3 Do's and Don'ts....................................................... 51

9.4 Initialization Setup................................................... 52

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements................................................ 8

7.7 Output Switching Characteristics .............................. 8

7.8 Typical Characteristics............................................ 10

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 14

8.3 Features Description............................................... 15

8.4 Device Functional Modes........................................ 28

9

10 Power Supply Recommendations ..................... 54

10.1 I_VDDDuring EEPROM BURN................................ 54

10.2 I_VDDDuring EEPROM TRANSFER....................... 54

11 Layout................................................................... 55

11.1 Layout Guidelines ................................................. 55

11.2 Layout Example .................................................... 55

12 器件和文档支持 ..................................................... 56

12.1 器件支持................................................................ 56

12.2 商标....................................................................... 56

12.3 静电放电警告......................................................... 56

12.4 术语表 ................................................................... 56

13 机械、封装和可订购信息....................................... 56

8

5 修订历史记录

Changes from Original (March 2014) to Revision A

Page

•

已更改器件信息表的标题行；将整篇文档中的“端子”修订为“引脚”；将处理额定值表更改为 ESD 额定值表；删除了正

值前的“+”；将交叉引用部分改为斜体；为表 3、4、5 和 6 添加了标题 ................................................................................. 1

•

Added "Ω" after "k" in EC table ............................................................................................................................................. 6

Added "Ω" after "k" in Output Switching table ....................................................................................................................... 8

Added "NOTE" to beginning of Applications and Implementations...................................................................................... 43

Changed title from Application Performance Plots to Application Curves; deleted reference to Figure 43 in first

sentence of first Application Curves section......................................................................................................................... 47

•

Added change "5 mA" to "50 mA" ........................................................................................................................................ 54

2

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

6 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP

Top View

GNDD

DRVEN1

DRVEN0

VIO

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

VDDB

DAC1

FETDRV1

GNDA

DAP

SDA

SCL

FETDRV0

DAC0

A1

A0

VSSB

Pin Functions

(1)

TYPE

DESCRIPTION

ESD STRUCTURES

NUMBER

NAME

VIO

1

GNDD

G

Lower power rail of the digital I/O

GNDA

2:3

4

DRVEN[1:0]

VIO

I

Asynchronous control of the Changeover Switches

Digital I/O power supply rail

5

SDA

I/O

I²C bi-directional data line

6

SCL

I

I²C clock input

GNDA

VIO

7:8

A[1:0]

I

I²C slave address selector

GNDA

9

VSSB

P

Output drive lower supply rail

DAC0 output

DAC0

DAC1

10, 14

O

VDDB

FETDRV0

FETDRV1

11, 13

O

Gate drive of the external FET device

VSSB

(1) G = Ground; I = Input; O = Output; P = Power

3

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Pin Functions (continued)

(1)

TYPE

DESCRIPTION

ESD STRUCTURES

NUMBER

NAME

VDD

Merril

Clamp

12

GNDA

G

Analog block lower rail

GNDA

VDD

15

VDDB

P

Output drive upper supply rail

GNDA

VDD

Merril

Clamp

16

---

VDD

DAP

P

Analog block upper rail

GNDA

Die Attach Pad. For best thermal, and noise performance

it should be soldered to the local system ground pad.

G

4

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

–5.5

–0.3

MAX

5.5

0.3

5.5

10

UNIT

VDD

VDDB

VIO

Supply voltage with respect to GNDA

V

VSSB

GNDD

VDDB to VSSB

Any other pins to GNDA

DAC output current

Current at all other pins

Storage temperature, T_stg

V

mA

°C

5

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

125

120

12

UNIT

Operational temperature

Specification temperature

DAC output load capacitance

Supply voltage range (VDD)

Digital I/O supply voltage

LDMOS mode VSSB = GNDA

GaN mode VSSB = –5 V

–40

–25

8

°C

µF

VDD

VIO

4.75

1.65

5.25

3.3

5

V

VDDB–VSSB

5

7.4 Thermal Information

PWP (HTSSOP)

16 PINS

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

38.2

21.3

15.1

0.5

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JB

14.9

1.4

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

7.5 Electrical Characteristics

Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V, T_A= 25°C. VDDB = 5 V ±5%, VSSB = GNDA, V_DACxoutput

range 0 V to 5 V; or VDDB = GNDA, VSSB = –5 V ±5%, V_DACxoutput range 0 V to –5V. DAC input code range 48 to 4047.

V_DACXload C_L= 10 µF.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG SIGNAL PATH CHARACTERISTICS (DAC, Buffer Amplifier, Internal Reference)

Resolution

12

–25°C < T_A< 120°C

Monotonic

Bits

DNL

INL

Differential non-linearity

Integral non-linearity

R_L= 100 kΩ, –25°C < T_A< 120°C

–0.99

−1.93

1

LSB

2.78

LDMOS mode, R_L= 100 kΩ,

–25°C < T_A< 120°C

–14

14

OE

Offset error⁽¹⁾

LDMOS mode, R_L= 100 kΩ

±1

mV

GaN mode, R_L= 100 kΩ, –25°C < T_A

120°C

<

–16.5

–0.72

–13.3

16.5

OETC

GE

Offset error temperature coefficient⁽¹⁾⁽²⁾

Gain error⁽¹⁾

R_L= 100 kΩ, –25°C < T_A< 120°C

43 μV/°C

0.74 %FS

20 ppm/°C

GETC

Gain error temperature coefficient⁽¹⁾⁽²⁾

BASEx = 1638 (V_DACX= 2 V at 24°C)

–25°C < T_A< 120°C

13.3

BASEx = 1638 (V_DACX= 2 V at 24°C)

±2.4

Residual error after one point

calibration^(1)(2)(3)(4)

REAOPC

mV

BASEx = 819 (V_DACX= 1 V at 24°C)

–25°C < T_A< 120°C

–11.3

11.3

BASEx = 819 (V_DACX= 1 V at 24°C)

LDMOS mode, R_L= 100 kΩ

LDMOS mode, I_OUT= 10 mA

LDMOS mode, R_L= 100 kΩ

LDMOS mode, I_OUT= –10 mA

±2.1

0

ZCO

Zero code output (V_DACx– VSSB)

mV

200

10

Full-scale output at code 4095 (VDDB –

FSO

I_O

V_DACx

)

150

Continuous output current per channel

allowed⁽⁵⁾

T_A= 125°C

10

12

mA

µF

R_L= 2 kΩ or ∞, –25°C < T_A< 120°C

R_L= 2 kΩ or ∞

C_L

Load capacitance⁽⁵⁾

10

3

DAC output resistance

DAC settling time

DACCODEx = 2048

C_L= 10 µF

Ω

250

µs

OUTPUT SWITCH DC CHARACTERISTICS

On Resistance of the switch between

DACx and FETDRVx

R_DRV

–25°C < T_A< 120°C

6

Ω

On Resistance of the switch between

FETDRVx and VSSB

R_G

11

TEMPERATURE SENSOR CHARACTERISTICS

Resolution

Temperature sensor error⁽²⁾

0.0625

25

°C/lsb

°C

TE

T_A= –40°C to 120°C

–3.2

3.2

Conversion time

ms

(1) The package mechanical stress-induced parameter shift may cause the parts to manifest behavior beyond the specified limits.

Mechanical stresses may also arise as a result of the PCB manufacturing process.

(2) Device specification is verified by characterization and is not tested in production.

(3) The specification is a calculated worst-case value based on the OE, OETC, GE, and GETC limits.

(4) The outcome of the REAOPC characterization of the PCB mounted devices is shown in Figure 4, Figure 5, and Figure 6 of the Typical

Characteristics. The 97, randomly selected, devices from 3 diffusion lots were installed on the 4-layer RO4003 Laminate using

Convection Reflow. The Look-Up-Table was set for maximum gain; for example, all DELx = 0xFF. While powered up, the devices were

subjected to 3 thermal cycles, from –40°C to 125°C, during which their REAOPC was recorded.

(5) Parameter based on the process data and circuit simulation.

6

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Electrical Characteristics (continued)

Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V, T_A= 25°C. VDDB = 5 V ±5%, VSSB = GNDA, V_DACxoutput

range 0 V to 5 V; or VDDB = GNDA, VSSB = –5 V ±5%, V_DACxoutput range 0 V to –5V. DAC input code range 48 to 4047.

V_DACXload C_L= 10 µF.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

EEPROM

Maximum EEPROM write cycles

100

DIGITAL INPUT CHARACTERISTICS (DRVEN0, DRVEN1, SDA, and SCL)

0.7 ×

VIO

V_IH

V_IL

Input high voltage

Input low voltage

–25°C < T_A< 120°C

0.3 ×

V

VIO

0.2 ×

VIO

Hysteresis

C_iND

Input capacitance

5

pF

DIGITAL INPUT CHARACTERISTICS (A0, A1)

0.7 ×

VIO

V_IH

V_IL

Input high voltage

Input low voltage

–25°C < T_A< 120°C

V

0.3 ×

VIO

R_UP

R_DN

Internal pullup resistance

Internal pulldown resistance

Max external capacitance⁽⁵⁾

17

kΩ

30

pF

DIGITAL OUTPUT CHARACTERISTICS (SDA)

I_OUT= 4 mA, –25°C < T_A< 120°C

I_OUT= 4 mA

0.4

V_OL

Output low voltage

V

0.16

4

Current from the supply rail through the

pullup resistor into the drain of the open-

drain output device, –25°C < T_A< 120°C

Open-drain output leakage current with

output high⁽⁵⁾

I_LEAK

C_OUT

±1

μA

Output capacitance

pF

SUPPLY CURRENT SPECIFICATIONS

Normal operation⁽⁶⁾, –25°C < T_A< 120°C

While executing EEPROM BURN⁽⁷⁾

2.6

4

9

I_DD

mA

µA

While transferring EEPROM content to

operating memory⁽⁸⁾

I²C inactive, –25°C < T_A< 120°C

I²C in fast mode, –25°C < T_A< 120°C

LDMOS mode, R_L= ∞, –25°C < T_A< 120°C

GaN mode, R_L= ∞, –25°C < T_A< 120°C

3

3.1

1.5

I_VIO

I_VDDB

I_VSSB

mA

–1.4

PWR

Power consumption, conversion mode

(Conv)

All output pins R_L= ∞

20

mW

(6) The normal operation current through the VDD excludes the current supplied to the external load, and excludes the current required by

the EPPROM BURNS and TRANSFERS.

(7) During the EEPROM BURN command execution the device activates internal systems that are not active during the Normal operation.

This causes a momentary increase in supply current through the VDDpin. The duration of this temporary surge in supply current is

typically 125 ms.

(8) During the data transfer from the EEPROM to the Operating memory there will be a momentary surge in supply current through the VDD

pin. The duration of this surge is typically 200 µs.

7

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

7.6 Timing Requirements

Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V. VDDB = 5 V ±5%, VSSB = GNDA; or VDDB = GNDA, VSSB

= –5V ±5%.

PARAMETER

I²C clock frequency

Clock low time

TEST CONDITIONS

MIN

MAX

UNIT

10

1.3

0.6

400

kHz

t_LOW

t_HIGH

Clock high time

After this period, the first clock pulse is

generated

µs

t_HD-STA

t_SU;STA

Hold time repeated START condition

0.6

Setup time for a repeated START

condition

t_HD;DAT

t_SU;DAT

t_f

Data hold time (Note x and y)

Data setup time

0

900

250

100

ns

µs

SDA fall time

I_L≤ 3 mA and C_L≤ 400 pF

t_SU;STO

Setup time for STOP condition

0.6

1.3

Bus free time between a STOP and

START condition

t_BUF

C_b

SDA capacitive load

400

50

pF

ns

Pulse width of spikes that must be

suppressed by the input filter

t_SP

SCL and SDA timeout

25

35

ms

7.7 Output Switching Characteristics

Unless otherwise noted: VDD = 5 V ±5%, VIO = 1.8 V to 3.3 V. VDDB = 5 V ±5%, VSSB = GNDA; or VDDB = GNDA, VSSB

= –5V ±5%.

PARAMETER

On time

TEST CONDITIONS

MIN

TYP

50

MAX

UNIT

t_ON

DACCODEx = 4095, R_L= 100 kΩ

t_OFF

Off time

50

ns

t_BBM

Break-before-make time

FETDRV output capacitance

15

C_FETDRV

10

pF

t

VD;DAT, VD;ACK

SDA

70%

30%

t

BUF

t

f

LOW

t

HD;STA

t

r

t

f

SP

SCL

70%

30%

t

HD;STA

SU;STA

t

SU;STO

t

HIGH

t

SU;DAT

HD;DAT

STOP START

REPEATED

START

Figure 1. I²C Timing

8

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

VIO

DRVENx

50%

GNDD

VDACx

90%

FETDRVx

VSSB

HiZ

t_BBM

t_ON

t_OFF

Figure 2. Switching

9

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

7.8 Typical Characteristics

Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO =

3.3 V, Temperature = 24°C, R_L= 100 kΩ.

2.1

1.8

35

30

25

20

15

10

5

MEAN = 0.76 mV

STDEV = 1.43 mV

1.5

1.2

0.9

0.6

0.3

0.0

œ0.3

œ0.6

œ0.9

œ1.2

œ1.5

Mean Error

+31

œ31

0

20

40

60

80

100 120

œ40 œ20

REAOPC (mV)

Temperature (°C)

C001

C008

BASE = 819

97 devices

PCB Mounted

3 Cycles: –40°C to 125°C

Figure 3. Temperature Sensor Error

Figure 4. REAOPC

35

30

25

20

15

10

5

MEAN = 0.72 mV

STDEV = 1.71 mV

MEAN = 0.66 mV

STDEV = 2.42 mV

30

25

20

15

10

5

0

REAOPC (mV)

C009

C010

BASE = 1638

97 devices

PCB Mounted

BASE = 3277

97 devices

PCB Mounted

3 Cycles: –40°C to 125°C

Figure 5. REAOPC

Figure 6. REAOPC

0.5

0.4

1.0

0.8

0.3

0.6

0.2

0.4

0.1

0.2

0.0

œ0.1

œ0.2

œ0.3

œ0.4

œ0.5

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Input Code (dec)

C003

Figure 7. DAC DNL

Figure 8. DAC INL

10

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Typical Characteristics (continued)

Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO =

3.3 V, Temperature = 24°C, R_L= 100 kΩ.

1.0

0.8

0.6

0.4

0.2

0.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

œ0.2

œ0.4

œ0.6

œ0.8

œ1.0

MAX

MIN

MAX

MIN

0

20

40

60

80 100 120 140

0

20

40

60

80 100 120 140

œ60 œ40 œ20

Temperature (°C)

C004

C005

Figure 9. DAC MIN/MAX DNL vs Temperature

Figure 10. DAC MIN/MAX INL vs Temperature

30

25

20

15

10

5

70

60

50

40

30

20

10

0

OE (mV)

GE (%)

C006

C007

TEMP = –40°C to 120°C

Figure 11. DAC Offset Error

Figure 12. DAC Gain Error

V_DACx

V_SCL

Time (100 µs/DIV)

C011

C012

DAC OVERRIDE MODE

C_L= 10 µF

I²C command triggers DAC step

Step size: 1/4 to 3/4 FS

DAC OVERRIDE MODE

C_L= 10 pF

I²C command triggers DAC step

Step size: 1/4 to 3/4 FS

Figure 13. DAC Step Response

Figure 14. DAC Step Response

11

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Typical Characteristics (continued)

Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO =

3.3 V, Temperature = 24°C, R_L= 100 kΩ.

V_DACx

V_SCL

Time (100 µs/DIV)

C013

C014

DAC OVERRIDE MODE

C_L= 10 µF

I²C command triggers DAC step

Step size: 3/4 to 1/4 FS

DAC OVERRIDE MODE

C_L= 10 pF

I²C command triggers DAC step

Step size: 3/4 to 1/4 FS

Figure 15. DAC Step Response

Figure 16. DAC Step Response

5

4

3

2

1

0

5

4

3

2

1

0

dacx= 1.38 V

V_DACx

V

dacx= 3.23 V

DACx

V

Vdacx= 4.46 V

DACx

0

1

2

3

4

5

0

20

40

60

80

100

120

œ40

œ20

V_DACx(V)

Temperature (°C)

C015

C016

Figure 17. R_DRVResistance vs DAC Output Level

Figure 18. R_DRVvs Temperature

90

80

70

60

50

40

30

20

10

0

60

50

40

30

20

10

0

20

40

60

80

100

120

œ40

œ20

t_ON(ns)

Temperature (°C)

C017

C018

Figure 20. Output Switch ON Time

Figure 19. Output Switch ON Time vs Temperature

12

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Typical Characteristics (continued)

Unless otherwise stated the plot data was collected under these conditions: VDD = 5 V, VDDB = 5 V, VSSB = GNDA, VIO =

3.3 V, Temperature = 24°C, R_L= 100 kΩ.

70

60

50

40

30

20

10

0

R_G(ꢀ)

C019

Figure 21. Ground Switch Resistance When Closed

13

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

8 Detailed Description

8.1 Overview

The LMP92066 is a dual temperature-dependent bias generator whose temperature-to-voltage transfer functions

are user defined. The device contains a digital temperature sensor that addresses two independently

programmable Look-Up-Tables (LUTs). The outputs of LUTs are sent on to their respective 12-bit DACs to

produce two independent output voltages. For added flexibility the device can be configured to provide bias

potential above or below GNDA.

In applications requiring rapid ON/OFF switching of the bias voltage, the LMP92066 provides asynchronous

control over its outputs. Dedicated digital input pins control analog output switching.

All aspects of the device functionality are controlled through internal registers. These registers, and the LUTs, are

accessible through the I²C-compatible interface.

The LMP92066 can operate autonomously of the system controller, once LUT coefficients have been committed

to its non-volatile memory, EEPROM. Upon power up the EEPROM content is automatically transferred to the

operating memory, and the device begins to produce required bias voltage.

8.2 Functional Block Diagram

VIO

VDD

VDDB

A[1:0]

SCL

I2C

Interface

&

DAC1

Controller

SDA

LUT1

DAC1

FETDRV1

DRVEN1

Temp.

Sensor

EPROM

LUT0

VSSB

DAC0

FETDRV0

DRVEN[1:0]

DRVEN0

VSSB

GNDD

GNDA

14

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

8.3 Features Description

8.3.1 Temperature Sensor

The onboard digital temperature sensor produces 12-bit, twos complement output, where the LSB represents

+0.0625°C, and MSB represents –128°C. The output of the temperature sensor is stored in the TEMPM and

TEMPL registers. These registers are updated automatically once the temperature sensor completes a new

conversion, approximately every 25 ms. The temperature sensor begins operation immediately after the supply

voltage at VDD has reached its minimum operating level. Initially, right after power up, TEMPM and TEMPL

registers contain 0s. The first measurement result is loaded into TEMPM and TEMPL registers 25 ms after power

up.

Table 1. Temperature Sensor Output

TEMPERATURE SENSOR

OUTPUT

TEMPERATURE (°C)

{TEMPM[3:0], TEMPL[7:0]}

100000000000

111001000000

111111111111

000000000001

000110000000

011111111111

–128.0000

–28.0000

–0.0625

0.0625

24.0000

127.9375

NOTE

The maximum output of the temperature sensor stored in the TEMPM and TEMPL

registers is 127.9375°C.

8.3.2 Look-Up-Table (LUT) and Arithmetic-Logic Unit (ALU)

The LUT is used to create an arbitrary transfer function which maps the temperature to the analog output of the

device. In concept, the temperature readout is used as a pointer to a table of discrete values that are

representative of the samples of the desired temperature-dependent function.

In order to minimize the storage requirements, the LMP92066 LUTs are indexed in 4°C increments. Also, the

stored values are only the increments, or first derivatives (Δs) of the modeled transfer function. The internal ALU

reconstructs the original transfer function by integrating the coefficients stored in the LUTs. The errors due to the

coarseness of the temperature quantization are significantly reduced through the use of linear interpolation,

which is also implemented in the ALU.

Consider the example shown in Figure 22. The target output vs temperature is shown in the top graph. V_DACxis a

smooth, monotonic function with, ideally, infinite precision. The LUT stores only the increments, or the rise, within

each 4°C interval.

In order to recreate the original transfer function, the series of increments must be summed together and added

to the constant BASE value. BASE represents the constant offset which is lost due to the differentiation - storage

of the increments only. This process must also be referenced to the common temperature point. This reference

temperature is called BASELINE in this document, and is fixed at 24°C.

15

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

V_DACx

û₄

BASE

24°C

Temperature

4°C 4°C

û V_DACx

û₄

LUT Index

1

2

3

4

BASELINE

Figure 22. Original Transfer Function

The LUT and ALU Organization, LUT Coefficient to Register Mapping, and The LUT Input and Output Ranges

sections below detail the operation of the LUTs and the ALUs.

8.3.2.1 LUT and ALU Organization

In Figure 23 TEMP represents the 12-bit input value to the LUT. This value is produced by the local temperature

sensor, or it can be provided by the user through the use of the OVERRIDE registers. The OVERRIDE modes

are described in the later sections.

TEMP is truncated, and TEMP[11:6] is used to index the LUT. The truncation is equivalent to reducing the TEMP

resolution from 0.0625°C/LSB to 4°C/LSB.

The overall transfer function is stored in the LUT as a set of unsigned 4-bit increments from the BASE value, that

is, LUT location (+1) stores the value of the increment Δ₁. This is shown in Figure 23. The BASELINE is 24°C

temperature reference point, and BASE is the numeric representation of the required output at 24°C

TEMP

INDEX

VALUE

128°C

K+1

K

û_(K+1)

û_K

36°C

32°C

28°C

24°C

20°C

+3

û₃

û₂

+2

+1

û₁

Temp.

Sensor

BASELINE

-1

BASE

û_-1

-(M-1)

-M

û_-(M-1)

û_-M

-28°C

Figure 23. LUT Organization

When TEMP is above 24°C, the LUT is addressed above the BASELINE address, all increments are added to

the BASE value to produce numeric equivalent of the analog output. When TEMP is below 24°C, LUT is

addressed below the BASELINE, all increments are subtracted from the BASE value to produce DACIN.

16

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Interpolation function is implemented in the ALU that follows the LUT. The truncated lower bits of the TEMP

value, REM = TEMP[5:0], are used to interpolate between data points stored in the LUT. A portion of increment,

αΔi, is added to form the final numeric output - the input data to the DAC. The factor α is a fraction of 4°C

temperature span, or equivalently it is a fraction of the 64-code temperature span.

REM

a

=

64

(1)

The process of calculating the DACIN, including the interpolation, is depicted in Figure 24. The DACIN is the final

12-bit value produced by the ALU and the LUT, and forwarded to the DAC for conversion to analog domain.

K

∑

DACIN = BASE + û_i+ . û_(K+1)

i=1

DACIN

.û_(K+1)

û_K+1

û_K

REM

û₃

û₂

û₁

M

BASE

∑

DACIN = BASE œ

û_-i+ . û_-M

i=1

û_-1

REM

û_-(M-1)

û_-M

.û_-M

LUT INDEX

(TEMP)

Figure 24. DACIN Calculation

Up to this point the algorithm description concerned only the generation of the monotonically increasing transfer

function. The device can also produce monotonically decreasing transfer function by setting the

DACx_BASEM.POL bit.

The effect of polarity reversal (POL = 1) on the overall transfer function is shown in Figure 25. The LUT content

is unchanged from the original example above. Note that now the LUT values stored at locations above

BASELINE address are subtracted from BASE value, and the LUT values stored at locations below BASELINE

address are added to the BASE value.

17

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

DACIN

û_-M

û_-(M-1)

û_-1

BASE

û₁

û₂

û₃

û_K

û_K+1

LUT INDEX

(TEMP)

Figure 25. Monotonically Decreasing Transfer Function

The expressions used in the calculation of the transfer function are summarized below:

LUT index > BASELINE:

K

≈

’

÷

◊

∆

DACIN = BASE + (-1)^POL

D_i+ aD_(K+1)

∆

_∆ƒ

i=1

«

(2)

(3)

LUT index < BASELINE:

M

≈

’

∆

÷

◊

DACIN = BASE - (-1)^POL

D_-i- aD_-M

∆

_∆ƒ

i=1

«

18

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

8.3.2.2 LUT Coefficient to Register Mapping

For the sake of convenience the preceding sections referred to LUT coefficients as Δ_K. These are stored in the

operating memory in the registers DELx. This is reflected in the Register Map section of this document. The

example of the Δ_Kto DELx register mapping is shown in Table 2 section below.

Table 2. ΔK to DELx Register Mapping

TEMPERATURE

FUNCTION INCREMENT

REGISTER ASSIGNMENT

–28°C

↓

Δ_–13

↓

DEL0

↓

20°C

28°C

↓

Δ_–1

Δ₊₁

↓

DEL12

DEL13

↓

124°C

128°C

Δ₊₂₆

DEL38

8.3.2.3 The LUT Input and Output Ranges

The programmable LUT input range spans temperatures –28°C to 128°C. For the temperatures below –28°C the

LUT output is linearly extrapolated; that is, the increment Δ_–13(register DEL0) stored at the location

corresponding to –28°C is used as the slope down to –40°C.

Extrapolated

LUT Range

LUT output

DEL0

-40°C

-28°C

-24°C

+124°C +128°C

Temperature Sensor Output

Figure 26. Temperature Sensor Output

Although the maximum output of the temperature sensor is 127.9375°C, the LUT index corresponding to 128°C

(DEL38) is required for proper interpolation when the temperature is above 124°C.

The increments stored in the LUT are 4-bit unsigned values. This limits the maximum slope of the transfer

function stored in the LUT to:

4LSB

^èC

₌16LSB ₌

SLOPE_MAX

4^èC

(4)

Given this slope limit imposed by the LUT structure, and the fact that the LUT input range is 156°C (from –28°C

to 128°C ), the maximum output range of the LUT due to the temperature sensor input is 624 LSBs, for the given

BASE value.

NOTE

The maximum span of 624 codes can reside anywhere within the 0 to 4095 code space of

the 12-bit DAC input. The total input code to the DAC is the sum of the increments (Δs)

and the 12-bit BASE value.

19

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

8.3.3 Analog Signal Path

The simplified schematic of one analog channel of the device is shown in Figure 27. The LMP92066 contains 2

such channels. The following sub-sections describe each of the individual blocks within a channel.

VDD

VDDB

DACxM.DAC

DACxL.DAC

0

1

DAC

BUFFER

DACx

1

2

DACxM_OVRD.DAC

DACxL_OVRD.DAC

S

OVRD_CTL.DAC

GNDA

VSSB

FETDRVx

DRVENx

VSSB

Figure 27. One Analog Channel Simplified Schematic

8.3.3.1 DAC

The DAC produces unipolar output voltage proportional to the 12-bit input code. The input code format is offset

binary, where 0x000 represents minimum and the 0xFFF full-scale input. The input code is produced by the

LUT/ALU and stored in the DACxM and DACxL read-only registers. The user can also insert the DAC input code

via the DACxM_OVRD and DACxL_OVRD registers, and by setting the OVRD_CTL.DAC bit. The DAC is

referenced to the internally generated 5 V.

The DAC transfer functions:

DACIN

V_DACx= 5A

(V)

4096

(5)

Where A is the Buffer Amplifier gain (see Buffer Amplifier) and DACIN is the 12-bit input code stored in either:

{ DACxM[3:0], DACxL[7:0] }

or

{ DACxM_OVRD[3:0], DACxL_OVRD[7:0] }

The LUT Input and Output Ranges describes the maximum output code span of the LUT, for the given base

value. This also implies that when DACxM and DACxL registers are selected as the DAC inputs, the maximum

V_DACxoutput excursion over temperature is:

4LSB

5V

dV_DACx= SLOPE_MAXx T_RANGEx V_LSB

=

x156èC x

=762mV

èC

4096

(6)

However, this limitation is lifted when using DACxM_OVRD and DACxL_OVRD registers as the DAC inputs. In

this case the DAC input range is full 4096 codes, and the output spans 0 V to 5 V.

8.3.3.2 Buffer Amplifier

The buffer amplifier provides the low impedance drive for the potential generated by the DAC. The output of the

amplifier is always available at the DACx output pin of the device. The buffer is designed to drive large capacitive

loads, as high as 10 µF.

The structure of the Buffer is such that it can produce output voltages above or below GNDA potential. Both

Buffer Amplifiers are biased from dedicated supply rails: VDDB and VSSB. The difference between the VDDB

and VSSB is nominally 5 V, but the span can be above or below GNDA. The gain A of the Buffer Amplifier

depends on the state of supply rails VDDB and VSSB.

20

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

When the span is above GNDA, or VDDB = 5 V and VSSB = 0 V, then the output buffer gain is A = 1. The net

effect on the output of the analog processing chain is shown in Figure 28. The DAC input codes in the range of

0x000 to 0xFFF are mapped to the output voltage in the range of 0 V to 5 V.

5V

VDDB

A=1

0V

VSSB

DACx Input Code

0x000

0xFFF

Figure 28. Output of Analog Processing Chain: Net Effect

If the span is below GNDA, or VDDB = 0 V and VSSB = –5 V, then the output buffer gain is A = –1. This

configuration is depicted Figure 29. This results in effective mapping of the DAC input codes in the range of

0x000 to 0xFFF, to the output voltage range of 0 V to –5 V.

0x000

0xFFF

DACx Input Code

0V

VDDB

A=-1

-5V

VSSB

Figure 29. Common Mode Voltage Below GNDA,

or VDDB = 0 V and VSSB = –5 V

NOTE

Both Buffer Amplifiers share the VDDB and VSSB rails. Therefore, both Buffers produce

gain of A = 1, or both produce gain of A = –1.

The state of the VDDB and VSSB supplies, whether their span is above or below GNDA is indicated by the state

of the DRV_STATUS.GAN bit, and can be read by the controller via the I²C interface.

21

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

8.3.3.3 Output On and Off Control

The LMP92066 facilitates rapid turnon and shutdown of the downstream devices. The FETDRVx outputs can be

switched ON or OFF by the DRVENx input, independently of the I²C bus transactions. The FETDRVx pin is

driven by the Buffer amplifier when the corresponding DRVENx input pin is asserted HIGH. Otherwise, the

FETDRVx pin is connected to VSSB.

The control and switch design was optimized for minimum delay between the DRVENx input and the FETDRVx

switching. The design also ensures that during the state transition there exists an instance when both switches at

FETDRVx are open; that is, no possibility for the crow-bar current to flow from the Buffer output to VSSB.

The switches are assured to default to the state where FETDRVx output is connected to VSSB at power up, as

long as logic 0 is present at the DRVENx input.

8.3.4 Memory

The internal memory of the device consists of 2 distinct areas: the user register set or operating memory and the

EEPROM (non-volatile storage).

The operating memory registers provide the control over device functionality, report internal status of the device,

and store the signal path data (LUT, temperature sensor output, etc). A section of operating memory, designated

as a SCRATCH PAD, is available for arbitrary data storage. All operating memory locations are directly

accessible to the user via the I²C bus.

The EEPROM is not directly accessible via the I²C bus. The EEPROM acquires its data via the transfer from the

operating memory, upon user issued command.

Sections READ and WRITE Access, Access Control, LUT, NOTEPAD Storage, and EEPROM, and Figure 30

detail the internal memory functionality.

8.3.4.1 READ and WRITE Access

The operating memory consists of individually addressable bytes whose content can be accessed via a single

I²C transaction. For 8-bit data, as soon as the I²C transfer is complete the transferred value takes effect.

The device also uses values longer that 8 bits — for example, with Temperature Sensor output, Temperature

Sensor Override input, and the DAC input and Override registers are 12-bit values which require storage in 2

adjacent registers. For these values any access should start with the register containing the upper 4 bits,

immediately followed by the access to the lower byte.

NOTE

It is the WRITE of the lower byte that results in the update of the 12-bit value. See

Table 3.

Table 3. Block Writing

I²C OPERATION

REGISTER

DATA

DESCRIPTION

Enable the BLOCK access and set the block length to 15. This

transfer results in the immediate update of the BLK_CNTL register

and immediate change of behavior of the I²C interface.

WRITE

BLK_CNTL

0x8F

Write the upper nibble of the Temperature Sensor override value.

This transaction does not result in the update of the

TEMPM_OVRD register. The transferred value is placed on a queue

awaiting the transfer of the lower byte. The output of the device is

not affected.

WRITE

TEMPM_OVRD

TEMPL_OVRD

0x08

0x00

Write the lower byte of the Temperature Sensor override value. This

transaction results in the update of both the TEMPM_OVRD and

TEMPL_OVRD registers. The output of the device changes

accordingly with the new setting.

22

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

8.3.4.2 Access Control

By default, all operating memory locations are open to READ access. The WRITE access is controlled by the

Access Level setting. Increasing the Access Level, broadens the scope of the WRITE access. There are 3

access levels available to the user; see Access Control.

User can change the current Access Level by writing a “password” sequence to the ACC_CNTL register. The

“password” sequences are 2 consecutive I²C byte transfers to the ACC_CNTL register. The data content of each

2 byte transfer is unique for each access level.

For example, to enter access level L2 perform the following 2 transfers:

Table 4. Memory Access Control

I²C OPERATION

REGISTER

DATA

DESCRIPTION

First byte of the “password”.

WRITE

ACC_CNTL

0xCD

Second byte of the “password”. After this transfer is

completed the access level is changed to L2.

WRITE

ACC_CNTL

0xF0

0x03

Optional:

Reading the ACC_CNTL serves as status report.

The possible returned values are:

0x00 – access level L0

READ

0x01 – access level L1 is activated

0x03 – access level L2 is activated (and due to

nesting, L1 is also indicated)

Table 5. EEPROM Access Levels

ACCESS LEVEL

SCOPE

Default. User has READ access only to all locations in the operating

memory.

L0

User has READ access to all locations, and WRITE access to ADR_LK

and BLK_CNTL registers.

L1

L2

User has READ and WRITE access to all operating memory locations.

NOTE

The access levels are nested. This means that L1 access level also gives all L0 level

functionality. L2 access level provides L1 and L0 functionality.

8.3.4.3 LUT, NOTEPAD Storage, and EEPROM

The LUT (its coefficients, BASE value, ALU control bits) and the NOTEPAD are stored in the operating memory

block spanning addresses 0x40 through 0x7F. This space is directly accessible (READ and WIRITE) via the I²C

bus.

There is an option to store the LUT and the NOTEPAD in the non-volatile memory, EEPROM. The move of data

from the operating memory to the EEPROM (BURN) is initiated by WRITING a command byte to the

EEPROM_CNTL register.

Upon power up the device automatically executes the TRANSFER of the EEPROM data to the operating

memory. The user can also issue a command via the I²C bus to force the TRANSFER of data from the EEPROM

to the operating memory.

Table 6. EEPROM Control

TRANSFER/BURN

I²C OPERATION

REGISTER

DATA

COMMENT

Transfer of data from the EEPROM to the

operating memory.

TRANSFER

WRITE

EEPROM_CNTL

0x4E

Transfer of data from the operating memory

to the EEPROM.

BURN

WRITE

EEPROM_CNTL

0xE4

23

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

The READ of the EEPROM_CNTL register returns the status of the BURN or TRANSFER.

Table 7. Status of BURN or TRANSFER

EEPROM_CNTL BIT FIELD

DESCRIPTION

0 - The TRANSFER or BURN has completed

1 – The TRANSFER or BURN is in progress

RDYB

1 – A bit error was detected during the transfer from EEPROM to

the operating memory. The error has been corrected and the data

is valid.

COR

1 – A bit error was detected during the transfer from EEPROM to

operating memory. The error was not corrected. LUT data is

compromised.

UCOR

0x00

Temp Sensor

and

DAC Data

0x05

0x07

RESERVED

Temp Sensor Status,

Override Control,

EEPROM Control

RESET,

Access Level Control

0x11

RESERVED

0x16 Block Access Control

RESERVED

0x18

Address Lock

RESERVED

0x1E

0x1F

Output Drive Status,

Device Version

I²C

RESERVED

0x40

BURN

COMMAND

Burn Counter,

LUT Coefficients,

LUT Control

EEPROM

TRANSFER

COMMAND

0x6B

0x6C

Note Pad

0x7F

Figure 30. Memory-to-EEPROM Mapping

24

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

8.3.5 I²C Interface

I²C bus is used for communication between the Master (the digital supervisor; for example, the microcontroller)

and the Slave (LMP92066). This interface provides the user full access to all Data, Status, and Control registers

of the device.

LMP92066 supports Standard-mode and Fast-mode, 100 kbit/s and 400 kbit/s, respectively.

All transactions follow the format:

•

Master begins all transactions by generating START condition.

All transfers comprise 8-bit bytes.

First byte following START must contain 7-bit Slave address.

First byte is followed by a READ/WRITE bit.

All subsequent bytes contain 8-bit data.

By default, the device assumes 1-byte data transfers. Block access can be enabled via BLK_CNTL register,

resulting in multi-byte transfers.

•

Bit order within a byte is always MSB first

ACK/NAK condition follows every byte transfer – this can be generated by either Master or the Slave

depending on direction of data transfer.

STOP condition generated by the MASTER terminates all transactions, and resets the I²C bus. LMP92066

resets its internal address pointer to 0x00.

•

8.3.5.1 Supported Data Transfer Formats

Table 8 lists all conditions defined by the I²C specification and supported by this device. All following bus

descriptions refer to the symbols listed in Table 8.

Table 8. I²C Symbol Set

CONDITION

SYMBOL

SOURCE

DESCRIPTION

START

S

Master

Begins all bus transactions

Terminates all transations and resets

bus

STOP

P

A

Master

ACK (Acknowledge)

Master/Slave

Handshaking bit (LOW)

NAK (Not

Acknowledge)

Handshaking bit (HIGH)

Active HIGH bit that follows

immediately after the slave address

sequence. Indicates that the master

is initiating the slave-to-master data

transfer.

READ

R

Master

Active LOW bit that follows

immediately after the slave address

sequence. Indicates that the master

is initiating the master-to-slave data

transfer.

WRITE

W

Sr

Master

Generated by master, same function

as the START condition (highlights

the fact that STOP condition is not

strictly necessary.)

REPEATED START

25

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

The single data byte transfers are shown in Figure 31 and Figure 32:

S

Slave Address

W

A

RegAddr[7:0]

A

Data[7:0]

A

P

From MASTER to SLAVE

From SLAVE to MASTER

Figure 31. Single-Byte WRITE Access Protocol

S

Slave Address

W

A

RegAddr[7:0]

A

Sr Slave Address

R

A

Data[7:0]

A

P

From MASTER to SLAVE

From SLAVE to MASTER

Figure 32. Single-Byte READ Access Protocol

Block Access functionality is provided to minimize the transfer overhead of large data sets. By default the

LMP92066 is ready to accept multi-byte transfers. Until the transaction is terminated by the STOP condition, the

device will READ (WRITE) the subsequent memory locations.

The size of the contiguous block can be limited by the user. This functionality can be enabled by setting

BLK_CNTL.EN bit. The 7-bit value of BLK_CNTL.SIZE=N sets the size of the contiguous memory block that can

be accessed via the block transfer.

If the Master generates a block transfer that is larger than (BLK_CNTL.SIZE + 1), the internal register pointer

wraps around to the First Register address and the access continue to subsequent memory locations. The

examples of the block WRITE and READ transactions are shown below in Figure 33 and Figure 34:

Address of the First Register of

the contiguous memory block

S

Slave Address

W

A

RegAddr[7:0]

A

Data[7:0]

A

Data[7:0]

A

Data[7:0]

A

P

From MASTER to SLAVE

From SLAVE to MASTER

Data to First Register

N bytes of data to

contiguous memory

locations following First

Register

Figure 33. Block WRITE Access —

BLK_CNTL.EN = 1, BLK_CNTL.SIZE = N

Address of the First Register of

the contiguous memory block

S

Slave Address

W

A

RegAddr[7:0]

A

Sr Slave Address

R

A

Data[7:0]

A

Data[7:0]

A

Data[7:0]

A

P

Data to First Register

N bytes of data to

contiguous memory

locations following First

Register

From MASTER to SLAVE

From SLAVE to MASTER

Figure 34. Block READ Access —

BLK_CNTL.EN = 1, BLK_CNTL.SIZE = N

26

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

8.3.5.2 Slave Address Selection

The I²C bus slave address is selected by installing shunts from A0 and A1 pins of the device to the VIO or GNDD

rails. The device discerns between 3 possible options for each pin: shunt to VIO, shunt to GNDD, or left not

connected (floating), for the total of 9 possible slave addresses.

The state of the A0 and A1 pins is tested after every occurrence of START condition on the I²C bus. However,

the user has an option to LOCK the acquired address by setting the ADR_LK.EN bit. Once the address is locked,

the device stores its Slave address internally and does not attempt to decode the address during subsequent I²C

transactions. The address lock can be disabled by resetting ADR_LK.EN bit. The device resets the ADR_LK.EN

upon power up.

Figure 35 and Figure 36 illustrate the operation of the address decoder circuit. The device internally attempts to

pull up, and then pull down, the Ax pin while monitoring the voltage at that pin. If the shunts are installed, the

weak pull-ups or pull-downs does not affect the voltage at the Ax pin; that is. the state is fixed by the shunt. If the

Ax pin floats, then pull-up and pull-down change the voltage at that pin.

VIO

Device

Terminal

LMP92066

UPx

SHUNT

R_UP

Ax

OUTx

R_DN

ENx

DNx

SHUNT

GNDD

Figure 35. I²C Address Decoder - Simplified Diagram

The address decoder operates during 2nd through 4th cycles of the SCL. The decoding of the state of Ax pins is

performed serially; that is, A0 is decoded first then A1. The functional diagram of the address decoder is shown

in Figure 36.

SCL

EN0

UP0

DN0

EN1

UP1

DN1

Figure 36. I²C Address Decoder - Functional Diagram

27

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

The interpretation of the OUTx values produced from the test phases is summarized in the following table. For

example: if a shunt is present between Ax and VIO (first case in the table), both UPx phase and DNx phase

result in OUTx being decoded as logical 1, unambiguously indicating the presence of the shunt to VIO, or HI

state of Ax.

Table 9. Address Decoder Output

TEST PHASE

DECODED Ax ↓

UPx

DNx

SHUNT to VIO: OUTx →

SHUNT to GNDD: OUTx →

NO SHUNT: OUTx →

1

0

1

0

HI

LO

N.C.

The mapping from the decoded Ax states to the I²C Slave address is shown in Table 10.

Table 10. Slave Address Space

DEVICE PINS

I²C SLAVE ADDRESS

A1

LO

N.C.

HI

A0

LO

N.C.

HI

[A6:A0]

0111111

1000000

1000001

LO

N.C.

HI

1000010

1000011

1000100

LO

N.C.

HI

1000101

HI

1000110

HI

1000111

The Slave Address alignment within the first byte following the START condition is shown in Figure 37:

S

A6 A5 A4 A3 A2 A1 A0 R/W

A

From MASTER to SLAVE

From SLAVE to MASTER

Figure 37. Slave Address Alignment

8.4 Device Functional Modes

The numeric signal path is shown in Figure 38. The signal flow is generally from left to right: the system input is

the temperature sensor, signal processing is done by the LUT/ALU, and the output is driven by the DACs - DAC

detail is omitted as DACs provide a conversion from numeric domain to voltage domain only, and they do not

affect the signal flow.

There are a number of multiplexers in the signal path which alter the data flow when their respective control bits

are set. The multiplexer states, and thus modes of device operation, are described in further detail below.

28

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Device Functional Modes (continued)

DAC1_BASEM.POL

DAC1_BASEM.BYP

S

0

LUT1

ALU

ꢀ

DAC1M.DAC

DAC1L.DAC

[11:6]

12

0

1

DAC1

12

DAC1M_OVRD.DAC

DAC1L_OVRD.DAC

1

S

[5:0]

DAC1_BASEM

DAC1_BASEL

12

OVRD_CTL.TEMP

TEMPM.TEMP

TEMPL.TEMP

Temp.

Sensor

S

0

12

OVRD_CTL.DAC

TEMPM_OVRD.TEMP

TEMPL_OVRD.TEMP

1

DAC0_BASEM.POL

DAC0_BASM.BYP

S

0

1

LUT0

ALU

ꢀ

DAC0M.DAC

DAC0L.DAC

S

0

1

[11:6]

12

DAC0

12

DAC0M_OVRD.DAC

DAC0L_OVRD.DAC

[5:0]

DAC0_BASEM.BASE

DAC0_BASEL.BASE

12

Figure 38. Modes of Operation

8.4.1 Default Operating Mode

This mode of operation is active upon power up. By default the OVRD_CTL.TEMP and OVRD_CTL.DAC are

cleared. The temperature sensor continuously updates readings every 25 ms (registers: TEMPM, TEMPL). Each

temperature sensor update triggers the ALU to re-calculate its output using the user defined coefficients stored in

the LUT. The ALU output is passed on to the DACs (registers: DACxM, DACxL) which ultimately drive the V_DACx

outputs. All of the functionality described here occurs automatically, without intervention from the system

controller, as long as the power is applied to the device supply pins: VDD, VIO, and VDDB.

29

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Device Functional Modes (continued)

8.4.2 Temperature Sensor Override

The temperature sensor output can be overridden by the externally supplied data. This capability may be used to

verify the validity of the function stored in the LUT. The externally supplied data can act as the temperature

sweep input and the output response due to temperature may be readily observed, without actually altering the

temperature of the test setup.

This functionality is facilitated by the multiplexer that follows the temperature sensor, and user writable data

registers TEMPM_OVRD and TEMPL_OVRD. TEMPM_OVRD[3:0] is the upper nibble of the temperature data.

TEMPL_OVRD[7:0] is the lower byte of the temperature data. The multiplexer control signal is the

OVRD_CTL.TEMP bit.

Table 11 shows an example of the I²C bus transfer sequence which results in externally supplied data indexing

the LUT.

Table 11. I²C Bus Transfer Sequence:

Externally Supplied Data Indexing LUT

I²C OPERATION

WRITE

REGISTER

ACC_CNTL

DATA

DESCRIPTION

First byte of the “password”

0xCD

0xF0

WRITE

ACC_CNTL

Second byte of the “password”. After this transfer is completed

the access level is changed to L2

READ

ACC_CNTL

0x03

0x01

Optional:

Reading the ACC_CNTL serves as status report.

0x03 – access level L2 is activated (and due to nesting, L1 is

also indicated)

WRITE

TEMPM_OVRD

TEMPL_OVRD

OVRD_CTL

Writes 0x1 as the value of the top nibble of the 12-bit, twos

complement, temperature value. After this transaction the

TEMPM_OVRD register is not updated, yet. The update takes

place only after the TEMPL_OVRD register is written.

Writes 0x01 into the lower byte of temperature value. After this

transaction completes both TEMPM_OVRD and

TEMPL_OVRD registers are updated. The 12-bit value in this

example is 0x101 which corresponds to 16.0625°C

Sets the OVRD_CTL.TEMP bit. This causes the temperature

stored in the TEMPM_OVRD and TEMPL_OVRD to index the

LUT.

READ

TEMPM

TEMPL

0x**

Optional:

Read the actual temperature reported by the temperature

sensor.

The temperature sensor override is cancelled by clearing the OVRD_CTL.TEMP bit.

NOTE

TEMPM_OVRD, TEMPL_OVRD and OVRD_CTL registers are in the volatile section of

memory and are not backed by EEPROM. Upon power up these registers are cleared.

8.4.3 ALU Bypass

It may be desirable that the device produces a predetermined constant output level as soon as it is powered up.

The ALU bypass mode does that. This mode is enabled by setting DACx_BASEM.BYP bit. Since

DACx_BASEM.BYP is stored in the EEPROM, its value is automatically loaded into the operating memory at

power up. If the stored value for DACx_BASEM.BYP is 1, upon power up the corresponding DAC output

immediately produces an analog output equivalent of the BASE.

In this mode of operation the ALU is bypassed, and the BASE value of the LUT is presented at the input of the

DAC. This is the result of DACx_BASEM.BYP, which controls the mux that follows the ALU in the signal path,

being set. Therefore, the output of the device is constant over the operating temperature range of the device.

30

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

NOTE

Each channel has its own BYP bit, and its own BASE value.

8.4.4 DAC Input Override

The DAC inputs words can be directly written via the I²C interface. In this mode the LMP92066 is a dual 12-bit

DAC. This functionality is facilitated by the multiplexers that precede the DACs, and user writable data registers

DACxM_OVRD and DACxL_OVRD. DACxM_OVRD[3:0] is the upper nibble of the DAC input word.

DACxL_OVRD[7:0] is the lower byte of the DAC input data.

The multiplexer control signal is the OVRD_CTL.DAC bit. This bit is shared by both channels; that is, both

channels are either in the DAC input override mode, or both are in the default mode.

Table 12 shows the example of the I²C bus transfer sequence which results in externally supplied data being the

source of input to the DACs.

Table 12. I²C Bus Transfer Sequence:

Externally Supplied Data Sourcing Input to DACs

I²C OPERATION

WRITE

REGISTER

ACC_CNTL

DATA

DESCRIPTION

First byte of the “password”

0xCD

0xF0

WRITE

ACC_CNTL

Second byte of the “password”. After this transfer is completed

the access level is changed to L2

READ

ACC_CNTL

0x03

0x08

0x00

0x04

0x00

0x02

Optional:

Reading the ACC_CNTL serves as status report.

0x03 – access level L2 is activated (and due to nesting, L1 is

also indicated)

WRITE

DAC0M_OVRD

DAC0L_OVRD

DAC1M_OVRD

DAC1L_OVRD

OVRD_CTL

Writes 0x8 as the value of the top nibble of the 12-bit, offset

binary, DAC0 input value. After this transaction the

DAC0M_OVRD register is not updated, yet. The update takes

place only after the DAC0L_OVRD register is written.

Writes 0x00 into the lower byte of the DAC0 input value. After

this transaction completes both DAC0M_OVRD and

DAC0L_OVRD registers are updated. The 12-bit value in this

example is 0x800.

Writes 0x4 as the value of the top nibble of the 12-bit, offset

binary, DAC1 input value. After this transaction the

DAC1M_OVRD register is not updated, yet. The update takes

place only after the DAC1L_OVRD register is written.

Writes 0x00 into the lower byte of the DAC1 input value. After

this transaction completes both DAC1M_OVRD and

DAC1L_OVRD registers are updated. The 12-bit value in this

example is 0x400.

Sets the OVRD_CTL.TEMP bit. This causes both multiplexers

that precede the DACs to start routing the DACx_OVRD

values to the inputs of their respective DACs. As a result the

outputs of the device are: VDAC0 = 2.5 V, and VDAC1 = 1.25

V

READ

DAC0M

DAC0L

0x**

Optional:

Read the values computed by the ALU.

NOTE

The DAC Input Override and Temperature Sensor Override modes are mutually exclusive.

The allowed values for OVRD_CTRL register are 0x00, 0x01 or 0x02.

NOTE

DACxM_OVRD, DACxL_OVRD and OVRD_CTL registers are in the volatile section of

memory and are not backed by EEPROM. Upon power up these registers are cleared.

31

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

8.4.5 LDMOS and GaN Drives

The LDMOS mode and the GaN mode result from 2 possible biasing methods of the DAC output buffers – these

were described in earlier sections of this data sheet.

The LDMOS mode is in effect when the VDDB and VSSB common mode is above GNDA. This mode is suitable

for biasing of the LDMOS Power Amplifiers, since the output produced by the LMP92066 is in the 0 V to 5 V

range. The GaN mode is in effect when the VDDB and VSSB common mode is below GNDA. This mode is

suitable for biasing of the GaN type Power Amplifiers, as the output produced by the LMP92066 is in the 0V to

–5V range.

8.5 Programming

8.5.1 Temperature Sensor Output Data Access Registers

The temperature sensor produces a 12-bit output value, TEMP[11:0], which is stored in 2 adjacent registers:

TEMPM and TEMPL.

The temperature sensor updates its output every 25 ms, nominally, but the exact instance of the update is

unknown to the user. It is possible that the temperature sensor produces a new value between READ operations

of TEMPM and TEMPL. Therefore, a synchronization mechanism was implemented, to assure that TEMPM and

TEMPL values correspond to the same temperature sample. The coherence of the temperature sensor data is

maintained if the READ sequence is: read TEMPM first, then TEMPL.

ACCESS ACCESS

ADDRESS

NAME

BIT

7

FUNCTION

RES

DESCRIPTION

TYPE

LEVEL

Reserved bit.

The value may be reported as 0 or 1

Reserved bit.

Always reported as 0.

6:5

4

*

0x00

TEMPM

R

L0

Reserved bit.

The value may be reported as 0 or 1.

RES

4-bit MSB nibble of the 12-bit Temperature Sensor

output word.

3:0

TEMP[11:8]

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit Temperature Sensor

output word.

0x01

TEMPL

R

L0

7:0

TEMP[7:0]

8.5.2 DAC Input Data Registers

The 12-bit data produced by the LUT and ALU is stored in the DAC0M and DAC0L, and DAC1M and DAC1L

pairs of registers. Unless overridden (see Override Control Register), the contents of these registers are

presented at each DAC inputs.

In cases where the user wants to read the temperature sensor output and resulting DACxM or DACxL data, the

following read order has to be maintained to assure the coherency of data: TEMPM, TEMPL, DAC0M, DAC0L,

DAC1M, DAC1L.

Coherency of the TEMPM is still maintained, and TEMPL read is omitted in the sequence above.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x02

DAC0M

R

L0

7:4

3:0

*

Reserved bit. Always report as 0.

DAC[11:8]

4-bit MSB nibble of the 12-bit DAC0 input word.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit Temperature Sensor

output word.

0x03

DAC0L

R

L0

7:0

DAC[7:0]

32

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x04

DAC1M

R

L0

7:4

3:0

*

Reserved bit. Always report as 0.

DAC[11:8]

4-bit MSB nibble of the 12-bit DAC1 input word.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x05

DAC1L

R

L0

7:0

TEMP[7:0]

8-bit LSB byte of the 12-bit DAC1 input word.

8.5.3 Temperature Sensor Status Register

This register may contain non-zero values immediately after the device power up. Within 100 ms of the power up

the TEMP_STATUS register clears, indicating the temperature sensor’s output is valid.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

If RDYB=0x00, the Temperature Sensor is initialized

and producing valid output.

0x07

TEMP_STATUS

R

L0

7:0

RBYB

8.5.4 Override Control Register

Override functionality allows the user to insert external data into the signal path of the device. When TEMP

override is enabled, the temperature sensor’s data is ignored, and the user-supplied data is used to index the

LUT (TEMPM_OVRD and TEMPL_OVRD, below). When DAC override is enabled the LUT and ALU produced

output is ignored, and both DAC0 and DAC1 use external data as their inputs (DAC0M_OVRD, DAC0L_OVRD

and DAC1M_OVRD and DAC1L_OVRD described below).

NOTE

Only 3 OVRD_CNTL[2:0] settings are allowed: 0x0, 0x1, 0x2; simultaneous DAC and

TEMP override is not allowed.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

7:4

3

*

Reserved bit. Always WRITE 0

RES

2

DAC override enable bit:

0: DAC input generated by LUT

1: DAC input is supplied from user accessible

registers DACxy_OVRD.

1

0

DAC

0x08

OVRD_CNTL

R/W

L2

DAC override enable bit:

0: DAC input generated by LUT

1: DAC input is supplied from user accesible

registers TEMPy_OVRD.

TEMP

8.5.5 Override Data Registers

These registers hold the externally supplied data to be inserted into the signal path of the device (see

OVRD_CNTL).

NOTE

Since override data are 12-bit words stored in 2 adjacent registers, it is the writing of the

lower byte that makes the new value take effect.

33

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

ACCESS ACCESS

ADDRESS

NAME

BIT

7:4

3:0

FUNCTION

*

DESCRIPTION

TYPE

LEVEL

Reserved bit. Always report as 0.

0x09

TEMPM_OVRD

R/W

L2

4-bit MSB nibble of the 12-bit Temperature Sensor

override input word.

TEMP[11:8]

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit Temperature Sensor

output word.

0x0A

TEMPL_OVRD

R/W

L2

7:0

TEMP[7:0]

ACCESS ACCESS

ADDRESS

NAME

BIT

7:4

3:0

FUNCTION

*

DESCRIPTION

TYPE

LEVEL

Reserved bit. Always report as 0.

0x0B

DAC0M_OVRD

R/W

L2

4-bit MSB nibble of the 12-bit DAC0 input override

word.

DAC[11:8]

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit DAC0 input override

word.

0x0C

DAC0L_OVRD

R/W

L2

7:0

DAC[7:0]

ACCESS ACCESS

ADDRESS

NAME

BIT

7:4

3:0

FUNCTION

*

DESCRIPTION

TYPE

LEVEL

Reserved bit. Always report as 0.

0x0D

DAC1M_OVRD

R/W

L2

4-bit MSB nibble of the 12-bit DAC1 input override

word.

DAC[11:8]

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit DAC1 input override

word.

0x0E

DAC1L_OVRD

R/W

L2

7:0

DAC[7:0]

8.5.6 EEPROM Control Register

Writing a command byte results in either the EEPROM BURN (the commitment of a section of operating memory

to non-volatile storage), or the TRANSFER (recall of the data in the non-volatile storage to the operating

memory.

Reading this register yields status information.

NOTE

UCOR and COR bits are updated only by the TRANSFER command.

34

LMP92066

www.ti.com.cn

ADDRESS

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

ACCESS ACCESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

Instruction to BURN EEPROM or TRANSFER

EEPROM content to operating memory:

0xE4: BURN EEPROM.

W

L2

7:0

*

0x4E: TRANSFER data from EEPROM to operating

memory.

7:3

2

*

Reserved bit.

1: More than one bit error was detected during the

TRANSFER, and correction was not possible.

0: No uncorrected errors were detected during the

TRANSFER.

0x0F

EEPROM_CNTL

UCOR

R

L0

1: A bit error was detected and corrected during the

TRANSFER.

0: No errors detected during the TRANSFER.

1

0

COR

1: BURN or TRANSFER in progress.

0: BURN or TRANSFER completed.

RDYB

8.5.7 Software RESET Register

Has the same effect as the power-on reset.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

WRITE 0xC3 to reset the deice to the power-up

default state.

0x10

RESET

W

L2

7:0

DAC[7:0]

8.5.8 Access Control Register

Changing the Access Level requires writing the 2-byte password sequence. Reading this register yields status

information.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

WRITE 2-byte password to change access level:

0xCD, 0xEF: Access Level L1.

W

L0

7:0

PSWD

0xCD, 0xF0: Access Level L2.

7:2

1

*

0x11

ACC_CNTL

1: Access Level L2 is enabled.

0: L2 not enabled.

R

L0

1: Access Level L1 is enabled.

0: L1 not enabled.

0

RES

8.5.9 Block I²C Access Control Register

The I²C master may request a continuous transfer of data from or to the slave. By default, the slave continues

advancing its internal register pointer to the end of the internal register space, and then wrap back to address

0x00 and continue on.

BLK_CNTL allows to limit the size of the contiguous memory accessed continuously.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

Enable the control of the I²C access block size:

1: Enabled.

7

EN

0: Block size control is disabled.

0x16

BLK_CNTL

R/W

L1

7-bit SIZE of the I²C access block. The continuous

I²C transaction accesses SIZE+1 memory locations,

and then wrap back to the starting address.

6:0

*

35

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

8.5.10 I²C Address LOCK Register

Allows the device to LOCK its own I²C slave address. Once the slave address is locked, the device does not

attempt to decode the state of A0 and A1 address setting pins on subsequent transactions.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

7:3

2

*

Always set to 0

RES

Reserved bit. Always write 0.

1

0x18

ADR_LK

R/W

L1

1: Lock the slave address

0: Slave address is not locked. Device decodes state

of A1 and A0 after every START condition of the I²C

bus.

0

EN

NOTE

The locked address is the one present at the A[1:0] pins during the I²C transaction that

follows the ADR_LK command.

8.5.11 Output Drive Supply Status Register

The device output stage can operate in either LDMOS or GaN modes. The mode is determined by the potential

applied to the VDDB and VSSB supply pins.

The device monitors the VDDB and VSSB supplies, and reports the mode of operation via the GaN status bit.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

Reserved. Always reports 0

TYPE

LEVEL

7:1

*

1: GaN mode supply rails detected; that is, VDDB =

GNDA,

VSSB = –5V.

0: LDMOS mode supply rails detected; that is, VDDB

0x1E

DRV-STATUS

R

L0

0

GAN

= +5V,

VSSB = GNDA.

8.5.12 Device Version Register

Factory set value.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x1F

VERSION

R

L0

7:0

VERSION

8-bit device revision number.

8.5.13 EEPROM Burn Counter

The value is incremented automatically at the start of BURN sequence.

This data is transferred automatically from the EEPROM to operating memory upon power up.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x40

BURN_CT

R

L0

7:0

COUNT

8-bit EEPROM BURN counter.

8.5.14 LUT Coefficient Registers

This data is transferred to the EEPROM when a BURN command sequence is issued.

This data is transferred automatically from the EEPROM to operating memory upon power up or after a software

reset.

36

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

NOTE

The LUT values are stored at locations corresponding to 4°C increments from –28°C to

128°C. There is no increment corresponding to 24°C because this temperature is a

BASELINE, and the corresponding LUT value is 12-bit BASE (see Look-Up-Table (LUT)

and Arithmetic-Logic Unit (ALU) ).

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x41

↓

DEL0

↓

7:4

DAC1[3:0]

4-bit LUT1 entry

4-bit LUT0 entry

0x4D

0x4E

↓

DEL12 (20°C)

DEL13 (28°C)

↓

R/W

L2

3:0

DAC0[3:0]

0x67

DEL38 (128°C)

8.5.15 LUT Control Registers

This data is transferred to the EEPROM when a BURN command sequence is issued.

This data is transferred automatically from the EEPROM to operating memory upon power up.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

Reserved bit. Always write 0.

TYPE

LEVEL

7

6

RES

Reserved bit. Always reported as 0.

ALU bypass control:

5

BYP

1: Bypass ALU. Send BASE value to DAC0.

0: ALU output sent to DAC0.

LUT increment polarity control:

1: All LUT values are treated as negatives. This

realizes a monotonically decreasing LUT0 transfer

function.

0x68

DAC0_BASEM

R/W

L2

4

POL

0: All LUT values are treated as positive numbers.

This realizes a monotonically increasing LUT0

transfer function.

4-bit MSB nibble of the 12-bit LUT0 BASE value

(LUT0 output at +24°C).

3:0

BASE[11:8]

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit BASE value (LUT0

output at +24°C).

0x69

DAC0_BASEL

R

L2

7:0

BASE[7:0]

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

7

6

RES

Reserved bit. Always write 0.

Reserved bit. Always reported as 0.

ALU bypass control:

5

BYP

1: Bypass ALU. Send BASE value to DAC1.

0: ALU output sent to DAC1.

LUT increment polarity control:

1: All LUT values are treated as negatives. This

realizes a monotonically decreasing LUT1 transfer

function.

0x6A

DAC1_BASEM

R/W

L2

4

POL

0: All LUT values are treated as positive numbers.

This realizes a monotonically increasing LUT1

transfer function.

4-bit MSB nibble of the 12-bit LUT1 BASE value

(LUT0 output at +24°C).

3:0

BASE[11:8]

37

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

8-bit LSB byte of the 12-bit BASE value (LUT1

output at +24°C).

0x6B

DAC1_BASEL

R

L2

7:0

BASE[7:0]

8.5.16 Notepad Registers

20 bytes of memory for arbitrary data storage. This data does not affect the operation of the device. This data is

transferred to the EEPROM when BURN command sequence is issued.

This data is transferred automatically from the EEPROM to operating memory upon power up.

ACCESS ACCESS

ADDRESS

NAME

BIT

FUNCTION

DESCRIPTION

TYPE

LEVEL

0x6C

↓

PAD0

↓

20 bytes of memory for arbitrary data storage. This

data does not affect the operation of the device.

This data is transferred to the EEPROM when BURN

command sequence is issued via I²C transaction.

R/W

L2

7:0

*

0x7F

PAD19

38

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

8.6 Register Map

BIT FIELDS

ACC.

LVL

ADDRESS TYPE

NAME

NOTES

POR

7

6

5

4

3

2

1

0

8'h00

8'h01

8'h02

8'h03

8'h04

8'h05

8'h06

8'h07

8'h08

8'h09

8'h0A

8'h0B

8'h0C

8'h0D

8'h0E

8'h0F

8'h10

8'h11

8'h12

8'h13

8'h14

8'h15

8'h16

8'h17

8'h18

8'h19

8'h1A

8'h1E

8'h1F

R

L0

L2

L0

L2

L0

L1

L0

L1

L0

TEMPM

TEMPL

DAC0M

DAC0L

DAC1M

DAC1L

RES

0

RES

TEMP[11:8]

DAC[11:8]

TEMP[7:0]

DAC[7:0]

R

DAC[7:0]

RES

R

TEMP_STATUS RDYB RDYB RDYB RDYB RDYB RDYB RDYB RDYB

8'hFF

R/W

W

OVRD_CNTL

TEMPM_OVRD

TEMPL_OVRD

DAC0M_OVRD

DAC0L_OVRD

DAC1M_OVRD

DAC1L_OVRD

EEPROM_CNTL

RESET

RES RES DAC TEMP

TEMP[11:8]

0

8'h01

8'h80

8'h00

8'h80

8'h00

TEMP[7:0]

DAC[11:8]

DAC[7:0]

F o r B U R N w r i t e : 8 ' h E 4

F o r T R A N S F E R w r i t e : 8 ' h 4 E

BURN or TRNASFER command

UCOR COR RDYB

R

W

SYSTEM RESET œ EQUIVALENT TO POWER-UP

write: 8'hC3

F o r L 1 w r i t e : 8 ' h C D , 8 ' h E F

F o r L 2 w r i t e : 8 ' h C D , 8 ' h F 0

W

ACC_CNTL

RES

ACCESS LEVEL PASSWORD

R

L2

L1

8'h00

R/W

W

0

RES

R

RES

R/W

R

RES

BLK_CNTL

RES

EN

SIZE

0

RES RES RES

RES RES EN

ADR_LK

RES

0

RES RES

GAN

RES

DRV_STATUS

VERSION

0

R

VERSION=8'hA0

39

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Register Map (continued)

BIT FIELDS

ACC.

LVL

ADDRESS TYPE

NAME

NOTES

POR

7

6

5

4

3

2

1

0

8'h40

8'h41

8'h42

8'h43

8'h44

8'h45

8'h46

8'h47

8'h48

8'h49

8'h4A

8'h4B

8'h4C

8'h4D

8'h4E

8'h4F

8'h50

8'h51

8'h52

8'h53

8'h54

8'h55

R

L0

BURN_CT

DEL0

R/W

L2

DAC1[3:0]

DAC0[3:0]

-28°C

-24°C

-20°C

-16°C

-12°C

-8°C

DEL1

DEL2

DEL3

DEL4

DEL5

DEL6

-4°C

DEL7

0°C

DEL8

4°C

DEL9

6°C

DEL10

DEL11

DEL12

DEL13

DEL14

DEL15

DEL16

DEL17

DEL18

DEL19

DEL20

12°C

16°C

20°C

28°C

32°C

36°C

40°C

44°C

48°C

52°C

56°C

40

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Register Map (continued)

BIT FIELDS

ACC.

ADDRESS TYPE

LVL

NAME

NOTES

POR

7

6

5

4

3

2

1

0

8'h56

8'h57

8'h58

8'h59

8'h5A

8'h5B

8'h5C

8'h5D

8'h5E

8'h5F

8'h60

8'h61

8'h62

8'h63

8'h64

8'h65

8'h66

8'h67

8'h668

8'h679

8'h6A

8'h6B

R/W

L2

DEL21

DEL22

DEL23

DEL24

DEL25

DEL26

DEL27

DEL28

DEL29

DEL30

DEL31

DEL32

DEL33

DEL34

DEL35

DEL36

DEL37

DEL38

DAC1[3:0]

DAC0[3:0]

BDAASCE0[[131:0:8]]

DAC0[3:0]

BASE[11:8]

60°C

64°C

68°C

72°C

76°C

80°C

84°C

88°C

92°C

96°C

100°C

104°C

108°C

112°C

116°C

120°C

124°C

128°C

12244°C°C

12248°C°C

24°C

DACD0E_BL3A7SEM RES RDEASC1[3B:Y0P] POL

DACD0E_LB3A8SEL DAC1[3:0] BASE[7:0]

DAC1_BASEM RES RES BYP POL

DAC1_BASEL BASE[7:0]

24°C

41

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Register Map (continued)

BIT FIELDS

ACC.

LVL

ADDRESS TYPE

NAME

NOTES

POR

7

6

5

4

3

2

1

0

8'h6C

8'h6D

8'h6E

8'h6F

8'h70

8'h71

8'h72

8'h73

8'h74

8'h75

8'h76

8'h77

8'h78

8'h79

8'h7A

8'h7B

8'h7C

8'h7D

8'h7E

8'h7F

R/W

L2

PAD0

PAD1

L2

PAD2

PAD3

PAD4

PAD5

PAD6

PAD7

PAD8

PAD9

PAD10

PAD11

PAD12

PAD13

PAD14

PAD15

PAD16

PAD17

PAD18

PAD19

42

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMP92066 was designed for ease of use. The device requires minimum external components to realize its

full functionality. In the typical application the bulk of the design effort is spent on characterization of the target

transfer function, and then developing a set of coefficients that the LMP92066 to accurately reproduce the target

function.

NOTE

The LMP92066 can approximate temperature dependent functions, V_DAC0,1(T), only if the

following requirements are met:

1. Each V_DAC0,1(T) must be unipolar. The range of the function must be either wholly positive, or

wholly negative. This is dictated by the structure of the Buffer Amplifier that drives the

FETDRVx. See the Buffer Amplifier section.

2. Both functions V_DAC0,1(T) must be of the same polarity. See the Buffer Amplifier section.

3. Each V_DAC0,1(T) must be monotonic. This is dictated by the structure of the LUTs. See the LUT

and ALU Organization section.

4. The maximum slope of each V_DAC0,1(T) is no greater than 4.88 mV/°C. This also limits the

maximum range, the minimum to maximum span, for the V_DAC0,1(T) to 761 mV. This is due to

the fact that the LUT stores the slope of the V_DAC0,1(T) as 4-bit values. See the The LUT Input

and Output Ranges section.

9.2 Typical Applications

9.2.1 Temperature Compensated Bias Generator for LDMOS Power Amplifer (PA)

The typical application for the LMP92066 is the biasing of the power amplifiers in an RF system. What is required

in such applications is for the PA drain current to remain constant over a wide range of operating temperatures.

The LMP92066 senses the PA temperature and adjust the bias potential at the gate of the PA in accordance with

the known V_GS(T), at I_D= constant, characteristic of the PA.

The typical application circuit for LDMOS applications is shown in Figure 39. A thermal path has to be provided

between the LMP92066 and the PA. This is typically accomplished through the close proximity of the 2 devices,

and the common metal layer. See also the Layout Example.

43

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Typical Applications (continued)

3.3V

5V

+

RF_IN

100n

47µ

VIO

VDD

VDDB

PA: LDMOS

FETDRV1

DAC1

ꢀ/4

10n

SDA

SCL

10µ

µC

RF_IN

LMP92066

DRVEN1

DRVEN0

A1

A0

FETDRV0

DAC0

ꢀ/4

PA: LDMOS

10n

GNDD GNDA VSSB

10µ

Figure 39. Temperature-Compensated Bias Generator

for LDMOS Power Amplifier (PA)

9.2.1.1 Design Requirements

The thermal characteristic of a hypothetical LDMOS PA is plotted in Figure 40. This characteristic was obtained

from the temperature sweep of the LDMOS gate-source voltage, V_GS, while keeping the drain current, I_D= 750

mA. The goal is to have the LMP92066 produce that same V_GSvs T characteristic which, when applied to the

gate of the PA device ensures constant I_Dthroughout the operating temperature range.

In the following sections the curve V_GSvs T are referred to as the Target Function, V_DAC(T).

2.50

2.45

2.40

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.00

0

20

40

60

80

100 120 140

œ40 œ20

Temperature (°C)

C023

Figure 40. Target Function to be Reproduced by the LMP92066:

V_GSvs T Characteristic of an LDMOS PA

The target function is approximated by the following polynomial (T unit is °C):

V_DAC(T) = 5.1ì10^-10(T)⁴- 2.63ì10^-8(T)³+ 3.58ì10^-6(T)²+ 5.14ì10^-4(T)+ 2.26

(7)

In the Detailed Design Requirements section the above expression is used to obtain the LUT coefficient values.

44

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Typical Applications (continued)

9.2.1.2 Detailed Design Requirements

Figure 41 outlines the LUT design procedure. The procedure is for one channel only – repeat for the second

available channel, as needed. In principle, the procedure follows the signal path backwards from the output,

which is ideally the target function V_DAC(T), back to the LUT coefficients, and each block’s processing has to be

“reversed”. Additional comments for each design step are listed below Figure 41.

Designate the target function

1

V_DAC(T)

No

Yes

Assign

pBUF(T) = -V_DAC(T)

V_DAC(T) > 0,

for all T

Assign

pBUF(T) = V_DAC(T)

2

3

VDDB = 0V,

VSSB = -5V

VDDB = 5V,

VSSB = 0V

No

Yes

Assign

cG(T) = -pBUF(T)

dpBUF(T)/dT > 0,

for all T

Assign

cG(T) = pBUF(T)

POL=1

POL=0

Sample cG(T) at T= -28, -24..24..128(°C)

Store fpBASE = cG(T=24°C)

Store as G(k), k=0..39

4

5

Difference G(k) samples

fpDEL(k) = G(k+1)-G(k), for k=0..38

Map Voltage to numeric domain,

and quantize

BASE = round( fpBASE x 4096/5 )

DEL(k) = round( fpDEL(k) x 4096/5 )

6

7

BASE (12-bit)

DEL(k) (4-bit)

Figure 41. Flowchart of the Generalized LUT Design Procedure

1. Before attempting to calculate the LUT coefficients for the given target function V_DAC(T), verify the

requirements listed in the Application Information section are met.

2. Test if the function is wholly positive, or negative. If necessary “undo” the action of the Buffer Amplifier. (See

the Buffer Amplifier section.) From now on consider the pre-buffer signal pBUFF(T). The design variable set

in this step is the state of the VDDB and VSSB supplies. V_DAC(T) is a strictly positive valued function,

therefore:

VDDB = 5 V

VSSB = GNDA

pBUFF(T) = V_DAC(T)

(8)

45

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Typical Applications (continued)

3. Check the slope of the pBUF(T). Record the sign of the slope, and from here on consider a positive slope

function cG(T). The design variable set in this step is the POL bit. pBUFF(T) is a monotonically increasing

function, therefore:

POL = 0

cG(T) = pBUFF(T)

(9)

4. Discretize the continuous cG(T) along its temperature domain, thus creating the sequence G(k). Maintain the

full precision of the G(k) values. Note the full precision cG(T) at T = 24°C — this is the full precision BASE

value, fpBASE, still in voltage domain.

G(0) = cG( - 28èC) = 2.2499

G(1) = cG( - 24èC) = 2.2508

G(2) = cG( - 20èC) = 2.2508

é

G(13) = cG(24èC) = 2.2747 = fpBASE

é

G(39) = cG(128èC) = 2.4667

5. Apply difference operation to the G(k) sequence, and obtain new sequence fpDEL(k). These are now the full

precision increments of the target function with each 4°C interval.

fpDEL(0) = G(1) - G(0) = 0.9528 ì10^-3

fpDEL(1) = G(2) - G(1) = 1.1846 ì10^-3

fpDEL(2) = G(3) - G(2) = 1.3891ì10^-3

é

fpDEL(38) = G(39) - G(38) = 16.9789 ì10^-3

6. Convert the full precision voltages of fpDEL(k) and fpBASE to a numeric, quantized domain. This reverses

the DAC action.

fpBASEì 4096

≈

’

BASE = round

= 1863₁₀= 747₁₆= 011101000111₂

∆

«

÷

5

◊

fpDEL(0)ì 4096

≈

’

DEL(0) = round

= 1 = 1 = 0001₂

10

16

∆

«

÷

5

◊

é

fpDEL(38)ì 4096

≈

’

DEL(38) = round

= 14₁₀= E₁₆= 1110₂

∆

÷

5

«

◊

7. Usually BYP bit is reset, BYP=0. However, in cases where it is desirable to bypass the LUT and ALU, and

have the DACx output produce voltage equivalent of the BASE value, set BYP = 1.

8. Repeat steps 1 to 6 to obtain POL, BYP, BASE, DELx values for the second channel.

9. Now have BYP, POL, BASE, and DEL(0..38) values ready to be programmed into the LUT.

NOTE

The device has to be in the L2 Access Level before commencing the WRITE access of

BYP, POL, BASE, DELx values. The register WRITE operation immediately affects the

operation of the device. However, operating memory is volatile, and BURN operation is

required to commit the LUT coefficients to non-volatile memory, EEPROM.

46

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Typical Applications (continued)

9.2.1.3 Application Curves

The output of the LMP92066 due to the coefficients calculated in the above procedure is shown in Figure 42.

Figure 43 shows the absolute difference between the target function and the measured response of the

LMP92066.

2.50

2.45

2.40

2.35

2.30

2.25

2.20

2.15

2.10

2.05

2.00

10

8

6

4

2

0

œ2

œ4

œ6

œ8

œ10

0

20

40

60

80

100 120 140

0

20

40

60

80

100 120 140

œ40 œ20

Temperature (°C)

C024

C025

Figure 42. Measured Response of the LMP92066

Resulting from the LUT Coefficients

Figure 43. Difference Between the Target Response

shown in Figure 40 and

(see Detailed Design Requirements)

Measured Response in Figure 42

9.2.2 Temperature Compensated Bias Generator for GaN Power Amplifer (PA)

The typical application for the LMP92066 is the biasing of the power amplifiers in an RF system. What is required

in such applications is for the PA drain current to stay constant over a wide range of operating temperatures. The

LMP92066 senses the PA temperature and adjust the bias potential at the gate of PA in accordance with the

known V_GS(T), at I_D= constant, characteristic of the PA.

47

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Typical Applications (continued)

3.3V

5V

+

RF_IN

100n

47µ

VDD

VDDB

VIO

PA: GaN

FETDRV1

ꢀ/4

10n

DAC1

+

SDA

SCL

10µ

µC

LMP92066

RF_IN

DRVEN1

DRVEN0

PA: GaN

A1

A0

FETDRV0

DAC0

ꢀ/4

10n

+

GNDD

GNDA VSSB

10µ

+

10µ

100n

-5V

Figure 44. Temperature-Compensated Bias Generator

for GaN Power Amplifier (PA)

9.2.2.1 Design Requirements

The thermal characteristic of a hypothetical GaN PA is plotted in Figure 45. This characteristic was obtained from

the temperature sweep of the GaN gate-source voltage, V_GS, while keeping the drain current, I_D= 750 mA. The

goal is to have the LMP92066 produce that same V_GSvs T characteristic which, when applied to the gate of the

PA device ensures constant ID throughout the operating temperature range.

In the following sections the curve V_GSvs T is referred to as the Target Function, V_DAC(T).

œ1.00

œ1.05

œ1.10

œ1.15

œ1.20

œ1.25

œ1.30

œ1.35

œ1.40

œ1.45

œ1.50

0

20

40

60

80

100 120 140

œ40 œ20

Temperature (°C)

C026

Figure 45. The Target Function to be Reproduced by the LMP92066:

V_GSvs T Characteristic of an GaN PA

48

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Typical Applications (continued)

The target function is approximated by the following polynomial (T unit is °C):

V_DAC(T) = 6.33ì10^-11(T)⁴-2.34ì10^-8(T)³-1.95ì10^-6(T)²-5.04ì10^-4(T)-1.26

9.2.2.2 Detailed Design Procedure

Figure 46 outlines the LUT design procedure. The procedure is for one channel only – repeat for the second

available channel, as needed.

In principle, the procedure follows the signal path backwards from the output, which is ideally the target function

V_DAC(T), back to the LUT coefficients, reversing the processing of each block. Additional comments for each

design step are listed below Figure 46.

Designate the target function

1

V_DAC(T)

No

Yes

Assign

pBUF(T) = -V_DAC(T)

V_DAC(T) > 0,

for all T

Assign

pBUF(T) = V_DAC(T)

2

3

VDDB = 0V,

VSSB = -5V

VDDB = 5V,

VSSB = 0V

No

Yes

Assign

cG(T) = -pBUF(T)

dpBUF(T)/dT > 0,

for all T

Assign

cG(T) = pBUF(T)

POL=1

POL=0

Sample cG(T) at T= -28, -24..24..128(°C)

Store fpBASE = cG(T=24°C)

Store as G(k), k=0..39

4

5

Difference G(k) samples

fpDEL(k) = G(k+1)-G(k), for k=0..38

Map Voltage to numeric domain,

and quantize

BASE = round( fpBASE x 4096/5 )

DEL(k) = round( fpDEL(k) x 4096/5 )

6

7

BASE (12-bit)

DEL(k) (4-bit)

Figure 46. Flowchart of the Generalized LUT Design Procedure

1. Before attempting to calculate the LUT coefficients for the given target function V_DAC(T), verify the

requirements listed in the Application Information section are met.

2. Test if the function is wholly positive, or negative. If necessary “undo” the action of the Buffer Amplifier. (See

the Buffer Amplifier section.) From now on consider the pre-buffer signal pBUFF(T). The design variable set

in this step is the state of the VDDB, VSSB supplies. V_DAC(T) is a strictly positive valued function, therefore:

49

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Typical Applications (continued)

VDDB = GNDA

VSSB = -5 V

pBUFF(T) = -V_DAC(T)

(10)

3. Check the slope of the pBUF(T). Record the sign of the slope, and from here on consider a positive slope

function cG(T). The design variable set in this step is the POL bit. pBUFF(T) is a monotonically increasing

function, therefore:

POL = 0

cG(T) = pBUFF(T)

(11)

4. Discretize the continuous cG(T) along its temperature domain, thus creating the sequence G(k). Maintain the

full precision of the G(k) values. Note the full precision cG(T) at T = 24°C — this is the full precision BASE

value, fpBASE, still in voltage domain.

G(0) = cG(-28èC) = 1.2477

G(1) = cG(-24èC) = 1.2495

G(2) = cG(-20èC) = 1.2513

é

G(13) = cG(24èC) = 1.2743 = fpBASE

é

G(39) = cG(128èC) = 1.3893

(12)

5. Apply difference operation to the G(k) sequence, and obtain new sequence fpDEL(k). These are now the full

precision increments of the target function with each 4°C interval.

fpDEL(0) = G(1) - G(0) = 1.8174 ì10^-3

fpDEL(1) = G(2) - G(1) = 1.8189 ì10^-3

fpDEL(2) = G(3) - G(2) = 1.8316 ì10^-3

é

fpDEL(38) = G(39) - G(38) = 6.4124 ì10^-3

6. Convert the full precision voltages of fpDEL(k) and fpBASE to a numeric, quantized domain. This reverses

the DAC action.

fpBASEì 4096

≈

’

BASE = round

= 1044₁₀= 414₁₆= 010000010100₂

∆

«

÷

◊

5

é

fpDEL(0)ì 4096

≈

’

DEL(0) = round

= 1 = 1 = 0001₂

10

16

∆

«

÷

5

◊

é

fpDEL(38)ì 4096

≈

’

DEL(38) = round

= 5₁₀= 5₁₆= 0101₂

∆

÷

5

«

◊

7. Usually BYP bit is reset, BYP=0. However, in cases where it is desirable to bypass the LUT and ALU, and

have the DACx output produce voltage equivalent of the BASE value, set BYP = 1.

8. Repeat steps 1 to 6 to obtain POL, BYP, BASE, DELx values for the second channel.

9. Now have BYP, POL, BASE, and DEL(0..38) values ready to be programmed into the LUT.

50

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Typical Applications (continued)

NOTE

The device has to be in the L2 Access Level before commencing the WRITE access of

BYP, POL, BASE, DELx values. The register WRITE operation immediately affects the

operation of the device. However, operating memory is volatile, and BURN operation is

required to commit the LUT coefficients to non-volatile memory, EEPROM.

9.2.2.3 Application Curves

The output of the LMP92066 due to the coefficients calculated in the above procedure is shown in Figure 47.

Figure 48 shows the absolute difference between the target function and the measured response of the

LMP92066.

œ1.00

œ1.05

œ1.10

œ1.15

œ1.20

œ1.25

œ1.30

œ1.35

œ1.40

œ1.45

œ1.50

10

8

6

4

2

0

œ2

œ4

œ6

œ8

œ10

0

20

40

60

80

100 120 140

0

20

40

60

80

100 120 140

œ40 œ20

Temperature (°C)

C027

C028

Figure 47. Measured Response of the LMP92066 Resulting

from the LUT Coefficients

Figure 48. Difference Between the Target Response

shown in Figure 45 and

(see Detailed Design Procedure)

Measured Response in Figure 47

9.3 Do's and Don'ts

9.3.1 Output Drive Switching

Some applications may require that the FETDRVx output reaches the level set by the DACx as fast as possible

after the assertion of DRVENx.

There are parameters which determine the delay between the assertion of DRVENx, and the FETDRVx output

achieving its final level as set by the DACx:

•

The delay between the DRVENx input the output switch.

The charge up time of the FETDRVx node once the output switch is closed.

The delay of the switch response to the DRVENx input, t_ON, is specified in the Electrical Characteristics table.

The charge up time of the FETDRVx node is dependent on the selection of the external components. Rapid rise

time of the FETDRVx output, is made possible through the use of the external capacitor C1. C1 is always

charged to the potential generated by the DACx, and used to provide instantaneous charge to the load present at

the FETDRVx when the output switch closes – the switch between DACx and FETDRVx pin.

C1 is chosen to be several orders of magnitude larger than the total capacitance present at the FETDRVx pin,

CEXT. In the typical application C1 is 10 µF, and CEXT is limited to 10 nF. See Figure 49. When the output

switch closes, a current flows from the C1, acting as a reservoir, to CEXT. This charge-up current is limited only

by the resistance of the output switch RDRV, resulting in very rapid slewing at the FETDRVx pin. RDRV is

specified in the Electrical Characteristics table.

For example, given the following parameters.

•

t_ON= 50 ns

51

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

Do's and Don'ts (continued)

•

R_DRV= 5 Ω

C_EXT= 10 nF

The total delay time between activation of DRVENx and FETDRVx achieving 95% of its final value is:

T_DELAY= t_ON+ 5τ = t_ON+ 5R_DRVC_EXT= 300 ns

(13)

NOTE

The charge current flowing into the C_EXTat the instant the output switch closes is relatively

large and of very short duration, which makes the parasitic inductance in the charge path

significant. This parasitic inductance is due to the bond wire and package pin between the

device die and the C_EXT, and is shown as LP in Figure 49. In some applications it may be

beneficial to insert a small resistance in the charge path, see R_EXTin Figure 49, to

dampen the resonance of the LP and C_EXT. Choice of R_EXTis highly application

dependent, but 5 Ω is a good initial selection.

LMP92066

DACx

+

C₁

FETDRV

P

A

x

DACx

R_DRV

L_P

R_EXT

C_EXT

DRVENx

Figure 49. Flow of Charge Current

9.4 Initialization Setup

9.4.1 Factory Default

At the factory the EEPROM is initialized such that all LUT increment values (Δ) are set to 0, BASE value is set to

0x00, and BYP and POL bits are set to 0. This results in the device producing constant output of 0V at DACx

pins upon power up, regardless of the temperature or mode or state at the DRVENx inputs.

9.4.2 At Power Up

The device is capable of autonomous operation upon power up, without intervention form the system controller.

When the power is applied and reaches the minimum level (approximately 4.1 V) the temperature sensor begins

operating, and the internal sequencer begins the transfer of LUT values from the EEPROM to the operating

memory. Once the transfer is complete, and the Temperature Sensor has completed the first conversion, the

ALU computes the DACs input values, and the DACs start producing output voltages representative of the

transfer functions implemented in the LUTs.

The control signal applied to the DRVENx input determines whether the DAC output voltage is present at the

FETDRVx output, or that output is driven to VSSB potential.

Figure 50 shows the typical power-up transient behavior at the DACx outputs. While VDD voltage is ramping up

from 0 to 5 V the DACx outputs initially follow the VDD. This is due to the fact that initially the device is in the

undefined state. When VDD reaches 4.1 V the internal reset occurs and clears the internal data path, resulting in

V_DACx= 0 V. The Temperature Sensor begins operation at the moment of reset, and 25 ms later produces its first

temperature measurement. This, in turn, causes the ALU to update DAC input data, resulting in new V_DACx

output.

52

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

Initialization Setup (continued)

VDD

V_DAC1

V_DAC0

Time (10 ms/DIV)

C020

VDD = 2V/div

V_DAC1= 1V/div

V_DAC0= 1V/div

Figure 50. Power-Up Transient Behavior

See also the Default Operating Mode section.

53

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

10 Power Supply Recommendations

The device rails VIO, VDD, and VDDB (VSSB in GaN mode) should be supplied from a well-regulated power

supply capable of sourcing at least 50 mA. The required supply levels are shown in the Specifications tables of

this document. Along with ceramic bypass capacitors, additional bulk capacitance is recommended on the VDD

node. The function of this bulk capacitance is to provide the momentary increases in the supply current

requirements due to the EEPROM activity. An electrolytic capacitor with a value of 10 μF to 47 μF is a typical

choice.

10.1 I_VDDDuring EEPROM BURN

Figure 51 shows the transient behavior of I_VDDdue to the EEPROM BURN operation. VSDA trace activity is used

as the trigger. The triggering event is the BURN command sent via the I²C interface. During the BURN the I_VDD

increases to almost 4 mA for 125 ms. The 10-mA peaking in I_VDDis due to the TRANSFER of newly stored data

from EEPROM back to the operating memory – this is part of the internal error detection and correction process.

I_VDD

V_SDA

Time (20 ms/DIV)

C021

I_VDD= 2mA/div

V_SDA= 5V/div

Figure 51. I_VDDTransient During EEPROM BURN

10.2 I_VDDDuring EEPROM TRANSFER

The transfer of data, from the EEPROM to the operating memory, results in the temporary increase in supply

current I_VDD. The total I_VDDincreases to about 10 mA for the duration of the TRANFER operation, typically 200

µs. Given the infrequent occurrence, and the short duration, the increased I_VDDcan be easily supplied by the

external bulk capacitors; that is, this does not represent an additional burden to the system power supply. The

typical I_VDDtransient during TRANSFER is shown in Figure 52. The triggering event is the TRANSFER command

issued via the I²C interface.

I_VDD

V_SDA

Time (200 µs/DIV)

C022

I_VDD= 2mA/div

V_SDA= 5V/div

Figure 52. I_VDDTransient During EEPROM Transfer

54

LMP92066

www.ti.com.cn

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

I_VDDDuring EEPROM TRANSFER (continued)

The TRANSFER operation occurs due to the following:

1. Power-On RESET

2. Software RESET

3. EEPROM TRANSFER command issued via the I²C interface

4. Upon completion of the EEPROM BURN operation, as a data verification step.

11 Layout

11.1 Layout Guidelines

The LMP92066 is a device for which the input signal is temperature. The primary path of heat conduction is

through the exposed PowerPAD on the underside of the package. The layout should provide direct, high thermal

conductivity path between the LMP92066 and the devices controlled by its output:

•

Use heavy copper layer as the thermal conduction path. This layer must be also a GND node.

If the heavy copper layer is not a top layer, use a dense array of vias to connect to both the LMP92066 and

the heat sources to maintain high thermal conductivity.

•

Place the LMP92066 in the geometric center between the multiple heat sources in order to minimize the

“thermal offsets” due to the temperature gradients.

11.2 Layout Example

ꢀ/4

D

G

1.8V œ 3.3V Supply

5V Supply

OPTIONAL

GNDD

DRVEN1

DRVEN0

VIO

VDD

VDDB

DAC1

5

FETDRV1

GNDA

10n

SDA

SCL

FETDRV0

DAC0

5

A1

A0

VSSB

I²

Location dependent on other slave devices present in the system

C bus pull-ups.

Details of the RF section are beyond

the scope of this document

ꢀ/4

D

G

Copper Pour

Power Ground

50

Thermal bridge between LMP92066 and the PAs

RF_IN

Figure 53. LMP92066 Layout

55

LMP92066

ZHCSCA9A –MARCH 2014–REVISED APRIL 2015

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 器件命名规则

REAOPC

一点校准后的残余误差是由于组成信号处理块的错误在模拟信号路径中得到的误差：其中的组成信号

处理块有 DAC，缓冲放大器，内部基准。 REAOPC 主要由偏移和增益温度漂移决定，这是因为初始

误差的绝大部分在一点校准的过程中被消除。 DAC 线性误差 (INL) 所造成的误差可被忽略，这是因

为这个误差在数量上微不足道。通过以下公式可预计 REAOPC：

REAOPC(T) = A[x(T) - x(T_O)]GE(T) + A[GE(T) - GE(T_O)]x(T_O) + û

5

A =

(V)

4096

GE(T) = Gain Error at temperature T

û = OE(T) - OE(T_O)

OE(T) = Offset error at temperature T

x(T) = DAC input code at temperature T

T_O= temperature at which One Point Calibration is performed

一点校准

一点校准是 LMP92066 的输出在系统中被调整，以实现所需响应的过程，此时温度为 T₀。通常情况

下，这个过程涉及总体系统输出变量的测量；例如，PA 的 I_D，在 LUT 中修改 BASE 值，以实现所

需的 PA 偏置电流。

12.2 商标

PowerPAD is a trademark of Texas Instruments Incorporated.

All other trademarks are the property of their respective owners.

12.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏

56

PACKAGE OUTLINE

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.6

6.2

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

0.19

4.5

4.3

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

4X 0.166 MAX

NOTE 5

2X 1.34 MAX

NOTE 5

THERMAL

PAD

0.25

GAGE PLANE

3.3

2.7

17

1.2 MAX

0.15

0.05

0 - 8

0.75

0.50

DETAIL A

TYPICAL

(1)

3.3

2.7

4214868/A 02/2017

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.4)

NOTE 9

SOLDER MASK

DEFINED PAD

(3.3)

16X (1.5)

SYMM

SEE DETAILS

1

16

16X (0.45)

(1.1)

TYP

17

SYMM

(3.3)

(5)

NOTE 9

14X (0.65)

8

9

(

0.2) TYP

VIA

(1.1) TYP

METAL COVERED

BY SOLDER MASK

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-16

4214868/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

PWP0016A

PowerPAD ^TMHTSSOP - 1.2 mm max height

PLASTIC SMALL OUTLINE

(3.3)

BASED ON

0.125 THICK

STENCIL

16X (1.5)

(R0.05) TYP

1

16

16X (0.45)

(3.3)

17

SYMM

BASED ON

0.125 THICK

STENCIL

14X (0.65)

9

8

SYMM

(5.8)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.69 X 3.69

3.3 X 3.3 (SHOWN)

3.01 X 3.01

0.125

0.15

0.175

2.79 X 2.79

4214868/A 02/2017

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMP92066PWPR
厂家：	TEXAS INSTRUMENTS
描述：	具有集成 EEPROM + 输出 ON/OFF 控制功能的双路、温度控制型 DAC \| PWP \| 16 \| -40 to 125 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总65页 (文件大小：1517K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMP92066PWPR [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E