LMP93601 [TI]

用于热电堆传感器的低噪声、高增益、3 通道 AFE;


型号：	LMP93601
厂家：	TEXAS INSTRUMENTS
描述：	用于热电堆传感器的低噪声、高增益、3 通道 AFE 传感器
文件：	总44页 (文件大小：3498K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

LMP93601 用于热电堆传感器的低噪声，高增益，3 通道模拟前端 (AFE)

1 特性

3 说明

•

高增益、高达 4096 可编程

LMP93601 是一款经优化的模拟前端 (AFE)，此模拟

前端用于检测热电堆阵列（高达 16 x 16）的占用情

况，以及热电堆质量流量传感器。此 AFE 以非常适合

于监控热电堆传感器的采样速率将出色噪声性能、低偏

移电压、高增益和低功耗组合在一起。

低增益误差漂移，< 10ppm/°C

低偏移电压和漂移；1uV，50nV/°C

低输入偏置电流，1.3nA

低输入偏移电流，120pA

针对电平位移的 VCM 输出信号，AVDD/3

三个差分抗电磁干扰 (EMI) 输入

16 位三角积分 (Δ∑) 模数转换器

低噪声性能，有效位数 (ENOB) 15.3 位

四输出数据速率，高达 1.3kSPS

针对 ADC 的内部电压基准

SPI 接口传输速率，20MHz

掉电检测

LMP93601 是一款采用超薄四方扁平无引线 (WQFN)-

24 封装的高精度，16 位，模数转换器 (ADC)。此器

件特有三个差分抗 EMI 输入，一个低噪声、高增益可

编程增益放大器 (PGA)，一个电平位移电压源，一个

内部基准和一个可编程采样速率。 LMP93601 通过一

个 SPI 兼容接口实现的很多集成特性和简单控制简化

了热电堆传感器信号的高精度测量。

器件信息

可编程增益放大器 (PGA) 超范围检测

单独的模拟和数字电源，2.7 至 5.5V

低流耗，1.1mA

部件号

LMP93601

封装

封装尺寸

WQFN (24)

5.00mm x 4.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

低功率关断模式，< 0.1µA

工作温度-25 至 85°C

2 应用范围

•

热电堆阵列测量

热电堆流量测量

桥式传感器接口

手势识别

模拟电源与偏移电压之间的关系图

4 简化热电堆阵列系统图

ꢀꢀ

±2

±4

Vref

SPI

±6

±25C

25°C

85°C

IR sensor

AFE

MCU

X by Y Array

LMP93601

±8

Digital

Data

Analog Data

±10

X-Decoder

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

AVDD (V)

C001

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNAS633

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

8.3 Feature Description................................................. 16

8.4 Device Functional Modes........................................ 21

8.5 Programming........................................................... 25

8.6 Register Maps......................................................... 27

8.7 Multi Byte Access (Auto Increment) Mode.............. 30

8.8 Multi-Channel Data Read........................................ 31

Application and Implementation ........................ 33

9.1 Application Information............................................ 33

9.2 Typical Applications ................................................ 33

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化热电堆阵列系统图............................................. 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 Handling Ratings....................................................... 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements................................................ 7

7.7 Noise Performance ................................................... 8

7.8 Typical Characteristics............................................ 12

Detailed Description ............................................ 15

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 15

10 Power Supply Recommendations ..................... 36

11 Layout................................................................... 36

11.1 Layout Guidelines ................................................. 36

11.2 Layout Example .................................................... 37

12 器件和文档支持 ..................................................... 38

12.1 商标....................................................................... 38

12.2 静电放电警告......................................................... 38

12.3 术语表 ................................................................... 38

13 机械封装和可订购信息 .......................................... 38

5 修订历史记录

Changes from Original (March 2014) to Revision A

Page

•

Added application curves ...................................................................................................................................................... 3

Changed Handling Ratings format ........................................................................................................................................ 3

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

6 Pin Configuration and Functions

LMP93601

24 Pin

Top View

VCM

IN1P

IN1N

IN2P

IN2N

IN3P

IN3N

19 IOVDD

18 SDO

17 SCLK

16 IOGND

15 CSB

LMP93601

14 SDI

13 DRDYB

Pin Functions

PIN⁽¹⁾

TYPE(I/O)⁽²⁾

DESCRIPTION

NAME

NUMBER

VCM

Analog in/output

Analog input

Analog ground

Digital input

Digital output

Digital input

Digital IO ground

Digital input

Digital output

Digital IO supply rail

Digital ground

Analog ground

Digital LDO

Sensor common mode bias voltage

Input signal positive pin

Input signal negative pin

Input signal positive pin

Input signal negative pin

Input signal positive pin

Input signal negative pin

INP1

INN1

INP2

INN2

INP3

INN3

AGND

PWDNB

RSTB

SYNC

XCLK

DRDYB

SDI

Enable, active low

Master reset, active low

Sync, active high

External clock source

Data ready signal, active low, push-pull

Serial data input

CSB

Chip select, active low

IOGND

SCLK

SDO

Serial interface clock

Serial data output; push-pull

IOVDD

DGND

AGND

XCAP2

XCAP1

AVDD

External Cap2

External Cap1

Analog supply rail

Analog

(1) For best performance, it is recommended that the DAP is connected to AGND (refer to Mechanical, Packaging and Orderable

Information ). All three “GND” connections (AGND, DGND and IOGND) must be connected to system ground and cannot be left floating.

(2) There is no pull-up/-down for any digital I/O

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

-0.3

MAX

6.0

UNIT

Analog Supply Voltage, AVDD

Digital Supply Range, IOVDD; ( IOVDD must always be lower than or equal to AVDD supply)

Voltage between any two analog pins

6.0

Voltage between any two digital pins

6.0

Voltage between XCAP2 and any GND (A, D or IO)

Input current at any pin

2.2

-5.0

+5.0

125

°C

Junction Temperature

(1) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

7.2 Handling Ratings

MIN

MAX

150

UNIT

T_stg

Storage temperature range

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

2000 K

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

500

(1) JEDEC document JEP155 states that 2000 -V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

MAX

5.5

UNIT

Analog Supply Voltage, AVDD

Fclk

2.7

3.6

2.7

4.4

MHz

Digital Supply Voltage, IOVDD

Supply Ground

AVDD

AGND = DGND = IOGND

-25 85

Temperature range

°C

7.4 Thermal Information

WQFN

24 PINS

SYMBOL

THERMAL METRIC

UNIT

Θ_JA

Θ_JC

Ψ_JB

Thermal resistance, junction to ambient

Thermal resistance, junction to case

Thermal resistance, junction to board

37.9

°C/W

4.8

19.4

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

7.5 Electrical Characteristics

Typical conditions: T_A=+25⁰C, AV_DD=IOV_DD=3.3 V, INP1/INN1 enabled with V_ICM=AV_DD/3. PGA gain=64, PGA over-range

masked, digital gain=1. SPS select=1057 SPS. f_XCLK=4.00 MHz. Conversion power mode. XCAP1=1 uF. XCAP2=0.1 uF.

SYMBOL

INPUTS

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Channel1 enabled with a 100 kΩ resistor

as input, channel 2 disabled with 1 V

peak-peak , 100 Hz signal as input.

Crosstalk across input

channels

XTLK

(1)

Differential input

impedance

10//7

MΩ//pF

Zin

Common mode input

impedance

100//4.5

MΩ//pF⁽¹⁾

I_B

Input bias current

-1.3

Input offset current on

differential channels

-200

I_os

Maximum of INP1-INN1, .., INP3-INN3

Input short on chip, PGA 64 DG =1, CH1

Input short on chip

Input offset current drift

on differential channels

-0.5

pA/⁰C

uV⁽²⁾

nV/⁰C

TCI_os

V_os

Input referred offset

voltage

-15

+15

Input referred offset drift

with temperature

TCV_os

Programmable gain settings =16; ± 3%

Programmable gain settings =32; ± 3%

Programmable gain settings =64; ± 3%

Programmable gain settings = 128; ± 3%

PGA bypass

-64

-32

-16

+64

+32

+16

Input differential range

for AVDD≥3V

Vdiff

± 8

±1

0.3

0.4

AVDD-

1.4

V⁽³⁾

PGA = 64 V/V; CMRR ≥ 80 dB

Input common mode

range.

V_ICM

PGA = 64 V/V ; CMRR ≥ 72 dB

-25 C to 85 C

AVDD-

1.45

See

Figure 16

Channel bandwidth

Output data rate

265

530

SPS

ODR

1057

1326

Programmable gain

settings

16, 32 , 64

and 128

V/V

PGA

Bypass mode

V/V

Programmable gain

settings

1, 2, 4, 8,

16 and 32

Digital Gain

Programmable gain

settings (analog and

digital)

16 - 4096

V/V

Total AFE Gain

Gain steps

2 x

0.3 %

-0.3 %

-9

Gain error

PGA bypassed

GE drift with temperature

ppm/⁰C

(1) Value from simulation

(2) The input referred offset is measure by an on-chip short.

(3) Temperature limits are ensured by statistical analysis or design

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

Typical conditions: T_A=+25⁰C, AV_DD=IOV_DD=3.3 V, INP1/INN1 enabled with V_ICM=AV_DD/3. PGA gain=64, PGA over-range

masked, digital gain=1. SPS select=1057 SPS. f_XCLK=4.00 MHz. Conversion power mode. XCAP1=1 uF. XCAP2=0.1 uF.

SYMBOL

ENOB⁽⁴⁾

PARAMETER

TEST CONDITION

MIN

TYP

15.3

MAX

UNIT

Bits

Effective number of bits

Total harmonic distortion 100 Hz, 50 mVpp differential input, PGA

(Linearity)

THD

16 V/V

RMS noise in a 1 kHz

0.67⁽⁵⁾

uVrms

PGA = 64 V/V

Noise

1/ƒ noise corner

127

dB⁽³⁾

V_ICM= 0.3 to AVDD-1.4 V

Common mode rejection

ratio (at DC)

V_ICM= 0.4 to AVDD-1.45 V, over

operating temperature range

-25 C to 85 C

CMRR

PSRR

Supply ; 2.7 to 5.5 V

120

dB⁽³⁾

Power supply rejection

ratio (at DC)

Supply ; 2.7 to 5.5 V, over operating

temperature range

-25 C to 85 C

VRF = 100 mVPP

f=400 MHz

EMIRR

EMI rejection ratio

f=900 MHz

f=1800 MHz

f=2400 MHz

VCM

V _VCM

Output voltage

Startup time

AVDD/3

Tstrp _VCM

Acc _VCM

TC _VCM

To within 90% of final value

Accuracy

0.2

Drift over temperature

Output current

Load regulation

Load range

0.5

ppm/⁰C

0.5

I _VCM

0 to 200uA

Zload _VCM

2.2//100

MΩ//nF

SLAVE SPI INTERFACE

Clock frequency

DIGITAL INPUT/OUTPUT CHARACTERISTICS

MHz

0.7x

IOVDD

VIH

VIL

Logical “1” Input Voltage

Logical “0” Input Voltage

0.3x

IOVDD

IOVDD-

0.150

VOH

Isource=300uA

Isink=300uA

IOGND

+0.150

VOL

POWER SUPPLY

AVDD

Analog supply voltage

range

2.7

5.5

Digital supply voltage

range

AVDD

V⁽⁶⁾

IOVDD

AVDD ≥ IOVDD

(4) ENOB is a DC ENOB spec, not the dynamic ENOB that is measured using FFT and SINAD:

2uV / Gain

ref

ENOB log₂

RMSNoise

(5) See Table 1 for detailed noise performance

(6) IOVDD always ≤ AVDD and IOVDD minimum is 2.7 V

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

Electrical Characteristics (continued)

Typical conditions: T_A=+25⁰C, AV_DD=IOV_DD=3.3 V, INP1/INN1 enabled with V_ICM=AV_DD/3. PGA gain=64, PGA over-range

masked, digital gain=1. SPS select=1057 SPS. f_XCLK=4.00 MHz. Conversion power mode. XCAP1=1 uF. XCAP2=0.1 uF.

SYMBOL

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

Shutdown Mode, XCLK off

Standby Mode

0.1

1.9

2.7

µA

I_IOVDD

Digital on AFE

Conversion Power Mode

Conversion Power Mode,

PGA bypassed

µA

Shutdown Mode, XCLK off

Standby Mode

0.1

175

1.1

250

1.6

µA

I_AVDD

Analog on AFE

Conversion Power Mode

Conversion Power Mode, 230 μA PGA

bypassed

230

µA

TEMPERATURE RANGE

Operating

–25

°C

7.6 Timing Requirements

Under typical conditions with maximum total load capacitance 10 pF.

MIN

TYP

MAX UNIT

t_PH

t_PL

t_SU

t_H

High Period, SCLK

Low Period, SCLK

SDI input setup time

SDI input hold time

SDO output hold time

CSB setup time

t_OD

t_CSS

t_CSH

t_IAG

13.5

CSB hold time

CSB high time

Figure 1. SPI Write Timing Diagram

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

CSB

SCLK

7-bit register

address (n)

R/W

SDI

8-bit data read

from address (n)

SDO

Figure 2. SPI Read Timing Diagram

7.7 Noise Performance

Table 1. Noise In µV_RMSat AVDD= 3.3 V, AGND = 0 V, and Internal Reference = 2.4 V_RMS

ODR (SPS)

PGA Gain (V/V)

D-Gain (V/V)

Vn (uVrms)

Below the resolution

of the 16 bit SDM.

Below the resolution

of the 16 bit SDM.

0.661

0.597

0.578

0.574

Below the resolution

of the 16 bit SDM.

0.516

0.396

0.368

0.361

0.362

0.556

0.321

0.287

0.281

0.275

0.277

0.298

0.254

0.247

0.242

0.240

265

128

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

Noise Performance (continued)

Table 1. Noise In µV_RMSat AVDD= 3.3 V, AGND = 0 V, and Internal Reference = 2.4 V_RMS(continued)

ODR (SPS)

PGA Gain (V/V)

D-Gain (V/V)

Vn (uVrms)

Below the resolution

of the 16 bit SDM.

0.944

0.888

0.831

0.810

0.816

0.509

0.609

0.543

0.517

0.521

0.511

0.569

0.421

0.397

0.396

0.397

0.395

0.377

0.348

0.340

0.341

0.340

0.339

530

128

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Noise Performance (continued)

Table 1. Noise In µV_RMSat AVDD= 3.3 V, AGND = 0 V, and Internal Reference = 2.4 V_RMS(continued)

ODR (SPS)

PGA Gain (V/V)

D-Gain (V/V)

Vn (uVrms)

1.565

1.517

1.410

1.409

1.398

1.401

0.932

0.903

0.834

0.839

0.829

0.824

0.667

0.596

0.580

0.579

0.574

0.501

0.481

0.476

0.473

0.470

1057

128

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

Noise Performance (continued)

Table 1. Noise In µV_RMSat AVDD= 3.3 V, AGND = 0 V, and Internal Reference = 2.4 V_RMS(continued)

ODR (SPS)

PGA Gain (V/V)

D-Gain (V/V)

Vn (uVrms)

2.331

1.743

1.665

1.648

1.681

1.189

0.975

0.981

0.954

0.941

0.937

0.733

0.677

0.670

0.667

0.660

0.663

0.575

0.546

0.541

0.537

0.540

0.538

1326

128

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7.8 Typical Characteristics

±2

±4

±6

±8

±10

±2

±4

±6

±8

±10

±25C

25°C

85°C

±25C

25°C

85°C

2.5

±50

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0.0

±50

0.5

1.0

1.5

2.0

2.5

AVDD (V)

Vcm (V)

C001

C002

Figure 3. Vos vs AVDD (V)

Figure 4. Vos vs Vcm (V)

0.20

0.15

AVDD=2.7 V

AVDD=3.3 V

AVDD=5.5 V

0.10

0.05

0.00

±0.05

±0.10

±0.15

±0.20

±5

±10

AVDD=2.7 V

AVDD=3.3 V

AVDD=5.5 V

Temperature (C)

100

Temperature (C)

100

C003

C004

Figure 5. Ibias vs Temperature

Figure 6. Ios vs Temperature

0.20

0.15

0.10

0.05

0.00

±0.05

±0.10

±0.15

±0.20

±5

±10

VCM=0.6 V

VCM=1.1 V

VCM=1.9 V

VCM=0.6 V

VCM=1.1 V

VCM=1.9 V

Temperature (C)

100

Temperature (C)

100

C005

C006

Figure 7. Ibias vs Temperature

Figure 8. Ios vs Temperature

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

Typical Characteristics (continued)

1.0

0.8

0.6

0.4

0.2

0.0

IAVDD_SD 3.3 V

IAVDD_SD 5.5 V

IOVDD_SD 3.3 V

IOVDD_SD 5.5 V

0.8

0.6

0.4

0.2

0.0

100

±25

Temperature (C)

C007

C008

Figure 9. IAVDD vs Temperature

Figure 10. IOVDD vs Temperature

1.3

1.2

1.1

1.0

0.9

0.8

IOVDD_2.7 V

IOVDD_3.3 V

IOVDD_5.5 V

IAVDD_2.7 V

IAVDD_3.3 V

IAVDD_5.5 V

100

Temperature (C)

C009

C010

Figure 11. I AVDD vs Temperature

Figure 12. IOVDD vs Temperature

300

250

200

150

100

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

IAVDD_Bypass 3.3 V

IOVDD_Bypass 3.3 V

IAVDD_STB 3.3 V

IOVDD_STB 3.3 V

100

Temperature (C)

C011

C012

Figure 13. IAVDD vs Temperature

Figure 14. IOVDD vs Temperature

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Characteristics (continued)

2.0

1.5

1.0

0.5

0.0

±0.5

±1.0

±1.5

PGA128

PGA64

PGA32

PGA16

PGA Bypass

±2.0

±25

100

Temperature (C)

C013

Figure 15. GE (%) vs Temperature

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

8 Detailed Description

8.1 Overview

The LMP93601 Analog-Front-End is a unique device designed from ground up specifically for interfacing to

16 x 16 MEMS (Micro-electro-mechanical systems) thermopile arrays, and thermopile mass flow sensors

with very low output signals in the range of 1 µV to 600 µV. For signal conditioning of thermopile sensors, the

AFE is required to have very low noise performance, very low offset voltage, very high gain, and low-power

consumption at sampling rates to process several frames per second.

The signal chain includes a PGA featuring low offset voltage (0.7 µVrms), low input bias current (–1.3 nA),

and programmable gain of 1x, 16x, 32x, 64x and 128x. The total gain of the signal path combined with the

programmable digital gain of the 16-bit Delta-Sigma data converter is up to 4096x.

The signal chain features excellent total noise performance of below 0.5 uVrms at programmable sampling

rates of up to 1.3 kSPS, while providing optimal power consumption during full operation (1.1 mA). The

device features ultra-low shutdown current (0.1 µA), and standby mode current of 250 µA.

Other features include Low EMI sensitivity due to EMI hardened input stage, Internal reference voltage for

the ADC, output reference voltage for thermopile sensors (VCM), a brown-out detector for low-battery

condition, synchronous serial communication (SPI) communication up to 20 MHz, flex routing multiplexer for

interfacing to multiple flow sensors, and PGA over range detection.

8.2 Functional Block Diagram

AVDD

XCAP2

XCAP1

XCAP2

IOVDD

PGA Over-range

Detect

Brownout

Detect

RSTB

LDO, VREF &

Comm. Mode

Generator

PWDNB

DRDYB

SYNC

Control Unit

AVDD/3

VCM

INP1

EMIF

INN1

INP2

INN2

INP3

INN3

CSB

SDO

SDI

16-bit û$'&

ûꢀ

Modulator

FIR

FLTR

SPI

PGA

SCLK

XCLK

LMP93601

AGND

DGND

IOGND

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8.3 Feature Description

8.3.1 Data Format

The LMP93601 provides 16 bits of data in binary two's complement format. The positive full-scale input produces

an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at

these codes for signals that exceed full-scale (FS). Table 2 summarizes the ideal output codes for different input

signals.

8.3.2 Transfer Function

The ADC output code in decimal is given by the relation:

Vdiff uPGA uDGu 2¹⁶

code_dec

2u Vref

(1)

Table 2. Example of ADC Output Code

CODE (HEX)

1946

CODE (DEC)

PGA (V/V)

DG (V/V)

VDIF (V)

7.404E-3

6470

12288

-12036

-4

3000

14.063E-3

-55.096E-3

-4.578E-6

D0FC

FFFC

8.3.3 Input Routing Mux

The LMP93601 offers 5 differential input channel configurations for its 3 differential input pairs:

•

For 1-ch system: One of the 3 channels, Ch1, Ch2, or Ch3 is enabled

For 2-ch system: Ch1 & Ch2 are enabled

For 3-ch system: Ch1, Ch2, Ch3 are enabled

8.3.4 Programmable Gain Amplifier

The PGA provides a high input impedance to interface with signal sources that may have relatively high output

impedance, such as thermopiles. The Programmable Gain amplifier gain can be programmed to 16, 32 64, and

128 V/V.

The maximum differential input voltage (Vdiff) of the PGA is ±64 mV when the programmed analog gain is 16

V/V. With analog gain programmed to 64V/V the maximum differential input voltage of the PGA is ±16 mV.

The input common mode voltage range of the PGA is AGND+0.3+Vdiff*Gain/2 to AVDD-1.40-Vdiff*Gain/2.

The PGA also has an EMIRR filter incorporated. The EMIRR filter is a single pole roll off providing enhanced

noise immunity for unwanted RF signals.

8.3.5 PGA Bypass Mode

The PGA can be bypassed to access the 16 bit Delta-Sigma modulator directly. This mode results in a typical

gain of 1 V/V at a supply current of typically 230 µA. The input common mode range in the PGA-bypass mode is

rail to rail and the maximum differential input voltage that can be applied to the Delta-Sigma modulator is ± 1.2

Vpp differential. The typical noise at 1057 SPS is 20 uVrms. Typical input impedance in the PGA bypass mode is

1.3 MΩ//7 pF. In the PGA-bypass mode, the PGA and overrange detectors are disabled. To access the PGA-

bypass mode the following SPI write sequence must be followed in this exact order:

Table 3. PGA Bypass Mode SPI Write Sequence

ADDRESS

0x1

WRITE

Program as normal

See Table 4 below

8'h01

DESCRIPTION

0x02

0x03

0x05

Mask PGA OR detectors (else the conversion will read 7FFF)

First write to address 0x60

0x60

8'h93

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Table 3. PGA Bypass Mode SPI Write Sequence (continued)

ADDRESS

WRITE

8'h60

8'h10

8'h28

8'h01

DESCRIPTION

0x60

0x63

0x61

0x04

0x00

Second write to address 0x60

Override

PGA bypass and OR detectors shutdown

Conversion mode

lock

Table 4. PGA Bypass Register 0x03 Setting Description

ADDR [6:0]

NAME

# OF BITS

TYPE

DEFAULT

DESCRIPTION

PGA settings for

differential channels

[6:4] Digital 3’b000: 1

3’b001: 2

3’b010: 4

3’b011: 8

3’b100: 16

3’b101: 32(default)

3’b110-111: Reserved

[1:0] Analog

0x03

Config3

R/W

8’h52

2’b00: 16

2’b01: 32

2’b10: 64 (default)

2’b11: 128 [7] always 0

[2] Bypass PGA, bit [1:0]

would be ignored

To exit the PGA-bypass mode, a reset is required, either via the RSTB or SPI. Failure to follow this exact

sequence may result in the device becoming unresponsive, thereby requiring a reset, either via the RSTB or SPI.

8.3.6 Over-Range Detection

The PGA has over-range detection and when signals are outside the minimum or maximum allowed signal, an

out of range condition will be reported as “0x7FFF” for the corresponding channel. A status register provides

further details of the out of range condition. The overrange detectors are at the output of the PGA and check for

five conditions:

•

PGA positive output low

PGA negative output low

PGA positive output high

PGA negative output high

PGA differential output high

The “output high” overrange detectors typically trip at AVDD-1.28 V. Both “output low” overrange detectors

typically trip at 0.11 V and the differential overrange detector is typically at +1.22 and -1.22 V differential.

For example, if the input common mode is below 0.11 V and a zero differential voltage (shorted input) is applied,

both the PGA positive and PGA negative “output low” detectors would trip. Likewise, if the input common mode is

over AVDD-1.28 and a zero differential voltage (shorted input) is applied, both the PGA positive and PGA

negative “output high” detectors would trip.

For the differential output high detector to trip, the output of the PGA has to be greater than 1.22 V or less than

–1.22 V. At a gain of 64, this would translate to an input referred differential voltage of Vdiff = 1.22/64 = 19 mV

8.3.7 Analog-To-Digital Converter (ADC)

The 16 bit Sigma Delta Modulator (SDM) takes the output signal of the PGA and converts this signal into a high

resolution bit stream that is further processed by the digital filters. The 2.4 V reference for the SDM is internally

generated and requires a high-performance, low ESR (<0.1 Ω), and Low ESL(<1nH) 1uF (±10%) external bypass

capacitor for optimal performance on the XCAP1 pin. This reference should not be used to drive external

circuitry.

The SDM clock uses a divided-down external clock (XCLK).

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8.3.8 Programmable Digital Filters

A programmable digital filter behind the SDM reconstructs the signal from the SDM output bit stream. The filter

consists of programmable filter stages. Each of the stages further filters and decimates the bit stream so that the

data rate and bandwidth of the signal is reduced and at the same time the resolution is enhanced.

An example of the filter response when programmed for 265, 530, 1057 or 1326 SPS is shown in Figure 16.

Figure 16. Bandwidth and Module Noise Performance

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8.3.9 Common Mode Voltage Generator

The common mode reference generator (VCM) provides an AVDD/3 reference. It can drive a 100nF (±10%)

external capacitance with typical ESR/ESL of 0.1 Ω and 1 nH. It can also be used to drive guard traces placed

around the input PCB traces to reduce PCB leakage currents to the inputs. The VCM can be disabled with the

Reference Enable register. In case the VCM is disabled, an external common mode voltage that tracks the

common mode of the input channel(s) needs to be connected to the VCM pin to function as a reference for the

over-range detection circuitry. In case the VCM is disabled, it is recommended to add an external 10 kΩ series

resistor.

8.3.10 Low Drop-Out Regulator (LDO)

The on chip LDO generates 1.2V for the digital core. A 100nF (+/-10%) external capacitance with low ESR/ESL

(typical 0.1 ohm and 1 nH) is required on the XCAP2 pin to provide adequate supply bypass for the internal

digital core. The LDO should not be used to drive external circuitry.

8.3.11 External Clock

The LMP93601 does not have an internal oscillator and needs an external clock, XCLK. The XCLK needs to be

running all the time when the LMP93601 is operating. The SYNC, DRDYB, and RSTB are synchronous to XCLK.

The LMP93601 operating range for XCLK is 3.6 to 4.4 MHz.

8.3.12 Operating Modes

The LMP93601 can be programmed to convert data in continuous-time or single shot modes.

8.3.13 Data Ready Function (DRDYB)

DRDYB is an active low output signal. It is asserted when new data is ready to be read and should be used by

the MCU for data capturing.

When DRDYB is asserted, the MCU can capture the data any time before the next DRDYB is asserted. The time

is defined as 1/ODR. Please note that if data is not read within the time period, it will be over-written internally in

the LMP93601 by the new data.

For DRDYB de-assertion, it is normally cleared by a data read. In the following example: it is de-asserted on the

14^thSCLK rising edge.

If data has not been read when the new data is about to be ready, DRDYB will be de-asserted for 15 XCLK

periods (defined as t_DRDYB) so that LMP93601 can re-assert the DRDYB. Once this happens, the µC should wait

for the next DRDYB assertion before issuing an SPI read protocol.

DRDYB assertion and de-assertion is synchronous to XCLK and SCLK respectively in normal operation.

Figure 17. DRDYB Behavior for A Complete Read Operation

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t1/ODRt

DRDYB

SDO

tDRDYB

ch3

ch1

ch2

ch3

ch1

ch2

ch3

ch1

CONV

DRDYB

The above example is to show how DRDYB functions if more than 1 channel is enabled. DRDBYB is only issued every round-robin. DRDYB is de-asserted when

the LMP93601 starts to output data.

ch1

CONV

DRDYB

The above example is to show how DRDYB functions if only 1 channel is enabled. DRDYB is de-asserted when the LMP93601 starts to output data.

Figure 18. DRDYB Behavior for an Incomplete Read Operation

8.3.14 Synchronous Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) interface allows access to the control registers of the LMP93601. The serial

interface is a generic 4-wire synchronous interface compatible with SPI type of interfaces used on many

microcontrollers and DSP controllers. A typical serial interface access cycle is exactly 16 bits long, which

includes an 8-bit command field (R/WB + 7-bit address) to provide a maximum of 128 direct access addresses,

and an 8-bit data field.

LMP93601’s SCLK can be in either idle high or idle low state when CSB is de-asserted. The first incoming data

on the SCLK rising edge, and all incoming data at SDI is captured on the SCLK rising edge. Outgoing data is

sourced at SDO on the SCLK falling edge and the MCU can capture data from the LMP93601 on the SCLK

rising edge.

8.3.15 Power Management Mode; Standby, Conversion and Shutdown

The device can be placed in Standby and Conversion mode via the SPI. In Conversion mode, the ADC and PGA

are operating and converting data. In Standby mode the PGA and ADC are disabled and not converting data. In

Standby mode the contents of the registers are unaffected, and there is a drastic power reduction. Only the

internal reference, LDO, VCM driver and the digital are on.

The reaction time going from Standby mode to Conversion mode is approximately 100 µs.

The LMP93601 can be put in shutdown mode by taking the PWDNB pin low. In shutdown mode, all internal

circuitry is disabled and no register settings are maintained. The power consumption is very low (< 0.1 uA).

Releasing the PWDNB (taking it high) will “wake up” the device and it will return to the default Standby mode.

Wake up time from shutdown can be up to 10 ms.

Table 5. Wake Up Time From Low Power Modes

Mode

Registers

Power

Wake Up Time

Programmable via

Shutdown

Not maintained

~0.1 µA

Less than 10 ms to go to

Standby mode

PWDNB pin

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Table 5. Wake Up Time From Low Power Modes (continued)

Mode

Registers

Power

Wake Up Time

Programmable via

Standby

Maintained

~175 µA

~100 µs to go to

conversion mode

SPI

Conversion

Maintained

1.1 mA

n/a

SPI

8.3.16 Power-On Sequence and Reset (POR) Function

An internal power on reset is generated after both the internal LDO (to supply the internal digital) and IOVDD

reach valid values. The internal LDO will reach stable values only after the AVDD has reached at least 2.7 V.

The device should be powered up with AVDD enabled and stabilized first, then the IOVDD. This allows the

device to start in the default power up state and ensures that the internal power on reset is generated after both

the internal LDO (to supply the internal digital) and IOVDD reach valid values. The internal LDO will reach stable

values only after the AVDD has reached at least 2.7 V for 1 ms. Alternatively, AVDD and IOVDD can be

connected together, but this can result in an erroneous brown-out condition being reported when the ramp time

of the supplies is slower than 0.1 V/ms. For example, if the AVDD = IOVDD are linearly ramped from 0 to 3.3 V

in longer than 330 µs, the brown could possibly trigger and be logged in the status register and the first

conversion result could read ‘7FFF’. To avoid this erroneous brown-out report, three alternative solutions are

available:

a. After the supplies are stable, reset the part (either with the RSTB pin or with a soft reset via SPI). After this

reset, the part can be programmed and used as intended.

b. Or, after the supplies are stable, program the part as desired, but before initiating the first conversion, read

back the status register(s) of the enabled channel(s) to clear the erroneous brown-out status.

c. Or, wait supplying the XCLK to the part until after the supplies are stable

8.3.17 Brown-Out Detection Function

A brown-out detection circuit monitors the AVDD. It triggers an alarm only when AVDD falls below ~2.55 V and

stays below 2.55 V for more than 16 fxclk cycles. The brown-out detection has a hysteresis of ~65 mV. The

alarm will result in “0x7FFF” data and the appropriate channel status register(s) can be read to decode the alarm.

The brown-out error function can be masked via SPI with the “alarm mask” register.

8.3.18 Reset Function

The device can be reset to the default (Standby) state via the SPI or taking the RSTB pin low. The reaction time

from the reset (either via SPI or RSTB pin) to the device getting to Standby mode is on the order of 100 µs. See

Table 6

8.4 Device Functional Modes

8.4.1 Single-Shot Mode

In Single Shot mode each conversion is triggered by a Start Trigger from the microcontroller unit (MCU) to the

LMP93601 by pulsing the SYNC pin or via a start SPI command (SYNC is recommended for exact timing

control). After the LOCK bit is set, the external µC should wait 3 XCLK cycles before it sends a start trigger. This

is to allow the internal synchronizer enough time to synchronize the SPI write of the LOCK bit into the XCLK

domain. This assumes the analog has already settled (otherwise, allow ~100 µs to go from standby to conversion

mode).

The SYNC has typical setup/hold time of 20 ns with respect to XCLK, as shown in Figure 19.

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Device Functional Modes (continued)

t_hold

XCLK

SYNC

t_setup

DRDYB

t_valid

Figure 19. Single Shot Sync Setup/Hold Time

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Device Functional Modes (continued)

See Figure 20 for details regarding the Single Shot Flow Chart.

MCU sets the

Sensor Select Mux

Lines

System Power-Up

Start Trigger can

be issuedby

pulsingthe SYNC

pinor writingthe

START Command

viaSPI

MCU Issues

Start Trigger

Read LMP93601

Status

Check if

DRDYB Falling

Edge detected by

MCU?

LMP93601

initializationis

complete

Device Ready?

Yes

(1) MCU Switches

the Sensor Select

Mux Lines for the

next conversion

(2) MCU Issues a

Read for the

Note: MCU can

readthe

conversiondata

anytime before

the next DRDYB

assertion

Write

Configuration

current conversion

result

Lock Configuration

Figure 20. Single Shot Flow Chart

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Device Functional Modes (continued)

8.4.2 Continuous Mode

In Continuous mode the LMP93601 only requires a single Start Trigger to start. The Start Trigger can start either

by a SYNC or a Start command via the SPI (SYNC is recommended). After the LOCK bit is set, the external

MCU should wait 3 XCLK cycles before it sends a start trigger. This allows the internal synchronizer enough time

to synchronize the SPI write of the LOCK bit into the XCLK domain. This assumes the analog has already settled

(else allow ~100 µs to go from standby to conversion mode).

It will convert all enabled channels without requiring another Start Trigger. Figure 21 shows the Continuous Mode

Flow Chart.

System Power-Up

MCU sets the

Start Trigger can be

issued by pulsing the

SYNC pin or writing

the START Command

via SPI

Sensor Select Mux

Lines

Read LMP93601

Status

MCU Issues

Start Trigger

Note: It only needs to

be provided once.

Check if

LMP93601

initialization is

complete

Device Ready?

Yes

Note: MCU ensures

that there is enough

settling from DRDYB

to next conversion

start.

DRDYB Falling

Edge detected by

MCU?

Yes

Write

Configuration

(1) MCU Switches

the Sensor Select

Mux Lines for the

next conversion

(2) MCU Issues a

Read for the

Note: MCU can read

the conversion data

anytime before the

Lock Configuration

next DRDYB assertion

current conversion

result

Figure 21. Continuous Mode Flow Chart

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8.5 Programming

8.5.1 Window to Capture Data and Status

SPI Protocols can be asynchronous to XCLK. Data and status read can only happen between the consecutive

DRDYB falling edges. For example, after DRDYB is asserted by the LMP93601, the MCU has to finish reading

all data before DRDYB is asserted again.

For best performance in continuous acquisition mode, it is recommended to read the data within 70 µs after

DRDYB is asserted in order to keep the SPI activity during conversion to a minimum.

NOTE

The de-assertion of DRDYB happens after a data read command is received.

Prior Ch1

conversion is

over-ranged

T_{no_rd}

tT_rdt

Input

Condition

Over-range

ch2

Good

ch2

Good

ch1

Good

ch1

Good

ch2

Good

ch1

Good

ch2

Good

ch1

CONV

DRDYB

Good data

Over-range data

Good data

Ch1 data

Good data

Over-range data

Ch2 data

Ch1 status

Status: Good

Status: over-range

Status: Good

Ch2 status

Status: Good

Status: over-range

Data Read

Status Read

Ch2 status

not cleared.

Ch2 status is cleared since the

previous status is read and a

within-range data is converted.

Ch1 data is over-

Ch1 status is

cleared only after

it is read.

written but over-

ranged status is still

available.

Ch1 & Ch2

status is read.

Ch1 status is cleared after it is read even though the latest data is within range.

Ch2 status is not cleared since the current status is still over-range. It is cleared only after a within-range data is converted.

*DRDYB is de-asserted by data read.

**Since data is not read by the MCU, DRDYB is de-asserted by the LMP93601 automatically so that it can be asserted again

when the new data is available. In this case, both data & status should not be read by the MCU during the T_{no_rd}time duration.

Figure 22. Channel Data Transfer Timing Diagram

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Programming (continued)

Prior Ch1

conversion is

over-ranged

Input

Good

Over-range

Good

ch2

Good

ch1

Good

ch2

Good

ch1

Good

ch2

Good

ch1

Condition

ch2

ch1

CONV

DRDYB

Ch1 data

Ch2 data

Over-range data

Good data

Over-range data

Good data

Status: over-range (1)

Status: Good

Good data

Status: Good

Status: over-range (2)

Status: Good

Ch1 status

Ch2 status

Status: Good

Data Read

Status Read

Ch1 status is

cleared only after

it is read.

Ch1 status(1) is over-

written by a different

over-range status(2).

Ch1 & Ch2

status is read.

If the LMP93601 gets multiple over-ranged data, the latest status is reported.

*DRDYB is de-asserted by SPI data read.

Figure 23. Channel Data Transfer Timing Diagram

8.5.2 Single Byte Access

WRITE: A single byte write access is a total of 16 SCLK periods during CSB assertion. Incoming data is captured

on the rising edge of the SCLK. A command byte consists of an R/W bit and a 7-bit address field and R/W = 0

for write protocols.

CSB

SCLK

SDI

7-bit register

address (n)

8-bit data written

to address (n)

R/W

Figure 24. Single Byte Write Access

READ: Similar to a write, the LMP93601 captures incoming data on the SCLK rising edge. After the 8th rising

edge, the LMP93601 output data is sourced on the SCLK falling edge and the MCU should capture it on the

rising edge. R/W = 1 for read protocols.

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Programming (continued)

CSB

SCLK

7-bit register

address (n)

R/W

SDI

8-bit data read

from address (n)

SDO

Figure 25. Single Byte Read Access

8.6 Register Maps

Table 6. LMP93601 Internal Registers

ADDR

[6:0]

Name

# of Bits

Type

Default

Description

Locked when

conversion is

enabled?

0x00

0x01

Lock

R/W⁽¹⁾

‘h00

[0]

n/a⁽²⁾

0: configuration bits are writeable (default)

1: configuration bits are read-only (that is, locked)

unless noted.

[7:1] always 0

Config1

R/W⁽¹⁾

‘h00

[7] continuous/single shot:

0: Continuous – the part will convert all enabled

channels sequentially in a round-robin manner.

After all channels are converted, it will repeat the

round-robin. (default)

1: Single-Shot - the part will convert all enabled

channels once in a round-robin manner after

receiving a start-trigger (SYNC pulse preferred). It

will wait for the next trigger before converting all

enabled channels again.

[2:0] Channel enable

Channel enable configuration for the 3 channels

(Ch1-3):

3’b000: Only Ch1 is enabled(default)

3’b001: Only Ch2 is enabled

3’b010: Only Ch3 is enabled

3’b011: Only Ch1 & Ch2 enabled

3’b100: Ch1, 2, & 3 enabled

3’b101, 3’b110, 3’b111: Reserved

[6:3]: always 0

(1) R/W = Read or Write

(2) n/a = not applicable

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Table 6. LMP93601 Internal Registers (continued)

ADDR

[6:0]

Name

# of Bits

Type

Default

Description

Locked when

conversion is

enabled?

0x02

Config2

R/W⁽¹⁾

’h82

[7] Reference Output Enables for VCM

0: Disable the corresponding VCM output

1: Enable the corresponding VCM output

(default)

VCM = AVDD/3

[1:0] SPS select

Global setting for all enabled channels

2’b00: 265 sps

2’b01: 530 sps

2’b10: 1057 sps(default)

2’b11: 1326 sps

[6:2] always 0

0x03

Config3

R/W⁽¹⁾

’h52

PGA settings for differential channels. All

channels will always have the same setting.

[6:4] Digital

3’b000: 1

3’b001: 2

3’b010: 4

3’b011: 8

3’b100: 16

3’b101: 32(default)

3’b110-111: Reserved

[1:0] Analog

2’b00: 16

2’b01: 32

2’b10: 64 (default)

2’b11: 128

[7], [3:2] always 0

[2] , Bypass PGA, bit [1:0] would be ignored.

See for more details

0x04

Config4

R/W⁽¹⁾

‘h00

[0] Power Mode

0: Standby (default)

1: Conversion Mode (user still has to write the

lock bit and then provide a start-trigger before

conversion starts)

[7:1] always 0

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Table 6. LMP93601 Internal Registers (continued)

ADDR

[6:0]

Name

# of Bits

Type

Default

Description

Locked when

conversion is

enabled?

0x05

Alarm

mask

R/W⁽¹⁾

‘h00

[7] Brownout Mask

0: when brown-out is detected, all enabled

channels’ conversion result will be 0x7FFF

(default)

1: when brown-out is detected, the conversion

result is not affected.

[6]: Digital Gain Over range Mask

0: when digital gain over-range is detected for a

channel, its conversion result will be 0x7FFF

(default)

1: when digital gain over-range is detected,

conversion result is not affected.

[0] PGA over-range Mask

0: when any of the PGA over-range is detected

for a channel, its conversion result will be 0x7FFF

(default)

1: when any of the PGA over-range is detected,

conversion result is not affected

[5:1] always 0

0x06

sdo_cfg

R/W⁽¹⁾

‘h00

[0] SDO always driven mode

0: SDO only driven during the read back frames

of a SPI read, all other time, SDO is in Hi-Z

(Default)

1: SDO always driven mode: SDO driven high by

LMP93601 except during the read back frame of

a SPI read

[7:1] always 0

[0]: Soft reset

0x07

Soft reset

R/W⁽¹⁾

‘h00

0: normal (Default)

1: Reset all registers hence part will be in default

condition

To reset via SPI, one should write first a 1 to this

bit and then a 0.

[7:1] always 0

[7] Start

0x0f

START

WO⁽³⁾

n/a⁽²⁾

Only writeable

if LOCK is 1

This is a write-only location. If written, it will act as

the trigger to start the conversion sequence.

In continuous mode, the round robin is triggered

by a write to this register. The round robin will be

repeated so only 1 write is needed.

In Single-Shot mode, the round robin is triggered

by a write to this register and all enabled

channels will be converted once. The chip will

wait for the next write to the START register

before starting the next round robin conversion.

NOTE: For accurate timing control, SYNC pulse

start-trigger is preferred since it is

synchronous to the XCLK domain.

[6:0] always 0

(3) WO = Write Only

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Table 6. LMP93601 Internal Registers (continued)

ADDR

[6:0]

Name

# of Bits

Type

Default

Description

Locked when

conversion is

enabled?

NOTE The following status register addresses are mapped in ascending order for easy read-back.

0x10

general

Status

RO⁽⁴⁾

‘h00

[0]: when this bit is high, the LMP93601 is ready

to be programmed.

n/a⁽²⁾

0x11

Status1

RO⁽⁴⁾

n/a⁽²⁾

[7:0]: Status for CH1:

[0] - Digital gain overrange

[1] - PGA positive output low

[2] - PGA negative output low

[3] - PGA positive output high

[4] - PGA negative output high

[5] - PGA differential output high

[6] - Sign of PGA out.

This alone does not trigger 7FFF error code.

[7] Brown out

0x12

0x13

Status2

Status3

RO⁽⁴⁾

n/a⁽²⁾

[7:0] Status for CH2:

same bit map as CH1 status (above)

[7:0] Status for CH3:

n/a⁽²⁾

same bit map as CH1 status (above)

Channel Results:

When over-range is detected, the corresponding channel result will read back 0x7FFF, unless it is masked.

When brown-out is detected, the converted channel result will read back 0x7FFF, unless it is masked.

NOTE The following channel result register addresses are mapped in ascending order for easy read-back.

0x20

0x21

0x22

0x23

0x24

0x25

0x7E

0x7F

CH1 LSB

CH1 MSB

CH2 LSB

CH2 MSB

CH3 LSB

CH3 MSB

Chip ID

RO⁽⁴⁾

n/a⁽²⁾

8’h73

8’h00

CH1 Result[7:0]

CH1 Result[15:8]

CH2 Result[7:0]

n/a⁽²⁾

CH2 Result[15:8]

CH3 Result[7:0]

CH3 Result[15:8]

LMP93601 chip ID

LMP93601 Revision ID

Revision

(4) RO = Read Only

8.7 Multi Byte Access (Auto Increment) Mode

This interface will support address auto-increment feature. An access cycle may be extended to multiple

registers simply by keeping the CSB asserted beyond the stated 16 clocks of the standard 16-bit protocol. In this

mode, CSB must be asserted during 8*(1+N) clock cycles of SCLK, where N is the number of bytes to write or

read during the access cycle. The auto-incrementing address mode is useful to access a block of registers of

incrementing addresses.

WRITE: Example: if 2 bytes of data are sent by the MCU to the LMP93601, both addresses (n) and (n+1) will be

written at the 16th and 24th rising edges of SCLK respectively. Similarly, if another 8 bits of data is sent, they will

be written in the next address location.

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

Multi Byte Access (Auto Increment) Mode (continued)

CSB

SCLK

SDI

7-bit register

address (n)

8-bit data written

to address (n)

8-bit data written

to address(n+1)

R/W

Figure 26. Example Multi Byte Write Access

READ: Example: if a read address is sent from the MCU to the LMP93601, the LMP93601 will first output the

data at location (n). If another 8 SCLKs are sent, the data at location (n+1) will be output. Similarly, the

LMP93601 will continue to send the data at the next address location until CSB is de-asserted.

CSB

SCLK

7-bit register

address (n)

R/W

SDI

8-bit data read

from address (n)

8-bit data read from

address (n+1)

SDO

Figure 27. Example Multi Byte Read Access

NOTE

If a read (or write) is not 8*(1+N) clock cycles, the last byte will not be read or written. For

example if 20 clocks were used, only the 1^stdata byte is being written, not the 2^ndone.

8.8 Multi-Channel Data Read

CH1, CH2 and CH3 results can be read by a single SPI transaction in Little Endian Format:

•

Byte Level: Ch1[7:0], Ch1[15:8], Ch2[7:0], Ch2[15:8], Ch3[7:0], Ch3[15:8]…..

Bit Level: Ch1[7], [6], [5], [4], [3], [2], [1], [0], [15], [14], [13], [12]. [11], [10], [9], [8], Ch2[7]……..

The overhead is a single byte of command which consists of a READ bit and a 7-bit address field.

NOTE

ADC rate is 1326 SPS (max). If all 3 channels are enabled, the conversion rate for each

channel is 1326 SPS/3 = 426SPS.

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Multi-Channel Data Read (continued)

CSB

16 17

24 25

SCLK

R + 7-bit Address

SDI

Ch1[7:0]

Ch1[15:8]

Ch2[7:0]

Ch2[15:8]

Ch3[7:0]

Ch3[15:8]

SDO

Figure 28. Example Multi Channel Read Access

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Micro-electro-mechanical systems (MEMS) thermopile sensor arrays are gaining popularity in building

automation applications for efficient control of heating, ventilation, and air conditioning (HVAC) system in

residential and commercial buildings. The sensors are installed in the building rooms for detecting the presence

and the motion of the occupants in the rooms. Depending on the presence or absence of people in the room, the

HVAC system is turned on or off respectively. In addition, the thermopile sensor are used for detecting flow of air

in the in the duct-work system in the buildings.

A typical MEMS thermopile array sensor consists of a number of thermopile elements arranged in a matrix

configuration. Each element of the array is accessed by selecting the corresponding XY address in the array

using internal or external decoder circuits. An output frame consists of differential signals form X by Y elements.

Each frame is transferred to the analog-front-end via OUTP (positive output) and OUTN (negative output) output

pins of the sensor in serial format. The analog output signal of the MEMS thermopile sensor is in the micro volt

range. It needs to be amplified significantly before made available to the input of an ADC for digitization.

9.2 Typical Applications

3.3V

VDD

DVDD

RSTB

PWDNB

DRDYB

SYNC

PGA Over-range

Detect

Brownout

Detect

GPIO

INT

Y_3

Y_0

LDO, VREF &

Comm. mode

Generator

Control Unit

VCM

AVDD/3

Vref

IR sensor

X by Y Array

GPIO

External

MPU

INP1

INN1

OUTP

OUTN

EMIF

AGND

CSB

SDO

SDI

CSB

SDI

16-bit û$'&

PGA

INP2

INN2

INP3

INN3

ûꢀ

FIR

SPI

SDO

Modulator FLTR

SCLK

XCLK

X-Decoder

SCLK

LMP93601

GPTM

GPIO

GND

X_3

X_0

AGND

DGND

IOGND

Figure 29. LMP93601 Thermopile Array Interface

9.2.1 Design Requirements

The application requires a microcontroller (MCU) such as Texas Instruments MSP430x, or TM4C129x series of

MCUs connected via Synchronous Serial Interface (SPI) to the LMP93601 AFE. As shown in Figure 29, the X

and Y decoder lines of the thermopile sensor (transducer) needs to be interfaced to the GPIO (General Purpose

Input Output) pins of the MCU. The LMP93601 would require an external clock signal of 4 MHz (±3%).The timer

subsystem of the MCU is well suited to generate the clock signal. A timer output pin shall be used to interface

the output of the MCU timer to the XCLK pin of the LMP93601.

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Applications (continued)

The device provides a reference voltage output (VCM) source to center the output of the sensor around AVDD/3.

If the sensor does not provide a reference input pin, the INPx, INNx inputs of the LMP93601 should be

connected (pulled-up) to VCM output via 2.2 MΩ resistors.

The data converter of the LMP93601 is an incremental delta-sigma type ADC, the modulator is reset after every

conversion. Therefore, after each thermopile element is sampled and the ADC modulator goes through a reset,

there is no possibility of any trace of signal from the previously sampled element.

To sample each thermopile element in the sensor array, the X and Y decoder signals must be provided over the

GPIO, then firmware should allow settling of the data on the decoder. The SYNC pin is provided to signal the

beginning of conversion to LMP93601 ADC. A GPIO of the MCU needs to be interfaced to the SYNC input pin of

the LMP93601 for this purpose.

9.2.2 Detailed Design Procedure

In thermopile array systems, settling time of the signal path plays an important role when higher frame transfer

rates are desired. A frame is an array of X by Y thermopile elements. While the data from each pixel is being

transferred out of the sensor in a sequence, the MUX output must settle to the proper voltage from the element

in the array that is being accessed. The total analog signal path settling time is determined by combined sensor’s

settling time (t_ssnsr) and AFE’s settling time (t_safe). The settling time is determined by the sum of capacitances of

the following: pixel in the array, sensor’s MUX, AFE’s MUX, PCB, AFE’s input stage, and sensor’s resistance.

To achieve faster settling time, total capacitance in the signal path should be kept as low as possible. Therefore,

the system designers should take the resistance of the sensor and the related capacitance into consideration to

achieve optimal performance of the signal path. For example, the pixel-to-pixel settling time should be keep

below 70 μs to process five frame per second (1326 SPS) using a 16 x 16 array sensor. A simplified thermopile

array sensor equivalent circuit is shown in Figure 30.

Sensor MUX

RS1

Sensor side

CS1

OUTP

Ccm

Pixel 1

VCM

Pixel

RSn

OUTN

CSn

Ccm

Pixel n

Figure 30. Simplified Thermopile Sensor Array

The value of biasing resistors; R1 and R2, should be much higher than the value of the sensor output resistance

RSx (that is, R1 = R2 > 10 * RSx).

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

Typical Applications (continued)

The bias current of the sensor and the leakage current of the sensor’s MUX should be considered as well. In

Figure 31 R1 and R2 need to be matched closely to avoid introduction of differential offset error voltage in the

signal path due to mismatched current flow through these resistors. Moreover, Ios through RSx needs to be

calibrated out over temperature. To simplify the circuit in Figure 31 the MUX inside the AFE is not shown.

Figure 31.

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

10 Power Supply Recommendations

The LMP93601 requires two sources of power, AVDD and IOVDD. These pins can be supplied from the

same supply rail as the MCU, from separate regulators or from a battery source. However, it is recommend

that the MCU and the IOVDD share the same supply and the AVDD be supplied from a separate regulator.

In any case, for proper operation, the supply range must remain within the 2.7 V to 5.5 V limits and IOVDD

must always be lower than or equal to AVDD supply. It is highly recommended that during power up, the

AVDD and IOVDD supplies ramp up in a manner to ensure the "IOVDD ≤ AVDD" requirement is not violated.

11 Layout

11.1 Layout Guidelines

To achieve high noise performance of the LMP93601, particular attention must be paid to the layout of the input

signals, inputs INPx and INNx. To avoid introduction of differential noise into the pins, the input traces must lay

out symmetrically.

Proper power-supply decoupling is required on both AVDD and IOVDD. The Supply pins should be decoupled

with at least a 0.1 μF bypass capacitor each. The bypass capacitors should be placed as close to the power-

supply pins as possible with a low impedance connection. For very sensitive systems, or for systems in harsh

noise environments, avoiding the use of vias for connecting the bypass capacitor may offer superior bypass and

noise immunity.

It is recommended that in the layout, analog components [such as ADCs, amplifiers, references, digital-to-analog

converters (DACs), and analog MUXs] be separated from digital components [such as microcontrollers, complex

programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF)

transceivers, universal serial bus (USB) transceivers, and switching regulators]. The best placement for each

application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is

no single layout that is perfect for every design and careful consideration must always be used when designing

with any analog component.

TI recommends placing 47 Ω resistors in series with all digital input and output pins (CS, SCLK, DIN,

DOUT/DRDY, and DRDY). This resistance smooths sharp transitions, suppresses overshoot, and offers some

overvoltage protection. Care must be taken to still meet all SPI timing requirements because the additional

resistors interact with the bus capacitances present on the digital signal lines.

TI also strongly recommends that digital components, especially RF portions, be kept as far as practically

possible from analog circuitry in a given system. Additionally, one should minimize the distance that digital

control traces run through analog areas and avoid placing these traces near sensitive analog components. Digital

return currents usually flow through a ground path that is as close as possible to the digital path. If a solid ground

connection to a plane is not available, these currents may find paths back to the source that interfere with analog

performance. The implications that layout has on the temperature-sensing functions are much more significant

than for ADC functions.

The internal ADC reference supply of the LMP93601 requires a 1 µF high performance (low ESR & ESL) cap on

the XCAP1. This cap must be placed in the immediate proximity of the pin. For best performance it is

recommended that the DAP be connected to AGND. All three "GND" connections (AGND, DGND, and IOGND)

must be connected to system ground and cannot be left floating.

LMP93601

www.ti.com.cn

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

11.2 Layout Example

XCAP1

$ꢀVHFWLRQꢀRIꢀ3&%¶Vꢀ

GND Plain

XCAP2

AVDD Filter CAP

CAP to be placed in close

proximity of XCAP1 pin

Symmetrical input

signal traces

IO GND

Digital signal Edge

Smoothing Resistor

Grounded DAP

Figure 32. LMP93601 Layout Example

LMP93601

ZHCSC60A –MARCH 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

12 器件和文档支持

12.1 商标

All trademarks are the property of their respective owners.

12.2 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMP93601NHZR

LMP93601NHZT

ACTIVE

WQFN

NHZ

4500 RoHS & Green

250 RoHS & Green

Level-1-260C-UNLIM

-25 to 85

L93601

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMP93601NHZR

LMP93601NHZT

WQFN

NHZ

4500

250

330.0

178.0

12.4

4.3

5.3

1.3

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMP93601NHZR

LMP93601NHZT

WQFN

NHZ

4500

250

367.0

208.0

367.0

191.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

NHZ0024B

SQA24B (Rev A)

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMP93601 [TI]

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SI9135_11

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SI9130_11

SI9137

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SI9137LG

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