LMR23615DRRR [TI]

SIMPLE SWITCHER® 36V、1.5A 同步降压转换器 | DRR | 12 | -40 to 125;


型号：	LMR23615DRRR
厂家：	TEXAS INSTRUMENTS
描述：	SIMPLE SWITCHER® 36V、1.5A 同步降压转换器 \| DRR \| 12 \| -40 to 125 转换器
文件：	总36页 (文件大小：2490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMR23615

ZHCSHR3B –JUNE 2017 –REVISED AUGUST 2020

LMR23615 SIMPLE SWITCHER^®36V、1.5A 同步降压转换器

1 特性

3 说明

• 4V 至36V 的输入电压范围

• 1.5A 持续输出电流

• 集成同步整流

• 具有内部补偿的电流模式控制

• 最短导通时间：60ns

• 可调开关频率

• 轻负载下采用PFM 模式

• 与外部时钟频率同步

• 75µA 静态电流

• 软启动至预偏置负载

• 支持高占空比运行模式

• 具有断续模式的输出短路保护

• 过热保护

• 带PowerPAD^™的12 引脚WSON 可湿性侧面封装

• 使用LMZM22602 模块缩短产品上市时间

• 使用LMR23615 并借助WEBENCH^®Power

Designer 创建定制设计方案

LMR23615 SIMPLE SWITCHER^®是一款易于使用的

36V、1.5A 同步降压稳压器，具有 4V 至 36V 的宽输

入电压范围，适用于从非稳压源进行电源调节的各种工

业应用。该器件采用峰值电流模式控制来实现简单控制

环路补偿和逐周期电流限制。该器件具有 75µA 的静态

电流，因此适用于电池供电系统。2µA 的超低关断电

流可进一步延长电池使用寿命。内部环路补偿意味着用

户无需执行冗长乏味的环路补偿设计任务，并且能够最

大程度地减少所需的外部组件。该器件的扩展系列产品

能够以引脚到引脚兼容的封装提供 2.5A (LMR23625)

和 3A (LMR23630) 负载电流选项，从而可以实现简单

且最佳的 PCB 布局。利用精密使能端输入可以简化稳

压器控制和系统电源时序。保护特性包括逐周期电流限

制、间断模式短路保护和过多功率耗散而引起的热关

断。

器件信息

器件型号⁽¹⁾

LMR23615

封装尺寸（标称值）

封装

2 应用

WSON (12)

3.00mm × 3.00mm

• 工厂和楼宇自动化系统：PLC CPU、HVAC 控制、

电梯控制

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 资产跟踪

• 通用宽输入电压调节

空白

V_INup to 36 V

100

C_IN

VIN

BOOT

EN/SYNC

AGND

C_BOOT

V_OUT

R_FBT

C_OUT

R_FBB

VCC

V_OUT= 5 V

V_OUT= 3.3 V

C_VCC

PGND

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

LMR2

简化版原理图

效率与负载间的关系，V_IN= 12V

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAV8

LMR23615

ZHCSHR3B –JUNE 2017 –REVISED AUGUST 2020

www.ti.com.cn

Table of Contents

7.3 Feature Description...................................................10

7.4 Device Functional Modes..........................................16

8 Application and Implementation..................................17

8.1 Application Information............................................. 17

8.2 Typical Applications.................................................. 17

9 Power Supply Recommendations................................23

10 Layout...........................................................................24

10.1 Layout Guidelines................................................... 24

10.2 Layout Example...................................................... 26

11 Device and Documentation Support..........................27

11.1 Device Support........................................................27

11.2 接收文档更新通知................................................... 27

11.3 支持资源..................................................................27

11.4 Trademarks............................................................. 27

11.5 静电放电警告...........................................................27

11.6 术语表..................................................................... 27

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Characteristics.................................................6

6.7 Switching Characteristics............................................6

6.8 Typical Characteristics................................................7

7 Detailed Description........................................................9

7.1 Overview.....................................................................9

7.2 Functional Block Diagram...........................................9

Information.................................................................... 27

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (February 2018) to Revision B (July 2020)

Page

• 向节1 添加了LMZM33602 要点........................................................................................................................ 1

• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

Changes from Revision * (June 2017) to Revision A (February 2018)

Page

• 首次发布量产数据数据表；添加了WEBENCH 内容.......................................................................................... 1

• 在应用中将“可编程逻辑控制器电源”更改为“工厂和楼宇自动化系统...”......................................................1

• 删除了“多功能打印机和工业电源”并重新编写了应用.................................................................................... 1

• 将“应用”中的“HVAC 系统”更改为“通用宽输入电压调节”....................................................................... 1

• Changed the BOOT Capacitor value on Pin Functions to indicate value from 470nF to 100nF or higher......... 3

• Change the Abs Max Rating for EN/SYNC to AGND to V_IN+ 0.3 from 42V...................................................... 4

• Changed Typical Value for VIN_UVLO Rising threshold typical from 3.6-V to 3.7-V and minimum Falling

threshold from 3-V to 2.9-V ................................................................................................................................5

• Change 图7-8from V_OUT= 5 V, f_SW= 1600 kHz to V_OUT= 5 V, f_SW= 2100 kHz............................................. 13

• Changed from V_OUT= 7 V to 36 V to V_IN= 7 V to 36 V on 图8-7 ................................................................... 22

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5 Pin Configuration and Functions

PGND

VIN

BOOT

VCC

PAD

VIN

EN/SYNC

AGND

图5-1. 12-Pin WSON DRR Package With Thermal Pad (Top View)

Pin Functions

I/O

DESCRIPTION

NUMBER

NAME

Switching output of the regulator. Internally connected to both power MOSFETs. Connect to

power inductor.

1, 2

Boot-strap capacitor connection for high-side driver. Connect a high-quality 100nF to 470nF

capacitor from BOOT to SW.

BOOT

Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND. Do

not connect external loading to this pin. Never short this pin to ground during operation.

VCC

Feedback input to regulator, connect the feedback resistor divider tap to this pin.

Connect a resistor R_Tfrom this pin to AGND to program switching frequency. Leave floating for

400-kHz default switching frequency.

Analog ground pin. Ground reference for internal references and logic. Connect to system

ground.

AGND

Enable input to regulator. High=On, Low=Off. Can be connected to VIN. Do not float. Adjust the

input under voltage lockout with two resistors. The internal oscillator can be synchronized to an

external clock by coupling a positive pulse into this pin through a small coupling capacitor. See

节7.3.4 for detail.

EN/SYNC

9, 10

VIN

Input supply voltage.

N/A

Not for use. Leave this pin floating.

Power ground pin, connected internally to the low side power FET. Connect to system ground,

PAD, AGND, ground pins of C_INand C_OUT. Path to C_INmust be as short as possible.

PGND

PAD

Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path

of the die. Must be used for heat sinking to ground plane on PCB.

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6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

–5.5

–0.3

–1

MAX

UNIT

VIN to PGND

V_IN+ 0.3

4.5

EN/SYNC to AGND

FB to AGND

Input voltages

RT to AGND

4.5

AGND to PGND

SW to PGND

0.3

V_IN+ 0.3

SW to PGND less than 10-ns transients

BOOT to SW

–5

Output voltages

5.5

–0.3

–40

–65

VCC to AGND

4.5⁽²⁾

150

Junction temperature, T_J

Storage temperature, T_stg

°C

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.

6.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM)⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged-device model (CDM)⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)

MIN

MAX UNIT

VIN

Input voltage⁽¹⁾

–5

–0.3

EN/SYNC

1.2

Output voltage, V_OUT

Output current, I_OUT

1.5

125

Operating junction temperature, T_J

°C

–40

(1) Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see 节6.5.

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6.4 Thermal Information

LMR23615

THERMAL METRIC^{(1) (2)}

DRR (WSON)

(12 PINS)

41.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

Junction-to-board thermal resistance

°C/W

0.3

ψ_JT

16.5

ψ_JB

R_θJC(top)

R_θJC(bot)

R_θJB

39.1

3.4

16.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Determine power rating at a specific ambient temperature (T_A) with a maximum junction temperature (T_J) of 125°C (see 节6.3).

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLY (VIN PIN)

V_IN

Operation input voltage

3.3

2.9

3.9

3.5

Rising threshold

3.7

3.3

VIN_UVLO

Undervoltage lockout thresholds

Falling threshold

I_SHDN

I_Q

Shutdown supply current

V_EN= 0 V, V_IN= 12 V, T_J= –40 °C to 125°C

μA

Operating quiescent current

(non- switching)

V_IN=12 V, V_FB= 1.2 V, T_J= –40 °C to

125°C, PFM mode

ENABLE (EN/SYNC PIN)

V_{EN_H}

Enable rising threshold voltage

1.4

0.4

1.55

0.4

1.7

V_{EN_HYS}

V_WAKE

Enable hysteresis voltage

Wake-up threshold

V_IN= 4 V to 36 V, V_EN= 2 V

V_IN= 4 V to 36 V, V_EN= 36 V

100 nA

I_EN

Input leakage current at EN pin

μA

VOLTAGE REFERENCE (FB PIN)

V_IN= 4 V to 36 V, T_J= 25 °C

0.985

0.980

1.015

1.020

V_REF

Reference voltage

V_IN= 4 V to 36 V, T_J= –40 °C to 125°C

I_{LKG_FB}

Input leakage current at FB pin V_FB= 1 V

INTERNAL LDO (VCC PIN)

V_CC

Internal LDO output voltage

4.1

3.2

2.8

Rising threshold

Falling threshold

2.8

2.4

3.6

3.2

VCC undervoltage lockout

thresholds

VCC_UVLO

CURRENT LIMIT

I_{HS_LIMIT}

I_{LS_LIMIT}

I_{L_ZC}

Peak inductor current limit

2.9

1.9

3.9

2.5

4.9

3.2

Valley inductor current limit

Zero cross current limit

–0.04

INTEGRATED MOSFETS

High-side MOSFET ON-

resistance

R_{DS_ON_HS}

V_IN= 12 V, I_OUT= 1 A

160

mΩ

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Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Low-side MOSFET ON-

resistance

R_{DS_ON_LS}

V_IN= 12 V, I_OUT= 1 A

mΩ

THERMAL SHUTDOWN

T_SHDNThermal shutdown threshold

T_HYSHysteresis

162

170

178

°C

6.6 Timing Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX UNIT

HICCUP MODE

(1)

N_OC

Number of cycles that LS current limit is tripped to enter hiccup mode

Hiccup retry delay time

Cycles

T_OC

SOFT START

Internal soft-start time. The time of internal reference to increase from 0 V

to 1 V

T_SS

(1) Specified by design.

6.7 Switching Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

SW (SW PIN)

T_{ON_MIN}

Minimum turnon time

Minimum turnoff time

90 ns

(1)

T_{OFF_MIN}

100

SYNC (EN/SYNC PIN)

f_{SW_DEFAULT}Oscillator default frequency

RT pin open circuit

340

150

400

200

460 kHz

250 kHz

2425 kHz

2200 kHz

Minimum adjustable frequency

Maximum adjustable frequency

SYNC frequency range

R_T= 198 kΩ with 1% accuracy

R_T= 17.8 kΩ with 1% accuracy

F_ADJ

1750

200

2150

f_SYNC

Amplitude of SYNC clock AC

signal (measured at SYNC pin)

V_SYNC

2.8

5.5

Minimum sync clock ON and OFF

time

T_{SYNC_MIN}

100

(1) Ensured by design.

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6.8 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 1600 kHz, L = 4.7 µH, C_OUT= 47 µF,

T_A= 25 °C.

100

V_IN= 12 V

V_IN= 24 V

V_IN= 36 V

V_IN= 8 V

V_IN= 12 V

V_IN= 24 V

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

LMR2

f_SW= 1000 kHz

V_OUT= 5 V

f_SW= 1000 kHz

V_OUT= 3.3 V

图6-1. Efficiency vs Load Current

图6-2. Efficiency vs Load Current

100

V_IN= 8 V

V_IN= 12 V

V_IN= 24 V

V_IN= 8 V

V_IN= 12 V

V_IN= 20 V

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

LMR2

f_SW= 2200 kHz

V_OUT= 5 V

f_SW= 2200 kHz (Sync)

V_OUT= 3.3 V

图6-3. Efficiency vs Load Current

图6-4. Efficiency vs Load Current

5.12

5.1

V_IN= 12 V

V_IN= 24 V

V_IN= 36 V

5.11

5.09

5.1

5.09

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5.08

I_OUT= 1.5 A

I_OUT= 0.2 A

I_OUT= 0 A

5.07

5.06

5.05

5.04

5.03

5.02

5.01

0.2

0.4

0.6

0.8

I_OUT(A)

1.2

1.4

1.6

V_IN(V)

LMR2

f_SW= 1000 kHz

V_OUT= 5 V

f_SW= 1000 kHz

V_OUT= 5 V

图6-5. Load Regulation

图6-6. Line Regulation

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5.5

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.5

5.5

5.3

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.5

I_OUT= 0 A

I_OUT= 0.2 A

I_OUT= 0.8 A

I_OUT= 1.5 A

I_OUT= 0.2 A

I_OUT= 0.8 A

I_OUT= 1.5 A

4.5

V_IN(V)

5.5

4.5

V_IN(V)

5.5

LMR2

f_SW= 1000 kHz

V_OUT= 5 V

f_SW= 2200 kHz

V_OUT= 5 V

图6-7. Dropout Curve

图6-8. Dropout Curve

3.67

3.66

3.65

3.64

3.63

3.62

3.61

-50

Temperature (°C)

100

150

-50

Temperature (°C)

100

150

D008

D009

V_IN= 12 V

V_FB= 1.1 V

图6-10. VIN UVLO Rising Threshold vs Junction

图6-9. I_Qvs Junction Temperature

Temperature

4.5

0.425

0.42

LS Limit

HS Limit

3.5

2.5

0.415

-50

Temperature (èC)

100

150

LMR2

0.41

V_IN= 12 V

-50

Temperature (°C)

100

150

D010

图6-12. HS and LS Current Limit vs Junction

图6-11. VIN UVLO Hysteresis vs Junction

Temperature

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7 Detailed Description

7.1 Overview

The LMR23615 SIMPLE SWITCHER^®regulator is an easy-to-use synchronous step-down DC-DC converter

operating from a 4-V to 36-V supply voltage. It is capable of delivering up to 1.5-A DC load current with good

thermal performance in a small solution size. An extended family is available in multiple current options from 1.5

A to 3 A in pin-to-pin compatible packages.

The LMR23615 employs constant frequency peak-current-mode control. The device enters PFM mode at light

load to achieve high efficiency. The device is internally compensated, which reduces design time, and requires

few external components. The switching frequency is adjustable from 200 kHz to 2.2 MHz, leaving the RT pin

open for 400-kHz default switching frequency. The LMR23615 is also capable of synchronization to an external

clock within the range of 200 kHz to 2.2 MHz.

Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for

a wide range of applications. Protection features include thermal shutdown, VIN and VCC undervoltage lockout,

cycle-by-cycle current limit, and hiccup-mode short-circuit protection.

The LMR236xx family requires very few external components and has a pinout designed for simple, optimum

PCB layout.

7.2 Functional Block Diagram

EN/SYNC

VCC

SYNC Signal

SYNC

Detector

VCC

Enable

LDO

VIN

Precision

Enable

Internal

CBOOT

HS I Sense

REF

TSD

UVLO

PWM CONTROL LOGIC

PFM

Detector

OV/UV

Detector

Slope

Comp

Freq

Foldback

Zero

Cross

HICCUP

Detector

SYNC Signal

LS I

Sense

Oscillator

AGND

PGND

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7.3 Feature Description

7.3.1 Fixed-Frequency, Peak-Current-Mode Control

The following operating description of the LMR23615 refers to 节 7.2 and to the waveforms in 图 7-1. The

LMR23615 device is a step-down, synchronous buck regulator with integrated high-side (HS) and low-side (LS)

switches (synchronous rectifier). The LMR23615 supplies a regulated output voltage by turning on the HS and

LS NMOS switches with controlled duty cycle. During high-side switch ON-time, the SW pin voltage swings up to

approximately V_IN, and the inductor current I_Lincrease with linear slope (V_IN–V_OUT) / L. When the HS switch is

turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor current

discharges through the LS switch with a slope of –V_OUT/ L. The control parameter of a buck converter is

defined as duty cycle D = t_ON/ T_SW, where t_ONis the high-side switch ON time and T_SWis the switching period.

The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck

converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the

input voltage: D = V_OUT/ V_IN.

V_SW

D = t_ON/ T_SW

V_IN

t_ON

t_OFF

-V_D

T_SW

i_L

I_LPK

I_OUT

Di_L

图7-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LMR23615 employs fixed-frequency peak-current-mode control. A voltage-feedback loop is used to get

accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak

inductor current is sensed from the high-side switch and compared to the peak current threshold to control the

on-time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer

external components, makes it easy to design, and provides stable operation with almost any combination of

output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load

condition, the LMR23615 operates in PFM mode to maintain high efficiency.

7.3.2 Adjustable Frequency

The switching frequency can be programmed by the resistor from the RT pin to ground. The frequency is

inversely proportional to the R_Tresistance. The RT pin can be left floating, and the LMR23615 operates at 400-

kHz default switching frequency. The RT pin is not designed to be shorted to ground. For a desired frequency,

typical R_Tresistance can be found by 方程式 1. 表 7-1 gives typical R_Tvalues for a given switching frequency

(f_SW).

R_T(kΩ) = 40200 / f_SW(kHz) –0.6

(1)

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250

200

150

100

500

1000

1500

2000

2500

Switching Frequency (kHz)

C008

图7-2. RT vs Frequency Curve

表7-1. Typical Frequency Setting RT Resistance

f_SW(kHz)

R_T(kΩ)

200

350

200

115

500

78.7

53.6

39.2

26.1

19.6

17.8

750

1000

1500

2000

2200

7.3.3 Adjustable Output Voltage

A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating

temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI

recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the low-

side resistor R_FBBfor the desired divider current and use Equation 2 to calculate high-side R_FBT. R_FBTin the

range from 10 kΩ to 100 kΩ is recommended for most applications. A lower R_FBTvalue can be used if static

loading is desired to reduce V_OUToffset in PFM operation. Lower R_FBTreduces efficiency at very light load. Less

static current goes through a larger R_FBTand might be more desirable when light load efficiency is critical.

However, R_FBTlarger than 1 MΩ is not recommended because it makes the feedback path more susceptible to

noise. Larger R_FBTvalue requires more carefully designed feedback path on the PCB. The tolerance and

temperature variation of the resistor dividers affect the output voltage regulation.

OUT

FBT

FBB

图7-3. Output Voltage Setting

V_OUT- V_REF

V_REF

R_FBT

ìR_FBB

(2)

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7.3.4 Enable/Sync

The voltage on the EN pin controls the ON or OFF operation of LMR23615 device. A voltage less than 1 V

(typical) shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator. The

EN pin is an input and cannot be left open or floating. The simplest way to enable the operation of the

LMR23615 is to connect the EN to V_IN. This allows self-start-up of the LMR23615 when V_INis within the

operation range.

Many applications benefit from the employment of an enable divider R_ENTand R_ENB(图 7-4) to establish a

precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility

power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,

such as a battery discharge level. An external logic signal can also be used to drive EN input for system

sequencing and protection.

VIN

R_ENT

EN/SYNC

R_ENB

图7-4. System UVLO by Enable Divider

The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can

be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at the

EN pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse

detector, and the minimum SYNC clock ON and OFF time must be longer than 100 ns (typical). A 3.3-V or a

higher amplitude pulse signal coupled through a 1-nF capacitor C_SYNCis a good starting point. Keeping R_ENT//

R_ENB(R_ENTparallel with R_ENB) in the 100-kΩ range is a good choice. R_ENTis required for this synchronization

circuit, but R_ENBcan be left unmounted if system UVLO is not needed. Switching action of the LMR23615 device

can be synchronized to an external clock from 200 kHz to 2.2 MHz. 图 7-6 and 图 7-7 show the device

synchronized to an external system clock.

VIN

R_ENT

C_SYNC

EN/SYNC

R_ENB

Clock

Source

图7-5. Synchronizing to External Clock

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图7-6. Synchronizing in PWM Mode

7.3.5 VCC, UVLO

图7-7. Synchronizing in PFM Mode

The LMR23615 integrates an internal LDO to generate V_CCfor control circuitry and MOSFET drivers. The

nominal voltage for V_CCis 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place a

high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible

to VCC, grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, or shorted to

ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23615 device.

VCC undervoltage lockout (UVLO) prevents the LMR23615 from operating until the V_CCvoltage exceeds 3.2 V

(typical). The VCC_UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to

temporary V_INdrops.

7.3.6 Minimum ON-Time, Minimum-OFF Time, and Frequency Foldback at Dropout Conditions

Minimum ON-time, T_{ON_MIN}, is the smallest duration of time that the HS switch can be on. T_{ON_MIN}is typically 60

ns in the LMR23615. Minimum OFF-time, T_{OFF_MIN}, is the smallest duration that the HS switch can be off.

T_{OFF_MIN}is typically 100 ns in the LMR23615. In CCM operation, T_{ON_MIN}and T_{OFF_MIN}limit the voltage

conversion range given a selected switching frequency.

The minimum duty cycle allowed is:

D_MIN= T_{ON_MIN}× f_SW

(3)

And the maximum duty cycle allowed is:

D_MAX= 1 –T_{OFF_MIN}× f_SW

(4)

Given fixed T_{ON_MIN}and T_{OFF_MIN}, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LMR23615 device, a frequency foldback scheme is employed to extend the maximum duty cycle

when T_{OFF_MIN}is reached. The switching frequency decreases once longer duty cycle is needed under low V_IN

conditions. Wide range of frequency foldback allows the LMR23615 output voltage stay in regulation with a

much lower supply voltage V_IN. This leads to a lower effective drop-out voltage.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size, and efficiency. The maximum operation supply voltage can be found by:

V_OUT

IN_MAX

ì T_{ON_MIN}

(

)

(5)

At lower supply voltage, the switching frequency decreases once T_{OFF_MIN}is tripped. The minimum V_INwithout

frequency foldback can be approximated by:

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V_OUT

IN_MIN

1- f

(

ì T_{OFF _MIN}

)

(6)

Taking considerations of power losses in the system with heavy load operation, V_{IN_MAX}is higher than the result

calculated in 方程式5. With frequency foldback, V_{IN_MIN}is lowered by decreased f_SW

2500

2000

1500

1000

500

0.5 A

1.0 A

1.5 A

5.5

6.5

Input Voltage (V)

7.5

LMR2

图7-8. Frequency Foldback at Dropout (V_OUT= 5 V, f_SW= 2100 kHz)

7.3.7 Internal Compensation and C_FF

The LMR23615 is internally compensated as shown in 节 7.2. The internal compensation is designed such that

the loop response is stable over the entire operating frequency and output voltage range. Depending on the

output voltage, the compensation loop phase margin can be low with all ceramic capacitors. An external

feedforward capacitor C_FFis recommended to be placed in parallel with the top resistor divider R_FBTfor optimum

transient performance.

V_OUT

C_FF

R_FBT

R_FBB

图7-9. Feedforward Capacitor for Loop Compensation

The feedforward capacitor C_FFin parallel with R_FBTplaces an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by

f_{Z _ CFF}

2pìC_FFìR_FBT

(

)

(7)

An additional pole is also introduced with C_FFat the frequency of

f_{P _ CFF}

2pìC_FFìR_FBT//R_FBB

(

)

(8)

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The zero f_{Z_CFF}adds phase boost at the crossover frequency and improves transient response. The pole f_P-CFF

helps maintaining proper gain margin at frequency beyond the crossover. 表 8-1 lists the combination of C_OUT

C_FFand R_FBTfor typical applications, designs with similar C_OUTbut R_FBTother than recommended value, adjust

C_FFsuch that (C_FF× R_FBT) is unchanged and adjust R_FBBsuch that (R_FBT/ R_FBB) is unchanged.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have

different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most C_FF.

Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low

enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at

the output may not need any C_FF. The location of this ESR zero frequency can be calculated with Equation 9:

f_{Z _ESR}

2pìC

ìESR

(

)

OUT

(9)

The C_FFcreates a time constant with R_FBTthat couples in the attenuate output voltage ripple to the FB node. If

the C_FFvalue is too large, it can couple too much ripple to the FB and affect V_OUTregulation. Therefore,

calculate C_FFbased on output capacitors used in the system. At cold temperatures, the value of C_FFmight

change based on the tolerance of the chosen component. This may reduce its impedance and ease noise

coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of C_FFcan be

reduced.

7.3.8 Bootstrap Voltage (BOOT)

The LMR23615 device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT

and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when

the high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor

is 0.1 μF to 0.47 μF . TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage

rating of 16 V or higher for stable performance over temperature and voltage.

7.3.9 Overcurrent and Short-Circuit Protection

The LMR23615 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and

valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.

High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See 节 7.2

for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold

I_{HS_LIMIT}, which is constant. Thus the peak current limit of the high-side switch is not affected by the slope

compensation and remains constant over the full duty-cycle range.

The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor

current begins to ramp down. The LS switch does not turn OFF at the end of a switching cycle if its current is

above the LS current limit I_{LS_LIMIT}. The LS switch is kept ON so that inductor current keeps ramping down, until

the inductor current ramps below the LS current limit I_{LS_LIMIT}. Then the LS switch turns OFF, and the HS

switches on, after a dead time. This is somewhat different than the more typical peak-current limit and results in

方程式10 for the maximum load current.

_IN- V_OUT

(

)

V_OUT

I_{OUT _MAX}= I_{LS _LIMIT}

2ì f_SWìL

(10)

If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup-current-

protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms, typically, before

the LMR23615 tries to start again. If an overcurrent or short-circuit fault condition still exist, hiccup repeats until

the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,

prevents over-heating and potential damage to the device.

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7.3.10 Thermal Shutdown

The LMR23615 provides an internal thermal shutdown to protect the device when the junction temperature

exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature

falls below 155°C (typical), the device reinitiates the power up sequence controlled by the internal soft-start

circuitry.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The EN pin provides electrical on- and off-control for the LMR23615. When V_ENis below 1 V (typical), the device

is in shutdown mode. The LMR23615 also employs VIN and VCC UVLO protection. If V_INor V_CCvoltage is

below their respective UVLO level, the regulator is turned off.

7.4.2 Active Mode

The LMR23615 is in active mode when V_ENis above the precision enable threshold, and V_INand V_CCare above

their respective UVLO level. The simplest way to enable the LMR23615 is to connect the EN pin to VIN pin. This

allows self start-up when the input voltage is in the operating range: 4 V to 36 V. See 节 7.3.5 and 节 7.3.4 for

details on setting these operating levels.

In active mode, depending on the load current, the LMR23615 will be in one of three modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple.

2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation.

3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load.

7.4.3 CCM Mode

CCM operation is employed in the LMR23615 device when the load current is higher than half of the peak-to-

peak inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a

minimum in this mode, and the maximum output current of 1.5 A can be supplied by the device.

7.4.4 Light Load Operation

When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR23615 operate in

DCM , also known as diode emulation mode (DEM). In DCM, the LS switch is turned off when the inductor

current drops to I_{L_ZC}(–40 mA typical). Both switching losses and conduction losses are reduced in DCM,

compared to forced PWM operation at light load.

At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum

HS switch ON time (t_{ON_MIN}) or the minimum peak inductor current I_{PEAK_MIN}(300 mA typical) is reached, the

switching frequency decreasse to maintain regulation. In PFM, switching frequency is decreased by the control

loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM

operation due to less frequent switching actions. The external clock synchronizing is not valid when the

LMR23615 device enters into PFM mode.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

The LMR23615 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 1.5 A. The following design procedure can be used to select

components for the LMR23615. Alternately, the WEBENCH^®software may be used to generate complete

designs. When generating a design, the WEBENCH software utilizes iterative design procedure and accesses

comprehensive databases of components. See 节8.2.2.1 and ti.com for more details.

8.2 Typical Applications

The LMR23615 only requires a few external components to convert from a wide voltage range supply to a fixed

output voltage. 图8-1 shows a basic schematic.

V_IN12 V

C_BOOT

BOOT

0.1 ꢀF

VIN

V_OUT

5 V/1.5 A

C_IN

10 ꢀF

4.7 ꢀH

EN/

SYNC

R_FBT

88.7 kΩ

PAD

C_FF

22 pF

C_OUT

33 ꢀF

C_VCC

2.2 ꢀF

R_FBB

22.1 kΩ

VCC

PGND

AGND

R_T

24.3 kΩ

图8-1. Application Circuit

The external components must fulfill the needs of the application, but also the stability criteria of the device

control loop. 表8-1 can be used to simplify the output filter component selection.

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表8-1. L, C_OUT, and C_FFTypical Values

f_SW(kHz)

V_OUT(V)

3.3

L (µH) ⁽¹⁾

C_OUT(µF) ⁽²⁾

C_FF(pF)⁽⁴⁾

220

R_FBT(kΩ)⁽³⁾

200

150

88.7

243

510

120

200

See note⁽⁵⁾

100

3.3

120

88.7

243

510

400

See note⁽⁵⁾

3.3

4.7

5.6

1000

2200

88.7

243

See note⁽⁵⁾

3.3

2.2

3.3

88.7

(1) Inductance value is calculated based on V_IN= 36 V.

(2) All the C_OUTvalues are after derating. Add more when using ceramic capacitors.

(3) R_FBT= 0 Ωfor V_OUT= 1 V. R_FBB= 22.1 kΩfor all other V_OUTsettings.

(4) For designs with R_FBTother than recommended value, adjust C_FFso that (C_FF× R_FBT) is unchanged and adjust R_FBBsuch that (R_FBT

R_FBB) is unchanged.

(5) High ESR C_OUTgives enough phase boost and C_FFnot needed.

8.2.1 Design Requirements

Detailed design procedure is described based on a design example. For this design example, use the

parameters listed in 表8-2 as the input parameters.

表8-2. Design Example Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage, V_IN

12 V typical, range from 8 V to 28 V

Output voltage, V_OUT

5 V

1.5 A

Maximum output current I_{O_MAX}

Transient response 0.2 A to 1.5 A

Output voltage ripple

50 mV

400 mV

1600 kHz

Input voltage ripple

Switching frequency, f_SW

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23615 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

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Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of LMR23615 is externally adjustable using a resistor divider network. The divider network is

comprised of top feedback resistor R_FBTand bottom feedback resistor R_FBB. Equation 11 is used to determine

the output voltage:

V_OUT- V_REF

V_REF

R_FBT

ìR_FBB

(11)

For example, choosing the value of R_FBBas 22.1 kΩ, the desired output voltage set to 5 V, and the V_REF= 1 V,

the R_FBBvalue is calculated using Equation 11. The formula yields to a value 88.7 kΩ.

8.2.2.3 Switching Frequency

The switching frequency can be adjusted by R_Tresistance from RT pin to ground. Use 方程式 1 to calculate the

required value of R_T. The device can also be synchronized to an external clock for a desired frequency. See 节

7.3.4 for more details.

For 1600 kHz frequency, the calculated R_Tis 24.5 kΩ, and standard value 24.3 kΩ is selected to set the

frequency approximate to 1600 kHz.

8.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The

inductance is based on the desired peak-to-peak ripple current Δi_L. Because the ripple current increases with

the input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use 方

程式 13 to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the amount of

inductor ripple current relative to the maximum output current of the device. A reasonable value of K_INDwould be

20% to 40%. During an instantaneous short or overcurrent operation event, the RMS and peak inductor current

can be high. The inductor current rating must be higher than the current limit of the device.

V_OUTì V

- V_OUT

(

)

IN_MAX

Di_L=

V_{IN_MAX}ìL ì f_SW

(12)

(13)

- V_OUT

V_OUT

IN_MAX

L_MIN

I_OUTìK_IND

_{IN_MAX}ì f_SW

In general, it is preferable to choose lower inductance in switching power supplies, because lower inductance

usually corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But

inductance that is too low can generate an inductor current ripple that is too large such that overcurrent

protection at the full load could be falsely triggered. It also generates more conduction loss and inductor core

loss. Larger inductor current ripple also implies larger output voltage ripple with same output capacitors. With

peak-current-mode control, TI does not recommend having an inductor current ripple that is too small. A larger

peak-current ripple improves the comparator signal-to-noise ratio.

For this design example, choose K_IND= 0.4, the minimum inductor value is calculated to be 4.3 µH. Choose the

nearest standard 4.7-μH ferrite inductor with a capability of 2-A RMS current and 4-A saturation current.

8.2.2.5 Output Capacitor Selection

Choose the output capacitor(s), C_OUTwith care because it directly affects the steady-state output-voltage ripple,

loop stability, and the voltage over/undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going

through the ESR of the output capacitors:

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DV_{OUT_ESR}= Di_LìESR = K_INDìI_OUTìESR

(14)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Di_L

K_INDìI_OUT

DV_{OUT _C}

8ì f ìC_OUT

(

)

(

)

(15)

where

• K_IND= Ripple ratio of the inductor ripple current (Δi_L/ I_OUT

)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,

output capacitors provide the required charge before the inductor current can slew up to the appropriate level.

The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop.

The output capacitance must be large enough to supply the current difference for four clock cycles to maintain

the output voltage within the specified range. Equation 16 shows the minimum output capacitance needed for

specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy

stored in the inductor, which causes an output voltage overshoot. Equation 17 calculates the minimum

capacitance required to keep the voltage overshoot within a specified range.

4ì I_OH-I_OL

(

)

C_OUT

f_SWì V_US

(16)

(17)

I_O²_H-I_O²_L

C_OUT

ìL

+ V_OS- V_O²_UT

(

)

OUT

where

• I_OL= Low level output current during load transient

• I_OH= High level output current during load transient

• V_US= Target output voltage undershoot

• V_OS= Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR}= ΔV_{OUT_C}= 50 mV, and

choose K_IND= 0.4. Equation 14 yields ESR no larger than 83.3 mΩ, and Equation 15 yields C_OUTno smaller

than 0.9 μF. For the target over/undershoot range of this design, V_US= V_OS= 5% × V_OUT= 250 mV. The C_OUT

can be calculated to be no smaller than 14 μF and 4.1 μF by Equation 16 and Equation 17, respectively.

Taking into account the derating factor of ceramic capacitor over temperature and voltage, one 33-μF, 16-V

ceramic capacitor with 5-mΩ ESR is selected.

8.2.2.6 Feedforward Capacitor

The LMR23615 device is internally compensated. Depending on the V_OUTand frequency f_SW, if the output

capacitor C_OUTis dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To

improve the phase boost an external feedforward capacitor C_FFcan be added in parallel with R_FBT. C_FFis

chosen such that phase margin is boosted at the crossover frequency without C_FF. A simple estimation for the

crossover frequency (f_X) without C_FFis shown in Equation 18, assuming C_OUThas very small ESR, and C_OUT

value is after derating.

8.32

f_X

V_OUTìC_OUT

(18)

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Equation 19 for C_FFwas tested:

C_FF

4pì f_XìR_FBT

(19)

For designs with higher ESR, C_FFis not needed when C_OUThas very high ESR, and C_FFcalculated from 方程式

19 should be reduced with medium ESR. 表8-1 can be used as a quick starting point.

For the application in this design example, a 18-pF, 50-V, COG capacitor is selected.

8.2.2.7 Input Capacitor Selection

The LMR23615 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,

depending on the application. The typical recommended value for the high-frequency decoupling capacitor is 4.7

μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating.

To compensate the derating of ceramic capacitors, a voltage rating twice the maximum input voltage is

recommended. Additionally, some bulk capacitance can be required, especially if the LMR23615 circuit is not

located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to

the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R

ceramic capacitors are used. A 0.1-μF for high-frequency filtering and place it as close as possible to the device

pins.

8.2.2.8 Bootstrap Capacitor Selection

Every LMR23615 design requires a bootstrap capacitor (C_BOOT). The recommended capacitor is 0.1 μF and

rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap

capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

8.2.2.9 VCC Capacitor Selection

The VCC pin is the output of an internal LDO for the LMR23615 device. To insure stability of the device, place a

minimum of 2.2-μF, 16-V, X7R capacitor from this pin to ground.

8.2.2.10 Undervoltage Lockout Setpoint

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down

or brownouts when the input voltage is falling. Equation 20 can be used to determine the V_INUVLO level.

R_ENT+ R_ENB

R_ENB

= V_ENHì

IN_RISING

(20)

The EN rising threshold (V_ENH) for LMR23615 is set to be 1.55 V (typical). Choose the value of R_ENBto be 287

kΩ to minimize input current from the supply. If the desired V_INUVLO level is at 6 V, then the value of R_ENTcan

be calculated using Equation 21:

≈

’

IN_RISING

R_ENT

-1 ìR

∆

ENB

V_ENH

◊

(21)

Equation 21 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by

Equation 22, where EN hysteresis (V_{EN_HYS}) is 0.4 V (typical).

R_ENT+ R_ENB

R_ENB

= V_ENH- V_{EN_HYS}

(

)

IN_FALLING

(22)

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8.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 1600 kHz, L = 4.7 µH, C_OUT= 47 µF, T_A= 25 °C.

V_OUT= 5 V

I_OUT= 1.5 A

f_SW= 1600 kHz

I_OUT= 1.5 A

V_OUT= 5 V

I_OUT= 0 mA

f_SW= 1600 kHz

I_OUT= 1.5 A

图8-2. CCM Mode

图8-3. PFM Mode

V_IN= 12 V

V_OUT= 5 V

V_IN= 12 V

V_OUT= 5 V

图8-4. Start-Up by V_IN

图8-5. Start-Up by EN

V_IN= 12 V

V_IN= 7 V to 36 V,

2 V / μs

V_OUT= 5 V

I_OUT= 0.2 A to 1.5 A, 100 mA / μs

图8-6. Load Transient

图8-7. Line Transient

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V_OUT= 5 V

I_OUT= 1 A to short

V_OUT= 5 V

I_OUT= short to 1 A

图8-8. Short Protection

图8-9. Short Recovery

9 Power Supply Recommendations

The LMR23615 is designed to operate from an input voltage supply range between 4 V and 36 V. This input

supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the

input supply rail must be low enough that an input current transient does not cause a high enough drop at the

LMR23615 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is

located more than a few inches from the LMR23615, additional bulk capacitance may be required in addition to

the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic

capacitor is a typical choice.

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10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB

with the best power-conversion performance, thermal performance, and minimized generation of unwanted EMI.

1. The input bypass capacitor C_INmust be placed as close as possible to the VIN and PGND pins. Grounding

for both the input and output capacitors should consist of localized top side planes that connect to the PGND

pin and PAD.

2. Place bypass capacitors for V_CCclose to the VCC pin and ground the bypass capacitor to device ground.

3. Minimize trace length to the FB pin net. Both feedback resistors, R_FBTand R_FBBmust be located close to the

FB pin. Place C_FFdirectly in parallel with R_FBT. If V_OUTaccuracy at the load is important, ensure that the

V_OUTsense is made at the load. Route V_OUTsense path away from noisy nodes and preferably through a

layer on the other side of a shielded layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

5. Have a single point ground connection to the plane. Route the ground connections for the feedback and

enable components to the ground plane. This prevents any switched or load currents from flowing in the

analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior.

6. Make V_IN, V_OUTand ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

7. Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat sinking

to keep the junction temperature below 125°C.

10.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass

capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing

ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load

current without excessive heating. Use short, thick traces or copper pours (shapes) for high-current conduction

path to minimize parasitic resistance. The output capacitors must be placed close to the V_OUTend of the inductor

and closely grounded to PGND pin and exposed PAD.

Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the

exposed PAD.

10.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is

connected to the source of the internal LS switch. They must be connected directly to the grounds of the input

and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load

variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The

other side of the ground plane contains much less noise and should be used for sensitive routes.

TI recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal

path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat

sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground

plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper

thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough

copper thickness provides low current conduction impedance, proper shielding, and lower thermal resistance.

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The thermal characteristics of the LMR23615 are specified using the parameter R_θJA, which characterize the

junction temperature of silicon to the ambient temperature in a specific system. Although the value of R_θJAis

dependent on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use the following relationship:

T_J= P_D× R_θJA+ T_A

(23)

(24)

P_D= V_INx I_IN× (1 –Efficiency) –1.1 × I_OUT²× DCR in watt

where

• T_J= junction temperature in °C

• P_D= device power dissipation in watt

• R_θJA= junction-to-ambient thermal resistance of the device in °C/W

• T_A= ambient temperature in °C

• DCR = inductor DC parasitic resistance in ohm

The recommended operating junction temperature of the LMR23615 is 125°C. R_θJAis highly related to PCB

size and layout, as well as environmental factors such as heat sinking and air flow.

10.1.3 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

C_FFclose to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider and C_FFcloser to the FB pin reduces

the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace

from V_OUTto the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the

load to the feedback resistor divider away from the SW node path and the inductor to avoid contaminating the

feedback signal with switch noise, while also minimizing the trace length. This is most important when high-value

resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the

resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in

between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage

feedback path from EMI noises.

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10.2 Layout Example

Output

Inductor

Output Bypass

Capacitor

PGND

Input Bypass

Capacitor

BOOT

Capacitor

BOOT

VCC

VIN

VCC

Capacitor

EN/SYNC

AGND

UVLO Adjust

Resistor

Thermal VIA

VIA (Connect to GND Plane)

Output Voltage

Set Resistor

图10-1. LMR23615 Layout

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23615 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

11.4 Trademarks

PowerPAD^™is a trademark of TI.

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

SIMPLE SWITCHER^®and are registered trademarks of TI.

所有商标均为其各自所有者的财产。

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMR23615DRRR

LMR23615DRRT

ACTIVE

WSON

DRR

3000 RoHS & Green

250 RoHS & Green

Level-2-260C-1 YEAR

-40 to 125

23615

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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23-Jun-2023

OTHER QUALIFIED VERSIONS OF LMR23615 :

Automotive : LMR23615-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMR23615DRRR

LMR23615DRRT

WSON

DRR

3000

250

330.0

180.0

12.4

3.3

1.0

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMR23615DRRR

LMR23615DRRT

WSON

DRR

3000

250

367.0

213.0

367.0

191.0

38.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DRR0012D

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

1.7 0.1

2.5

2.5 0.1

10X 0.5

0.3

0.2

12X

0.38

0.28

12X

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

4223146/D 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRR0012D

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.7)

12X (0.53)

SYMM

12X (0.25)

SYMM

(2.5)

10X (0.5)

(1)

(R0.05) TYP

(0.6)

(2.87)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL EDGE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223146/D 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRR0012D

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.47)

12X (0.53)

12X (0.25)

METAL

TYP

(0.675)

SYMM

10X (0.5)

(1.15)

(R0.05) TYP

(0.74)

(2.87)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80.1% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4223146/D 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMR23615DRRR [TI]

相关型号：

LMR23615DRRT

LMR23615QDRRRQ1

LMR23615QDRRTQ1

LMR23625

LMR23625-Q1

LMR23625CDDA

LMR23625CDDAR

LMR23625CFDDA

LMR23625CFDDAR

LMR23625CFPDRRR

LMR23625CFPDRRT

LMR23625CFPQDRRRQ1