LMR23625CQDDARQ1 [TI]

通过汽车级认证的 SIMPLE SWITCHER® 4V 至 36V、2.5A 同步降压转换器 | DDA | 8 | -40 to 125;


型号：	LMR23625CQDDARQ1
厂家：	TEXAS INSTRUMENTS
描述：	通过汽车级认证的 SIMPLE SWITCHER® 4V 至 36V、2.5A 同步降压转换器 \| DDA \| 8 \| -40 to 125 开关光电二极管转换器
文件：	总41页 (文件大小：3345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

LMR23625-Q1 SIMPLE SWITCHER^®36V、2.5A 同步降压转换器

1 特性

2 应用

•

符合汽车应用标准

•

汽车信息娱乐系统：仪表组、音响主机、汽车抬头

显示

•

具有符合 AEC-Q100 标准的下列特性：

•

USB 充电

一般电池供电应用

空白

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

–

器件 HBM ESD 分类等级 H1C

器件 CDM ESD 分类等级 C4A

3 说明

•

4V 至 36V 的输入范围

2.5A 持续输出电流

集成同步整流

LMR23625-Q1 SIMPLE SWITCHER^®是一款简便易用

的 36V、2.5A 同步降压稳压器。该器件具有 4V 至

36V 的宽输入范围，适用于从工业到汽车各类应用中

非稳压电源的电压调节。采用峰值电流模式控制来实现

简单控制环路补偿和逐周期电流限制。其静态电流低至

75µA，因此适用于电池供电类系统。内部环路补偿意

味着用户不用承担设计环路补偿组件的枯燥工作。这样

还能够最大限度地减少外部元件数。该器件还具有固定

频率强制脉冲宽度调制模式 (FPWM) 模式选项，可在

轻载时实现较小的输出电压纹波。该器件的扩展系列产

品能够以引脚到引脚兼容的封装提供 1A (LMR23610-

Q1)、1.5A (LMR23615-Q1) 和 3A (LMR23630-Q1) 负

载电流选项，从而可以实现简单且最佳的 PCB 布局。

利用精密使能端输入可以简化稳压器控制和系统电源定

序。保护特性包括逐周期电流限制、间断模式短路保

护和过多功率耗散而引起的热关断。

最短导通时间：60ns

内置补偿功能，便于使用

2.1MHz 固定开关频率

在轻负载条件下，有脉频调制 (PFM) 和强制脉宽调

制 (PWM) 两种模式可供选项

•

与外部时钟频率同步

对于 PFM 选项，无负载条件下的静态电流为 75µA

电源正常选项

软启动至预偏置负载

支持高占空比运行模式

具有间断模式的输出短路保护

8 引脚 HSOIC 和 12 引脚 WSON 可湿侧面，具有

PowerPAD™封装选项

使用 LMR23625-Q1 并借助 WEBENCH^®电源设计

器创建定制设计

•

器件信息⁽¹⁾

器件型号

封装

HSOIC (8)

WSON (12)

封装尺寸（标称值）

4.90mm × 3.90mm

3.00mm x 3.00mm

LMR23625-Q1

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化原理图

效率与负载间的关系，V_IN= 12V，PFM 选项

V_INup to 36 V

C_IN

100

VIN

BOOT

EN/SYNC

AGND

C_BOOT

V_OUT

R_FBT

C_OUT

R_FBB

VCC

C_VCC

V_OUT= 5 V

V_OUT= 3.3 V

PGND

0.0001

0.001

0.01

0.1

I_OUT(A)

D000

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAR5

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

8.3 Feature Description................................................. 11

8.4 Device Functional Modes........................................ 17

Application and Implementation ........................ 18

9.1 Application Information............................................ 18

9.2 Typical Applications ................................................ 18

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison ............................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions ...................... 4

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 5

7.6 Timing Characteristics............................................... 6

7.7 Switching Characteristics.......................................... 7

7.8 Typical Characteristics.............................................. 8

Detailed Description ............................................ 10

8.1 Overview ................................................................. 10

8.2 Functional Block Diagram ....................................... 10

10 Power Supply Recommendations ..................... 25

11 Layout................................................................... 25

11.1 Layout Guidelines ................................................. 25

11.2 Layout Examples................................................... 27

12 器件和文档支持 ..................................................... 28

12.1 器件支持................................................................ 28

12.2 接收文档更新通知 ................................................. 28

12.3 社区资源................................................................ 28

12.4 商标....................................................................... 28

12.5 静电放电警告......................................................... 28

12.6 Glossary................................................................ 28

13 机械、封装和可订购信息....................................... 28

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (April 2017) to Revision B

Page

•

在 12 引脚 WSON 中添加了“可湿”.......................................................................................................................................... 1

删除了“汽车电池稳压、工业电源、电信和数据通信系统”并修改了首页“应用”中措辞 ............................................................ 1

对 WSON 封装器件的 RTM 版本进行了编辑性更改............................................................................................................... 1

Revising the title for WSON Pin Configuration and Functions to be "12-Pin WSON with PGOOD" ..................................... 3

Updated the WSON Pin Functions Title to "WSON with PGOOD" ........................................................................................ 3

Updating the ESD Ratings to include WSON ESD numbers ................................................................................................ 4

Updating the Electrical Characteristic Table EN Pin to EN/SYNC Pin................................................................................... 5

Adding WSON Only to PGOOD Electrical Characteristic Table ........................................................................................... 5

Adding WSON Peak and Valley Inductor Current limit row ................................................................................................... 6

Adding WSON High Side and Low Side MOSFET ON-resistance ........................................................................................ 6

Changes from Original (December 2016) to Revision A

Page

•

已更改更改了第 1 页中的效率图；添加了 WEBENCH 链接.................................................................................................. 1

Changed the value of HBM to ±2000 from ±2500.................................................................................................................. 4

Changed this efficiency graph ................................................................................................................................................ 8

Updated efficiency graphs ..................................................................................................................................................... 8

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

5 Device Comparison

Table 1. Package Comparison

PACKAGE

PART NUMBER

LMR23625CQDDARQ1

FIXED 2.1 MHz

POWER GOOD

FPWM

Yes

SOIC (8)

LMR23625CFQDDARQ1

LMR23625CFPQDRRRQ1

Yes

WSON (12)

Yes

6 Pin Configuration and Functions

DDA Package

8-Pin SOIC

Top View

DRR Package

12-Pin WSON with PGOOD

Top View

BOOT

VCC

PGND

VIN

PGND

VIN

BOOT

VCC

PAD

VIN

AGND

EN/

SYNC

EN/SYNC

PGOOD

AGND

Pin Functions

(1)

I/O

DESCRIPTION

WSON with

PGOOD

NAME

SOIC

Switching output of the regulator. Internally connected to both power MOSFETs.

Connect to power inductor.

1, 2

Bootstrap capacitor connection for high-side driver. Connect a high-quality 470-nF

capacitor from BOOT to SW.

BOOT

Internal bias supply output for bypassing. Connect a 2.2-μF, 16-V or higher capacitance

bypass capacitor from this pin to AGND. Do not connect external loading to this pin.

Never short this pin to ground during operation.

VCC

Feedback input to regulator, connect the feedback resistor divider tap to this pin.

Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail

or other DC voltage no higher than 12 V.

PGOOD

N/A

Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float.

Adjust the input undervoltage lockout with two resistors. The internal oscillator can be

synchronized to an external clock by coupling a positive pulse into this pin through a

small coupling capacitor. See EN/SYNC for detail.

EN/SYNC

Analog ground pin. Ground reference for internal references and logic. Connect to

system ground.

AGND

VIN

9, 10

Input supply voltage.

Power ground pin, connected internally to the low side power FET. Connect to system

ground, PAD, AGND, ground pins of C_INand C_OUT. Path to C_INmust be as short as

possible.

PGND

Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation

path of the die. Must be used for heat sinking to ground plane on PCB.

PAD

N/A

Not for use. Leave this pin floating.

(1) A = Analog, P = Power, G = Ground.

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)

(1)

PARAMETER

VIN to PGND

MIN

–0.3

–5.5

–0.3

–1

MAX

UNIT

V_IN+ 0.3

4.5

EN/SYNC to AGND

FB to AGND

Input voltages

PGOOD to AGND

AGND to PGND

0.3

SW to PGND

V_IN+ 0.3

SW to PGND less than 10-ns transients

BOOT to SW

–5

Output voltages

–0.3

–40

–65

5.5

(2)

VCC to AGND

4.5

Junction temperature, T_J

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.

7.2 ESD Ratings

VALUE

±2000

±2500

±1000

±750

UNIT

(1)

Human-body model (HBM) for SOIC

Human-body model (HBM) for WSON with PGOOD

Charged-device model (CDM) for SOIC

V_(ESD)

Electrostatic discharge

Charged-device model (CDM) for WSON with PGOOD

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)

(1)

MIN

MAX

UNIT

VIN

EN/SYNC

–5

–0.3

Input voltage

1.2

PGOOD

Input current

PGOOD pin current

Output voltage, V_OUT

Output current, I_OUT

2.5

125

Operating junction temperature, T_J

–40

°C

(1) Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensured specific

performance limits. For specified specifications, see Electrical Characteristics.

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

7.4 Thermal Information

LMR23625-Q1

THERMAL METRIC⁽¹⁾⁽²⁾

DDA (SOIC)

8 PINS

42.0

DDR (WSON

12 PINS

41.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

5.9

0.3

23.4

16.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

45.8

39.1

ψ_JB

3.6

3.4

R_θJC(bot)

23.4

16.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Determine power rating at a specific ambient temperature (T_A) with a maximum junction temperature (T_J) of 125°C, which is illustrated in

Recommended Operating Conditions section.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

PARAMETER

POWER SUPPLY (VIN PIN)

V_INOperation input voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

3.3

2.9

3.9

3.5

Rising threshold

3.7

3.3

VIN_UVLO Undervoltage lockout thresholds

Falling threshold

I_SHDN

I_Q

Shutdown supply current

V_EN= 0 V, V_IN= 12 V, T_J= –40°C to 125°C

μA

Operating quiescent current (non-

switching)

V_IN=12 V, V_FB= 1.1 V, T_J= –40°C to 125°C, PFM

mode

ENABLE (EN/SYNC PIN)

V_{EN_H}

Enable rising threshold voltage

1.4

0.4

1.55

0.4

1.7

V_{EN_HYS}

V_WAKE

Enable hysteresis voltage

Wake-up threshold

V_IN= 4 V to 36 V, V_EN= 2 V

V_IN= 4 V to 36 V, V_EN= 36 V

100

μA

I_EN

Input leakage current at EN pin

VOLTAGE REFERENCE (FB PIN)

V_IN= 4 V to 36 V, T_J= 25°C

V_IN= 4 V to 36 V, T_J= –40°C to 125°C

V_FB= 1 V

0.985

0.98

1.015

1.02

V_REF

Reference voltage

I_{LKG_FB}

Input leakage current at FB pin

POWER GOOD (PGOOD PIN) WSON Only

Power-good flag overvoltage

tripping threshold

V_{PG_OV}

% of reference voltage

104% 107% 110%

Power-good flag undervoltage

tripping threshold

V_{PG_UV}

92%

94% 96.5%

V_{PG_HYS}

Power-good flag recovery hysteresis

1.5%

1.5

Minimum V_INfor valid PGOOD

output

V_{IN_PG_MIN}

50 μA pullup to PGOOD pin, V_EN= 0 V, T_J= 25°C

50 μA pullup to PGOOD pin, V_IN= 1.5 V, V_EN= 0 V

0.4

V_{PG_LOW}

PGOOD low level output voltage

0.5 mA pullup to PGOOD pin, V_IN=13.5 V,

V_EN= 0 V

0.4

INTERNAL LDO (VCC PIN)

V_CC

Internal LDO output voltage

4.1

Rising threshold

Falling threshold

2.8

2.4

3.2

2.8

3.6

3.2

VCC undervoltage lockout

thresholds

VCC_UVLO

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT LIMIT

HSOIC package

WSON package

HSOIC package

WSON package

3.6

4.0

2.8

2.9

4.8

5.5

6.2

I_{HS_LIMIT}

Peak inductor current limit

6.6

3.5

4.6

I_{LS_LIMIT}

Valley inductor current limit

Zero cross current limit

3.6

4.2

I_{L_ZC}

–0.04

Negative current limit (FPWM

option)

I_{L_NEG}

–2.7

–2

–1.3

INTEGRATED MOSFETS

R_{DS_ON_HS}High-side MOSFET ON-resistance

HSOIC package, V_IN= 12 V, I_OUT= 1 A

WSON package, V_IN= 12 V, I_OUT= 1 A

HSOIC package V_IN= 12 V, I_OUT= 1 A

WSON package, V_IN= 12 V, I_OUT= 1 A

185

160

105

mΩ

R_{DS_ON_LS}

Low-side MOSFET ON-resistance

THERMAL SHUTDOWN

T_SHDNThermal shutdown threshold

T_HYSHysteresis

162

170

178

°C

7.6 Timing Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

HICCUP MODE

Number of cycles that LS current limit is

tripped to enter hiccup mode

(1)

N_OC

Cycles

SOIC package

T_OC

Hiccup retry delay time

WSON package

SOFT START

T_SS

SOIC package

Internal soft-start time. The time of internal

reference to increase from 0 V to 1 V

WSON package

POWER GOOD

T_{PGOOD_RISE}

Power-good flag rising transition deglitch

delay

150

μs

T_{PGOOD_FALL}

Power-good flag falling transition deglitch

delay

(1) Specified by design.

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

7.7 Switching Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

SW (SW PIN)

f_SW

Default switching frequency

Minimum turnon time

1785

2100

2415 kHz

T_{ON_MIN}

(1)

T_{OFF_MIN}

Minimum turnoff time

100

SYNC (EN/SYNC PIN)

f_SYNC

SYNC frequency range

200

2.8

2200 kHz

Amplitude of SYNC clock AC signal

(measured at SYNC pin)

V_SYNC

5.5

T_{SYNC_MIN}

Minimum sync clock ON and OFF time

100

(1) Specified by design.

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 2100 kHz, L = 2.2 µH, C_OUT= 47 µF, T_A= 25°C.

100

PFM, V_IN= 8 V

PFM, V_IN= 12 V

PFM, V_IN= 24 V

FPWM, V_IN= 8 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

PFM, V_IN= 12 V

PFM, V_IN= 24 V

FPWM, V_IN= 8 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

0.0001

0.001

0.01

0.1

0.0001

0.001

0.01

0.1

I_OUT(A)

D002

D001

f_SW= 2100 kHz

V_OUT= 3.3 V

f_SW= 2100 kHz

V_OUT= 5 V

Figure 2. Efficiency vs Load Current

Figure 1. Efficiency vs Load Current

100

PFM, V_IN= 8 V

PFM, V_IN= 12 V

PFM, V_IN= 24 V

PFM, V_IN= 36 V

FPWM, V_IN= 8 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

FPWM, V_IN= 36 V

PFM, V_IN= 12 V

PFM, V_IN= 24 V

PFM, V_IN= 36 V

FPWM, V_IN= 8 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

FPWM, V_IN= 36 V

0.0001

0.001

0.01

0.1

0.0001

0.001

0.01

0.1

I_OUT(A)

D003

D004

f_SW= 1000 kHz

(Sync)

V_OUT= 5 V

f_SW= 1000 kHz

(Sync)

V_OUT= 3.3 V

Figure 3. Efficiency vs Load Current

Figure 4. Efficiency vs Load Current

5.08

5.06

5.04

5.02

5.01

V_IN= 8 V

V_IN= 12 V

V_IN= 24 V

V_IN= 8 V

V_IN= 12 V

V_IN= 24 V

4.99

4.98

4.97

4.96

4.95

4.98

4.96

0.5

1.5

2.5

0.5

1.5

2.5

I_OUT(A)

D005

D006

PFM Option

V_OUT= 5 V

Figure 5. Load Regulation

FPWM Option

V_OUT= 5 V

Figure 6. Load Regulation

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 2100 kHz, L = 2.2 µH, C_OUT= 47 µF, T_A= 25°C.

5.5

3.6

3.3

4.5

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 1.5 A

I_OUT= 2.0 A

I_OUT= 2.5 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 1.5 A

I_OUT= 2.0 A

I_OUT= 2.5 A

2.7

3.5

2.4

4.5

5.5

3.3

3.5

3.7

3.9

4.1

4.3

4.5

V_IN(V)

D007

D008

V_OUT= 5 V

V_OUT= 3.3 V

Figure 8. Dropout Curve

Figure 7. Dropout Curve

3.67

3.66

3.65

3.64

3.63

3.62

3.61

-50

100

150

-50

100

150

Temperature (°C)

D008

D009

V_IN= 12 V

V_FB= 1.1 V

Figure 9. I_Qvs Junction Temperature

Figure 10. VIN UVLO Rising Threshold vs Junction

Temperature

5.5

0.425

LS Limit

HS Limit

0.42

0.415

0.41

4.5

3.5

-50

100

150

-50

100

150

Temperature (°C)

D010

D011

V_IN= 12 V

Figure 11. VIN UVLO Hysteresis vs Junction Temperature

Figure 12. HS and LS Current Limit vs Junction

Temperature

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

8 Detailed Description

8.1 Overview

The LMR23625-Q1 SIMPLE SWITCHER^®regulator is an easy-to-use synchronous step-down DC-DC converter

operating from a 4-V to 36-V supply voltage. It is capable of delivering up to 2.5-A, DC-load current with good

thermal performance in a small solution size. An extended family is available, for both the SOIC and WSON

packages, in multiple current options from 1 A to 3 A in pin-to-pin compatible packages.

The LMR23625-Q1 employs fixed-frequency peak-current-mode control. The device enters PFM mode at light

load to achieve high efficiency. A user-selectable FPWM option is provided to achieve low output voltage ripple,

tight output voltage regulation, and constant switching frequency. The device is internally compensated, which

reduces design time and requires few external components. The LMR23625-Q1 is capable of synchronization to

an external clock within the range of 200 kHz to 2.2 MHz.

Additional features such as precision enable, power-good flag, and internal soft-start provide a flexible and easy

to use solution for a wide range of applications. Protection features include thermal shutdown, VIN and VCC

undervoltage lockout (UVLO), cycle-by-cycle current limit, and hiccup-mode short-circuit protection.

The family requires very few external components and has a pinout designed for simple, optimum PCB layout.

8.2 Functional Block Diagram

VCC

EN/SYNC

SYNC Signal

SYNC

VCC

LDO

VIN

Detector

Enable

Precision

Enable

CBOOT

Internal

HS I Sense

REF

TSD

UVLO

(PGOOD)

PWM CONTROL LOGIC

PFM

Detector

OV/UV

Detector

Slope

Comp

Freq

Foldback

Zero

Cross

HICCUP

Detector

AGND

SYNC Signal

Oscillator

LS I Sense

PGND

LMR23625-Q1

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8.3 Feature Description

8.3.1 Fixed-Frequency Peak-Current-Mode Control

The following operating description of the LMR23625-Q1 refer to the Functional Block Diagram and to the

waveforms in Figure 13. LMR23625-Q1 is a step-down synchronous buck regulator with integrated high-side

(HS) and low-side (LS) switches (synchronous rectifier). The LMR23625-Q1 supplies a regulated output voltage

by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time, the

SW pin voltage swings up to approximately V_IN, and the inductor current i_Lincrease with linear slope (V_IN– V_OUT

)

/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through

dead time. Inductor current discharges through the LS switch with a slope of –V_OUT/ L. The control parameter of

a buck converter is defined as duty cycle D = t_ON/ T_SW, where t_ONis the high-side switch ON time and T_SWis the

switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In

an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage: D = V_OUT/ V_IN.

V_SW

D = t_ON/ T_SW

V_IN

t_ON

t_OFF

-V_D

T_SW

i_L

I_LPK

I_OUT

Di_L

Figure 13. SW Node and Inductor Current Waveforms in

Continuous Conduction Mode (CCM)

The LMR23625-Q1 employs fixed-frequency peak-current-mode control. A voltage feedback loop is used to get

accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak

inductor current is sensed from the high-side switch and compared to the peak current threshold to control the

ON-time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer

external components, makes it easy to design, and provides stable operation with almost any combination of

output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load

condition, the LMR23625-Q1 operates in PFM mode to maintain high efficiency (PFM option) or in FPWM mode

for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM option).

8.3.2 Adjustable Output Voltage

A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating

temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI

recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the low-

side resistor R_FBBfor the desired divider current and use Equation 1 to calculate high-side R_FBT. R_FBTin the

range from 10 kΩ to 100 kΩ is recommended for most applications. A lower R_FBTvalue can be used if static

loading is desired to reduce V_OUToffset in PFM operation. Lower R_FBTreduces efficiency at very light load. Less

static current goes through a larger R_FBTand might be more desirable when light load efficiency is critical. R_FBT

larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise. Larger

R_FBTvalue requires more carefully designed feedback path on the PCB. The tolerance and temperature variation

of the resistor dividers affect the output voltage regulation.

LMR23625-Q1

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www.ti.com.cn

Feature Description (continued)

OUT

FBT

FBB

Figure 14. Output Voltage Setting

V_OUT- V_REF

R_FBT

ìR_FBB

V_REF

(1)

8.3.3 EN/SYNC

The voltage on the EN pin controls the ON or OFF operation of LMR23625-Q1. A voltage less than 1 V (typical)

shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator. The EN pin is

an input and cannot be left open or floating. The simplest way to enable the operation of the LMR23625-Q1 is to

connect the EN to V_IN. This allows self-start-up of the LMR23625-Q1 when V_INis within the operation range.

Many applications benefit from the employment of an enable divider R_ENTand R_ENB(Figure 15) to establish a

precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility

power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,

such as a battery discharge level. An external logic signal can also be used to drive EN input for system

sequencing and protection.

VIN

R_ENT

EN/SYNC

R_ENB

Figure 15. System UVLO by Enable Divider

The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can

be synchronized by AC coupling a positive edge into the EN pin. The AC-coupled peak-to-peak voltage at the EN

pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse

detector, and the minimum SYNC clock ON- and OFF-time must be longer than 100 ns (typical). A 3.3-V or a

higher amplitude pulse signal coupled through a 1-nF capacitor C_SYNCis a good starting point. Keeping R_ENT//

R_ENB(R_ENTparallel with R_ENB) in the 100-kΩ range is a good choice. R_ENTis required for this synchronization

circuit, but R_ENBcan be left unmounted if system UVLO is not needed. LMR23625-Q1 switching action can be

synchronized to an external clock from 200 kHz to 2.2 MHz. Figure 17 and Figure 18 show the device

synchronized to an external system clock.

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Feature Description (continued)

VIN

R_ENT

C_SYNC

EN/SYNC

R_ENB

Clock

Source

Figure 16. Synchronize to External Clock

Figure 17. Synchronizing in PWM Mode

Figure 18. Synchronizing in PFM Mode

8.3.4 VCC, UVLO

The LMR23625-Q1 integrates an internal LDO to generate V_CCfor control circuitry and MOSFET drivers. The

nominal voltage for V_CCis 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place

high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible

to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded or shorted

to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23625-Q1

device.

VCC UVLO prevents the LMR23625-Q1 from operating until the V_CCvoltage exceeds 3.2 V (typical). The VCC

UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to temporary V_INdrops.

8.3.5 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions

Minimum ON-time, T_{ON_MIN}, is the smallest duration of time that the HS switch can be on. T_{ON_MIN}is typically 60

ns in the LMR23625-Q1. Minimum OFF-time, T_{OFF_MIN}, is the smallest duration that the HS switch can be off.

T_{OFF_MIN}is typically 100 ns in the LMR23625-Q1. In CCM operation, T_{ON_MIN}and T_{OFF_MIN}limit the voltage

conversion range given a selected switching frequency.

The minimum duty cycle allowed is:

D_MIN= T_{ON_MIN}× f_SW

(2)

(3)

And the maximum duty cycle allowed is:

D_MAX= 1 – T_{OFF_MIN}× f_SW

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Feature Description (continued)

Given fixed T_{ON_MIN}and T_{OFF_MIN}, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LMR23625-Q1, a frequency foldback scheme is employed to extend the maximum duty cycle when

T_{OFF_MIN}is reached. The switching frequency decreases once longer duty cycle is needed under low V_IN

conditions. Wide range of frequency foldback allows the LMR23625-Q1 output voltage stay in regulation with a

much lower supply voltage V_IN. This leads to a lower effective dropout voltage.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size, and efficiency. The maximum operation supply voltage can be found by:

V_OUT

IN_MAX

ì T_{ON_MIN}

(

)

(4)

At lower supply voltage, the switching frequency decreases once T_{OFF_MIN}is tripped. The minimum V_INwithout

frequency foldback can be approximated by:

V_OUT

IN_MIN

1- f

(

ì T_{OFF _MIN}

)

(5)

Taking considerations of power losses in the system with heavy load operation, V_{IN_MAX}is higher than the result

calculated in Equation 4. With frequency foldback, V_{IN_MIN}is lowered by decreased f_SW

2500

2000

1500

1000

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 1.5 A

500

I_OUT= 2.0 A

I_OUT= 2.5 A

4.9

5.3

5.7

6.1

6.5

6.9

7.3 7.7

V_IN(V)

D010

Figure 19. Frequency Foldback at Dropout (V_OUT= 5 V, f_SW= 2100 kHz)

8.3.6 Power Good (PGOOD)

The LMR23625AP has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is

within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault

protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage.

Voltage detected by the PGOOD pin must never exceed 15 V; limit the maximum current into this pin to 1 mA. A

resistor divider pair can be used to divide the voltage down from a higher potential. A typical range of pullup

resistor value is 10 kΩ to 100 kΩ.

When the FB voltage is within the power-good band, +6% above and –6% below the internal reference VREF

typically, the PGOOD switch is turned off, and the PGOOD voltage is pulled up to the voltage level defined by

the pullup resistor or divider. When the FB voltage is outside of the tolerance band, +7% above or –7% below

VREF typically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled low to indicate power bad.

A glitch filter prevents false-flag operation for short excursions in the output voltage, such as during line and load

transients. The values for the various filter and delay times can be found in Typical Characteristics. Power-good

operation can best be understood by reference to Figure 20.

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Feature Description (continued)

V_REF

107%

106%

94%

93%

PGOOD

High

Low

Figure 20. Power-Good Flag

8.3.7 Internal Compensation and C_FF

The LMR23625-Q1 is internally compensated as shown in Functional Block Diagram. The internal compensation

is designed such that the loop response is stable over the entire operating frequency and output voltage range.

Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors.

An external feed-forward capacitor C_FFis recommended to be placed in parallel with the top resistor divider R_FBT

for optimum transient performance.

V_OUT

C_FF

R_FBT

R_FBB

Figure 21. Feed-forward Capacitor for Loop Compensation

The feed-forward capacitor C_FFin parallel with R_FBTplaces an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by:

f_{Z _ CFF}

2pìC_FFìR_FBT

(

)

(6)

An additional pole is also introduced with C_FFat the frequency of:

f_{P _ CFF}

2pìC_FFìR_FBT//R_FBB

(

)

(7)

The zero f_{Z_CFF}adds phase boost at the crossover frequency and improves transient response. The pole f_P-CFF

helps maintaining proper gain margin at frequency beyond the crossover. Table 2 lists the combination of C_OUT

C_FFand R_FBTfor typical applications, designs with similar C_OUTbut R_FBTother than recommended value, adjust

C_FFsuch that (C_FF× R_FBT) is unchanged, and adjust R_FBBsuch that (R_FBT/ R_FBB) is unchanged.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have

different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most C_FF.

Electrolytic capacitors have much larger ESR and the ESR zero frequency would be low enough to boost the

phase up around the crossover frequency. Designs using mostly electrolytic capacitors at the output may not

need any C_FF. See Equation 8

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Feature Description (continued)

f_{Z _ESR}

2pìC

ìESR

(

)

OUT

(8)

The C_FFcreates a time constant with R_FBTthat couples in the attenuate output voltage ripple to the FB node. If

the C_FFvalue is too large, it can couple too much ripple to the FB and affect V_OUTregulation. Therefore, calculate

C_FFbased on output capacitors used in the system. At cold temperatures, the value of C_FFmight change based

on the tolerance of the chosen component. This may reduce its impedance and ease noise coupling on the FB

node. To avoid this, more capacitance can be added to the output or the value of C_FFcan be reduced.

8.3.8 Bootstrap Voltage (BOOT)

The LMR23625-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and

SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the

high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is

0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16V or

higher for stable performance over temperature and voltage.

8.3.9 Overcurrent and Short-Circuit Protection

The LMR23625-Q1 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and

valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.

High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See the

Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum-

peak-current threshold I_{HS_LIMIT}, which is constant. So the peak-current limit of the high-side switch is not affected

by the slope compensation and remains constant over the full duty-cycle range.

The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor

current begins to ramp down. The LS switch is not turned OFF at the end of a switching cycle if its current is

above the LS current limit I_{LS_LIMIT}. The LS switch is kept ON so that inductor current keeps ramping down, until

the inductor current ramps below the LS current limit I_{LS_LIMIT}. The LS switch is then turned OFF, and the HS

switch is turned on after a dead time. This is somewhat different than the more typical peak-current limit and

results in Equation 9 for the maximum load current.

V - V

(

)

V_OUT

OUT

I_{OUT _MAX}= I_{LS _LIMIT}

2ì f_SWìL

(9)

If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup current

protection mode is activated. In hiccup mode the regulator is shut down and kept off for 5 ms typically before the

LMR23625-Q1 tries to start again. If overcurrent or short-circuit fault condition still exists, hiccup repeats until the

fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,

prevents overheating and potential damage to the device.

For FPWM option, the inductor current is allowed to go negative. If this current exceeds I_{L_NEG}, the LS switch is

turned off until the next clock cycle. This is used to protect the LS switch from excessive negative current.

8.3.10 Thermal Shutdown

The LMR23625-Q1 provides an internal thermal shutdown to protect the device when the junction temperature

exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature

falls below 155°C (typical), the device reinitiates the power-up sequence controlled by the internal soft-start

circuitry.

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LMR23625-Q1. When V_ENis below 1 V (typical), the

device is in shutdown mode. The LMR23625-Q1 also employs VIN and VCC UVLO protection. If V_INor V_CC

voltage is below their respective UVLO level, the regulator is turned off.

8.4.2 Active Mode

The LMR23625-Q1 is in active mode when V_ENis above the precision enable threshold, V_INand V_CCare above

their respective UVLO level. The simplest way to enable the LMR23625-Q1 is to connect the EN pin to VIN pin.

This allows self startup when the input voltage is in the operating range: 4 V to 36 V. See VCC, UVLO and

EN/SYNC for details on setting these operating levels.

In active mode, depending on the load current, the LMR23625-Q1 is in one of four modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple (for both PFM and FPWM options).

2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation (only for PFM option).

3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for

PFM option).

4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for

FPWM option).

8.4.3 CCM Mode

CCM operation is employed in the LMR23625-Q1 when the load current is higher than half of the peak-to-peak

inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in

this mode and the maximum output current of 2.5 A can be supplied by the LMR23625-Q1.

8.4.4 Light Load Operation (PFM Option)

For PFM option, when the load current is lower than half of the peak-to-peak inductor current in CCM, the

LMR23625-Q1 operates in DCM, also known as diode emulation mode (DEM). In DCM, the LS switch is turned

off when the inductor current drops to I_{L_ZC}(–40 mA typical). Both switching losses and conduction losses are

reduced in DCM, compared to forced PWM operation at light load.

At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum

HS switch ON-time (t_{ON_MIN}) or the minimum peak inductor current I_{PEAK_MIN}(300 mA typical) is reached, the

switching frequency decreases to maintain regulation. In PFM, switching frequency is decreased by the control

loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM

operation due to less frequent switching actions. The external clock synchronizing is not valid when LMR23625-

Q1 enters into PFM mode.

8.4.5 Light Load Operation (FPWM Option)

For FPWM option, LMR23625-Q1 is locked in PWM mode at full load range. This operation is maintained, even

at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light

load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In

this mode, a negative current limit of I_{L_NEG}is imposed to prevent damage to the regulators low side FET. When

in FPWM mode the converter synchronizes to any valid clock signal on the EN/SYNC input.

LMR23625-Q1

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www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMR23625-Q1 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a

lower DC voltage with a maximum output current of 2.5 A. The following design procedure can be used to select

components for the LMR23625-Q1. Alternately, the WEBENCH software may be used to generate complete

designs. When generating a design, the WEBENCH software utilizes iterative design procedure and accesses

comprehensive databases of components. See Custom Design With WEBENCH® Tools and ti.com for more

details.

9.2 Typical Applications

The LMR23625-Q1 only requires a few external components to convert from a wide voltage-range supply to a

fixed-output voltage. Figure 22 shows a basic schematic.

V_IN12 V

C_BOOT

BOOT

VIN

0.1 ꢀF

V_OUT

5 V/2.5 A

C_IN

10 ꢀF

2.2 ꢀH

EN/

SYNC

PAD

C_FF

18 pF

R_FBT

88.7 kΩ

C_OUT

33 ꢀF

R_FBB

22.1 kΩ

C_VCC

2.2 ꢀF

VCC

PGND

AGND

Figure 22. LMR23625-Q1 Application Circuit

The external components have to fulfill the needs of the application, but also the stability criteria of the device

control loop. Table 2 can be used to simplify the output filter component selection.

Table 2. L, C_OUTand C_FFTypical Values

(1)

(2)

f_SW(kHz)

2100

V_OUT(V)

L (µH)

2.2

C_OUT(µF)

C_FF(pF)⁽³⁾

R_FBT(kΩ)⁽⁴⁾

3.3

2100

2.2

88.7

(1) Inductance value is calculated based on V_IN= 20 V.

(2) All the C_OUTvalues are after derating. Add more when using ceramic capacitors.

(3) High ESR C_OUTwill give enough phase boost and C_FFnot needed.

(4) For designs with R_FBTother than recommended value, please adjust C_FFsuch that (C_FF× R_FBT) is unchanged and adjust R_FBBsuch

that (R_FBT/ R_FBB) is unchanged.

9.2.1 Design Requirements

Detailed design procedure is described based on a design example. For this design example, use the

parameters listed in Table 3 as the input parameters.

Table 3. Design Example Parameters

DESIGN PARAMETER

EXAMPLE VALUE

LMR23625-Q1

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ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

Table 3. Design Example Parameters (continued)

Input voltage, V_IN

Output voltage, V_OUT

12 V typical, range from 8 V to 28 V

5 V

2.5 A

Maximum output current I_{O_MAX}

Transient response 0.2 A to 2.5 A

Output voltage ripple

50 mV

400 mV

2100 kHz

Input voltage ripple

Switching frequency f_SW

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23625-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Output Voltage Setpoint

The output voltage of LMR23625-Q1 is externally adjustable using a resistor divider network. The divider network

is comprised of top feedback resistor R_FBTand bottom feedback resistor R_FBB. Equation 10 is used to determine

the output voltage:

V_OUT- V_REF

R_FBT

ìR_FBB

V_REF

(10)

Choose the value of R_FBBto be 22.1 kΩ. With the desired output voltage set to 5 V and the V_REF= 1 V, the R_FBB

value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.

9.2.2.3 Switching Frequency

The default switching frequency of the LMR23625-Q1 is 2100 kHz. For other switching frequencies, the device

must be synchronized to an external clock, see EN/SYNC for more details.

9.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The

inductance is based on the desired peak-to-peak ripple current Δi_L. Since the ripple current increases with the

input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use

Equation 12 to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the

amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of

K_INDis 20% to 40%. During an instantaneous short or over current operation event, the RMS and peak inductor

current can be high. The inductor current rating must be higher than the current limit of the device.

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www.ti.com.cn

V_OUTì V

- V_OUT

(

)

IN_MAX

Di_L=

V_{IN_MAX}ìL ì f_SW

(11)

(12)

- V_OUT

V_OUT

IN_MAX

L_MIN

I_OUTìK_IND

V_{IN_MAX}ì f_SW

In general, it is preferable to choose lower inductance in switching power supplies, because it usually

corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low

of an inductance can generate too large of an inductor current ripple such that over current protection at the full

load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor

current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode

control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple

improves the comparator signal to noise ratio.

For this design example, choose K_IND= 0.4, the minimum inductor value is calculated to be 1.9 µH. Choose the

nearest standard 2.2-μH ferrite inductor with a capability of 3.5-A RMS current, and 6-A saturation current.

9.2.2.5 Output Capacitor Selection

Choose the output capacitor(s), C_OUT, with care since it directly affects the steady-state output-voltage ripple,

loop stability, and the voltage over/undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going

through the ESR of the output capacitors:

DV_{OUT_ESR}= Di_LìESR = K_INDìI_OUTìESR

(13)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Di_L

K_INDìI_OUT

DV_{OUT _C}

8ì f ìC_OUT

(

)

(

)

(14)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,

output capacitors provide the required charge before the inductor current can slew up to the appropriate level.

The regulator control loop usually needs four or more clock cycles to respond to the output voltage droop. The

output capacitance must be large enough to supply the current difference for four clock cycles to maintain the

output voltage within the specified range. Equation 15 shows the minimum output capacitance needed for

specified output undershoot. When a sudden large load decrease occurs, the output capacitors absorb energy

stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum

capacitance required to keep the voltage overshoot within a specified range.

4ì I_OH-I_OL

(

)

C_OUT

f_SWì V_US

(15)

I_OH²-I_OL

C_OUT

(V_OUT+ V_OS)²- V_OUT

where

•

K_IND= Ripple ratio of the inductor ripple current (Δi_L/ I_OUT

I_OL= Low level output current during load transient

I_OH= High level output current during load transient

V_US= Target output voltage undershoot

)

V_OS= Target output voltage overshoot

(16)

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR}= ΔV_{OUT_C}= 50 mV and chose

K_IND= 0.4. Equation 13 yields ESR no larger than 50 mΩ and Equation 14 yields C_OUTno smaller than 1.2 μF.

For the target over/undershoot range of this design, V_US= V_OS= 5% × V_OUT= 250 mV. The C_OUTcan be

calculated to be no smaller than 17.5 μF and 5.3 μF by Equation 15 and Equation 16 respectively. Consider of

derating, one 33-μF, 16-V ceramic capacitor with 5-mΩ ESR is used.

9.2.2.6 Feed-Forward Capacitor

The LMR23625-Q1 is internally compensated. Depending on the V_OUTand frequency f_SW, if the output capacitor

C_OUTis dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the

phase boost an external feed-forward capacitor C_FFcan be added in parallel with R_FBT. Choose C_FFis so that

phase margin is boosted at the crossover frequency without C_FF. A simple estimation for the crossover frequency

(f_X) without C_FFis shown in Equation 17, assuming C_OUThas very small ESR, and C_OUTvalue is after derating.

8.32

f_X

V_OUTìC_OUT

(17)

Equation 18 for C_FFwas tested:

C_FF

4pì f_XìR_FBT

(18)

For designs with higher ESR, C_FFis not needed when C_OUThas very high ESR; reduce C_FFcalculated from

Equation 18 with medium ESR. Table 2 can be used as a quick starting point.

For the application in this design example, a 18-pF, 50-V COG capacitor is selected.

9.2.2.7 Input Capacitor Selection

The LMR23625-Q1 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,

depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7

μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is

recommended. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input

voltage. Additionally, some bulk capacitance can be required, especially if the LMR23625-Q1 circuit is not

located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the

voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R ceramic

capacitors are used. For high-frequency filtering place a 0.1-µF capacitor as close as possible to the device pins.

9.2.2.8 Bootstrap Capacitor Selection

Every LMR23625-Q1 design requires a bootstrap capacitor (C_BOOT). The recommended capacitor is 0.1 μF and

rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap

capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

9.2.2.9 VCC Capacitor Selection

The VCC pin is the output of an internal LDO for LMR23625-Q1. To insure stability of the device, place a

minimum of 2.2-μF, 16-V, X7R capacitor from VCC pin to ground.

9.2.2.10 Undervoltage Lockout Setpoint

The system UVLO is adjusted using the external voltage divider network of R_ENTand R_ENB. The UVLO has two

thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the

input voltage is falling. Use Equation 19 to determine the V_INUVLO level.

R_ENT+ R_ENB

= V_ENHì

IN_RISING

R_ENB

(19)

The EN rising threshold (V_ENH) for LMR23625-Q1 is set to be 1.55 V (typical). Choose the value of R_ENBto be

287 kΩ to minimize input current from the supply. If the desired V_INUVLO level is at 6 V, the value of R_ENTcan

be calculated using Equation 20:

≈

’

IN_RISING

R_ENT

-1 ìR

∆

ENB

V_ENH

◊

(20)

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

Equation 20 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by

Equation 21, where EN hysteresis (V_{EN_HYS}) is 0.4 V (typical).

R_ENT+ R_ENB

= V_ENH- V_{EN_HYS}

(

)

IN_FALLING

R_ENB

(21)

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 2100 kHz, L = 2.2 µH, C_OUT= 47 µF, T_A= 25°C.

V_OUT= 5 V

I_OUT= 2.5 A

f_SW= 2100 kHz

V_OUT= 5 V

I_OUT= 100 mA

f_SW= 2100 kHz

Figure 23. CCM Mode

Figure 24. DCM Mode

V_OUT= 5 V

I_OUT= 0 mA

f_SW= 2100 kHz

V_OUT= 5 V

I_OUT= 0 mA

f_SW= 2100 kHz

Figure 25. PFM Mode

Figure 26. FPWM Mode

V_IN= 12 V

V_OUT= 5 V

I_OUT= 2 A

V_IN= 12 V

V_OUT= 5 V

I_OUT= 2 A

Figure 27. Start-Up by V_IN

Figure 28. Start-Up by EN

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 2100 kHz, L = 2.2 µH, C_OUT= 47 µF, T_A= 25°C.

V_IN= 12 V

V_OUT= 5 V

I_OUT= 0.2 A to 2.5

V_OUT= 7 V to 36

V_OUT= 5 V

I_OUT= 2.5 A

A, 100 mA / μs

V, 2 V / μs

Figure 29. Load Transient

Figure 30. Line Transient

V_OUT= 5 V

I_OUT= 2 A to short

V_OUT= 5 V

I_OUT= short to 2 A

Figure 31. Short Protection

Figure 32. Short Recovery

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

10 Power Supply Recommendations

The LMR23625-Q1 is designed to operate from an input voltage supply range between 4 V and 36 V. This input

supply must be able to withstand the maximum input current and maintain a stable voltage. The resistance of the

input supply rail must be low enough that an input current transient does not cause a high enough drop at the

LMR23625-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply

is located more than a few inches from the LMR23625-Q1, additional bulk capacitance may be required in

addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47-μF or 100-μF

electrolytic capacitor is a typical choice.

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB

with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

1. The input bypass capacitor C_INmust be placed as close as possible to the VIN and PGND pins. Grounding

for both the input and output capacitors must consist of localized top side planes that connect to the PGND

pin and PAD.

2. Place bypass capacitors for V_CCclose to the VCC pin and ground the bypass capacitor to device ground.

3. Minimize trace length to the FB pin net. Both feedback resistors, R_FBTand R_FBBmust be located close to the

FB pin. Place C_FFdirectly in parallel with R_FBT. If V_OUTaccuracy at the load is important, make sure V_OUT

sense is made at the load. Route V_OUTsense path away from noisy nodes and preferably through a layer on

the other side of a shielded layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

5. Have a single point ground connection to the plane. Route he ground connections for the feedback and

enable components to the ground plane. This prevents any switched or load currents from flowing in the

analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior.

6. Make V_IN, V_OUTand ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

7. Provide adequate device heat sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125°C.

11.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more EMI is generated. High-frequency ceramic bypass

capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing

ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible, just wide enough to carry the load current

without excessive heating. Short, thick traces or copper pours (shapes) must be used for high-current conduction

path to minimize parasitic resistance. Place the output capacitors close to the V_OUTend of the inductor and

closely grounded to PGND pin and exposed PAD.

Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the

exposed PAD.

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

Layout Guidelines (continued)

11.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and

PGND pins must be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is

connected to the source of the internal LS switch. They must be connected directly to the grounds of the input

and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load

variations. Constrain the PGND trace, as well as VIN and SW traces, to one side of the ground plane. The other

side of the ground plane contains much less noise and must be used for sensitive routes.

TI recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal

path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat

sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground

plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper

thickness for the four layers, starting from the top of 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough

copper thickness provides low current-conduction impedance, proper shielding and lower thermal resistance.

The thermal characteristics of the LMR23625-Q1 are specified using the parameter R_θJA, which characterize the

junction temperature of silicon to the ambient temperature in a specific system. Although the value of R_θJAis

dependent on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use Equation 22:

T_J= P_Dx R_θJA+ T_A

where

•

T_J= junction temperature in °C

P_D= V_IN× I_IN× (1 – efficiency) – 1.1 × I_OUT²× DCR in Watt

DCR = Inductor DC parasitic resistance in Ω

r_θJA= Junction-to-ambient thermal resistance of the device in °C/W

T_A= ambient temperature in °C

(22)

The maximum operating junction temperature of the LMR23625-Q1 is 125°C. R_θJAis highly related to PCB size

and layout, as well as environmental factors such as heat sinking and air flow.

11.1.3 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

C_FFclose to the FB pin, rather than close to the load. The FB pin is the input to the EA, so it is a high impedance

node and very sensitive to noise. Placing the resistor divider and C_FFcloser to the FB pin reduces the trace

length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from

V_OUTto the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the

load to the feedback resistor divider away from the SW node path and the inductor to avoid contaminating the

feedback signal with switch noise, while also minimizing the trace length. This is most important when high-value

resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the

resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane in

between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage

feedback path from EMI noises.

LMR23625-Q1

www.ti.com.cn

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

11.2 Layout Examples

Output Bypass

Capacitor

Output Inductor

Input Bypass

Capacitor

PGND

VIN

BOOT Capacitor

BOOT

VCC

AGND

VCC

Capacitor

EN/

SYNC

UVLO Adjust Resistor

Output Voltage Set

Resistor

Thermal VIA

VIA (Connect to GND Plane)

Figure 33. SOIC Layout

Output

Inductor

Output Bypass

Capacitor

PGND

Input Bypass

Capacitor

BOOT

Capacitor

BOOT

VCC

VIN

VCC

Capacitor

EN/SYNC

AGND

UVLO Adjust

Resistor

PGOOD

Thermal VIA

Output Voltage

Set Resistor

VIA (Connect to GND Plane)

Figure 34. WSON Layout

LMR23625-Q1

ZHCSFR1B –DECEMBER 2016–REVISED MARCH 2018

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 使用 WEBENCH® 工具创建定制设计

请单击此处，使用 LMR23625-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计。

1. 首先键入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMR23625CFPQDRRRQ1

LMR23625CFPQDRRTQ1

LMR23625CFQDDAQ1

LMR23625CFQDDARQ1

LMR23625CQDDAQ1

ACTIVE

WSON

DRR

DDA

3000 RoHS & Green

Level-2-260C-1 YEAR

-40 to 125

362PQ

Samples

250

RoHS & Green

362PQ

ACTIVE SO PowerPAD

NIPDAUAG

F25CFQ

F25CQ

2500 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

LMR23625CQDDARQ1

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMR23625-Q1 :

Catalog : LMR23625

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMR23625CFPQDRRRQ1 WSON

LMR23625CFPQDRRTQ1 WSON

DRR

DDA

3000

250

330.0

180.0

330.0

12.4

12.8

3.3

6.4

3.3

5.2

1.0

2.1

8.0

12.0

LMR23625CFQDDARQ1

2500

PowerPAD

LMR23625CQDDARQ1

DDA

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

PowerPAD

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMR23625CFPQDRRRQ1

LMR23625CFPQDRRTQ1

LMR23625CFQDDARQ1

LMR23625CQDDARQ1

WSON

DRR

DDA

3000

250

367.0

213.0

366.0

367.0

191.0

364.0

38.0

35.0

50.0

SO PowerPAD

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

LMR23625CFQDDAQ1

LMR23625CQDDAQ1

DDA

HSOIC

517

7.87

635

4.25

Pack Materials-Page 3

PACKAGE OUTLINE

DRR0012D

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

1.7 0.1

2.5

2.5 0.1

10X 0.5

0.3

0.2

12X

0.38

0.28

12X

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

4223146/D 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRR0012D

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.7)

12X (0.53)

SYMM

12X (0.25)

SYMM

(2.5)

10X (0.5)

(1)

(R0.05) TYP

(0.6)

(2.87)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL EDGE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223146/D 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DRR0012D

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.47)

12X (0.53)

12X (0.25)

METAL

TYP

(0.675)

SYMM

10X (0.5)

(1.15)

(R0.05) TYP

(0.74)

(2.87)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80.1% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4223146/D 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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重要声明和免责声明

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