LMR23630APDRRT [TI]

SIMPLE SWITCHER® 36V、3A 同步降压转换器 | DRR | 12 | -40 to 125;


型号：	LMR23630APDRRT
厂家：	TEXAS INSTRUMENTS
描述：	SIMPLE SWITCHER® 36V、3A 同步降压转换器 \| DRR \| 12 \| -40 to 125 转换器
文件：	总45页 (文件大小：3301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMR23630

ZHCSF93E –DECEMBER 2015 –REVISED AUGUST 2020

LMR23630 SIMPLE SWITCHER^®36V、3A 同步降压转换器

1 特性

3 说明

• 4V 至36V 的输入电压范围

• 3A 持续输出电流

• 集成同步整流

• 电流模式控制

• 最短导通时间：60ns

• 内置补偿功能，便于使用

• 400kHz 开关频率和可调频率选项

• PFM 和强制PWM 模式选项

• 与外部时钟频率同步

• 对于PFM 选项，无负载条件下的静态电流为75µA

• 软启动至预偏置负载

• 支持高占空比运行模式

• 精密使能输入

• 具有断续模式的输出短路保护

• 过热保护

• 带PowerPAD^™的8 引脚HSOIC 封装

• 带PowerPAD^™的12 引脚WSON 可湿性侧面封装

• 使用LMZM33603 模块缩短产品上市时间

• 使用LMR23625 并借助WEBENCH^®Power

Designer 创建定制设计方案

LMR23630 SIMPLE SWITCHER^®是一款易于使用的

36V、3A 同步降压稳压器，具有 4V 至 36V 的宽输入

电压范围，适用于从非稳压源进行电源调节的各种工业

应用。该器件采用峰值电流模式控制来实现简单控制环

路补偿和逐周期电流限制。它具有 75μA 的静态电

流，因此适用于电池供电型系统。凭借 2μA 的超低关

断电流，可进一步延长电池使用寿命。内部环路补偿意

味着用户不用承担设计环路补偿组件的枯燥工作。这样

还能够最大限度地减少外部元件数。该器件可选用恒定

频率 FPWM 模式，在轻载条件下实现小输出电压纹

波。该器件的扩展系列产品 (HSOIC) 能够以引脚对引

脚兼容的封装（可用于实现简单且优化的 PCB 布局）

提供负载电流为 1A (LMR23610) 和 2.5A (LMR23625)

的选件。利用精密使能端输入可以简化稳压器控制和系

统电源时序。保护特性包括逐周期电流限制、间断模式

短路保护和过多功率耗散而引起的热关断。

器件信息

器件型号⁽¹⁾

LMR23630

封装尺寸（标称值）

4.89mm × 3.90mm

3.00mm × 3.00mm

封装

HSOIC (8)

WSON (12)

2 应用

(1) 如需了解所有不同可用选件的详细器件型号，请参阅数据表末

尾的可订购产品附录。

• 工厂和楼宇自动化系统：PLC CPU、HVAC 控制、

电梯控制

• 资产跟踪

• 通用宽输入电压调节

V_INup to 36 V

100

C_IN

VIN

BOOT

EN/SYNC

AGND

C_BOOT

V_OUT

R_FBT

C_OUT

R_FBB

VCC

C_VCC

PGND

V_OUT= 5 V

V_OUT= 3.3 V

0.0001

简化版原理图

0.001

0.01

0.1

I_OUT(A)

D001

效率与负载间的关系V_IN= 12V，PFM 选项

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAH2

LMR23630

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ZHCSF93E –DECEMBER 2015 –REVISED AUGUST 2020

Table of Contents

8.4 Device Functional Modes..........................................20

9 Application and Implementation..................................21

9.1 Application Information............................................. 21

9.2 Typical Applications.................................................. 21

10 Power Supply Recommendations..............................28

11 Layout...........................................................................28

11.1 Layout Guidelines................................................... 28

11.2 Layout Example...................................................... 29

11.3 Compact Layout for EMI Reduction........................ 29

11.4 Ground Plane and Thermal Considerations............30

11.5 Feedback Resistors................................................ 31

12 Device and Documentation Support..........................32

12.1 Device Support....................................................... 32

12.2 接收文档更新通知................................................... 32

12.3 支持资源..................................................................32

12.4 Trademarks.............................................................32

12.5 静电放电警告.......................................................... 32

12.6 术语表..................................................................... 32

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................4

Pin Functions.................................................................... 5

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................7

7.6 Timing Requirements..................................................9

7.7 Switching Characteristics............................................9

7.8 Typical Characteristics..............................................10

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................13

Information.................................................................... 32

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (February 2018) to Revision E (July 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1

• 向节1 添加了LMZM33630 要点........................................................................................................................ 1

Changes from Revision C (June 2017) to Revision D (February 2018)

Page

• 在应用中将“可编程逻辑控制器电源”更改为“工厂和楼宇自动化系统...”......................................................1

• 删除了“多功能打印机和工业电源”并重新编写了应用.................................................................................... 1

• 将“应用”中的“HVAC 系统”更改为“通用宽输入电压调节”....................................................................... 1

• Added "2.2-µF, 16-V" for VCC pin bypass capacitor ..........................................................................................5

• Change the Max Recommend Operating Condition for Iout to be 3-A from 2.5-A ............................................ 6

• Consolidating all the common EC table characteristic between HSOIC and WSON, for example Operation

Input Voltage, VIN_UVLO, I_ENand Mnimum turn-on time ................................................................................. 7

• Changed Typical Value for VIN_UVLO Rising threshold typical from 3.6-V to 3.7-V and minimum Falling

threshold from 3-V to 2.9-V ................................................................................................................................7

• Changed the operating from "4.5-V" ... to "4-V" in Device Functional Modes ..................................................20

• Changed from V_OUT= 7 V to 36 V to V_IN= 7 V to 36 V on 图9-9 ................................................................... 26

Changes from Revision B (April 2017) to Revision C (June 2017)

Page

• 删除了“汽车电池稳压”且重新编写了应用...................................................................................................... 1

• 添加了“WSON 封装和选项”............................................................................................................................1

• Added Device Comparison Table ...................................................................................................................... 4

• Change EN Abs Max to EN/SYNC Abs Max ..................................................................................................... 6

• Updating ESD Ratings to include HSOIC and WSON .......................................................................................6

• Corrected Equation 17 denominator from "(V_OUTx V_OS)" to "(V_OUT+ V_OS)"....................................................23

• clarified equations Equation 23 and Equation 24 ............................................................................................ 30

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Changes from Revision A (July 2016) to Revision B (April 2017)

Page

• Changed spec from 6.0 to 6.2 for max under Current Limit................................................................................7

• Changed spec from 4.2 to 4.6 for max under Current Limit................................................................................7

Changes from Revision * (December 2015) to Revision A (July 2016)

Page

• 将“产品预发布”更改为“量产数据”，并添加了所有其余部分.......................................................................1

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5 Device Comparison Table

ADJUSTABLE

FIXED 400 kHz FREQUENCY

RESISTOR

PACKAGE

PART NUMBER

POWER GOOD FPWM

LMR23630ADDA

yes

HSOIC (8)

LMR23630AFDDA

LMR23630DRR

yes

WSON (12) (Pin 6 is RT)

LMR23630FDRR

LMR23630APDRR

yes

WSON (12) (Pin 6 is PGOOD)

yes

6 Pin Configuration and Functions

图6-1. DRR Package 12-Pin WSON With RT and Thermal Pad Top View

图6-2. DRR Package 12-Pin WSON With PGOOD and Thermal Pad Top View

PGND

BOOT

VCC

VIN

Thermal Pad

(9)

AGND

EN/SYNC

图6-3. DDA Package 8-Pin HSOIC Top View

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Pin Functions

I/O ⁽¹⁾

DESCRIPTION

HSOI WSON With

WSON With

PGOOD

NAME

Switching output of the regulator. Internally connected to both power

MOSFETs. Connect to power inductor.

1, 2

Boot-strap capacitor connection for high-side driver. Connect a high quality

100nF or 470nF capacitor from BOOT to SW.

BOOT

Internal bias supply output for bypassing. Connect 2.2-µF, 16-V bypass

capacitor from this pin to AGND. Do not connect external loading to this

pin. Never short this pin to ground during operation.

VCC

Feedback input to regulator, connect the midpoint of feedback resistor

divider to this pin.

N/A

Connect a resistor RT from this pin to AGND to program switching

frequency. Leave floating for 400-kHz default switching frequency.

N/A

Open drain output for power-good flag. Use a 10-kΩto 100-kΩpullup

resistor to logic rail or other DC voltage no higher than 12 V.

N/A

PGOOD

Enable input to regulator. High = On, Low = Off. Can be connected to VIN.

Do not float. Adjust the input undervoltage lockout with two resistors. The

internal oscillator can be synchronized to an external clock by coupling a

positive pulse into this pin through a small coupling capacitor. See 节8.3.4

for details.

EN/SYNC

Analog ground pin. Ground reference for internal references and logic.

Connect to system ground.

AGND

VIN

9, 10

Input supply voltage.

Power ground pin, connected internally to the low side power FET.

PGND

Connect to system ground, PAD, AGND, ground pins of C_INand C_OUT

Path to C_INmust be as short as possible.

Low impedance connection to AGND. Connect to PGND on PCB. Major

heat dissipation path of the die. Must be used for heat sinking to ground

plane on PCB.

PAD

N/A

N/A Not for use. Leave this pin floating.

(1) A = Analog, P = Power, G = Ground.

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) ⁽¹⁾

PARAMETER

MIN

–0.3

–5.5

–0.3

–1

MAX

UNIT

VIN to PGND

V_IN+ 0.3

4.5

EN/SYNC to AGND

FB to AGND

Input voltages

RT to AGND

4.5

PGOOD to AGND

AGND to PGND

0.3

SW to PGND

V_IN+ 0.3

SW to PGND less than 10 ns transients

BOOT to SW

–5

Output voltages

5.5

–0.3

–40

–65

4.5⁽²⁾

150

VCC to AGND

T_J

Junction temperature

Storage temperature

°C

T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM) for HSOIC ⁽¹⁾

±2000

Human-body model (HBM) for WSON with RT and

PGOOD⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

Charged-device model (CDM) for HSOIC and WSON RT⁽²⁾

Charged-device model (CDM) for WSON PGOOD⁽²⁾

±1000

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) ⁽¹⁾

MIN

MAX UNIT

VIN

1.2

EN/SYNC

–5

–0.3

Input voltage

PGOOD

Input current

Output voltage

Output current

Temperature

PGOOD pin current

V_OUT

I_OUT

Operating junction temperature, T_J

125

°C

–40

(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits.

For ensured specifications, see 节7.5.

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7.4 Thermal Information

THERMAL METRIC ^{(1) (2)}

DDA (8 PINS) DRR (12 PINS)

UNIT

°C/W

R_θJA

Junction-to-ambient thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (top) thermal resistance

Junction-to-case (bottom) thermal resistance

Junction-to-board thermal resistance

42.0

5.9

41.5

0.3

ψ_JT

23.4

45.8

3.6

16.5

39.1

3.4

ψ_JB

R_θJC(top)

R_θJC(bot)

R_θJB

23.4

16.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Determine power rating at a specific ambient temperature T_Awith a maximum junction temperature (T_J) of 125°C (see 节7.3).

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLY (VIN PIN)

V_IN

Operation input voltage

3.3

2.9

3.9

3.5

VIN_UVLO

Undervoltage lockout thresholds

Rising threshold

3.7

3.3

Falling threshold

V_EN= 0 V, V_IN= 12 V, T_J= –40°C to

125°C

I_SHDN

I_Q

Shutdown supply current

μA

Operating quiescent current (non-

switching)

V_IN=12 V, V_FB= 1.1 V, T_J= –40°C to

125°C, PFM mode

ENABLE (EN/SYNC PIN)

V_{EN_H}

Enable rising threshold voltage

1.4

0.4

1.55

0.4

1.7

V_{EN_HYS}

V_WAKE

Enable hysteresis voltage

Wake-up threshold

μA

V_IN= 4 V to 36 V, V_EN= 2 V

V_IN= 4 V to 36 V, V_EN= 36 V

100

I_EN

Input leakage current at EN pin

VOLTAGE REFERENCE (FB PIN)

V_IN= 4.0 V to 36 V, T_J= 25 °C

V_IN= 4.0 V to 36 V, T_J= –40°C to 125°C

V_FB= 1 V

0.985

0.98

1.015

1.02

V_REF

Reference voltage

I_{LKG_FB}

Input leakage current at FB pin

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Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER GOOD (PGOOD PIN)

Power-good flag overvoltage

tripping threshold

V_{PG_OV}

% of reference voltage

104%

92%

107%

94%

110%

Power-good flag undervoltage

tripping threshold

V_{PG_UV}

% of reference voltage

96.5%

Power-good flag recovery

hysteresis

V_{PG_HY S}

V_{IN_PG_MIN}

1.5%

Minimum V_INfor valid PGOOD

output

50 μA pullup to PGOOD pin, V_EN= 0 V, T_J

= 25°C

1.5

0.4

50 μA pullup to PGOOD pin, V_IN= 1.5 V,

V_EN= 0 V

V_{PG_LOW}

PGOOD low level output voltage

0.5 mA pullup to PGOOD pin, V_IN= 13.5 V,

V_EN= 0 V

INTERNAL LDO (VCC PIN)

V_CC

Internal LDO output voltage

4.1

3.2

2.8

Rising threshold

Falling threshold

2.8

2.4

3.6

3.2

VCC undervoltage lockout

thresholds

VCC_UVLO

CURRENT LIMIT

I_{HS_LIMIT}Peak inductor current limit

HSOIC package

3.8

5.5

6.2

6.6

4.6

4.2

WSON package

HSOIC package

2.9

3.6

I_{LS_LIMIT}

Valley inductor current limit

Zero cross current limit

WSON package

3.6

I_{L_ZC}

HSOIC and WSON package

–0.04

Negative current limit (FPWM

option)

I_{L_NEG}

SOIC and WSON package

–2.7

–2

–1.3

INTEGRATED MOSFETS

R_{DS_ON_HS}High-side MOSFET ON-resistance

SOIC package, V_IN= 12 V, I_OUT= 1 A

WSON package, V_IN= 12 V, I_OUT= 1 A

SOIC package, V_IN= 12 V, I_OUT= 1 A

WSON package, V_IN= 12 V, I_OUT= 1 A

185

160

105

mΩ

R_{DS_ON_LS}

Low-side MOSFET ON-resistance

THERMAL SHUTDOWN

T_SHDNThermal shutdown threshold

T_HYSHysteresis

162

170

178

°C

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7.6 Timing Requirements

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)

MIN

NOM

MAX UNIT

HICCUP MODE

Number of cycles that LS current

(1)

N_OC

Cycles

limit is tripped to enter hiccup mode

SOIC package

T_OC

Hiccup retry delay time

WSON package

SOFT START

SOIC package, the time of internal

reference to increase from 0 V to 1 V

T_SS

Internal soft-start time

WSON package, the time of internal

reference to increase from 0 V to 1 V

POWER GOOD

Power-good flag rising transition

T_{PGOOD_RISE}

150

μs

deglitch delay

Power-good flag falling transition

deglitch delay

T_{PGOOD_FALL}

(1) Ensured by design.

7.7 Switching Characteristics

Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)

PARAMETER

MIN

TYP

MAX UNIT

SW (SW PIN)

T_{ON_MIN}

Minimum turnon time

Minimum turnoff time

WSON package

(1)

T_{OFF_MIN}

100

OSCILLATOR (RT and EN/SYNC PIN)

f_{SW_DEFAULT}Oscillator default frequency

Minimum adjustable frequency

Fixed frequency version or RT pin open

circuit

340

400

460 kHz

150

1750

200

250 kHz

2425 kHz

2200 kHz

R_T= 198 kΩ with 1% accuracy

R_T= 17.8 kΩ with 1% accuracy

f_ADJ

Maximum adjustable frequency

SYNC frequency range

2150

f_SYNC

Amplitude of SYNC clock AC

signal (measured at SYNC pin)

V_SYNC

2.8

5.5

Minimum sync clock ON-time

and OFF-time

T_{SYNC_MIN}

100

(1) Specified by design.

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7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 400 kHz, L = 8.2 µH, C_OUT= 150 µF,

T_A= 25°C.

100

PFM, V_IN= 12 V

PFM, V_IN= 24 V

PFM, V_IN= 36 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

FPWM, V_IN= 36 V

PFM, V_IN= 12 V

PFM, V_IN= 24 V

PFM, V_IN= 36 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

FPWM, V_IN= 36 V

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

D001

D002

f_SW= 400 kHz

V_OUT= 5 V

f_SW= 400 kHz

V_OUT= 3.3 V

图7-1. Efficiency vs Load Current

图7-2. Efficiency vs Load Current

100

PFM, V_IN= 12 V

PFM, V_IN= 24 V

PFM, V_IN= 36 V

FPWM, V_IN= 12 V

PFM, V_IN= 12 V

PFM, V_IN= 24 V

PFM, V_IN= 36 V

FPWM, V_IN= 12 V

FPWM, V_IN= 24 V

FPWM, V_IN= 36 V

FPWM, V_IN= 24 V

FPWM, V_IN= 36 V

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

1E-5

0.0001

0.001

0.01

I_OUT(A)

0.1

D003

D004

f_SW= 200 kHz (Sync)

V_OUT= 5 V

f_SW= 200 kHz (Sync)

V_OUT= 3.3 V

图7-3. Efficiency vs Load Current

图7-4. Efficiency vs Load Current

5.09

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5.015

5.01

5.005

V_IN= 12 V

V_IN= 24 V

V_IN= 36 V

V_IN= 12 V

V_IN= 24 V

V_IN= 36 V

4.99

0.5

1.5

I_OUT(A)

2.5

0.5

1.5

I_OUT(A)

2.5

D005

D004

FPWM Version

V_OUT= 5 V

PFM version

V_OUT= 5 V

图7-6. Load Regulation

图7-5. Load Regulation

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5.5

3.6

3.3

4.5

2.7

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

I_OUT= 0.5 A

I_OUT= 1.0 A

I_OUT= 2.0 A

I_OUT= 3.0 A

3.5

2.4

3.3

4.5

V_IN(V)

5.5

3.5

3.7

3.9

V_IN(V)

4.1

4.3

4.5

D006

D007

V_OUT= 5 V

V_OUT= 3.3 V

图7-7. Dropout Curve

图7-8. Dropout Curve

3.67

3.66

3.65

3.64

3.63

3.62

3.61

-50

Temperature (°C)

100

150

Temperature (°C)

100

150

D008

D009

V_IN= 12 V

V_FB= 1.1 V

图7-10. VIN UVLO Rising Threshold vs Junction

图7-9. I_Qvs Junction Temperature

Temperature

0.425

0.42

5.5

LS Limit

HS Limit

4.5

0.415

3.5

0.41

-50

Temperature (°C)

100

150

Temperature (°C)

100

150

D010

D011

V_IN= 12 V

图7-11. VIN UVLO Hysteresis vs Junction

图7-12. HS and LS Current Limit vs Junction

Temperature

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8 Detailed Description

8.1 Overview

The LMR23630 SIMPLE SWITCHER^®regulator is an easy-to-use synchronous step-down DC-DC converter

operating from 4-V to 36-V supply voltage. The device delivers up to 3-A DC load current with good thermal

performance in a small solution size. For both the HSOIC and WSON packages, an extended family is available

in multiple current options from 1 A to 3 A in pin-to-pin compatible packages.

The LMR23630 employs constant frequency peak-current-mode control. The device enters PFM mode at light

load to achieve high efficiency. A user-selectable FPWM version is provided to achieve low output voltage ripple,

tight output voltage regulation, and constant switching frequency. The switching frequency is 400 kHz for the

fixed-frequency version. For the version which has RT pin, the switching frequency is adjustable from 200 kHz to

2.2 MHz. The device is internally compensated, which reduces design time and requires few external

components. The LMR23630 is capable of synchronization to an external clock within the range of 200 kHz to

2.2 MHz.

Additional features such as precision enable, power-good flag, and internal soft-start provide a flexible and easy-

to-use solution for a wide range of applications. Protection features include thermal shutdown, VIN and VCC

undervoltage lockout, cycle-by-cycle current limit, and hiccup-mode short-circuit protection.

The family requires very few external components and has a pinout designed for simple, optimum PCB layout.

8.2 Functional Block Diagram

VCC

EN/SYNC

SYNC Signal

SYNC

Detector

VCC

Enable

LDO

VIN

Precision

Enable

CBOOT

Internal

HS I Sense

REF

TSD

UVLO

(PGOOD)

PWM CONTROL LOGIC

PFM

Detector

OV/UV

Detector

Slope

Comp

Freq

Foldback

Zero

Cross

HICCUP

Detector

AGND

SYNC Signal

(RT)

Oscillator

LS I Sense

PGND

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8.3 Feature Description

8.3.1 Fixed Frequency Peak Current Mode Control

The following operating description of the LMR23630 refers to 节 8.2 and to the waveforms in 图 8-1. The

LMR23630 is a step-down synchronous buck regulator with integrated high-side (HS) and low-side (LS) switches

(synchronous rectifier). The LMR23630 supplies a regulated output voltage by turning on the HS and LS NMOS

switches with controlled duty cycle. During high-side switch ON-time, the SW pin voltage swings up to

approximately V_IN, and the inductor current i_Lincrease with linear slope (V_IN–V_OUT) / L. When the HS switch is

turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor current

discharges through the LS switch with a slope of –V_OUT/ L. The control parameter of a buck converter is

defined as duty cycle D = t_ON/ T_SW, where t_ONis the high-side switch ON-time and T_SWis the switching period.

The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck

converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the

input voltage: D = V_OUT/ V_IN.

V_SW

D = t_ON/ T_SW

V_IN

t_ON

t_OFF

-V_D

T_SW

i_L

I_LPK

I_OUT

Di_L

图8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LMR23630 employs fixed-frequency peak-current-mode control. A voltage feedback loop is used to get

accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak

inductor current is sensed from the high-side switch and compared to the peak current threshold to control the

ON-time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer

external components, makes it easy to design, and provides stable operation with almost any combination of

output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load

condition, the LMR23630 operates in PFM mode to maintain high efficiency (PFM option) or in FPWM mode for

low output-voltage ripple, tight output-voltage regulation, and constant switching frequency (FPWM option).

8.3.2 Adjustable Frequency

The switching frequency can be programmed for the adjustable-switching-frequency version of LMR23630 by

the impedance R_Tfrom the RT pin to ground. The frequency is inversely proportional to the R_Tresistance. The

RT pin can be left floating and the LMR23630 operates at 400-kHz default switching frequency. The RT pin is not

designed to be shorted to ground. For a desired frequency, typical R_Tresistance can be found by 方程式 1. 表

8-1 gives typical R_Tvalues for a given f_SW

R_T(kΩ) = 40200 / f_SW(kHz) –0.6

(1)

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250

200

150

100

500

1000

1500

2000

2500

Switching Frequency (kHz)

C008

图8-2. RT vs Frequency Curve

表8-1. Typical Frequency Setting RT Resistance

f_SW(kHz)

R_T(kΩ)

200

350

200

115

500

78.7

53.6

39.2

26.1

19.6

17.8

750

1000

1500

2000

2200

8.3.3 Adjustable Output Voltage

A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating

temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI

recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the

lowside resistor RFBB for the desired divider current and use Equation 2 to calculate high-side R_FBT. R_FBTin the

range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static

loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load.

Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical.

However, RFBT larger than 1 MΩis not recommended because it makes the feedback path more susceptible to

noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and

temperature variation of the resistor dividers affect the output voltage regulation.

OUT

FBT

FBB

图8-3. Output Voltage Setting

V_OUT- V_REF

V_REF

R_FBT

ìR_FBB

(2)

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8.3.4 Enable/Sync

The voltage on the EN/SYNC pin controls the ON or OFF operation of LMR23630. A voltage less than 1 V

(typical) shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator. The

EN/SYNC pin is an input and cannot be left open or floating. The simplest way to enable the operation of the

LMR23630 is to connect the EN to V_IN. This allows self-start-up of the LMR23630 when V_INis within the

operation range.

Many applications can benefit from the employment of an enable divider R_ENTand R_ENB(图 8-4) to establish a

precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility

power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,

such as a battery discharge level. An external logic signal can also be used to drive EN input for system

sequencing and protection.

VIN

R_ENT

EN/SYNC

R_ENB

图8-4. System UVLO by Enable Divider

The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can

be synchronized by AC-coupling a positive edge into the EN pin. The AC-coupled peak-to-peak voltage at the

EN pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse

detector, and the minimum SYNC clock ON-time and OFF-time must be longer than 100 ns (typical). A 3.3-V or

a higher amplitude pulse signal coupled through a 1-nF capacitor C_SYNCis a good starting point. Keeping R_ENT//

R_ENB(R_ENTparallel with R_ENB) in the 100 kΩ range is a good choice. R_ENTis required for this synchronization

circuit, but R_ENBcan be left unmounted if system UVLO is not needed. LMR23630 switching action can be

synchronized to an external clock from 200 kHz to 2.2 MHz. 图 8-6 and 图 8-7 show the device synchronized to

an external system clock.

VIN

R_ENT

C_SYNC

EN/SYNC

R_ENB

Clock

Source

图8-5. Synchronize to External Clock

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图8-6. Synchronizing in PWM Mode

图8-7. Synchronizing in PFM Mode

8.3.5 VCC, UVLO

The LMR23630 integrates an internal LDO to generate V_CCfor control circuitry and MOSFET drivers. The

nominal voltage for V_CCis 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place a

high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible

to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, or shorted

to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23630.

VCC undervoltage lockout (UVLO) prevents the LMR23630 from operating until the V_CCvoltage exceeds 3.3 V

(typical). The VCC UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to

temporary V_INdrops.

8.3.6 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions

Minimum ON-time, T_{ON_MIN}, is the smallest duration of time that the HS switch can be on. T_{ON_MIN}is typically 60

ns in the LMR23630. Minimum OFF-time, T_{OFF_MIN}, is the smallest duration that the HS switch can be off.

T_{OFF_MIN}is typically 100 ns in the LMR23630. In CCM operation, T_{ON_MIN}and T_{OFF_MIN}limit the voltage

conversion range given a selected switching frequency.

The minimum duty cycle allowed is:

D_MIN= T_{ON_MIN}× f_SW

(3)

And the maximum duty cycle allowed is:

D_MAX= 1 –T_{OFF_MIN}× f_SW

(4)

Given fixed T_{ON_MIN}and T_{OFF_MIN}, the higher the switching frequency the narrower the range of the allowed duty

cycle. In the LMR23630, a frequency foldback scheme is employed to extend the maximum duty cycle when

T_{OFF_MIN}is reached. The switching frequency decreases once longer duty cycle is needed under low V_IN

conditions. Wide range of frequency foldback allows the LMR23630 output voltage stay in regulation with a

much lower supply voltage V_IN. This leads to a lower effective dropout voltage.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution

size and efficiency. The maximum operation supply voltage can be found by:

V_OUT

IN_MAX

ì T_{ON_MIN}

(

)

(5)

At lower supply voltage, the switching frequency decreases once T_{OFF_MIN}is tripped. The minimum V_INwithout

frequency foldback can be approximated by:

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V_OUT

IN_MIN

1- f

(

ì T_{OFF _MIN}

)

(6)

Taking considerations of power losses in the system with heavy load operation, V_{IN_MAX}is higher than the result

calculated in 方程式5. With frequency foldback, V_{IN_MIN}is lowered by decreased f_SW

450

400

350

300

250

200

150

I_OUT= 0.5 A

I_OUT= 1.0 A

100

I_OUT= 2.0 A

I_OUT= 3.0 A

4.6

4.8

5.2

5.4

5.6

5.8

6.2

6.4

V_IN(V)

D013

图8-8. Frequency Foldback at Dropout (V_OUT= 5 V, f_SW= 400 kHz)

8.3.7 Power Good (PGOOD)

The power-good version of LMR23630 has a built in power-good flag shown on PGOOD pin to indicate whether

the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of

multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an

appropriate DC voltage. Voltage detected by the PGOOD pin must never exceed 15 V, and limit the maximum

current into this pin to 1 mA. A typical range of pullup resistor value is 10 kΩ to 100 kΩ.

When the FB voltage is within the power-good band, +6% above and –6% below the internal reference voltage

V_REFtypically, the PGOOD switch is turned off, and the PGOOD voltage is as high as the pulled-up voltage.

When the FB voltage is outside of the tolerance band, +7% above or –7% below V_REFtypically, the PGOOD

switch is turned on, and the PGOOD pin voltage is pulled low to indicate power bad. A glitch filter prevents false

flag operation for short excursions in the output voltage, such as during line and load transients. The values for

the various filter and delay times can be found in 节 7.6. Power-good operation can best be understood by

reference to 图8-9.

V_REF

107%

106%

94%

93%

PGOOD

High

Low

图8-9. Power-Good Flag

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8.3.8 Internal Compensation and C_FF

The LMR23630 is internally compensated as shown in 节8.2. The internal compensation is designed so that the

loop response is stable over the entire operating frequency and output voltage range. Depending on the output

voltage, the compensation loop phase margin can be low with all ceramic capacitors. TI recommends an

external feed-forward capacitor C_FFbe placed in parallel with the top resistor divider R_FBTfor optimum transient

performance.

V_OUT

C_FF

R_FBT

R_FBB

图8-10. Feed-forward Capacitor for Loop Compensation

The feed-forward capacitor C_FFin parallel with R_FBTplaces an additional zero before the crossover frequency of

the control loop to boost phase margin. The zero frequency can be found by:

f_{Z _ CFF}

2pìC_FFìR_FBT

(

)

(7)

An additional pole is also introduced with C_FFat the frequency of:

f_{P _ CFF}

2pìC_FFìR_FBT//R_FBB

(

)

(8)

The zero f_{Z_CFF}adds phase boost at the crossover frequency and improves transient response. The pole f_P-CFF

helps maintaining proper gain margin at frequency beyond the crossover. 表 9-1 lists the combination of C_OUT

C_FFand R_FBTfor typical applications, designs with similar C_OUTbut R_FBTother than recommended value, adjust

C_FFsuch that (C_FF× R_FBT) is unchanged and adjust R_FBBsuch that (R_FBT/ R_FBB) is unchanged.

Designs with different combinations of output capacitors need different C_FF. Different types of capacitors have

different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.

Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low

enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at

the output may not need any CFF. The location of this ESR zero frequency can be calculated with Equation 9:

f_{Z _ESR}

2pìC

ìESR

(

)

OUT

(9)

The C_FFcreates a time constant with R_FBTthat couples in the attenuate output voltage ripple to the FB node. If

the C_FFvalue is too large, it can couple too much ripple to the FB and affect V_OUTregulation. Therefore,

calculate C_FFbased on output capacitors used in the system. At cold temperatures, the value of C_FFmight

change based on the tolerance of the chosen component. This may reduce its impedance and ease noise

coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of C_FFcan be

reduced.

8.3.9 Bootstrap Voltage (BOOT)

The LMR23630 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and

SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the

high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is

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0.1 μF to 0.47 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage

rating of 16 V or higherfor stable performance over temperature and voltage.

8.3.10 Overcurrent and Short-Circuit Protection

The LMR23630 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and

valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating.

High-side MOSFET overcurrent protection is implemented by the nature of the peak-current-mode control. The

HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is

compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See the 节

8.2 for more details. The peak current of HS switch is limited by a clamped maximum peak current threshold

I_{HS_LIMIT}which is constant. Thus, the peak current limit of the high-side switch is not affected by the slope

compensation and remains constant over the full duty cycle range.

The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor

current begins to ramp down. The LS switch is not turned OFF at the end of a switching cycle if its current is

above the LS current limit I_{LS_LIMIT}. The LS switch is kept ON so that inductor current keeps ramping down, until

the inductor current ramps below the LS current limit I_{LS_LIMIT}. Then the LS switch is turned OFF, and the HS

switch is turned on after a dead time. This is somewhat different than the more typical peak current limit and

results in Equation 10 for the maximum load current.

_IN- V_OUT

(

)

V_OUT

I_{OUT _MAX}= I_{LS _LIMIT}

2ì f_SWìL

(10)

If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup current

protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms typically before the

LMR23630 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup will repeat until the

fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,

prevents over-heating and potential damage to the device.

For FPWM version, the inductor current is allowed to go negative. If this current exceed I_{L_NEG}, the LS switch is

turned off until the next clock cycle. This is used to protect the LS switch from excessive negative current.

8.3.11 Thermal Shutdown

The LMR23630 provides an internal thermal shutdown to protect the device when the junction temperature

exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature

falls below 155°C (typical), the device reinitiates the power-up sequence controlled by the internal soft-start

circuitry.

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LMR23630. When V_ENis below 1 V (typical), the

device is in shutdown mode. The LMR23630 also employs VIN and VCC UVLO protection. If V_INor V_CCvoltage

is below their respective UVLO level, the regulator is turned off.

8.4.2 Active Mode

The LMR23630 is in active mode when V_ENis above the precision enable threshold, V_INand V_CCare above their

respective UVLO level. The simplest way to enable the LMR23630 is to connect the EN pin to VIN pin. This

allows self startup when the input voltage is in the operating range 4 V to 36 V. See 节 8.3.5 and 节 8.3.4 for

details on setting these operating levels.

In active mode, depending on the load current, the LMR23630 is in one of four modes:

1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

peak-to-peak inductor current ripple (for both PFM and FPWM options).

2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of

the peak-to-peak inductor current ripple in CCM operation (only for PFM option).

3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for

PFM option).

4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for

FPWM option).

8.4.3 CCM Mode

CCM operation is employed in the LMR23630 when the load current is higher than half of the peak-to-peak

inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple is at a minimum in

this mode, and the maximum output current of 3 A can be supplied by the LMR23630.

8.4.4 Light Load Operation (PFM Version)

For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the

LMR23630 operates in DCM, also known as diode emulation mode (DEM). In DCM, the LS switch is turned off

when the inductor current drops to I_{L_ZC}(–40 mA typical). Both switching losses and conduction losses are

reduced in DCM, compared to forced PWM operation at light load.

At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum

HS switch ON-time (t_{ON_MIN}) or the minimum peak inductor current I_{PEAK_MIN}(300 mA typ) is reached, the

switching frequency decreases to maintain regulation. In PFM, switching frequency is decreased by the control

loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM

operation due to less frequent switching actions. The external clock synchronizing is not valid when the

LMR23630 device enters into PFM mode.

8.4.5 Light Load Operation (FPWM Version)

For FPWM version, LMR23630 is locked in PWM mode at full load range. This operation is maintained, even at

no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load

efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this

mode, a negative current limit of I_{L_NEG}is imposed to prevent damage to the regulators low side FET. When in

FPWM mode the converter synchronizes to any valid clock signal on the EN/SYNC input.

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The LMR23630 is a step-down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 3 A. The following design procedure can be used to select

components for the LMR23630. Alternately, the WEBENCH^®software may be used to generate complete

designs. When generating a design, the WEBENCH^®software utilizes iterative design procedure and accesses

comprehensive databases of components. See www.ti.com for more details.

9.2 Typical Applications

The LMR23630 only requires a few external components to convert from a wide voltage-range supply to a fixed

output voltage. 图9-1 shows a basic schematic.

V_IN12 V

C_BOOT

0.47 ꢀF

BOOT

VIN

V_OUT

5 V/3 A

10 ꢀH

C_IN

10 ꢀF

R_FBT

88.7 kΩ

EN/

SYNC

PAD

C_FF

47 pF

C_OUT

100 ꢀF

C_VCC

2.2 ꢀF

VCC

R_FBB

22.1 kΩ

PGND

AGND

图9-1. LM23630 Application Circuit

The external components must fulfill the needs of the application, but also the stability criteria of the device

control loop. 表9-1 can be used to simplify the output filter component selection.

表9-1. L, C_OUT, and C_FFTypical Values

f_SW(kHz)

V_OUT(V)

L (µH) ⁽²⁾

C_OUT(µF) ⁽³⁾

C_FF(pF)

150

R_FBT(kΩ)^{(4) (5)}

3.3

300

200

100

88.7

243

510

100

200

3.3

See⁽¹⁾

6.8

150

100

88.7

243

510

400

3.3

See⁽¹⁾

3.3

4.7

2.2

1000

2200

88.7

3.3

88.7

(1) High ESR C_OUTgives enough phase boost and C_FFnot needed.

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(2) Inductance value is calculated based on V_IN= 36 V.

(3) All the C_OUTvalues are after derating. Add more when using ceramic capacitors.

(4) R_FBT= 0 Ωfor V_OUT= 1 V. R_FBB= 22.1 kΩfor all other V_OUTsetting.

(5) For designs with R_FBTother than recommended value, please adjust C_FFsuch that (C_FF× R_FBT) is unchanged and adjust R_FBBsuch

that (R_FBT/ R_FBB) is unchanged.

9.2.1 Design Requirements

Detailed design procedure is described based on a design example. For this design example, use the

parameters listed in 表9-2 as the input parameters.

表9-2. Design Example Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage, V_IN

12 V typical, range from 8 V to 28 V

Output voltage, V_OUT

5 V

3 A

Maximum output current I_{O_MAX}

Transient response 0.2 A to 2.5 A

Output voltage ripple

50 mV

400 mV

400 kHz

Input voltage ripple

Switching frequency f_SW

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23625 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Output Voltage Setpoint

The output voltage of LMR23630 is externally adjustable using a resistor divider network. The divider network is

comprised of top feedback resistor R_FBTand bottom feedback resistor R_FBB. Equation 11 is used to determine

the output voltage:

V_OUT- V_REF

V_REF

R_FBT

ìR_FBB

(11)

Choose the value of R_FBBto be 22.1 kΩ. With the desired output voltage set to 5 V and the V_REF= 1 V, the R_FBB

value can then be calculated using Equation 11. The formula yields to a value 88.7 kΩ.

9.2.2.3 Switching Frequency

The default switching frequency of the LMR23630 is 400 kHz. For other switching frequency, the device must be

synchronized to an external clock, see 节8.3.4 for more details.

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9.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The

inductance is based on the desired peak-to-peak ripple current Δi_L. Because the ripple current increases with

the input voltage, the maximum input voltage is always used to calculate the minimum inductance L_MIN. Use

Equation 12 to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the

amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of

K_INDshould be 20% to 40%. During an instantaneous short or overcurrent operation event, the RMS and peak

inductor current can be high. The inductor current rating should be higher than the current limit of the device.

V_OUTì V

- V_OUT

(

)

IN_MAX

Di_L=

V_{IN_MAX}ìL ì f_SW

(12)

(13)

- V_OUT

V_OUT

IN_MAX

L_MIN

I_OUTìK_IND

_{IN_MAX}ì f_SW

In general, it is preferable to choose lower inductance in switching power supplies, because it usually

corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,

inductance that is too low can generate an inductor current ripple that is too high so that overcurrent protection

at the full load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger

inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current

mode control, TI does not recommend having an inductor current ripple that is too small. A larger peak-current

ripple improves the comparator signal-to-noise ratio.

For this design example, choose K_IND= 0.4, the minimum inductor value is calculated to be 8.56 µH. Choose the

nearest standard 8.2 μH ferrite inductor with a capability of 4-A RMS current and 6-A saturation current.

9.2.2.5 Output Capacitor Selection

Choose the output capacitor(s), C_OUT, with care because it directly affects the steady-state output-voltage ripple,

loop stability, and the voltage over/undershoot during load-current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going

through the equivalent series resistance (ESR) of the output capacitors:

DV_{OUT_ESR}= Di_LìESR = K_INDìI_OUTìESR

(14)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Di_L

K_INDìI_OUT

DV_{OUT _C}

8ì f ìC_OUT

(

)

(

)

(15)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the

sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,

output capacitors provide the required charge before the inductor current can slew up to the appropriate level.

The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop.

The output capacitance must be large enough to supply the current difference for four clock cycles to maintain

the output voltage within the specified range. Equation 17 shows the minimum output capacitance needed for

specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy

stored in the inductor. which results in an output voltage overshoot. Equation 14 calculates the minimum

capacitance required to keep the voltage overshoot within a specified range.

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(16)

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4ì I_OH-I_OL

(

)

C_OUT

f_SWì V_US

I_O²_H-I_O²_L

C_OUT

ìL

+ V_OS- V_O²_UT

(

)

OUT

(17)

where

• I_OL= Low level output current during load transient

• I_OH= High level output current during load transient

• V_US= Target output voltage undershoot

• V_OS= Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR}= ΔV_{OUT_C}= 50 mV, and

chose K_IND= 0.4. Equation 16 yields ESR no larger than 41.7 mΩ and Equation 17 yields C_OUTno smaller than

7.5 μF. For the target over/undershoot range of this design, V_US= V_OS= 5% × V_OUT= 250 mV. The C_OUTcan

be calculated to be no smaller than 108 μF and 28.5 μF by Equation 15 and Equation 17, respectively.

Consider of derating, one 47-μF, 16-V and one 100-μF, 10-V ceramic capacitor with 5-mΩ ESR are used in

parallel.

9.2.2.6 Feed-Forward Capacitor

The LMR23630 is internally compensated. Depending on the V_OUTand frequency f_SW, if the output capacitor

C_OUTis dominated by low-ESR (ceramic types) capacitors, it could result in low phase margin. To improve the

phase boost an external feed-forward capacitor C_FFcan be added in parallel with R_FBT. C_FFis chosen such that

phase margin is boosted at the crossover frequency without C_FF. A simple estimation for the crossover

frequency (f_X) without C_FFis shown in Equation 18, assuming C_OUThas very small ESR, and C_OUTvalue is after

derating.

8.32

f_X

V_OUTìC_OUT

(18)

Equation 19 for C_FFwas tested:

C_FF

4pì f_XìR_FBT

(19)

For designs with higher ESR, C_FFis not needed when C_OUThas very high ESR and C_FFcalculated from

Equation 19 must reduced with medium ESR. 表9-1 can be used as a quick starting point.

For the application in this design example, a 47-pF, 50-V, COG capacitor is selected.

9.2.2.7 Input Capacitor Selection

The LMR23630 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,

depending on the application. The typical recommended value for the high-frequency decoupling capacitor is 4.7

μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating.

To compensate the derating of ceramic capacitors, a voltage rating twice the maximum input voltage is

recommended. Additionally, some bulk capacitance can be required, especially if the LMR23630 circuit is not

located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to

the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R

ceramic capacitors are used. A 0.1-μF for high-frequency filtering and place it as close as possible to the device

pins.

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9.2.2.8 Bootstrap Capacitor Selection

Every LMR23630 design requires a bootstrap capacitor (C_BOOT). TI recommends a capacitor of 0.47 μF, ated

16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap

capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

9.2.2.9 VCC Capacitor Selection

The VCC pin is the output of an internal LDO for LMR23630. To insure stability of the device, place a minimum of

2.2-μF, 16V, X7R capacitor from this pin to ground.

9.2.2.10 Undervoltage Lockout Setpoint

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down

or brown outs when the input voltage is falling. The following equation can be used to determine the V_INUVLO

level.

R_ENT+ R_ENB

R_ENB

= V_ENHì

IN_RISING

(20)

The EN rising threshold (V_ENH) for LMR23630 is set to be 1.55 V (typical). Choose the value of R_ENBto be 287

kΩ to minimize input current from the supply. If the desired V_INUVLO level is at 6 V, then the value of R_ENTcan

be calculated using Equation 21:

≈

’

IN_RISING

R_ENT

-1 ìR

∆

ENB

V_ENH

◊

(21)

Equation 21 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by

Equation 22, where EN hysteresis (V_{EN_HYS}) is 0.4 V (typical).

R_ENT+ R_ENB

R_ENB

= V_ENH- V_{EN_HYS}

(

)

IN_FALLING

(22)

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, f_SW= 400 kHz, L = 8.2 µH, C_OUT= 150 µF, T_A= 25 °C.

V_OUT= 5 V

I_OUT= 3 A

f_SW= 400 kHz

V_OUT= 5 V

I_OUT= 150 mA

f_SW= 400 kHz

I_OUT= 2 A

图9-2. CCM Mode

图9-3. DCM Mode

V_OUT= 5 V

I_OUT= 0 mA

f_SW= 400 kHz

V_OUT= 5 V

I_OUT= 0 mA

图9-4. PFM Mode

图9-5. FPWM Mode

V_IN= 12 V

V_OUT= 5 V

I_OUT= 2 A

V_IN= 12 V

V_OUT= 5 V

图9-6. Start Up by V_IN

图9-7. Start Up by EN

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V_IN= 12 V

V_OUT= 5 V

I_OUT= 3 A

I_OUT= 0.3 A to 3 A, 100 mA / μs

V_IN= 7 V to 36 V, 2 V / μs

图9-8. Load Transient

图9-9. Line Transient

V_OUT= 5 V

I_OUT= 1 A to short

V_OUT= 5 V

I_OUT= short to 1 A

图9-10. Short Protection

图9-11. Short Recovery

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10 Power Supply Recommendations

The LMR23630 is designed to operate from an input voltage supply range between 4.5 V and 36 V for the

HSOIC package and 4 V to 36 V for the WSON package. This input supply must be able to withstand the

maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough

that an input current transient does not cause a high enough drop at the LMR23630 supply voltage that can

cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from

the LMR23630, additional bulk capacitance may be required in addition to the ceramic input capacitors. The

amount of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.

11 Layout

11.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB

with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

1. The input bypass capacitor C_INmust be placed as close as possible to the VIN and PGND pins. Grounding

for both the input and output capacitors should consist of localized top side planes that connect to the PGND

pin and PAD.

2. Place bypass capacitors for V_CCclose to the VCC pin and ground the bypass capacitor to device ground.

3. Minimize trace length to the FB pin net. Both feedback resistors, R_FBTand R_FBBshould be located close to

the FB pin. Place C_FFdirectly in parallel with R_FBT. If V_OUTaccuracy at the load is important, make sure V_OUT

sense is made at the load. Route V_OUTsense path away from noisy nodes and preferably through a layer on

the other side of a shielded layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.

5. Have a single point ground connection to the plane. The ground connections for the feedback and enable

components should be routed to the ground plane. This prevents any switched or load currents from flowing

in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or

erratic output voltage ripple behavior.

6. Make V_IN, V_OUTand ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the

ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be

connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking

to keep the junction temperature below 125 °C.

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11.2 Layout Example

Output Bypass

Capacitor

Output Inductor

Input Bypass

Capacitor

PGND

VIN

BOOT Capacitor

BOOT

VCC

AGND

VCC

Capacitor

EN/

SYNC

UVLO Adjust Resistor

Output Voltage Set

Resistor

Thermal VIA

VIA (Connect to GND Plane)

图11-1. Sample HSOIC Package Layout

Output

Inductor

Output Bypass

Capacitor

PGND

Input Bypass

Capacitor

BOOT

Capacitor

BOOT

VCC

VIN

VCC

Capacitor

EN/SYNC

AGND

UVLO Adjust

Resistor

Thermal VIA

VIA (Connect to GND Plane)

Output Voltage

Set Resistor

图11-2. Sample WSON Package Layout

11.3 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass

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capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing

ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load

current without excessive heating. Use short, thick traces or copper pours (shapes) high current conduction path

to minimize parasitic resistance. Place the output capacitors close to the V_OUTend of the inductor and closely

grounded to PGND pin and exposed PAD.

Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the

exposed PAD.

11.4 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is

connected to the source of the internal LS switch. They must be connected directly to the grounds of the input

and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load

variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The

other side of the ground plane contains much less noise and should be used for sensitive routes.

TI also recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary

thermal path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane

heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system

ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper

thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough

copper thickness provides low current conduction impedance, proper shielding, and lower thermal resistance.

The thermal characteristics of the LMR23630 are specified using the parameter R_θJA, which characterize the

junction temperature of silicon to the ambient temperature in a specific system. Although the value of R_θJAis

dependent on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use the following relationship:

T_J= P_D× R_θJA+ T_A

(23)

(24)

P_D= V_IN× I_IN× (1 –Efficiency) –1.1 × I_OUT²× DCR in watt

where

• T_J= junction temperature in °C

• P_D= device power dissipation in watt

• R_θJA= junction-to-ambient thermal resistance of the device in °C/W

• T_A= ambient temperature in °C

• DCR = inductor DC parasitic resistance in ohm

The maximum operating junction temperature of the LMR23630 is 125°C. R_θJAis highly related to PCB size and

layout, as well as environmental factors such as heat sinking and air flow.

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11.5 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

C_FFclose to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider and C_FFcloser to the FB pin reduces

the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace

from V_OUTto the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to

the feedback resistor divider should be routed away from the SW node path and the inductor to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most

important when high value resistors are used to set the output voltage. TI recommends routing the voltage sense

trace and place the resistor divider on a different layer than the inductor and SW node path, such that there is a

ground plane in between the feedback trace and inductor/SW node polygon. This provides further shielding for

the voltage feedback path from EMI noises.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR23625 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

12.4 Trademarks

PowerPAD^™is a trademark of TI.

TI E2E^™is a trademark of Texas Instruments.

SIMPLE SWITCHER^®is a registered trademark of TI.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMR23630ADDA

LMR23630ADDAR

LMR23630AFDDA

LMR23630AFDDAR

LMR23630APDRRR

LMR23630APDRRT

LMR23630DRRR

LMR23630DRRT

LMR23630FDRRR

LMR23630FDRRT

ACTIVE SO PowerPAD

DDA

DRR

RoHS & Green

NIPDAUAG

Level-2-260C-1 YEAR

-40 to 125

F30A

Samples

2500 RoHS & Green

75 RoHS & Green

NIPDAUAG

F30AF

3630P

23630

3630F

2500 RoHS & Green

3000 RoHS & Green

NIPDAUAG

ACTIVE

WSON

250

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Jun-2023

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMR23630 :

Automotive : LMR23630-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMR23630ADDAR

LMR23630AFDDAR

PowerPAD

DDA

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

330.0

12.8

6.4

5.2

2.1

8.0

12.0

PowerPAD

LMR23630APDRRR

LMR23630APDRRT

LMR23630DRRR

LMR23630DRRT

LMR23630FDRRR

LMR23630FDRRT

WSON

DRR

3000

250

330.0

180.0

330.0

180.0

330.0

180.0

12.4

3.3

1.0

8.0

12.0

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMR23630ADDAR

LMR23630AFDDAR

LMR23630APDRRR

LMR23630APDRRT

LMR23630DRRR

LMR23630DRRT

SO PowerPAD

WSON

DDA

DRR

2500

3000

250

366.0

367.0

213.0

367.0

213.0

367.0

213.0

364.0

367.0

191.0

367.0

191.0

367.0

191.0

50.0

38.0

35.0

38.0

35.0

38.0

35.0

WSON

3000

250

WSON

LMR23630FDRRR

LMR23630FDRRT

WSON

3000

250

WSON

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

LMR23630ADDA

LMR23630AFDDA

DDA

HSOIC

517

7.87

635

4.25

Pack Materials-Page 3

PACKAGE OUTLINE

DRR0012D

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

SECTION A-A

TYPICAL

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

1.7 0.1

2.5

2.5 0.1

10X 0.5

0.3

0.2

12X

0.38

0.28

12X

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

4223146/D 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DRR0012D

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.7)

12X (0.53)

SYMM

12X (0.25)

SYMM

(2.5)

10X (0.5)

(1)

(R0.05) TYP

(0.6)

(2.87)

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL EDGE

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223146/D 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRR0012D

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

(0.47)

12X (0.53)

12X (0.25)

METAL

TYP

(0.675)

SYMM

10X (0.5)

(1.15)

(R0.05) TYP

(0.74)

(2.87)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80.1% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4223146/D 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMR23630APDRRT [TI]

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