LMR33630ADDA_技术文档

LMR33630

ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

LMR33630 SIMPLE SWITCHER^®3.8V 至 36V、3A

同步降压转换器

1 特性

2 应用

•

提供功能安全

•

电机驱动系统：无人机、交流逆变器、

变频驱动器、伺服系统

工厂和楼宇自动化系统：

PLC CPU、HVAC 控制、电梯控制

通用宽输入电压电源

– 可帮助进行功能安全系统设计的文档

专用于条件严苛的工业应用

– 输入电压范围：3.8V 至 36V

– 输出电压范围：1V 至 24V

– 输出电流：3A

•

3 说明

– 75mΩ/50mΩ R_DS-ON功率 MOSFET

LMR33630 SIMPLE SWITCHER^®稳压器是一款简单

易用的同步降压直流/直流转换器，可提供出色的效

率，适用于条件严苛的工业应用。LMR33630 能够使

用高达 36V 的输入电压驱动高达 3A 的负载电流，还

以超小的解决方案尺寸提供出色的轻负载效率和输出精

度。电源正常状态标志和精密使能端等特性有助于实现

灵活而又易用的解决方案，适用于广泛的应用。

LMR33630 在轻负载条件下自动折返频率以提高效

率。此器件通过集成技术省去了大部分外部元件，并提

供专为实现简单 PCB 布局而设计的引脚排列方式。保

护特性包括热关断、输入欠压锁定、逐周期电流限制和

断续短路保护。LMR33630 采用 8 引脚 HSOIC 封装和

具有可湿性侧面的 12 引脚 3mm × 2mm 新一代 VQFN

封装。该器件还具有符合 AEC-Q100 标准的版本。

– 峰值电流模式控制

– 最短导通时间很短，只有 68ns

– 频率：400kHz、1.4MHz、2.1MHz

– 结温范围为 –40°C 至 +125°C

– 低 EMI 和低开关噪声

– 集成补偿网络

低 EMI 和开关噪声

– HotRod^™封装

– 并行输入电流路径

可在所有负载下进行高效电源转换

– 峰值效率 > 95%

•

– 低至 25µA 的工作静态电流

灵活的系统接口

– 电源正常状态标志和精密使能端

使用 TPSM53603 模块缩短产品上市时间

使用 LMR33630 并借助 WEBENCH^®Power

Designer 创建定制设计方案

•

器件信息

封装⁽¹⁾

器件型号

LMR33630

封装尺寸（标称值）

5.00mm × 4.00mm

3.00mm × 2.00mm

HSOIC (8)

VQFN (12)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

100

95

90

85

80

75

BOOT

V_IN

C_IN

VIN

EN

C_BOOT

L1

V_OUT

C_OUT

SW

PGND

VCC

8V

12V

70

65

PG

FB

R_FBT

C_VCC

24V

60

36V

R_FBB

55

0.01

AGND

0.1

Output Current (A)

1

10

C021

效率与输出电流间的关系 V_OUT= 5V，400kHz，VQFN

简化版原理图

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSAN3

LMR33630

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

6 Pin Configuration and Functions

SW

12

1

2

11 PGND

PGND

VIN

1

2

3

4

8

7

6

5

SW

PGND

BOOT

VCC

FB

THERMAL PAD

10 VIN

VIN

EN

9

8

EN

PG

3

4

NC

PG

BOOT

Not to scale

6

7

5

图 6-1. DDA Package 8-Pin HSOIC With PowerPAD

FB

AGND

VCC

^™Top View

图 6-2. RNX Package 12-Pin VQFN Top View

表 6-1. Pin Functions

TYPE

DESCRIPTION

HSOIC

VQFN

NAME

Power ground terminal. Connect to system ground and AGND. Connect to bypass

capacitor with short wide traces.

1

1,11

2,10

9

PGND

G

P

A

Input supply to regulator. Connect a high-quality bypass capacitor or capacitors

directly to this pin and PGND.

2

3

VIN

EN

Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN;

Do not float.

Open drain power-good flag output. Connect to suitable voltage supply through a

current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN =

Low. Can be left open when not used.

4

5

6

8

7

5

PG

FB

A

P

Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not

float. Do not ground.

Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to

external loads. Can be used as logic supply for power-good flag. Connect a high-

quality 1-µF capacitor from this pin to GND.

VCC

Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF

capacitor from this pin to the SW pin. On the VQFN package connect the SW pin to

NC on the PCB. This simplifies the connection from the C_BOOTcapacitor to the SW

pin.

7

8

4

BOOT

SW

P

Regulator switch node. Connect to power inductor. On the VQFN package connect

the SW pin to NC on the PCB. This simplifies the connection from the C_BOOT

capacitor to the SW pin.

12

Analog ground for regulator and system. Ground reference for internal references and

logic. All electrical parameters are measured with respect to this pin. Connect to

system ground on PCB. For the HSOIC package, the pad on the bottom of the device

serves as both the AGND connection and a thermal connection to the heat sink

ground plane. This pad must be soldered to a ground plane to achieve good electrical

and thermal performance.

THERMAL

PAD

6

3

AGND

NC

G

On the VQFN package the SW pin must be connected to NC on the PCB. This

simplifies the connection from the C_BOOTcapacitor to the SW pin. This pin has no

internal connection to the regulator.

—

A = Analog, P = Power, G = Ground

2

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Table of Contents

8.3 Feature Description...................................................11

8.4 Device Functional Modes..........................................14

9 Application and Implementation..................................18

9.1 Application Information............................................. 18

9.2 Typical Application.................................................... 18

9.3 What to Do and What Not to Do............................... 29

10 Layout...........................................................................31

10.1 Layout Guidelines................................................... 31

10.2 Layout Example...................................................... 33

11 Device and Documentation Support..........................35

11.1 Device Support........................................................35

11.2 Documentation Support.......................................... 35

11.3 接收文档更新通知................................................... 35

11.4 支持资源..................................................................35

11.5 Trademarks............................................................. 36

11.6 静电放电警告...........................................................36

11.7 术语表..................................................................... 36

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 3

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................2

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................6

7.6 Timing Characteristics.................................................7

7.7 System Characteristics............................................... 8

7.8 Typical Characteristics................................................9

8 Detailed Description......................................................10

8.1 Overview...................................................................10

8.2 Functional Block Diagram.........................................10

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision E (May 2020) to Revision F (November 2020)

Page

向特性添加了功能安全项目................................................................................................................................1

更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1

•

• Added RNX pinout drawing................................................................................................................................ 2

• Added VQFN package drawing........................................................................................................................ 33

Changes from Revision D (March 2019) to Revision E (May 2020)

Page

•

添加了指向 TPSM53603 产品页面的链接...........................................................................................................1

Changes from Revision C (June 2018) to Revision D (March 2019)

Page

• Changed heading to device option .................................................................................................................... 4

• Changed Minimum peak current to reflect ATE data.......................................................................................... 6

• Changed zero cross to reflect ATE data.............................................................................................................6

• Changed to new current limit equation............................................................................................................. 13

• Added new de-rate curve..................................................................................................................................23

Changes from Revision B (April 2018) to Revision C (June 2018)

Page

• Changed heading to device option .................................................................................................................... 4

• Added graphs for Typical Switching Frequency in Dropout Mode ...................................................................16

Changes from Revision A (February 2018) to Revision B (April 2018)

Page

•

在整个数据表中添加了 WSON 信息................................................................................................................... 1

• Changed block diagram to fix drawing error.....................................................................................................10

• Added RNX package drawings ......................................................................................................................0

Changes from Revision * (August 2017) to Revision A (February 2018)

Page

•

首次发布量产数据数据表.................................................................................................................................... 1

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5 Device Comparison Table

DEVICE OPTION

LMR33630ADDA

LMR33630BDDA

LMR33630CDDA

LMR33630ARNX

LMR33630BRNX

LMR33630CRNX

PACKAGE

FREQUENCY

400 kHz

RATED CURRENT

OUTPUT VOLTAGE

3 A

DDA (8-pin HSOIC)

5 × 4 mm

1400 kHz

2100 kHz

400 kHz

Adjustable

RNX (12-pin VQFN)

3 × 2 × 0.85 mm

1400 kHz

2100 kHz

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

PARAMETER

MIN

–0.3

0

MAX

38

UNIT

VIN to PGND

EN to AGND⁽²⁾

FB to AGND

V_IN+ 0.3

5.5

V

PG to AGND⁽²⁾

22

AGND to PGND

0.3

Voltages

–0.3

–3.5

–0.3

–40

–55

SW to PGND

V_IN+ 0.3

38

SW to PGND less than 100-ns transients

BOOT to SW

V

5.5

VCC to AGND⁽⁴⁾

5.5

T_J

Junction temperature⁽³⁾

Storage temperature

150

°C

T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V

(3) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.

(4) Under some operating conditions the VCC LDO voltage may increase beyond 5.5V.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM) ⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM) ⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating temperature range of –40 °C to 125 °C (unless otherwise noted) ⁽¹⁾

MIN

3.8

0

MAX

UNIT

VIN to PGND

EN ⁽²⁾

36

V_IN

18

24

3

Input voltage

V

PG⁽²⁾

0

(3)

Adjustable output voltage

Output current

V_OUT

1

V

A

I_OUT

0

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see 节 7.5.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

(3) The maximum output voltage can be extended to 95% of V_IN; contact TI for details. Under no conditions should the output voltage be

allowed to fall below zero volts.

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7.4 Thermal Information

The value of R_θJAgiven in this table is only valid for comparison with other packages and can not be used for design

purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do

not represent the performance obtained in an actual application. For design information see Maximum Ambient Temperature

section.

LMR336x0

THERMAL METRIC^{(1) (2)}

DDA (HSOIC)

8 PINS

42.9⁽²⁾

54

RNX (VQFN)

12 PINS

72.5⁽²⁾

35.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

13.6

23.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.3

0.8

ψ_JT

13.8

23.5

ψ_JB

R_θJC(bot)

4.3

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The value of R_θJAgiven in this table is only valid for comparison with other packages and can not be used for design purposes. These

values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the

performance obtained in an actual application. For design information see Maximum Ambient Temperature section.

7.5 Electrical Characteristics

Limits apply over the operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and

maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric

norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:

V_IN= 12 V, V_EN= 4 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE

Minimum operating input

voltage

V_IN

3.8

34

10

V

Non-switching input current;

measured at VIN pin ⁽²⁾

I_Q

V_FB= 1.2 V

EN = 0

24

5

µA

Shutdown quiescent current;

measured at VIN pin

I_SD

ENABLE

V_EN-VCC-H

EN input level required to turn

on internal LDO

Rising threshold

Falling threshold

Rising threshold

1

V

EN input level required to turn

off internal LDO

V_EN-VCC-L

V_EN-H

0.3

1.2

EN input level required to start

switching

1.231

1.26

V_EN-HYS

I_LKG-EN

INTERNAL SUPPLIES

Hysteresis below V_EN-H

Hysteresis below V_EN-H; falling

V_EN= 3.3 V

100

0.2

mV

nA

Enable input leakage current

Internal LDO output voltage

appearing at the VCC pin

VCC

4.75

5

5.25

V

6 V ≤ V_IN≤ 36 V

Bootstrap voltage

undervoltage lock-out

threshold⁽³⁾

V_BOOT-UVLO

2.2

VOLTAGE REFERENCE (FB PIN)

V_FBFeedback voltage; ADJ option

0.985

1

1.015

50

V

Current into FB pin; ADJ

option

I_FB

FB = 1 V

0.2

nA

CURRENT LIMITS⁽⁴⁾

I_SC

High-side current limit

Low-side current limit

LMR33630

3.85

2.9

4.5

3.5

5.05

4.1

A

I_LIMIT

I_PEAK-MIN

Minimum peak inductor current LMR33630

0.69

6

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Limits apply over the operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and

maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric

norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:

V_IN= 12 V, V_EN= 4 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Zero current detector

threshold

I_ZC

-0.106

A

SOFT START

t_SS

Internal soft-start time

2.9

4

6

ms

POWER GOOD (PG PIN)

Power-good upper threshold -

V_PG-HIGH-UP

V_PG-HIGH-DN

V_PG-LOW-UP

V_PG-LOW-DN

t_PG

% of FB voltage

105%

103%

92%

90%

60

107%

105%

94%

110%

108%

97%

95%

170

rising

Power-good upper threshold -

falling

% of FB voltage

Power-good lower threshold -

rising

Power-good lower threshold -

falling

92%

Power-good glitch filter

delay⁽¹⁾

µs

V_IN= 12 V, V_EN= 4 V

V_EN= 0 V

76

35

150

60

R_PG

Power-good flag R_DSON

Ω

Minimum input voltage for

proper PG function

V_IN-PG

50-µA, EN = 0 V

2

V

V_PG

PG logic low output

50-µA, EN = 0 V, V_IN= 2V

0.2

OSCILLATOR

ƒ_SW

Switching frequency

"A" Version

340

1.2

1.8

400

1.4

2.1

460

1.6

2.4

2.3

kHz

MHz

"B" Version

ƒ_SW

"C" Version, DDA package

"C" Version, RNX package

ƒ_SW

MOSFETS

High-side MOSFET ON-

resistance

R_DS-ON-HS

R_DS-ON-LS

RNX package

DDA package

RNX package

DDA package

75

95

50

66

145

160

95

mΩ

High-side MOSFET ON-

resistance

Low-side MOSFET ON-

resistance

Low-side MOSFET ON-

resistance

110

(1) See Power-Good Flag Output for details.

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) When the voltage across the C_BOOTcapacitor falls below this voltage, the low side MOSFET is turned on to recharge C_BOOT

.

(4) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.

7.6 Timing Characteristics

Limits apply over the operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and

maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric

norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN

= 12 V, V_EN= 4 V.

MIN

NOM

68

75

52

50

7

MAX

UNIT

t_ON-MIN

t_OFF-MIN

t_ON-MAX

Minimum switch on-time

Minimum switch off-time

Maximum switch on-time

RNX package

DDA package

RNX package

DDA package

80

ns

108

70

ns

85

ns

9

µs

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7.7 System Characteristics

The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 125°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Operating input voltage range

V_OUT= 3.3 V, I_OUT= 0 A

3.8

36

V

V_OUT= 5 V, V_IN= 7 V to 36 V, I_OUT= 0 A to

max. load

2.5%

1.5%

2.5%

1.5%

–1.5%

Output voltage regulation for V_OUT= 5

V⁽¹⁾

V_OUT= 5 V, V_IN= 7 V to 36 V, I_OUT= 1 A to

max. load

V_OUT

V_OUT= 3.3 V, V_IN= 3.8 V to 36 V, I_OUT= 0 A

to max. load

Output voltage regulation for V_OUT= 3.3

V⁽¹⁾

V_OUT= 3.3 V, V_IN= 3.8 V to 36 V, I_OUT= 1 A

to max. load

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 0 A,

R_FBT= 1 MΩ

I_SUPPLY

Input supply current when in regulation

25

µA

V_OUT= 5 V, I_OUT= 1A

Dropout at –1% of regulation,

ƒ_SW= 140 kHz

V_DROP

150

mV

Dropout voltage; (V_IN– V_OUT

)

D_MAX

V_HC

Maximum switch duty cycle⁽²⁾

V_IN= V_OUT= 12 V, I_OUT= 1 A

98%

0.4

FB pin voltage required to trip short-circuit

hiccup mode

V

t_HC

t_D

Time between current-limit hiccup burst

Switch voltage dead time

94

2

ms

ns

°C

Shutdown temperature

Recovery temperature

165

148

T_SD

Thermal shutdown temperature

(1) Deviation is with respect to V_IN=12 V, I_OUT= 1 A.

(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒ_MIN

=

1 / (t_ON-MAX+ t_OFF-MIN). D_MAX= t_ON-MAX/(t_ON-MAX+ t_OFF-MIN).

8

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7.8 Typical Characteristics

Unless otherwise specified the following conditions apply: T_A= 25°C and V_IN= 12 V

36

34

32

30

28

26

24

22

20

12

11

10

9

8

7

6

5

4

-40C

25C

-40C

25C

3

2

1

125C

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

Input Voltage (V)

C005

C003

V_FB= 1.2 V

EN = 0 V

图 7-1. Non-Switching Input Supply Current

图 7-2. Shutdown Supply Current

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

1000

900

800

700

-40C

600

UP

DN

25C

125C

35

500

0

20

40

60

80

100 120 140

œ40 œ20

0

5

10

15

20

25

30

40

Temperature (C)

C006

Input Voltage (V)

C004

V_OUT= 0 V

ƒ_S= 400 kHz

See 图 9-31

图 7-4. Precision Enable Thresholds

图 7-3. Short-Circuit Output Current

1,200

1,100

1,000

900

800

700

-40C

25C

600

DN

UP

500

125C

400

0

5

10

15

20

25

30

35

40

INPUT VOLTAGE (1V/Div)

Input Voltage (V)

C006

I_OUT= 0 A

V_OUT= 5 V

See 图 9-31

I_OUT= 1 mA

See 图 9-31

ƒ_SW= 400 kHz

图 7-5. UVLO Thresholds

图 7-6. I_PEAK-MIN

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8 Detailed Description

8.1 Overview

The LMR33630 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial

applications. Advanced high speed circuitry allows the device to regulate from an input voltage of 20 V, while

providing an output voltage of 3.3 V at a switching frequency of 2.1 MHz. The innovative architecture allows the

device to regulate a 3.3-V output from an input of only 3.8 V. The regulator automatically switches modes

between PFM and PWM depending on load. At heavy loads, the device operates in PWM at a constant

switching frequency. At light loads, the mode changes to PFM with diode emulation allowing DCM. This reduces

the input supply current and keeps efficiency high. The device features internal loop compensation which

reduces design time and requires fewer external components than externally compensated regulators.

The LMR33630 is available in an ultra-miniature VQFN package with wettable flanks. This package features

extremely small parasitic inductance and resistance, enabling very high efficiency while minimizing switch node

ringing and dramatically reducing EMI. The VIN/PGND pin layout is symmetrical on either side of the VQFN

package. This allows the input current magnetic fields to partially cancel, resulting in reduce EMI generation.

8.2 Functional Block Diagram

VCC

VIN

INT. REG.

BIAS

OSCILLATOR

BOOT

ENABLE

LOGIC

HS CURRENT

SENSE

EN

ꢀ

1.0V

Reference

PWM

COMP.

ERROR

AMPLIFIER

CONTROL

LOGIC

DRIVER

SW

+

-

+

-

FB

LS CURRENT

SENSE

PFM MODE

CONTROL

PG

POWER GOOD

CONTROL

AGND PGND

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8.3 Feature Description

8.3.1 Power-Good Flag Output

The power-good flag function (PG output pin) of the LMR33630 can be used to reset a system microprocessor

whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as

current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation

for short excursions of the output voltage, such as during line and load transients. The timing parameters of the

glitch filter are found in 节 7.5. Output voltage excursions lasting less than t_PGdo not trip the power-good flag.

Power-good operation can best be understood by reference to 图 8-1 and 图 8-2. Note that during initial power

up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good

flag goes high. This delay only occurs during start-up and is not encountered during normal operation of the

power-good function.

The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic

supply. It can also be pulled up to either VCC or V_OUT, through a 100-kΩ resistor, as desired. If this function is

not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN

low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the power-

good flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device

is enabled and about 65 mA when the device is disabled. The internal current limit protects the device from any

transient currents that can occur when discharging a filter capacitor connected to this output.

V_OUT

V_{PG-HIGH_UP (107%)}

V_PG-HIGH-DN

(105%)

V_PG-LOW-UP

(95%)

V_{PG-LOW-DN (93%)}

PG

High = Power Good

Low = Fault

图 8-1. Static Power-Good Operation

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Glitches do not cause false operation nor reset timer

V_OUT

V

_PG-LOW-UP(95%)

_PG-LOW-DN(93%)

V

< t_PG

PG

t_PG

图 8-2. Power-Good-Timing Behavior

t_PG

8.3.2 Enable and Start-up

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use

of an external voltage divider to provide an adjustable input UVLO (see 节 9.2.2.10). Applying a voltage of ≥

V_{EN-VCC_H}causes the device to enter standby mode, powering the internal VCC, but not producing an output

voltage. Increasing the EN voltage to V_EN-Hfully enables the device, allowing it to enter start-up mode and

starting the soft-start period. When the EN input is brought below V_EN-Hby V_EN-HYS, the regulator stops running

and enters standby mode. Further decrease in the EN voltage to below V_EN-VCC-Lcompletely shuts down the

device. This behavior is shown in 图 8-3. The EN input can be connected directly to VIN if this feature is not

needed. This input must not be allowed to float. The values for the various EN thresholds can be found in 节

7.5 .

The LMR33630 uses a reference-based soft start that prevents output voltage overshoots and large inrush

currents as the regulator is starting up. A typical start-up waveform is shown in 图 8-4, indicating typical timings.

The rise time of the output voltage is about 4 ms (see 节 7.5).

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EN

V_EN-H

V_EN-Hœ V_EN-HYS

V_EN-VCC-H

V_EN-VCC-L

VCC

5V

0

VOUT

V_OUT

0

图 8-3. Precision Enable Behavior

EN, 3V/Div

VOUT, 2V/Div

PG, 5V/Div

Inductor Current, 3A/Div

2ms/Div

图 8-4. Typical Start-up Behavior V_IN= 12 V, V_OUT= 5 V, I_OUT= 3 A

8.3.3 Current Limit and Short Circuit

The LMR33630 incorporates both peak and valley inductor current limit to provide protection to the device from

overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current

runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum

output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for

sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to implement

DEM at light loads (see the Glossary). The typical value of this current limit is found under I_ZCin 节 7.5 .

When the device is overloaded, the valley of the inductor current may not reach below I_LIMIT(see 节 7.5) before

the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing the switching

frequency to drop. Further overload causes the switching frequency to continue to drop, and the inductor ripple

current to increase. When the peak of the inductor current reaches the high-side current limit, I_SC(see 节 7.5),

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the switch duty cycle is reduced and the output voltage falls out of regulation. This represents the maximum

output current from the converter and is given approximately by 方程式 1.

I_LIMIT+I_SC

I_OUT

=

max

2

(1)

If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters

into hiccup mode. In this mode, the device stops switching for t_HC(see 节 7.7), or about 94 ms and then goes

through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for

about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in 图 8-5 as long as the short-

circuit-condition persists. This mode of operation helps reduce the temperature rise of the device during a hard

short on the output. The output current is greatly reduced during hiccup mode. Once the output short is removed

and the hiccup delay is passed, the output voltage recovers normally as shown in 图 8-6.

Short Applied

Short Removed

VOUT, 2V/Div

Inductor Current, 1A/Div

Inductor Current,

1A/Div

50ms/Div

图 8-5. Inductor Current Burst in Short-Circuit

图 8-6. Short-Circuit Transient and Recovery

Mode

8.3.4 Undervoltage Lockout and Thermal Shutdown

The LMR33630 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin).

When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC falls below

about 3 V, the device shuts down, regardless of EN status. Because the LDO is in dropout during these

transitions, the above values roughly represent the input voltage levels during the transitions.

Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction

temperature reaches about 165°C the device shuts down; re-start occurs when the temperature falls to about

148°C.

8.4 Device Functional Modes

8.4.1 Auto Mode

In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator

operates in PFM. At higher loads, the mode changes to PWM. The load current for which the device moves from

PFM to PWM can be found in 节 9.2.3. The output current at which the device changes modes depends on the

input voltage, inductor value, and the nominal switching frequency. For output currents above the curve, the

device is in PWM mode. For currents below the curve, the device is in PFM. The curves apply for and the BOM

shown in 表 9-4 and a nominal switching frequency of 400 kHz. At higher switching frequencies, the load at

which the mode change occurs is greater. For applications where the switching frequency must be known for a

given condition, the transition between PFM and PWM must be carefully tested before the design is finalized.

In PWM mode, the regulator operates as a constant frequency converter using PWM to regulate the output

voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and

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modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and

low output voltage ripple.

In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The

duration of the burst depends on how long it takes the inductor current to reach I_PEAK-MIN. The periodicity of

these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see

the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current

required to regulate the output voltage at light loads. PFM results in very good light-load efficiency, but also

yields larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage

occurs at light loads. The actual switching frequency and output voltage ripple depends on the input voltage,

output voltage, and load. Typical switching waveforms in PFM and PWM are shown in 图 8-7 and 图 8-8.

See 节 9.2.3 for output voltage variation with load in auto mode.

SW,

5V/Div

SW,

5V/Div

VOUT,

10mV/Div

VOUT,

10mV/Div

Inductor

Current,

0.5A/Div

Inductor

Current,

2A/Div

2µs/Div

50µs/Div

图 8-7. Typical PFM Switching Waveforms V_IN= 12 图 8-8. Typical PWM Switching Waveforms V_IN= 12

V, V_OUT= 5 V, I_OUT= 10 mA

V, V_OUT= 5 V, I_OUT= 3 A, ƒ_S= 400 kHz

8.4.2 Dropout

The dropout performance of any buck regulator is affected by the R_DSONof the power MOSFETs, the DC

resistance of the inductor and the maximum duty cycle that the controller can achieve. As the input voltage level

approaches the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value (see

节 7.6). Beyond this point, the switching can become erratic, and the output voltage falls out of regulation. To

avoid this problem, the LMR33630 automatically reduces the switching frequency to increase the effective duty

cycle and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the

input and output voltage when the output has dropped by 1% of its nominal value. Under this condition, the

switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit

detection threshold is not activated when in dropout mode. Typical dropout characteristics can be found in 图

8-9, 图 8-10, 图 8-11, and 图 8-12.

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6

5.5

5

0.45

0.4

0.35

0.3

0.25

0.2

4.5

4

1A

2A

3A

0A

0.15

0.1

3.5

3

5V

0.05

0

3.3V

4

4.5

5

5.5

6

6.5

7

0

0.5

1

1.5

2

2.5

3

3.5

Input Voltage (V)

Output Current (A)

C017

C011

图 8-9. Overall Dropout Characteristic V_OUT= 5 V

图 8-10. Typical Dropout Voltage versus Output

Current in Frequency Foldback ƒ_SW= 140 kHz

2.4

2.2

2

2.4

2.2

2

1.8

1.6

1.4

1.2

1

1.8

1.6

1.4

1.2

1

0.8

1A

0.6

0.4

0.2

0

0.4

0.2

0

2A

3A

2A

3A

3.5

4

4.5

5

5.5

6

6.5

7

7.5

8

3.5

4

4.5

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5 10

Input Voltage (V)

C026

C025

图 8-11. Typical Switching Frequency in Dropout

图 8-12. Typical Switching Frequency in Dropout

Mode V_OUT= 3.3 V, f_SW= 2.1 MHz

Mode V_OUT= 5 V, f_SW= 2.1 MHz

8.4.3 Minimum Switch On-Time

Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times

associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum

conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend

the minimum controllable duty cycle, the LMR33630 automatically reduces the switching frequency when the

minimum on-time limit is reached. This way the converter can regulate the lowest programmable output voltage

at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before

frequency foldback occurs is found in 方程式 2. The values of t_ONand f_SWcan be found in 节 7.5. As the input

voltage is increased, the switch on-time (duty-cycle) reduces to regulate the output voltage. When the on-time

reaches the limit, the switching frequency drops, while the on-time remains fixed. This relationship is highlighted

in 图 8-13 for a nominal switching frequency of 2.1 MHz.

V_OUT

V

Ç

IN

t_ON∂ f_SW

(2)

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2.6

2.4

2.2

2

1.8

1.6

1.4

1.2

1

1A

2A

3A

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38

Input Voltage (V)

C024

图 8-13. Switching Frequency versus Input Voltage V_OUT= 3.3 V

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9 Application and Implementation

Note

以下应用部分的信息不属于 TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The LMR33630 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC

voltage with a maximum output current of 3 A. The following design procedure can be used to select

components for the LMR33630. Alternately, the WEBENCH Design Tool can be used to generate a complete

design. This tool utilizes an iterative design procedure and has access to a comprehensive database of

components. This allows the tool to create an optimized design and allows the user to experiment with various

options.

Note

In this data sheet, the effective value of capacitance is defined as the actual capacitance under D.C.

bias and temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic

capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a large

voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias the

capacitance drops considerably. Large case sizes and/or higher voltage ratings are better in this

regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum

effective capacitance up to the required value. This can also ease the RMS current requirements on a

single capacitor. A careful study of bias and temperature variation of any capacitor bank should be

made in order to ensure that the minimum value of effective capacitance is provided.

9.2 Typical Application

图 9-1 shows a typical application circuit for the LMR33630. This device is designed to function over a wide

range of external components and system parameters. However, the internal compensation is optimized for a

certain range of external inductance and output capacitance. As a quick start guide, 图 9-1 provides typical

component values for a range of the most common output voltages. The values given in the table are typical.

Other values can be used to enhance certain performance criterion as required by the application. Note that for

the VQFN package, the input capacitors are split and placed on either side of the package; see 节 9.2.2.6 for

more details.

L

V_OUT

V_IN

6 V to 36 V

SW

VIN

EN

8 µH

5 V

3 A

C_IN

C_HF

220 nF

C_BOOT

10 µF

C_OUT

4x 22 µF

BOOT

0.1 µF

R_FBT

C_FF

PG

100 kΩ

PG

100 kΩ

VCC

FB

C_VCC

1 µF

PGND

AGND

R_FBB

24.9 kΩ

图 9-1. Example Application Circuit (400 kHz)

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9.2.1 Design Requirements

表 9-1 provides the parameters for our detailed design procedure example:

表 9-1. Detailed Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

12 V (6 V to 36 V)

5 V

Output voltage

Maximum output current

Switching frequency

0 A to 3 A

400 kHz

表 9-2. Typical External Component Values

C_OUT(RATED

L (µH) CAPACITANC

E)

ƒ_SW

(kHz)

V_OUT(V)

C_IN+ C_HF

C_BOOT

C_VCC

C_FF

R_FBT(Ω)

R_FBB(Ω)

400

1400

2100

400

3.3

5

6.8

2.2

1.2

8

4 × 22 µF

2 × 22 µF

4 × 22 µF

2 × 22 µF

4 × 22 µF

4 × 10 µF

100 k

43.2 k

24.9 k

9.09 k

10 µF + 220 nF

100 nF

1 µF

open

1400

2100

400

5

2.2

1.5

15

5

12

1400

2100

4.7

3.3

9.2.2 Detailed Design Procedure

The following design procedure applies to 图 9-1 and 表 9-1.

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR33630 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a

more compact design. For this example, 400 kHz was chosen.

9.2.2.3 Setting the Output Voltage

The output voltage of the LMR33630is externally adjustable using a resistor divider network. The range of

recommended output voltage is found in 节 7.3. The divider network is comprised of R_FBTand R_FBB, and closes

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the loop between the output voltage and the converter. The converter regulates the output voltage by holding the

voltage on the FB pin equal to the internal reference voltage, V_REF. The resistance of the divider is a

compromise between excessive noise pick-up and excessive loading of the output. Smaller values of resistance

reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for R_FBTis 100 kΩ;

with a maximum value of 1 MΩ. If a 1 MΩ is selected for R_FBT, then a feedforward capacitor must be used

across this resistor to provide adequate loop phase margin (see 节 9.2.2.9). Once R_FBTis selected, 方程式 3 is

used to select R_FBB. V_REFis nominally 1 V (see 节 7.5 for limits).

R_FBT

R_FBB

=

»

…

ÿ

V_OUT

V_REF

-1

Ÿ

⁄

(3)

For this 5-V example, R_FBT= 100 kΩ and R_FBB= 24.9 kΩ are chosen.

9.2.2.4 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on

the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the

maximum output current. Experience shows that the best value for inductor ripple current is 30% of the

maximum load current. Note that when selecting the ripple current for applications with much smaller maximum

load than the maximum available from the device, the maximum device current should be used. 方程式 4 can be

used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For this

example, K = 0.3 was chosen and an inductance L = 8.1 µH was found; the next standard value of 8 µH was

selected.

(

V

_IN- V_OUT

)

V_OUT

L =

∂

f_SW∂K ∂I_OUTmax

V

IN

(4)

Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current limit,

I_SC(see 节 7.5). This ensures that the inductor does not saturate even during a short circuit on the output. When

the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise

very rapidly. Although the valley current limit, I_LIMIT, is designed to reduce the risk of current run-away, a

saturated inductor can cause the current to rise to high values very rapidly. This can lead to component damage;

do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation

characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft

saturation, allowing for some relaxation in the current rating of the inductor. However, they have more core

losses at frequencies typically above 1 MHz. In any case, the inductor saturation current must not be less than

the device low-side current limit, I_LIMIT(see 节 7.5). The maximum inductance is limited by the minimum current

ripple required for the current mode control to perform correctly. As a rule-of-thumb, the minimum inductor ripple

current must be no less than about 10% of the device maximum rated current under nominal conditions.

V_OUT

L_MINí 0.28 ∂

f_SW

(5)

9.2.2.5 Output Capacitor Selection

The value of the output capacitor and the ESR of the capacitor determine the output voltage ripple and load

transient performance. The output capacitor bank is usually limited by the load transient requirements, rather

than the output voltage ripple. 方程式 6 can be used to estimate a lower bound on the total output capacitance

and an upper bound on the ESR, which is required to meet a specified load transient.

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K²

12

»

…

ÿ

DI_OUT

f_SW∂ DV_OUT∂K

C_OUT

í

∂

(

1- D

)

∂

(

1+ K

)

+

∂

(

2 - D

)

Ÿ

⁄

(

2 + K

)

∂ DV_OUT

ESR Ç

K²

1

»

ÿ

≈

’

2∂ DI_OUT1+ K +

∂∆1+

÷

…

Ÿ

∆

12

(1- D)

…

«

◊Ÿ

⁄

V_OUT

D =

V

IN

(6)

where

•

ΔV_OUT= output voltage transient

ΔI_OUT= output current transient

• K = ripple factor from 节 9.2.2.4

Once the output capacitor and ESR have been calculated, 方程式 7 can be used to check the peak-to-peak

output voltage ripple; V_r.

1

V_r@ DI_L∂ ESR²+

2

(

8∂ f_SW∂C_OUT

)

(7)

The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple

requirements.

For this example, a ΔV_OUT≤ 250 mV for an output current step of ΔI_OUT= 2 A is required. 方程式 6 gives a

minimum value of 52 µF and a maximum ESR of 0.11 Ω. Assuming a 20% tolerance and a 10% bias de-rating,

you arrive at a minimum capacitance of 72 µF. This can be achieved with a bank of 4 × 22-µF, 16-V ceramic

capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.

Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic

capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance. In

general, use a capacitor of at least 10 V for output voltages of 3.3 V or less and a capacitor of 16 V or more for

output voltages of 5 V and above.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and Bode plots are the best way to validate any given design and must always be completed

before the application goes into production. In addition to the required output capacitance, a small ceramic

placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1

nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board

parasitics.

The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000 µF,

whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the

regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-

up at full load and loop stability must be performed.

9.2.2.6 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple

current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is required

on the input of the LMR33630. This must be rated for at least the maximum input voltage that the application

requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input

voltage ripple and maintain the input voltage during load transients. In addition, a small case size, 220-nF

ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency

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bypass for the control circuits internal to the device. For this example a 4.7-µF, 50-V, X7R (or better) ceramic

capacitor is chosen. The 220 nF must also be rated at 50 V with an X7R dielectric. The VQFN (RNX) package

provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the

input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the

effectiveness of the input bypassing. In this example, a single 4.7-µF and two 100-nF ceramic capacitors at each

VIN/PGND location.

Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is

especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of

this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this

additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high

impedance.

Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate

worst case RMS value of this current can be calculated from 方程式 8 and must be checked against the

manufacturers' maximum ratings.

I_OUT

I_RMS

@

2

(8)

9.2.2.7 C_BOOT

The LMR33630 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor

stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of

100 nF and at least 10 V is required.

9.2.2.8 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output

requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, avoid

loading this output with any external circuitry. However, this output can be used to supply the pullup for the

power-good function (see 节 8.3.1). A value of 100 kΩ is a good choice in this case. The nominal output voltage

on VCC is 5 V; see 节 7.5 for limits. Do not short this output to ground or any other external voltage.

9.2.2.9 C_FFSelection

In some cases, a feedforward capacitor can be used across R_FBTto improve the load transient response or

improve the loop-phase margin. This is especially true when values of R_FBT> 100 kΩ are used. Large values of

R_FBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes

with the loop stability. A C_FFcan help to mitigate this effect. 方程式 9 can be used to estimate the value of C_FF.

The value found with 方程式 9 is a starting point; use lower values to determine if any advantage is gained by

the use of a C_FFcapacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters

with Feed-forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.

V_OUT∂C_OUT

C_FF

<

V_REF

V_OUT

120 ∂R_FBT

∂

(9)

9.2.2.10 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be

accomplished by using the circuit shown in 图 9-2. The input voltage at which the device turns on is designated

V_ON; while the turnoff voltage is V_OFF. First, a value for R_ENBis chosen in the range of 10 kΩ to 100 kΩ and

then 方程式 10 is used to calculate R_ENTand V_OFF

.

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VIN

R_ENT

EN

R_ENB

图 9-2. Setup for External UVLO Application

≈

’

V_ON

∆

÷

R_ENT

=

- 1 ∂R_ENB

÷

◊

V_{EN -H}

«

≈

’

V_{EN -HYS}

V_{EN -H}

∆

÷

V_OFF= V_ON∂ 1-

∆

«

◊

(10)

where

• V_ON= V_INturnon voltage

• V_OFF= V_INturnoff voltage

9.2.2.11 Maximum Ambient Temperature

As with any power conversion device, the LMR33630 dissipates internal power while operating. The effect of this

power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss and the effective thermal resistance,

R_θJAof the device and PCB combination. The maximum internal die temperature for the LMR33630 must be

limited to 125°C. This establishes a limit on the maximum device power dissipation and therefore the load

current. 方程式 11 shows the relationships between the important parameters. It is easy to see that larger

ambient temperatures (T_A) and larger values of R_θJAreduce the maximum available output current. The

converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating

conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.

Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be

measured directly. The correct value of R_θJAis more difficult to estimate. As stated in the Semiconductor and IC

Package Thermal Metrics Application Report, the value of R_θJAgiven in 节 7.4 is not valid for design purposes

and must not be used to estimate the thermal performance of the application. The values reported in that table

were measured under a specific set of conditions that are rarely obtained in an actual application.

(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

MAX

(

)

V_OUT

(11)

where

η = efficiency

•

The effective R_θJAis a critical parameter and depends on many factors such as power dissipation, air

temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent

component placement; to mention just a few. The HSOIC (DDA) package utilizes a die attach paddle, or thermal

pad (PAD) to provide a place to solder down to the PCB heat-sinking copper. This provides a good heat

conduction path from the regulator junction to the heat sink and must be properly soldered to the PCB heat sink

copper. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP is not available. This means that this

package exhibits a somewhat large value R_θJA. Typical examples of R_θJAvs copper board area can be found in

图 9-3 and 图 9-4. The copper area given in the graph is for each layer; the top and bottom layers are 2 oz.

copper each, while the inner layers are 1 oz. Typical curves of maximum output current vs ambient temperature

are shown in 图 9-5 and 图 9-6. This data was taken with a device/PCB combination giving an R_θJAas noted in

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the graph. It must be remembered that the data given in these graphs are for illustration purposes only, and the

actual performance in any given application depends on all of the previously mentioned factors.

70

65

60

55

50

45

40

44

42

40

38

36

34

32

30

28

26

24

22

20

RNX, 4L

60

DDA, 4L

60

0

10

20

30

40

50

70

0

10

20

30

40

50

70

Copper Area (cm²)

C005

Copper Area (cm²)

C003

图 9-3. Typical R_θJAversus Copper Area for a

Four-Layer Board and the HSOIC (DDA) Package

图 9-4. R_θJAversus Copper Board Area for the

VQFN (RNX) Package

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140

0

10 20 30 40 50 60 70 80 90 100 110 120 130 140

Ambient Temperature (°C)

C002

C006

V_IN= 12 V

ƒ_SW= 400 kHz

V_OUT= 5 V

V_IN= 12 V

ƒ_SW= 400 kHz

V_OUT= 5 V

R

_θJA= 30°C/W

R

_θJA= 50°C/W

图 9-5. Maximum Output Current versus Ambient

图 9-6. Maximum Output Current versus Ambient

Temperature

Use the following resources as a guide to optimal thermal PCB design and estimating R_θJAfor a given

application environment:

• Thermal Design by Insight not Hindsight

• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

• Semiconductor and IC Package Thermal Metrics

• Thermal Design Made Simple with LM43603 and LM43602

• PowerPAD^™Thermally Enhanced Package

• PowerPAD^™Made Easy

• Using New Thermal Metrics

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25°C. The circuit is shown in 图 9-31,

with the appropriate BOM from 表 9-3 or 表 9-4.

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

8V

5V

12V

24V

36V

12V

24V

36V

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

C009

C011

V_OUT= 5 V

400 kHz

DDA Package

V_OUT= 3.3 V

400 kHz

DDA Package

图 9-7. Efficiency

图 9-8. Efficiency

100

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

40

8V

5V

12V

24V

36V

12V

24V

36V

40

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

C012

C013

V_OUT= 3.3 V

1.4 MHz

DDA Package

V_OUT= 5 V

1.4 MHz

DDA Package

图 9-10. Efficiency

图 9-9. Efficiency

100

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

40

8V

5V

12V

24V

36V

12V

24V

36V

40

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

C014

C015

V_OUT= 5 V

2.1 MHz

DDA Package

V_OUT= 3.3 V

2.1 MHz

DDA Package

图 9-11. Efficiency

图 9-12. Efficiency

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100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

8V

12V

24V

36V

12V

24V

36V

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

C007

C008

V_OUT= 5 V

400 kHz

RNX Package

V_OUT= 3.3 V

400 kHz

RNX Package

图 9-13. Efficiency

图 9-14. Efficiency

100

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

8V

5V

12V

24V

36V

12V

24V

36V

50

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

C019

C020

V_OUT= 5 V

1.4 MHz

RNX Package

V_OUT= 3.3 V

1.4 MHz

RNX Package

图 9-15. Efficiency

图 9-16. Efficiency

100

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

8V

12V

24V

36V

12V

24V

36V

50

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

C010

C009

V_OUT= 5 V

2.1 MHz

RNX Package

V_OUT= 3.3 V

2.1 MHz

RNX Package

图 9-17. Efficiency

图 9-18. Efficiency

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5.06

5.055

5.05

32

30

28

26

24

22

20

8V

12V

24V

36V

5.045

5.04

5.035

5.03

5.025

5.02

5.015

5V

5.01

0

0.5

1

1.5

2

2.5

3

3.5

0

5

10

15

20

25

30

35

40

Output Current (A)

Input Voltage (V)

C011

C017

V_OUT= 5 V

I_OUT= 0 A

R_FBT= 1 MΩ

图 9-19. Line and Load Regulation

图 9-20. Input Supply Current

10000000

1000000

100000

10000

1000

0.6

0.5

0.4

0.3

0.2

0.1

0

9

PWM

8V

100

12V

24V

36V

PFM

;

10

5V

35

1

0.00001 0.0001

0.001

0.01

0.1

1

10

0

5

10

15

20

25

30

40

Output Current (A)

C014

Input Voltage (V)

C012

V_OUT= 5 V

ƒ_SW= 400 kHz

V_OUT= 5 V

ƒ_SW= 400 kHz

图 9-22. Switching Frequency versus Output

图 9-21. Mode Change Thresholds

Current

VOUT,

300mV/Div

VOUT,

300mV/Div

Output Current,

1A/Div

Output Current,

1A/Div

100µs/Div

0

V_IN= 12 V

V_OUT= 5 V

V_IN= 12 V

V_OUT= 5 V

t_f= t_r= 2 µs

I_OUT= 0 A to 3 A

t_f= t_r= 2 µs

I_OUT= 1 A to 3 A

图 9-23. Load Transient

图 9-24. Load Transient

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3.35

3.345

3.34

32

30

28

26

24

22

20

5V

12V

24V

36V

3.335

3.33

3.325

3.32

3.315

3.31

3.3V

0

5

10

15

20

25

30

35

40

0

0.5

1

1.5

2

2.5

3

3.5

Input Voltage (V)

Output Current (A)

C016

C011

V_OUT= 3.3 V

I_OUT= 0 A

V_OUT= 3.3 V

R_FBT= 1 MΩ

图 9-25. Line and Load Regulation

图 9-26. Input Supply Current

10000000

1000000

100000

10000

1000

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

9

PWM

5V

100

12V

24V

36V

10

PFM

;

3.3V

35

1

0.00001 0.0001

0.001

0.01

0.1

1

10

0

5

10

15

20

25

30

40

Output Current (A)

C015

Input Voltage (V)

C012

V_OUT= 3.3 V

ƒ_SW= 400 kHz

V_OUT= 3.3 V

ƒ_SW= 400 kHz

图 9-28. Switching Frequency versus Output

图 9-27. Mode Change Thresholds

Current

VOUT,

300mV/Div

VOUT,

300mV/Div

Output Current,

1A/Div

Output Current,

1A/Div

100µs/Div

0

V_IN= 12 V

t_f= t_r= 2 µs

V_OUT= 3.3 V

V_IN= 12 V

V_OUT= 3.3V

I_OUT= 1 A to 3 A

I_OUT= 0 A to 3 A

t_f= t_r= 2 µs

图 9-29. Load Transient

图 9-30. Load Transient

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L

V_OUT

V_IN

SW

VIN

EN

U1

C_BOOT

C_IN

C_HF

C_OUT

BOOT

0.1 µF

R_FBT

PG

100 kΩ

PG

100 kΩ

VCC

FB

C_VCC

1 µF

PGND

AGND

R_FBB

图 9-31. Circuit for Application Curves

The values in this table were selected to enhance certain performance criteria and may not represent typical

values.

表 9-3. BOM for Typical Application Curves DDA Package

V_OUT

3.3 V

5 V

FREQUENCY

400 kHz

R_FBB

C_OUT

C_IN+ C_HF

L

U1

4 × 22 µF

1 × 10 µF + 1 × 220 nF

LMR33630ADDA

LMR33630BDDA

LMR33630CDDA

LMR33630ADDA

LMR33630BDDA

LMR33630CDDA

43.3 kΩ

24.9 kΩ

6.8 µH, 14 mΩ

2.2 µH, 11.4 mΩ

1.2 µH, 16 mΩ

8 µH, 14 mΩ

2.2 µH, 11.4 mΩ

1.5 µH, 8.2 mΩ

1400 KHz

2100 kHz

400 kHz

5 V

1400 KHz

2100 kHz

5 V

表 9-4. BOM for Typical Application Curves RNX Package

V_OUT

3.3 V

5 V

FREQUENCY

400 kHz

R_FBB

C_OUT

C_IN+ C_HF

L

U1

4 × 22 µF

2 × 4.7 µF + 2 × 100 nF

LMR33630ARNX

LMR33630BRNX

LMR33630CRNX

LMR33630ARNX

LMR33630BRNX

LMR33630CRNX

43.3 kΩ

24.9 kΩ

6.8 µH, 14 mΩ

2.2 µH, 11.4 mΩ

1.2 µH, 7 mΩ

8 µH, 25 mΩ

2.2 µH, 11.4 mΩ

1.5 µH, 8.2 mΩ

1400 KHz

2100 kHz

400 kHz

5 V

1400 KHz

2100 kHz

5 V

9.3 What to Do and What Not to Do

• Don't: Exceed the Absolute Maximum Ratings.

• Don't: Exceed the ESD Ratings .

• Don't: Exceed the Recommended Operating Conditions.

• Don't: Allow the EN input to float.

• Don't: Allow the output voltage to exceed the input voltage, nor go below ground.

• Don't: Use the value of R_θJAgiven in the table to design your application. Use the information in 节 9.2.2.11.

• Do: Follow all the guidelines and suggestions found in this data sheet before committing the design to

production. TI application engineers are ready to help critique your design and PCB layout to help make your

project a success (see Support Resources).

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Power Supply Recommendations

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and

Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable of

delivering the required input current to the loaded regulator. The average input current can be estimated with 方

程式 12, where η is the efficiency.

V_OUT∂I_OUT

I_IN

=

V_IN∂ h

(12)

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input

capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to the

regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is

applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the

regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the

distance from the input supply to the regulator and/or use an aluminum or tantalum input capacitor in parallel

with the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and

reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and

help to hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability, as well as some of the effects mentioned above, unless it is designed carefully. The user guide

AN-2162 Simple Success With Conducted EMI From DCDC Converters provides helpful suggestions when

designing an input filter for any switching regulator.

In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not

recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the

output voltage of the regulator, the output capacitors discharge through the device back to the input. This

uncontrolled current flow can damage the device.

The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input

test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of

the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If

this scenario is considered likely, then a Schottky diode between the input supply and the output should be used.

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10 Layout

10.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can

disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB

layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,

the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter, the

most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power ground, as

shown in 图 10-1. This loop carries large transient currents that can cause large transient voltages when reacting

with the trace inductance. These unwanted transient voltages will disrupt the proper operation of the converter.

Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce

the parasitic inductance. 图 10-2 and 图 10-3 show recommended layouts for the critical components of the

LMR33630.

1. Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. VIN and

GND pins are adjacent, simplifying the input capacitor placement. With the VQFN package there are two

VIN/PGND pairs on either side of the package. This provides for a symmetrical layout and helps minimize

switching noise and EMI generation. A wide VIN plane must be used on a lower layer to connect both of the

VIN pairs together to the input supply; see 图 10-3.

2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device

and routed with short, wide traces to the VCC and GND pins.

3. Use wide traces for the C_BOOTcapacitor. Place C_BOOTclose to the device with short/wide traces to the

BOOT and SW pins. For the VQFN package, it is important to route the SW connection under the device to

the NC pin, and use this path to connect the BOOT capacitor to SW.

4. Place the feedback divider as close as possible to the FB pin of the device. Place R_FBB, R_FBT, and C_FF,

if used, physically close to the device. The connections to FB and GND must be short and close to those

pins on the device. The connection to V_OUTcan be somewhat longer. However, this latter trace must not be

routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of

the regulator.

5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act

as a heat dissipation path.

6. Connect the thermal pad to the ground plane. The SOIC package has a thermal pad (PAD) connection

that must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an

electrical ground connection for the regulator. The integrity of this solder connection has a direct bearing on

the total effective R_θJAof the application.

7. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces

any voltage drops on the input or output paths of the converter and maximizes efficiency.

8. Provide enough PCB area for proper heat sinking. As stated in 节 9.2.2.11, enough copper area must be

used to ensure a low R_θJA, commensurate with the maximum load current and ambient temperature. Make

the top and bottom PCB layers with two-ounce copper; and no less than one ounce. With the SOIC package,

use an array of heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB

layer. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to

the inner layer heat-spreading ground planes.

9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as

possible. At the same time the total area of this node should be minimized to help reduce radiated EMI.

See the following PCB layout resources for additional important guidelines:

• Layout Guidelines for Switching Power Supplies

• Simple Switcher PCB Layout Guidelines

• Construction Your Power Supply- Layout Considerations

• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

VIN

KEEP

CURRENT

LOOP

C_IN

SW

SMALL

GND

图 10-1. Current Loops with Fast Edges

10.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane

provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control

circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass

capacitors. PGND pins are connected directly to the source of the low side MOSFET switch, and also connected

directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching

frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be

constrained to one side of the ground planes. The other side of the ground plane contains much less noise and

must be used for sensitive routes.

TI recommends providing adequate device heat sinking by utilizing the thermal pad (PAD) of the device as the

primary thermal path. Use a minimum 4 × 3 array of 10-mil thermal vias to connect the PAD to the system

ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for

system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the

copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with

enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and

lower thermal resistance.

32

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

10.2 Layout Example

GND

INDUCTOR

HEATSINK

VOUT

C_OUT

C_HF

GND

C_IN

EN

PGOOD

C_VCC

VIN

R_FBB

GND

HEATSINK

VIA

Ground Plane

VIA

Bottom

Top Trace

Bottom Trace

图 10-2. Example Layout for HSOIC (DDA) Package

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

VOUT

INDUCTOR

C_OUT

GND

C_IN

C_HF

1

C_IN

C_HF

12

11

10

9

2

3

VIN

EN

VIN

4

8

PGOOD

5

6

7

C_VCC

R_FBB

GND

HEATSINK

INNER GND PLANE

Top Trace/Plane

Inner GND Plane

VIN Strap on Inner Layer

VIA to Signal Layer

Top

Inner GND Plane

VIN Strap and

GND Plane

VIA to GND Planes

VIA to VIN Strap

Signal traces

and GND Plane

Trace on Signal Layer

图 10-3. Example Layout for VQFN Package

34

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM33630 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• Thermal Design by Insight not Hindsight

• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

• Semiconductor and IC Package Thermal Metrics

• Thermal Design Made Simple with LM43603 and LM43602

• PowerPAD^TMThermally Enhanced Package

• PowerPAD^TMMade Easy

• Using New Thermal Metrics

• Layout Guidelines for Switching Power Supplies

• Simple Switcher PCB Layout Guidelines

• Construction Your Power Supply- Layout Considerations

• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

11.5 Trademarks

HotRod^™, TI E2E^™are trademarks of Texas Instruments.

PowerPAD^™is a trademark of TI.

WEBENCH^®is a registered trademark of Texas Instruments.

SIMPLE SWITCHER^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 静电放电警告

静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

36

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ZHCSHQ3F – AUGUST 2017 – REVISED NOVEMBER 2020

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RNX 12

2 x 3 mm, 0.5 mm pitch

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224286/A

PACKAGE OUTLINE

RNX0012B

VQFN-HR - 0.9 mm max height

SCALE 4.500

PLASTIC QUAD FLATPACK - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.05)

A

-

A

4

0

.

0

SECTION A-A

TYPICAL

0.9

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

1

SYMM

(0.2) TYP

5

7

4X 0.5

8

4

2X

0.675

PKG

2X

1.725

1.525

2X

1.125

0.65

A

11

1

12

0.3

0.2

0.1

PIN 1 ID

11X

0.3

0.2

C B A

C

0.5

0.3

11X

0.05

4223969/C 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RNX0012B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.25)

12

11X (0.6)

11X

1

2X (0.65)

11

(0.25)

(1.825)

(0.788)

2X

(1.125)

PKG

2X

(0.675)

4X (0.5)

8

(1.4)

4

(R0.05) TYP

5

7

SYMM

(1.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:25X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

PADS 1, 2, 10-12

(PREFERRED)

SOLDER MASK DETAILS

4223969/C 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RNX0012B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (0.25)

2X (0.812)

12

11X (0.6)

11X (0.25)

1

11

2X

(0.65)

(1.294)

EXPOSED METAL

PKG

2X

(1.125)

(0.282)

2X (0.675)

4X (0.5)

8

(1.4)

4

(R0.05) TYP

5

7

SYMM

(1.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PAD 12

87.7% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4223969/C 10/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RNX0012C

A

2.1

1.9

B

PIN 1 INDEX AREA

3.1

2.9

0.1 MIN

(0.13)

SECTION A-A

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

1

PKG

(0.2) TYP

5

7

(0.16)

4X 0.5

8

4

2X

0.675

PKG

2X

1.125

1.725

1.525

2X

0.65

A

11

1

12

PIN 1 ID

0.3

0.2

0.3

0.2

11X

0.5

0.3

0.1

C A B

C

11X

0.05

4225021/C 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RNX0012C

(0.25)

11X (0.6)

12

11X (0.25)

2X (0.65)

11

1

(1.825)

2X

(1.125)

(0.7875)

PKG

2X

(0.675)

4X (0.5)

8

(1.4)

4

5

7

PKG

(1.8)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE: 20X

0.075 MAX

ALL AROUND

0.075 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225021/C 05/2022

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN-HR - 1 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RNX0012C

2X (0.25)

2X (0.812)

11X (0.6)

11X (0.25)

12

2X (0.65)

1

11

EXPOSED

METAL

2X

(1.125)

(1.294)

(0.281)

PKG

2X

(0.675)

4X (0.5)

8

(1.4)

4

5

7

PKG

(1.8)

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.100 mm THICK STENCIL

FOR PAD 12

87.7% PRINTED COVERAGE BY AREA

SCALE: 20X

4225021/C 05/2022

NOTES: (continued)

5.

Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DDA0008J

PowerPAD^TMSOIC - 1.7 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.2

5.8

TYP

SEATING PLANE

PIN 1 ID

AREA

A

0.1 C

6X 1.27

8

1

2X

5.0

4.8

3.81

NOTE 3

4

5

0.51

8X

0.31

4.0

3.8

1.7 MAX

B

0.1

C A

B

NOTE 4

0.25

0.10

TYP

SEE DETAIL A

5

4

EXPOSED

THERMAL PAD

0.25

3.1

2.5

GAGE PLANE

0.15

0.00

0 - 8

1.27

0.40

1

8

DETAIL A

TYPICAL

2.6

2.0

4221637/B 03/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DDA0008J

PowerPAD^TMSOIC - 1.7 mm max height

PLASTIC SMALL OUTLINE

(2.95)

NOTE 9

SOLDER MASK

DEFINED PAD

(2.6)

SOLDER MASK

OPENING

SEE DETAILS

8X (1.55)

1

8

8X (0.6)

(3.1)

SOLDER MASK

SYMM

(1.3)

TYP

OPENING

(4.9)

NOTE 9

6X (1.27)

5

4

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

SYMM

(5.4)

(1.3) TYP

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221637/B 03/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

DDA0008J

PowerPAD^TMSOIC - 1.7 mm max height

PLASTIC SMALL OUTLINE

(2.6)

BASED ON

0.125 THICK

STENCIL

8X (1.55)

1

8

8X (0.6)

(3.1)

SYMM

BASED ON

0.127 THICK

STENCIL

6X (1.27)

5

4

SEE TABLE FOR

METAL COVERED

BY SOLDER MASK

SYMM

(5.4)

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.91 X 3.47

2.6 X 3.1 (SHOWN)

2.37 X 2.83

0.125

0.150

0.175

2.20 X 2.62

4221637/B 03/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDA0008B

PowerPAD^TMSOIC - 1.7 mm max height

S

C

A

L

E

2

.

4

0

PLASTIC SMALL OUTLINE

C

6.2

5.8

TYP

SEATING PLANE

A

PIN 1 ID

AREA

0.1 C

6X 1.27

8

1

2X

5.0

4.8

3.81

NOTE 3

4

5

0.51

8X

0.31

4.0

3.8

1.7 MAX

B

0.25

C A B

NOTE 4

0.25

0.10

TYP

SEE DETAIL A

5

4

EXPOSED

THERMAL PAD

0.25

3.4

2.8

9

GAGE PLANE

0.15

0.00

0 - 8

1.27

0.40

1

8

DETAIL A

TYPICAL

2.71

2.11

4214849/A 08/2016

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MS-012.

www.ti.com

EXAMPLE BOARD LAYOUT

DDA0008B

PowerPAD^TMSOIC - 1.7 mm max height

PLASTIC SMALL OUTLINE

(2.95)

NOTE 9

SOLDER MASK

DEFINED PAD

(2.71)

SOLDER MASK

OPENING

SEE DETAILS

8X (1.55)

1

8

8X (0.6)

(3.4)

SOLDER MASK

OPENING

TYP

9

SYMM

(1.3)

(4.9)

NOTE 9

6X (1.27)

5

4

(R0.05) TYP

METAL COVERED

BY SOLDER MASK

SYMM

(5.4)

(

0.2) TYP

VIA

(1.3) TYP

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DDA0008B

PowerPAD^TMSOIC - 1.7 mm max height

PLASTIC SMALL OUTLINE

(2.71)

BASED ON

0.125 THICK

STENCIL

8X (1.55)

(R0.05) TYP

8

1

8X (0.6)

(3.4)

BASED ON

0.125 THICK

STENCIL

SYMM

9

6X (1.27)

5

4

METAL COVERED

BY SOLDER MASK

SYMM

(5.4)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.03 X 3.80

2.71 X 3.40 (SHOWN)

2.47 X 3.10

0.125

0.150

0.175

2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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型号：	LMR33630ADDA
厂家：	TEXAS INSTRUMENTS
描述：	具有超低 EMI 的 SIMPLE SWITCHER® 3.8V 至 36V、3A 同步降压转换器 \| DDA \| 8 \| -40 to 125 转换器
文件：	总56页 (文件大小：4433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMR33630ADDA [TI]

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