LMR33630APCQRNXRQ1 [TI]
LMR336x0AP-Q1 3.8-V to 36-V, 2-A and 3-A Synchronous Step-Down Voltage Converter;
| 型号： | LMR33630APCQRNXRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMR336x0AP-Q1 3.8-V to 36-V, 2-A and 3-A Synchronous Step-Down Voltage Converter |
| 文件： | 总48页 (文件大小：4806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR33620AP-Q1, LMR33630AP-Q1
SNVSBQ5 – JUNE 2021
LMR336x0AP-Q1 3.8-V to 36-V, 2-A and 3-A Synchronous Step-Down Voltage
Converter
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Configured for rugged automotive applications
– Input voltage range: 3.8 V to 36 V
– Output voltage range: 1 V to 24 V
– Output current: 2 A, 3 A
– 75-mΩ/50-mΩ RDS-ON power MOSFETs
– Peak-current-mode control
– Short minimum on time of 68 ns
– Frequency: 400 kHz, 2.1 MHz
– Integrated compensation network
Low EMI and switching noise
– HotRod™ package
– Parallel input current paths
The LMR336x0AP-Q1 automotive-qualified regulator
is an easy-to-use, synchronous, step-down DC/DC
converter that delivers best-in-class efficiency for
rugged applications. The LMR336x0AP-Q1 drives up
to 2 A or 3 A of load current from an input of up
to 36 V. The LMR336x0AP-Q1 provides high light
load efficiency and output accuracy in a very small
solution size. Features such as a power-good flag
and precision enable provide both flexible and easy-
to-use solutions for a wide range of applications. The
LMR336x0AP-Q1 automatically folds back frequency
at light load to improve efficiency. Integration
eliminates most external components and provides
a pinout designed for simple PCB layout. Protection
features include thermal shutdown, input undervoltage
lockout, cycle-by-cycle current limit, and hiccup short-
circuit protection. The LMR336x0AP-Q1 is available
in a 12-pin 3-mm × 2-mm next generation VQFN
package with wettable flanks.
•
•
•
•
High power conversion at all loads
– Peak efficiency > 95%
– Low shutdown quiescent current of 5 µA
– Low operating quiescent current of 25 µA
Create a custom design using the LMR336x0AP-
Q1 with the WEBENCH® Power Designer
Device Information
PART NUMBER
LMR33620AP-Q1
LMR33630AP-Q1
PACKAGE(1)
BODY SIZE (NOM)
•
VQFN (12)
3.00 mm × 2.00 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
Infotainment and cluster
Telematics control unit
BOOT
VIN
CIN
VIN
EN
CBOOT
L1
VOUT
COUT
SW
PGND
VCC
PG
FB
RFBT
CVCC
RFBB
AGND
Simplified Schematic
Minimum Component Example
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR33620AP-Q1, LMR33630AP-Q1
SNVSBQ5 – JUNE 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................6
7.6 Timing Characteristics ................................................7
7.7 System Characteristics .............................................. 8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 18
9.3 What to Do and What Not to Do............................... 29
10 Power Supply Recommendations..............................30
11 Layout...........................................................................31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 33
12 Device and Documentation Support..........................34
12.1 Device Support....................................................... 34
12.2 Documentation Support.......................................... 34
12.3 Support Resources................................................. 34
12.4 Receiving Notification of Documentation Updates..34
12.5 Trademarks.............................................................35
12.6 Electrostatic Discharge Caution..............................35
12.7 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
DATE
REVISION
NOTES
June 2021
*
Initial release
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5 Device Comparison Table
DEVICE OPTION
PACKAGE
FREQUENCY
400 kHz
RATED CURRENT
OUTPUT VOLTAGE
LMR33630APAQRNXRQ1
LMR33630APCQRNXRQ1
LMR33620APAQRNXRQ1
LMR33620APCQRNXRQ1
3 A
3 A
2 A
2 A
2100 kHz
400 kHz
RNX (12-pin VQFN)
3 × 2 × 0.85 mm
Adjustable
2100 kHz
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6 Pin Configuration and Functions
SW
12
1
2
11 PGND
PGND
10 VIN
VIN
9
8
EN
PG
3
4
NC
BOOT
6
7
5
FB
AGND
VCC
Figure 6-1. 12-Pin VQFN RNX Package (Top View)
Table 6-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1, 11
2, 10
3
Power ground terminal. Connect to system ground and AGND. Connect to a bypass capacitor with short wide
traces.
PGND
VIN
G
P
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and PGND.
On the VQFN package, connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin. This pin has no internal connection to the regulator.
NC
—
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this pin to
the SW pin. On the VQFN package, connect the SW pin to NC on the PCB. This simplifies the connection from
the CBOOT capacitor to the SW pin.
4
5
BOOT
VCC
P
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be
used as logic supply for power-good flag. Connect a high quality 1-µF capacitor from this pin to GND.
Analog ground for regulator and system. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
6
AGND
FB
G
A
A
A
P
7
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not ground.
Open-drain power-good flag output. Connect to a suitable voltage supply through a current limiting resistor.
High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when not used.
8
PG
9
EN
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float.
Regulator switch node. Connect to the power inductor. On the VQFN package, the SW pin must be connected
to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW pin.
12
SW
(1) A = Analog, P = Power, G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
PARAMETER
MIN
–0.3
–0.3
–0.3
0
MAX
38
UNIT
VIN to PGND
EN to AGND(2)
FB to AGND
VIN + 0.3
5.5
V
PG to AGND(2)
22
Voltages
AGND to PGND
–0.3
–0.3
–3.5
–0.3
–0.3
–40
–55
0.3
SW to PGND
VIN + 0.3
38
SW to PGND less than 100-ns transients
BOOT to SW
V
5.5
VCC to AGND(4)
5.5
TJ
Junction temperature(3)
Storage temperature
150
°C
°C
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(3) Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
(4) Under some operating conditions the VCC LDO voltage can increase beyond 5.5 V.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating temperature range of –40°C to 125°C (unless otherwise noted) (1)
MIN
3.8
0
MAX
UNIT
VIN to PGND
EN (2)
36
VIN
18
24
2
Input voltage
V
PG(2)
0
(3)
Adjustable output voltage
Output current
VOUT
1
V
A
A
IOUT, LMR33620AP-Q1
IOUT, LMR33630AP-Q1
0
Output current
0
3
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Section 7.5.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
(3) The maximum output voltage can be extended to 95% of VIN; contact TI for details. Under no conditions should the output voltage be
allowed to fall below zero volts.
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7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application. For design information see Maximum Ambient Temperature
section.
LMR336x0AP-Q1
THERMAL METRIC(1) (2)
RNX (VQFN)
12 PINS
72.5(2)
35.9
UNIT
RθJA
Junction-to-ambient thermal resistance (JESD 51-7)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
23.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
23.5
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes.
These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For design information see Maximum Ambient Temperature section.
7.5 Electrical Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Minimum operating input
voltage
VIN
3.8
34
10
V
Nonswitching input current;
measured at VIN pin (2)
IQ
VFB = 1.2 V
EN = 0
24
5
µA
µA
Shutdown quiescent current;
measured at VIN pin
ISD
ENABLE
VEN-VCC-H
EN input level required to turn
on the internal LDO
Rising threshold
Falling threshold
Rising threshold
1
V
V
V
EN input level required to turn
off the internal LDO
VEN-VCC-L
VEN-H
0.3
1.2
EN input level required to start
switching
1.231
1.26
VEN-HYS
ILKG-EN
INTERNAL SUPPLIES
Hysteresis below VEN-H
Hysteresis below VEN-H; falling
VEN = 3.3 V
100
0.2
mV
nA
Enable input leakage current
Internal LDO output voltage
appearing at the VCC pin
VCC
6 V ≤ VIN ≤ 36 V
4.75
5
5.25
V
V
Bootstrap voltage
undervoltage lockout
threshold(3)
VBOOT-UVLO
2.2
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage; ADJ option
0.985
1
1.015
50
V
Current into FB pin; ADJ
option
IFB
FB = 1 V
0.2
nA
CURRENT LIMITS(4)
ISC
High-side current limit
High-side current limit
Low-side current limit
LMR33620AP-Q1
LMR33630AP-Q1
LMR33620AP-Q1
2.9
3.85
1.95
3.5
4.5
4
5.05
2.9
A
A
A
ISC
ILIMIT
2.45
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Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply:
VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILIMIT
Low-side current limit
LMR33630AP-Q1
2.9
3.5
4.1
A
A
A
A
IPEAK-MIN
IPEAK-MIN
IZC
Minimum peak inductor current LMR33620AP-Q1
Minimum peak inductor current LMR33630AP-Q1
Zero current detector threshold
0.54
0.69
-0.106
SOFT START
tSS
Internal soft-start time
2.9
4
6
ms
POWER GOOD (PG PIN)
Power-good upper threshold -
VPG-HIGH-UP
VPG-HIGH-DN
VPG-LOW-UP
VPG-LOW-DN
tPG
% of FB voltage
% of FB voltage
% of FB voltage
% of FB voltage
105%
103%
92%
90%
60
107%
105%
94%
110%
108%
97%
95%
170
rising
Power-good upper threshold -
falling
Power-good lower threshold -
rising
Power-good lower threshold -
falling
92%
Power-good glitch filter
delay(1)
µs
Ω
VIN = 12 V, VEN = 4 V
VEN = 0 V
76
35
150
60
RPG
Power-good flag RDSON
Minimum input voltage for
proper PG function
VIN-PG
50-µA, EN = 0 V
2
V
V
VPG
PG logic low output
50-µA, EN = 0 V, VIN = 2V
0.2
OSCILLATOR
ƒSW
Switching frequency
Switching frequency
"A" Version, RNX package
"C" Version, RNX package
340
1.8
400
2.1
460
2.3
kHz
ƒSW
MHz
MOSFETS
High-side MOSFET ON-
resistance
RDS-ON-HS
RDS-ON-LS
RNX package
RNX package
75
50
145
95
mΩ
mΩ
Low-side MOSFET ON-
resistance
(1) See Power-Good Flag Output for details.
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge CBOOT
.
(4) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
7.6 Timing Characteristics
Limits apply over the operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and
maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric
norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN
= 12 V, VEN = 4 V.
MIN
NOM
MAX
UNIT
tON-MIN
tOFF-MIN
tON-MAX
Minimum switch on-time
Minimum switch off time
Maximum switch on time
RNX package
RNX package
68
80
ns
52
70
ns
7
9
µs
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7.7 System Characteristics
The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to
the case of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
VOUT = 3.3 V, IOUT= 0 A
3.8
36
V
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to
max. load
–1.5%
–1.5%
–1.5%
–1.5%
2.5%
1.5%
2.5%
1.5%
Output voltage regulation for VOUT = 5 V(1)
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to
max. load
VOUT
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A
to max. load
Output voltage regulation for VOUT = 3.3
V(1)
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A
to max. load
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ
ISUPPLY
Input supply current when in regulation
25
µA
VOUT = 5 V, IOUT = 1A
Dropout at –1% of regulation,
ƒSW = 140 kHz
VDROP
DMAX
VHC
Dropout voltage; (VIN – VOUT
)
150
mV
Maximum switch duty cycle(2)
VIN = VOUT = 12 V, IOUT = 1 A
98%
0.4
FB pin voltage required to trip short-circuit
Hiccup mode
V
tHC
tD
Time between current-limit hiccup burst
Switch voltage dead time
94
2
ms
ns
°C
°C
Shutdown temperature
Recovery temperature
165
148
TSD
Thermal shutdown temperature
(1) Deviation is with respect to VIN =12 V, IOUT = 1 A.
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒMIN
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
=
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 12 V
36
34
32
30
28
26
24
22
20
12
11
10
9
8
7
6
5
4
-40C
25C
-40C
25C
3
2
1
125C
125C
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Input Voltage (V)
Input Voltage (V)
C005
C003
VFB = 1.2 V
EN = 0 V
Figure 7-1. Non-Switching Input Supply Current
Figure 7-2. Shutdown Supply Current
1000
1.35
1.30
1.25
1.20
1.15
1.10
900
800
700
-40C
600
25C
125C
35
UP
DN
1.05
1.00
500
0
20
40
60
80
100 120 140
0
5
10
15
20
25
30
40
œ40 œ20
Temperature (C)
Input Voltage (V)
C006
C004
VOUT = 0 V
ƒS = 400 kHz
See Figure 9-27
Figure 7-4. Precision Enable Thresholds
Figure 7-3. Short-Circuit Output Current
1,200
1,100
1,000
900
800
700
-40C
25C
125C
600
500
400
DN
UP
5
10
15
20
25
30
35
40
Input Voltage (V)
C006
0
IOUT = 0 A
VOUT = 5 V
See Figure 9-27
INPUT VOLTAGE (1V/Div)
ƒSW = 400 kHz
IOUT = 1 mA
See Figure 9-27
Figure 7-6. IPEAK-MIN
Figure 7-5. UVLO Thresholds
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8 Detailed Description
8.1 Overview
The LMR336x0AP-Q1 is a synchronous peak-current-mode buck regulator designed for a wide variety of
applications. Advanced high speed circuitry allows the device to regulate from an input voltage of 20 V, while
providing an output voltage of 3.3 V at a switching frequency of 2.1 MHz. The innovative architecture allows
the device to regulate a 3.3-V output from an input of only 3.8 V. The regulator automatically switches modes
between PFM and PWM, depending on load. At heavy loads, the device operates in PWM at a constant
switching frequency. At light loads, the mode changes to PFM with diode emulation allowing DCM. This reduces
the input supply current and keeps efficiency high. The device features internal loop compensation, which
reduces design time and requires fewer external components than externally compensated regulators.
The LMR336x0AP-Q1 is available in an ultra-miniature VQFN package with wettable flanks. This package
features extremely small parasitic inductance and resistance, enabling very high efficiency while minimizing
switch node ringing and dramatically reducing EMI. The VIN/PGND pin layout is symmetrical on either side of
the VQFN package. This allows the input current magnetic fields to partially cancel, resulting in reduce EMI
generation.
8.2 Functional Block Diagram
VCC
VIN
INT. REG.
BIAS
OSCILLATOR
BOOT
ENABLE
LOGIC
HS CURRENT
SENSE
EN
ꢀ
1.0V
Reference
PWM
COMP.
ERROR
AMPLIFIER
+
-
CONTROL
LOGIC
DRIVER
SW
+
-
FB
LS CURRENT
SENSE
PFM MODE
CONTROL
PG
POWER GOOD
CONTROL
AGND PGND
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8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR336x0AP-Q1 can be used to reset a system
microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault
conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents
false flag operation for short excursions of the output voltage, such as during line and load transients. The timing
parameters of the glitch filter are found in Section 7.5. Output voltage excursions lasting less than tPG do not trip
the power-good flag. Power-good operation can best be understood by reference to Figure 8-1 and Figure 8-2.
Note that during initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted
to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered
during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT through a 100-kΩ resistor, as desired. If this function is not
needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN low,
power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the power-good
flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device is
enabled and about 65 mA when the device is disabled. The internal current limit protects the device from any
transient currents that can occur when discharging a filter capacitor connected to this output.
VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN
(105%)
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
Figure 8-1. Static Power-Good Operation
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Glitches do not cause false operation nor reset timer
VOUT
V
PG-LOW-UP (95%)
PG-LOW-DN (93%)
V
< tPG
PG
tPG
Figure 8-2. Power-Good-Timing Behavior
tPG
tPG
8.3.2 Enable and Start-Up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see Section 9.2.2.10). Applying a voltage of
≥ VEN-VCC_H causes the device to enter Standby mode, powering the internal VCC, but not producing an output
voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter Start-up mode and start
the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the regulator stops running and
enters Standby mode. Further decrease in the EN voltage to below VEN-VCC-L completely shuts down the device.
This behavior is shown in Figure 8-3. The EN input can be connected directly to VIN if this feature is not needed.
This input must not be allowed to float. The values for the various EN thresholds can be found in Section 7.5.
The LMR336x0AP-Q1 uses a reference-based soft start that prevents output voltage overshoots and large
inrush currents as the regulator is starting up. A typical start-up waveform is shown in Figure 8-4, indicating
typical timings. The rise time of the output voltage is about 4 ms (see Section 7.5).
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EN
VEN-H
VEN-H œ VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VOUT
VOUT
0
Figure 8-3. Precision Enable Behavior
EN, 3V/Div
VOUT, 2V/Div
PG, 5V/Div
Inductor Current, 3A/Div
2ms/Div
Figure 8-4. Typical Start-Up Behavior VIN = 12 V, VOUT = 5 V, IOUT = 3 A
8.3.3 Current Limit and Short Circuit
The LMR336x0AP-Q1 incorporates both peak and valley inductor current limit to provide protection to the device
from overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor
current runaway during short circuits on the output, while both peak and valley limits work together to limit the
maximum output current of the converter. Cycle-by-cycle current limit is used for overloads, while Hiccup mode
is used for sustained short circuits. Finally, a zero current detector is used on the low-side power MOSFET to
implement DEM at light loads (see the Glossary). The typical value of this current limit is found under IZC in
Section 7.5.
When the device is overloaded, the valley of the inductor current may not reach below ILIMIT (see Section
7.5) before the next clock cycle. When this occurs, the valley current limit control skips that cycle, causing
the switching frequency to drop. Further overload causes the switching frequency to continue to drop, and the
inductor ripple current to increase. When the peak of the inductor current reaches the high-side current limit, ISC
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(see Section 7.5), the switch duty cycle is reduced and the output voltage falls out of regulation. This represents
the maximum output current from the converter and is given approximately by Equation 1.
ILIMIT +ISC
IOUT
=
max
2
(1)
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
Hiccup mode. In this mode, the device stops switching for tHC (see Section 7.7), or about 94 ms, and then goes
through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for
about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in Figure 8-5, as long as the
short-circuit-condition persists. This mode of operation helps reduce the temperature rise of the device during a
hard short on the output. The output current is greatly reduced during Hiccup mode. Once the output short is
removed and the hiccup delay is passed, the output voltage recovers normally as shown in Figure 8-6.
Short Released
Short triggered
Output
Voltage
2V/div
Inductor
Curent
2A/
Inductor
Curent
1A/
50ms/div
50ms/div
Figure 8-5. Inductor Current Burst in Short-Circuit
Mode
Figure 8-6. Short-Circuit Transient and Recovery
8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR336x0AP-Q1 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the
VCC pin). When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC
falls below about 3 V, the device shuts down, regardless of EN status. Since the LDO is in dropout during these
transitions, the above values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 165°C, the device shuts down. Re-start occurs when the temperature falls to about
148°C.
8.4 Device Functional Modes
8.4.1 Auto Mode
In Auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM. The load current for which the device moves from
PFM to PWM can be found in Section 9.2.3. The output current at which the device changes modes depends
on the input voltage, inductor value, and the nominal switching frequency. For output currents above the curve,
the device is in PWM mode. For currents below the curve, the device is in PFM. The curves apply for a nominal
switching frequency of 400 kHz and the BOM shown in Table 9-3. At higher switching frequencies, the load at
which the mode change occurs is greater. For applications where the switching frequency must be known for a
given condition, the transition between PFM and PWM must be carefully tested before the design is finalized.
In PWM mode, the regulator operates as a constant frequency converter using PWM to regulate the output
voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and
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modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and
low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.
The duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The periodicity
of these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency
(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current
required to regulate the output voltage at light loads. PFM results in very good light-load efficiency, but also
yields larger output voltage ripple and variable switching frequency. Also, a small increase in output voltage
occurs at light loads. The actual switching frequency and output voltage ripple depends on the input voltage,
output voltage, and load. Typical switching waveforms in PFM and PWM are shown in Figure 8-7 and Figure 8-8.
See Section 9.2.3 for output voltage variation with load in Auto mode.
SW,
5V/Div
SW,
5V/Div
VOUT,
10mV/Div
VOUT,
10mV/Div
Inductor
Current,
0.5A/Div
Inductor
Current,
2A/Div
2µs/Div
50µs/Div
Figure 8-7. Typical PFM Switching Waveforms VIN = Figure 8-8. Typical PWM Switching Waveforms VIN
12 V, VOUT = 5 V, IOUT = 10 mA = 12 V, VOUT = 5 V, IOUT = 3 A, ƒS = 400 kHz
8.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage
level approaches the output voltage, the off time of the high-side MOSFET starts to approach the minimum
value (see Section 7.6). Beyond this point, the switching can become erratic, and the output voltage falls out
of regulation. To avoid this problem, the LMR336x0AP-Q1 automatically reduces the switching frequency to
increase the effective duty cycle and maintain regulation. In this data sheet, the dropout voltage is defined as the
difference between the input and output voltage when the output has dropped by 1% of its nominal value. Under
this condition, the switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V
short circuit detection threshold is not activated when in dropout mode. Typical dropout characteristics can be
found in Figure 8-9, Figure 8-10, Figure 8-11, and Figure 8-12.
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6
5.5
5
0.45
0.4
0.35
0.3
0.25
0.2
4.5
4
1A
2A
3A
0A
0.15
0.1
3.5
3
5V
0.05
0
3.3V
4
4.5
5
5.5
6
6.5
7
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
Output Current (A)
C017
C011
Figure 8-9. Overall Dropout Characteristic
VOUT = 5 V
Figure 8-10. Typical Dropout Voltage vs Output
Current in Frequency Foldback ƒSW = 140 kHz
2.4
2.2
2
2.4
2.2
2
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
0.8
0.8
1A
1A
0.6
0.6
0.4
0.2
0
0.4
0.2
0
2A
3A
2A
3A
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5 10
Input Voltage (V)
Input Voltage (V)
C026
C025
Figure 8-11. Typical Switching Frequency in
Dropout Mode VOUT = 3.3 V, fSW = 2.1 MHz
Figure 8-12. Typical Switching Frequency in
Dropout Mode VOUT = 5 V, fSW = 2.1 MHz
8.4.3 Minimum Switch On Time
Every switching regulator has a minimum controllable on time dictated by the inherent delays and blanking
times associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR336x0AP-Q1 automatically reduces the switching frequency when
the minimum on time limit is reached. This way the converter can regulate the lowest programmable output
voltage at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage,
before frequency foldback occurs is found in Equation 2. The values of tON and fSW can be found in Section 7.5.
As the input voltage is increased, the switch on time (duty-cycle) reduces to regulate the output voltage. When
the on-time reaches the limit, the switching frequency drops, while the on time remains fixed. This relationship is
highlighted in Figure 8-13 for a nominal switching frequency of 2.1 MHz.
VOUT
V
Ç
IN
tON ∂ fSW
(2)
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2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
1A
2A
3A
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
Input Voltage (V)
C024
Figure 8-13. Switching Frequency vs Input Voltage VOUT = 3.3 V
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMR336x0AP-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 3 A. The following design procedure can be used to select
components for the LMR336x0AP-Q1. Alternately, the WEBENCH Design Tool can be used to generate a
complete design. This tool utilizes an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
options.
Note
In this data sheet, the effective value of capacitance is defined as the actual capacitance under
D.C. bias and temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic
capacitors with an X5R or better dielectric throughout. All high value ceramic capacitors have a
large voltage coefficient in addition to normal tolerances and temperature effects. Under D.C. bias
the capacitance drops considerably. Large case sizes and/or higher voltage ratings are better in this
regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum
effective capacitance up to the required value. This can also ease the RMS current requirements on
a single capacitor. A careful study of bias and temperature variation of any capacitor bank should be
made in order to ensure that the minimum value of effective capacitance is provided.
9.2 Typical Application
Figure 9-1 shows a typical application circuit for the LMR336x0AP-Q1. This device is designed to function over a
wide range of external components and system parameters. However, the internal compensation is optimized for
a certain range of external inductance and output capacitance. As a quick start guide, Table 9-1 provides typical
component values for a range of the most common output voltages. The values given in the table are typical.
Other values can be used to enhance certain performance criterion as required by the application. Note that for
the VQFN package, the input capacitors are split and placed on either side of the package; see Section 9.2.2.6
for more details.
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L
VOUT
VIN
6 V to 36 V
SW
VIN
EN
8 µH
5 V
3 A
CIN
10 µF
CHF
220 nF
CBOOT
COUT
BOOT
4x 22 µF
0.1 µF
RFBT
CFF
PG
100 kΩ
PG
100 kΩ
VCC
FB
CVCC
1 µF
PGND
AGND
RFBB
24.9 kΩ
Figure 9-1. Example Application Circuit (400 kHz)
9.2.1 Design Requirements
Table 9-1 provides the parameters for our detailed design procedure example:
Table 9-1. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
12 V (6 V to 36 V)
5 V
Output voltage
Maximum output current
Switching frequency
0 A to 3 A
400 kHz
Table 9-2. Typical External Component Values
ƒSW
(kHz)
COUT (RATED
CAPACITANCE)
VOUT (V)
L (µH)
RFBT (Ω) RFBB (Ω) CIN + CHF CBOOT
CVCC
1 µF
1 µF
1 µF
1 µF
1 µF
1 µF
CFF
10 µF + 220
400
2100
400
3.3
3.3
5
6.8
1.2
8
4 × 22 µF
100 k
100 k
100 k
100 k
100 k
100 k
43.2 k
43.2 k
24.9 k
24.9 k
9.09 k
9.09 k
100 nF
100 nF
100 nF
100 nF
100 nF
100 nF
open
open
open
open
open
open
nF
10 µF + 220
nF
2 × 22 µF
4 × 22 µF
2 × 22 µF
4 × 22 µF
4 × 10 µF
10 µF + 220
nF
10 µF + 220
nF
2100
400
5
1.5
15
3.3
10 µF + 220
nF
12
12
10 µF + 220
nF
2100
9.2.2 Detailed Design Procedure
The following design procedure applies to Figure 9-1 and Table 9-1.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR336x0AP-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
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The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example, 400 kHz was chosen.
9.2.2.3 Setting the Output Voltage
The output voltage of the LMR336x0AP-Q1 is externally adjustable using a resistor divider network. The range
of recommended output voltage is found in Section 7.3. The divider network is comprised of RFBT and RFBB
,
and closes the loop between the output voltage and the converter. The converter regulates the output voltage
by holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the
divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller values of
resistance reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is
100 kΩ; with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feedforward capacitor must be
used across this resistor to provide adequate loop phase margin (see Section 9.2.2.9). Once RFBT is selected,
Equation 3 is used to select RFBB. VREF is nominally 1 V (see Section 7.5 for limits).
RFBT
RFBB
=
»
…
ÿ
VOUT
VREF
-1
Ÿ
⁄
(3)
For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.
9.2.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based
on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of
the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, the maximum device current should be used. Equation 4 can
be used to determine the value of inductance. The constant K is the percentage of inductor current ripple. For
this example, K = 0.3 was chosen and an inductance L = 8.1 µH was found; the next standard value of 8 µH was
selected.
(
V
IN - VOUT
)
VOUT
L =
∂
fSW ∂K ∂IOUTmax
V
IN
(4)
Ideally, the saturation current rating of the inductor must be at least as large as the high-side switch current
limit, ISC (see Section 7.5). This ensures that the inductor does not saturate even during a short circuit on
the output. When the inductor core material saturates, the inductance falls to a very low value, causing the
inductor current to rise very rapidly. Although the valley current limit, ILIMIT, is designed to reduce the risk of
current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This can lead
to component damage; do not allow the inductor to saturate. Inductors with a ferrite core material have very
hard saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores
exhibit a soft saturation, allowing for some relaxation in the current rating of the inductor. However, they have
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more core losses at frequencies typically above 1 MHz. In any case, the inductor saturation current must not
be less than the device low-side current limit, ILIMIT (see the Section 7.5). The maximum inductance is limited
by the minimum current ripple required for the current mode control to perform correctly. As a rule-of-thumb, the
minimum inductor ripple current must be no less than about 10% of the device maximum rated current under
nominal conditions.
VOUT
LMIN í 0.28 ∂
fSW
(5)
9.2.2.5 Output Capacitor Selection
The value of the output capacitor and the ESR of the capacitor determine the output voltage ripple and load
transient performance. The output capacitor bank is usually limited by the load transient requirements, rather
than the output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance
and an upper bound on the ESR, which is required to meet a specified load transient.
K2
12
»
…
…
ÿ
DIOUT
fSW ∂ DVOUT ∂K
COUT
í
∂
(
1- D
)
∂
(
1+ K
)
+
∂
(
2 - D
)
Ÿ
Ÿ
⁄
(
2 + K
)
∂ DVOUT
ESR Ç
K2
1
»
ÿ
≈
’
2∂ DIOUT 1+ K +
∂∆1+
÷
÷
…
Ÿ
∆
12
(1- D)
…
«
◊Ÿ
⁄
VOUT
D =
V
IN
(6)
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Section 9.2.2.4
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the peak-to-peak
output voltage ripple; Vr.
1
Vr @ DIL ∂ ESR2 +
2
8∂ fSW ∂COUT
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example, a ΔVOUT ≤ 250 mV for an output current step of ΔIOUT = 2 A is required. Equation 6 gives a
minimum value of 52 µF and a maximum ESR of 0.11 Ω. Assuming a 20% tolerance and a 10% bias de-rating,
you arrive at a minimum capacitance of 72 µF. This can be achieved with a bank of 4 × 22-µF, 16-V ceramic
capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.
Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic
capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance. In
general, use a capacitor of at least 10 V for output voltages of 3.3 V or less and a capacitor of 16 V or more for
output voltages of 5 V and above.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range
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of 1 nF to 100 nF can be very helpful in reducing voltage spikes on the output caused by inductor and board
parasitics.
The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000
µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of
start-up at full load and loop stability must be performed.
9.2.2.6 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the
ripple current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is
required on the input of the LMR336x0AP-Q1. This must be rated for at least the maximum input voltage that
the application requires; preferably twice the maximum input voltage. This capacitance can be increased to help
reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case size,
220-nF ceramic capacitor must be used at the input, as close as possible to the regulator. This provides a high
frequency bypass for the control circuits internal to the device. For this example, a 4.7-µF, 50-V, X7R (or better)
ceramic capacitor is chosen. The 220 nF must also be rated at 50 V with an X7R dielectric. The VQFN (RNX)
package provides two input voltage pins and two power ground pins on opposite sides of the package. This
allows the input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus
improving the effectiveness of the input bypassing. In this example, a single 4.7-µF and two 100-nF ceramic
capacitors at each VIN/PGND location.
Many times, it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is
especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR
of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of
this additional capacitor also helps with momentary voltage dips caused by input supplies with unusually high
impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
worst case RMS value of this current can be calculated from Equation 8 and must be checked against the
manufacturers' maximum ratings.
IOUT
IRMS
@
2
(8)
9.2.2.7 CBOOT
The LMR336x0AP-Q1 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This
capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic
capacitor of 100 nF and at least 10 V is required.
9.2.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Section 8.3.1). A value of 100 kΩ is a good choice in this case. The nominal output
voltage on VCC is 5 V; see Section 7.5 for limits. Do not short this output to ground or any other external voltage.
9.2.2.9 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
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VOUT ∂COUT
VREF
VOUT
CFF
<
120 ∂RFBT
∂
(9)
9.2.2.10 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can
be accomplished by using the circuit shown in Figure 9-2. The input voltage at which the device turns on is
designated VON while the turn-off voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩ and then Equation 10 is used to calculate RENT and VOFF
.
VIN
RENT
EN
RENB
Figure 9-2. Setup for External UVLO Application
≈
’
VON
∆
∆
÷
RENT
=
- 1 ∂RENB
÷
◊
VEN -H
«
≈
’
VEN -HYS
VEN -H
∆
÷
÷
VOFF = VON ∂ 1-
∆
«
◊
(10)
where
•
•
VON = VIN turn-on voltage
VOFF = VIN turn-off voltage
9.2.2.11 Maximum Ambient Temperature
As with any power conversion device, the LMR336x0AP-Q1 dissipates internal power while operating. The effect
of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum internal die temperature for the LMR336x0AP-Q1
must be limited to 125°C. This establishes a limit on the maximum device power dissipation and therefore the
load current. Equation 11 shows the relationships between the important parameters. It is easy to see that
larger ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and
IC Package Thermal Metrics Application Report, the value of RθJA given in Section 7.4 is not valid for design
purposes and must not be used to estimate the thermal performance of the application. The values reported in
that table were measured under a specific set of conditions that are rarely obtained in an actual application.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(11)
where
η = efficiency
•
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The effective RθJA is a critical parameter and depends on many factors such as the following:
•
•
•
•
•
•
•
Power dissipation
Air temperature/flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement
And more
Due to the ultra-miniature size of the VQFN (RNX) package, a DAP is not available. This means that this
package exhibits a somewhat large RθJA value. A typical example of RθJA vs copper board area can be found in
RθJA vs Copper Board Area for the VQFN (RNX) Package. The copper area given in the graph is for each layer;
the top and bottom layers are 2 oz. copper each, while the inner layers are 1 oz. A typical curve of maximum
output current vs. ambient temperature is shown in RθJA vs Copper Board Area for the VQFN (RNX) Package.
This data was taken with a device/PCB combination giving an RθJA of about 50°C/W. It must be remembered
that the data given in these graphs are for illustration purposes only, and the actual performance in any given
application depends on all of the previously mentioned factors.
70
65
60
55
50
45
40
3.5
3
2.5
2
1.5
1
0.5
0
RNX, 4L
60
0
10
20
30
40
50
70
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Copper Area (cm2)
C005
Ambient Temperature (°C)
C006
VIN = 12 V
ƒSW = 400 kHz
VOUT = 5 V
RθJA = 50°C/W
Figure 9-3. RθJA vs Copper Board Area for the
VQFN (RNX) Package
Figure 9-4. Maximum Output Current vs Ambient
Temperature
Use the following resources as a guide to optimal thermal PCB design and estimating RθJA for a given
application environment:
•
•
•
•
•
•
•
Thermal Design by Insight not Hindsight
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Semiconductor and IC Package Thermal Metrics
Thermal Design Made Simple with LM43603 and LM43602
PowerPAD™ Thermally Enhanced Package
PowerPAD™ Made Easy
Using New Thermal Metrics
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. The circuit is shown in Figure
9-27, with the appropriate BOM from Table 9-3.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
8V
8V
12V
24V
36V
12V
24V
36V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
C007
C008
VOUT = 5 V
400 kHz
RNX Package
VOUT = 3.3 V
400 kHz
RNX Package
Figure 9-5. Efficiency
Figure 9-6. Efficiency
100
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
60
55
8V
8V
12V
24V
36V
12V
24V
36V
50
50
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
C010
C009
VOUT = 5 V
2.1 MHz
RNX Package
VOUT = 3.3 V
2.1 MHz
RNX Package
Figure 9-7. Efficiency
Figure 9-8. Efficiency
5.06
5.055
5.05
32
30
28
26
24
22
20
8V
12V
24V
36V
5.045
5.04
5.035
5.03
5.025
5.02
5.015
5V
35
5.01
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
40
Output Current (A)
Input Voltage (V)
C011
C017
VOUT = 5 V
VOUT = 5 V
IOUT = 0 A
RFBT = 1 MΩ
Figure 9-9. Line and Load Regulation
Figure 9-10. Input Supply Current
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0.6
0.5
0.4
0.3
10000
1000
100
10
9
PWM
0.2
0.1
0
8V
PFM
;
1
12V
18V
5V
35
0.1
0
5
10
15
20
25
30
40
0.00001 0.0001
0.001
0.01
0.1
1
10
Input Voltage (V)
Output Current (A)
C012
C022
VOUT = 5 V
ƒSW = 400 kHz
VOUT = 5 V
ƒSW = 2100 kHz
Figure 9-11. Mode Change Thresholds
Figure 9-12. Switching Frequency vs Output
Current
VOUT,
300mV/Div
VOUT,
300mV/Div
Output Current,
1A/Div
Output Current,
1A/Div
100µs/Div
100µs/Div
0
0
VIN = 12 V
tf = tr = 2 µs
VOUT = 5 V
IOUT = 0 A to 3 A
VIN = 12 V
VOUT = 5 V
IOUT = 1 A to 3 A
tf = tr = 2 µs
Figure 9-13. Load Transient
Figure 9-14. Load Transient
3.35
3.345
3.34
32
30
28
26
24
22
20
5V
12V
24V
36V
3.335
3.33
3.325
3.32
3.315
3.31
3.3V
35
0
5
10
15
20
25
30
40
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
Output Current (A)
C016
C011
VOUT = 3.3 V
IOUT = 0 A
RFBT = 1 MΩ
VOUT = 3.3 V
Figure 9-16. Input Supply Current
Figure 9-15. Line and Load Regulation
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0.8
10000
1000
100
10
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
9
PWM
5V
1
12V
18V
PFM
;
3.3V
35
0.1
0
5
10
15
20
25
30
40
0.00001 0.0001
0.001
0.01
0.1
1
10
Input Voltage (V)
Output Current (A)
C012
C023
VOUT = 3.3 V
ƒSW = 400 kHz
VOUT = 3.3 V
ƒSW = 2100 kHz
Figure 9-17. Mode Change Thresholds
Figure 9-18. Switching Frequency vs Output
Current
VOUT,
300mV/Div
VOUT,
300mV/Div
Output Current,
1A/Div
Output Current,
1A/Div
100µs/Div
100µs/Div
0
0
VIN = 12 V
VOUT = 3.3 V
IOUT = 0 A to 3 A
VIN = 12 V
VOUT = 3.3V
IOUT = 1 A to 3 A
tf = tr = 2 µs
tf = tr = 2 µs
Figure 9-19. Load Transient
Figure 9-20. Load Transient
VIN = 12 V
VOUT = 5 V
IOUT = 3 A
RNX package
VIN = 12 V
VOUT = 5 V
IOUT = 3 A
RNX package
ƒSW = 400 kHz
ƒSW = 400 kHz
Figure 9-21. Conducted EMI
Figure 9-22. Radiated EMI Biconical Antenna
(Horizontal)
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VIN = 12 V
VOUT = 5 V
IOUT = 3 A
VIN = 12 V
VOUT = 5 V
IOUT = 3 A
RNX package
ƒSW = 400 kHz
RNX package
ƒSW = 400 kHz
Figure 9-23. Radiated EMI Biconical Antenna
(Vertical)
Figure 9-24. Radiated EMI Log-Periodic Antenna
(Horizontal)
VIN = 12 V
VOUT = 5 V
IOUT = 3 A
VIN = 12 V
VOUT = 5 V
IOUT = 3 A
ƒSW = 400 kHz
RNX package
ƒSW = 400 kHz
RNX package
Figure 9-25. Radiated EMI Log-periodic Antenna
(Vertical)
Figure 9-26. Radiated EMI
Rod Antenna
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L
VOUT
VIN
SW
VIN
EN
U1
CBOOT
CIN
CHF
COUT
BOOT
0.1 µF
RFBT
PG
100 kΩ
PG
100 kΩ
VCC
FB
CVCC
1 µF
PGND
AGND
RFBB
Figure 9-27. Circuit for Application Curves
Table 9-3. BOM for Typical Application Curves RNX Package(1)
VOUT
3.3 V
3.3 V
5 V
FREQUENCY
RFBB
COUT
CIN + CHF
L
U1
400 kHz
43.3 kΩ
43.3 kΩ
24.9 kΩ
24.9 kΩ
4 × 22 µF
4 × 22 µF
4 × 22 µF
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
2 × 4.7 µF + 2 × 100 nF
2 × 4.7 µF + 2 × 100 nF
2 × 4.7 µF + 2 × 100 nF
6.8 µH, 14 mΩ
1.2 µH, 7 mΩ
8 µH, 25 mΩ
1.5 µH, 8.2 mΩ
LMR33630ARNX
LMR33630CRNX
LMR33630ARNX
LMR33630CRNX
2100 kHz
400 kHz
5 V
2100 kHz
(1) The values in this table were selected to enhance certain performance criteria and may not represent typical values.
Ferrite Bead
3.3µF
+
Input to
Regulator
Input Supply
Figure 9-28. Typical Input EMI Filter
Filter Used Only for EMI Measurements Found in Application Curves
9.3 What to Do and What Not to Do
•
•
•
•
•
•
Don't: Exceed the Absolute Maximum Ratings.
Don't: Exceed the ESD Ratings.
Don't: Exceed the Recommended Operating Conditions.
Don't: Allow the EN input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the value of RθJA given in the Thermal Information table to design your application. Use the
information in the Maximum Ambient Temperature section.
•
Do: Follow all the guidelines and suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make the
project a success (see the Support Resources).
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and
Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable
of delivering the required input current to the loaded regulator. The average input current can be estimated with
Equation 12.
VOUT ∂IOUT
IIN
=
VIN ∂ h
(12)
where
•
η is the efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to
the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient
is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause
the regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator, use an aluminum or tantalum input capacitor in parallel with the
ceramics, or both. The moderate ESR of these types of capacitors help damp the input resonant circuit and
reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and
help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead
to instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162
Simple Success With Conducted EMI From DCDC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this
device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than
the output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then a Schottky diode between the input supply and the output should be used.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter,
the most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power ground,
as shown in Figure 11-1. This loop carries large transient currents that can cause large transient voltages when
reacting with the trace inductance. These unwanted transient voltages will disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. Figure 11-2 shows a recommended layout for the critical components of the
LMR336x0AP-Q1.
1. Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. The VIN
and GND pins are adjacent, simplifying the input capacitor placement. With the VQFN package there are two
VIN/PGND pairs on either side of the package. This provides for a symmetrical layout and helps minimize
switching noise and EMI generation. A wide VIN plane must be used on a lower layer to connect both of the
VIN pairs together to the input supply; see Figure 11-2.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the
BOOT and SW pins. It is important to route the SW connection under the device to the NC pin, and use this
path to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF,
if used, physically close to the device. The connections to FB and GND must be short and close to those
pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act
as a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat sinking. As stated in Section 9.2.2.11, enough copper
area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient
temperature. Make the top and bottom PCB layers with two-ounce copper; and no less than one ounce.
If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the
inner layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node should be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
•
•
•
•
Layout Guidelines for Switching Power Supplies
Simple Switcher PCB Layout Guidelines
Construction Your Power Supply- Layout Considerations
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
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VIN
KEEP
CURRENT
LOOP
CIN
SW
SMALL
GND
Figure 11-1. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz /
1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding, and lower thermal resistance.
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11.2 Layout Example
VOUT
VOUT
INDUCTOR
COUT
COUT
COUT
COUT
GND
GND
CIN
CIN
CHF
CHF
12
1
2
11
10
9
3
4
VIN
EN
VIN
8
PGOOD
5
6
7
CVCC
RFBB
GND
GND
HEATSINK
HEATSINK
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
VIN Strap on Inner Layer
VIA to Signal Layer
VIA to GND Planes
VIA to VIN Strap
Top
Inner GND Plane
VIN Strap and
GND Plane
Signal traces
and GND Plane
Trace on Signal Layer
Figure 11-2. Example Layout for VQFN Package
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM33630-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
•
•
•
•
•
Thermal Design by Insight not Hindsight
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Semiconductor and IC Package Thermal Metrics
Thermal Design Made Simple with LM43603 and LM43602
PowerPADTM Thermally Enhanced Package
PowerPADTM Made Easy
Using New Thermal Metrics
Layout Guidelines for Switching Power Supplies
Simple Switcher PCB Layout Guidelines
Construction Your Power Supply- Layout Considerations
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
Copyright © 2021 Texas Instruments Incorporated
34
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Product Folder Links: LMR33620AP-Q1 LMR33630AP-Q1
LMR33620AP-Q1, LMR33630AP-Q1
www.ti.com
SNVSBQ5 – JUNE 2021
12.5 Trademarks
HotRod™, PowerPAD™, TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: LMR33620AP-Q1 LMR33630AP-Q1
LMR33620AP-Q1, LMR33630AP-Q1
SNVSBQ5 – JUNE 2021
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Submit Document Feedback
Product Folder Links: LMR33620AP-Q1 LMR33630AP-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR33620APAQRNXRQ1
LMR33620APCQRNXRQ1
LMR33630APAQRNXRQ1
LMR33630APCQRNXRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNX
RNX
RNX
RNX
12
12
12
12
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
620PAQ
NIPDAU
NIPDAU | SN
NIPDAU
620PCQ
630PAQ
630PCQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR33620APAQRNXRQ1 VQFN-
HR
RNX
RNX
RNX
RNX
RNX
12
12
12
12
12
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
2.25
2.25
2.3
3.25
3.25
3.2
1.05
1.05
1.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
LMR33620APCQRNXRQ1 VQFN-
HR
LMR33630APAQRNXRQ1 VQFN-
HR
LMR33630APAQRNXRQ1 VQFN-
HR
2.25
2.25
3.25
3.25
1.05
1.05
LMR33630APCQRNXRQ1 VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMR33620APAQRNXRQ1
LMR33620APCQRNXRQ1
LMR33630APAQRNXRQ1
LMR33630APAQRNXRQ1
LMR33630APCQRNXRQ1
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNX
RNX
RNX
RNX
RNX
12
12
12
12
12
3000
3000
3000
3000
3000
210.0
210.0
213.0
210.0
210.0
185.0
185.0
191.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RNX 12
2 x 3 mm, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224286/A
PACKAGE OUTLINE
RNX0012B
VQFN-HR - 0.9 mm max height
SCALE 4.500
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.9
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1
SYMM
(0.2) TYP
5
7
4X 0.5
8
4
2X
0.675
PKG
2X
1.725
1.525
2X
1.125
0.65
A
A
11
1
12
0.3
0.2
0.1
PIN 1 ID
11X
0.3
0.2
C B A
C
0.5
0.3
11X
0.05
4223969/C 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNX0012B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.25)
12
11X (0.6)
11X
1
2X (0.65)
11
(0.25)
(1.825)
(0.788)
2X
(1.125)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
(R0.05) TYP
5
7
SYMM
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
PADS 1, 2, 10-12
(PREFERRED)
SOLDER MASK DETAILS
4223969/C 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNX0012B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.25)
2X (0.812)
12
11X (0.6)
11X (0.25)
1
11
2X
(0.65)
(1.294)
EXPOSED METAL
PKG
2X
(1.125)
(0.282)
2X (0.675)
4X (0.5)
8
(1.4)
4
(R0.05) TYP
5
7
SYMM
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR PAD 12
87.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4223969/C 10/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RNX0012C
A
2.1
1.9
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1
PKG
(0.2) TYP
5
7
(0.16)
5X 0.5
8
4
2X
0.675
PKG
2X
1.125
1.725
1.525
2X
0.65
A
A
11
1
12
PIN 1 ID
0.3
0.2
0.3
0.2
11X
0.5
0.3
0.1
C A B
C
11X
0.05
4225021/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RNX0012C
(0.25)
11X (0.6)
12
11X (0.25)
2X (0.65)
11
1
(1.825)
2X
(1.125)
(0.7875)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
5
7
PKG
(1.8)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE: 20X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225021/A 06/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RNX0012C
2X (0.25)
2X (0.812)
11X (0.6)
11X (0.25)
12
2X (0.65)
1
11
EXPOSED
METAL
2X
(1.125)
(1.294)
(0.281)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
5
7
PKG
(1.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
FOR PAD 12
87.7% PRINTED COVERAGE BY AREA
SCALE: 20X
4225021/A 06/2019
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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