LMR36006-Q1 [TI]
4.2V 至 60V、0.6A 超小型同步降压转换器;
| 型号： | LMR36006-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4.2V 至 60V、0.6A 超小型同步降压转换器 转换器 |
| 文件： | 总51页 (文件大小：4975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR36006-Q1
ZHCSIN5D –AUGUST 2018 –REVISED AUGUST 2022
LMR36006-Q1 4.2V 至60V、0.6A 超小型同步降压转换器
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全型
• ADAS 摄像头模块
• 车身控制模块
3 说明
– 可帮助进行功能安全系统设计的文档
• 专为汽车应用而设计
LMR36006-Q1 稳压器是一款易于使用的同步降压直
流/直流转换器。该器件具有集成式高侧和低侧功率
MOSFET，能够提供高达 0.6A 的输出电流（在 4.2V
至60V 的宽输入电压范围内）。容差高达66V。
– 结温范围为–40°C 至+150°C
– 保护特性：热关断、输入欠压锁定、逐周期电流
限制和断续短路保护。
– 在0.6A 负载下具有0.2V 压降（典型值）
– ±1.5% 基准电压容差
– 提供3.3V 固定输出电压选项
• 适合可扩展的电源
LMR36006-Q1 采用峰值电流模式控制机制来提供最佳
的效率和输出电压精度。LMR36006-Q1 可利用高级高
速电路在 2.1MHz 的固定频率下实现从 20V 输入到 5V
输出的稳压。精密使能支持直接连接到宽输入电压或对
器件启动和关断进行精确控制，因此提供了灵活性。附
带内置滤波和延迟功能的电源正常状态标志可提供系统
状态的真实指示，免去了使用外部监测器的麻烦。
– 与以下器件引脚兼容：
• LMR36015-Q1（60V、1.5A）
• LMR33620/30-Q1（36V、2A 或3A）
– 400kHz、2.1MHz 频率选项
LMR36006-Q1 采用 HotRod™ 封装，实现了低 EMI、
更高的效率和超小的封装裸片比。此器件需要很少的外
部元件，并且具有可简化 PCB 布局的引脚排列。
LMR36006-Q1 的小型解决方案尺寸和各种功能旨在简
化各种终端设备的实现。
• 通过集成技术减小解决方案尺寸，降低成本
– 小型2mm × 3mm VQFN 封装（具有可湿性侧
面）
– 很少的外部组件
• 在整个负载范围内具有低功率耗散
– 400kHz（12 VIN、5 VOUT、0.6 A）时的效率为
94%
– 在PFM 模式中提高了轻负载效率
– 低至26µA 的工作静态电流
• 针对超低EMI 要求进行了优化
器件信息
封装(1)
器件型号
封装尺寸（标称值）
LMR36006-Q1
VQFN-HR (12)
2.00mm x 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 符合CISPR25 5 类标准
– HotRod™ 封装可更大限度地减少开关节点振铃
– 并行输入路径可更大限度减少寄生电感
– 展频可降低峰值发射
• 使用LMR36006-Q1 并借助WEBENCH® Power
Designer 创建定制设计方案
BOOT
VIN
VIN
CBOOT
EN
CIN
SW
VOUT
L1
COUT
PGND
LMR36006-Q1
PG
FB
VCC
RFBT
CVCC
RFBB
AGND
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAY7
LMR36006-Q1
ZHCSIN5D –AUGUST 2018 –REVISED AUGUST 2022
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
9.3 What to Do and What Not to Do............................... 33
10 Power Supply Recommendations..............................34
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 37
12 Device and Documentation Support..........................38
12.1 Device Support....................................................... 38
12.2 Documentation Support.......................................... 38
12.3 接收文档更新通知................................................... 38
12.4 支持资源..................................................................38
12.5 Trademarks.............................................................39
12.6 Electrostatic Discharge Caution..............................39
12.7 术语表..................................................................... 39
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................7
7.7 System Characteristics............................................... 8
7.8 Typical Characteristics................................................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
Information.................................................................... 39
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (October 2019) to Revision D (August 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• 向特性添加了功能安全要点................................................................................................................................1
• Included LMR36006BQRNXRQ1 in the Device Comparison Table. ..................................................................3
Changes from Revision B (February 2019) to Revision C (October 2019)
Page
• 向节1 添加了EMI 说明...................................................................................................................................... 1
• Added 图9-17 through 图9-26 ........................................................................................................................27
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5 Device Comparison Table
ORDERABLE PART
NUMBER
OUTPUT VOLTAGE
SPREAD
SPECTRUM
PACKAGE QUANTITY
fSW
FPWM
LMR36006AQRNXTQ1
LMR36006AQRNXRQ1
LMR36006BQRNXRQ1
LMR36006FSCQRNXTQ1
LMR36006FSCQRNXRQ1
LMR36006FSC3RNXTQ1
LMR36006FSC3RNXRQ1
Adjustable
Adjustable
Adjustable
Adjustable
Adjustable
3.3-V fixed
3.3-V fixed
No
No
No
No
400 kHz
400 kHz
1 MHz
250
3000
3000
250
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2.1 MHz
2.1 MHz
2.1 MHz
2.1 MHz
3000
250
3000
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6 Pin Configuration and Functions
SW
12
1
2
11 PGND
10 VIN
PGND
VIN
9
3
4
EN
NC
PG
8
BOOT
6
7
5
AGND
VCC
FB
图6-1. 12-Pin VQFN-HR RNX Package (Top View)
表6-1. Pin Functions
NO.
NAME
PGND
VIN
TYPE
DESCRIPTION
1, 11
2, 10
G
P
Power ground terminal. Connect to system ground and AGND. Connect to CIN with short wide traces.
Input supply to regulator. Connect to CIN with short wide traces.
Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the
SW pin. This pin has no internal connection to the regulator.
3
4
NC
—
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this
pin to the SW pin. Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin.
BOOT
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
GND.
5
VCC
P
Analog ground for regulator and system. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
6
7
AGND
FB
G
A
Feedback input to regulator. Connect to output voltage node for fixed VOUT applications. Connect to tap
point of feedback voltage divider. Do not float. Do not ground.
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. Goes low when EN = Low. Can be open or grounded when
not used.
8
PG
A
9
EN
A
P
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float.
Regulator switch node. Connect to power inductor. Connect the SW pin to NC on the PCB. This
simplifies the connection from the CBOOT capacitor to the SW pin.
12
SW
A = Analog, P = Power, G = Ground
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating junction temperature range of -40°C to 150°C (unless otherwise noted)(1)
MIN
MAX
66
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
Output voltage
Output voltage
VIN to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–0.3
-40
EN to AGND
66.3
5.5
V
FB to AGND
V
PG to AGND
22
V
AGND to PGND
SW to PGND
0.3
V
66.3
66.3
5.5
V
SW to PGND less than 10-ns transients
CBOOT to SW
V
V
VCC to AGND
5.5
V
Junction Temperature TJ
Storage temperature, Tstg
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
V(ESD)
±2500
V
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
V(ESD)
±750
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 ℃to 150 ℃(unless otherwise noted)(1)
MIN
4.2
0
MAX
UNIT
VIN to PGND
EN to PGND(2)
PG to PGND(2)
IOUT
60
V
V
V
A
Input voltage
60
0
18
Output current
0
0.6
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
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7.4 Thermal Information
LMR36006
THERMAL METRIC(1)
RNX (VQFN-HR)
UNIT
12 PINS
72.5
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.9
23.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.8
23.5
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating quiescent current (non-
switching)(2)
IQ-nonSW
ISD
VEN = 3.3 V (PFM variant only)
VEN = 0 V
18
26
5
36
µA
µA
Shutdown quiescent current;
measured at VIN pin
ENABLE (EN PIN)
VEN-VCC-H
VEN-VCC-L
VEN-VOUT-H
Enable input high level for VCC output VENABLE rising
1.14
1.3
V
V
Enable input low level for VCC output
Enable input high level for VOUT
VENABLE falling
0.3
VENABLE rising
1.157
1.231
110
V
VEN-VOUT-HYS Enable input hysteresis for VOUT
ILKG-EN Enable input leakage current
INTERNAL LDO (VCC PIN)
Hysteresis below VENABLE-H; falling
VEN = 3.3V
mV
nA
0.2
VCC
Internal VCC voltage
4.75
3.6
5
5.25
4.0
V
V
6 V ≤VIN ≤60 V
VCC-UVLO-
Internal VCC undervoltage lockout
Internal VCC undervoltage lockout
VCC rising
3.8
Rising
VCC-UVLO-
VCC falling
3.1
3.3
3.5
V
Falling
VOLTAGE REFERENCE (FB PIN)
VOUT-3.3V-Fixed Output voltage
3.23
3.3
1
3.37
V
V
VFB
Feedback voltage
0.985
1.015
ILKG-VOUT-3.3V-
Feedback leakage current
Feedback leakage current
VOUT = 3.3 V (Fixed Option)
FB = 1 V
1.4
0.2
1.8
µA
nA
Fixed
ILKG-FB
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(3)
Low-side current limit(3)
0.8
0.6
1
0.8
1.2
A
A
A
A
ILS-LIMIT
IPEAK-MIN
IL-NEG
0.95
Minimum inductor peak current(3)
Negative current limit(3)
0.18
FPWM variant only
-0.95
–0.6 –0.25
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Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
VPG-LOW-DN
Power-Good upper threshold - rising
% of FB voltage
105%
90%
107%
93%
110%
95%
Power-Good lower threshold - falling
% of FB voltage
% of FB voltage
Power-Good hysteresis (rising &
falling)
VPG-HYS
TPG
2%
Power-Good rising/falling edge
deglitch delay
80
140
200
2
µs
V
Minimum input voltage for proper
Power-Good function
VPG-VALID
RPG
Power-Good on-resistance
Power-Good on-resistance
VEN = 2.5 V
VEN = 0 V
80
35
165
90
Ω
Ω
RPG
OSCILLATOR
FOSC
Internal oscillator frequency
Internal oscillator frequency
2.1-MHz variant
400-kHz variant
1.95
340
2.1
2.35
460
MHz
kHz
FOSC
400
MOSFETS
RDS-ON-HS
RDS-ON-LS
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
IOUT = 0.5 A
IOUT = 0.5 A
225
150
435
280
mΩ
mΩ
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
7.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
MIN
NOM
MAX
83
73
12
6
UNIT
tON-MIN
tOFF-MIN
tON-MAX
tSS
Minimum switch on-time
Minimum switch off-time
Maximum switch on-time
Internal soft-start time
55
ns
53
ns
7
µs
3
4.5
ms
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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7.7 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃to 150℃. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
4.2
60
V
Adjustable output voltage
regulation(1)
VOUT
PFM operation
2.5%
1.5%
3.37
–1.5%
–1.5%
3.28
Adjustable output voltage
regulation(1)
VOUT
VOUT
FPWM operation
FPWM operation
Voltage regulation for VOUT = 3.3 V
fixed(1)
3.33
V
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
Input supply current when in
regulation
ISUPPLY
DMAX
VHC
26
98%
0.4
µA
Maximum switch duty cycle(2)
FB pin voltage required to trip short-
circuit hiccup mode
V
Time between current-limit hiccup
burst
tHC
tD
94
2
ms
ns
%
Switch voltage dead time
Frequency span of spread spectrum
operation
FsSS
±4
Triangular spread spectrum
repetition frequency
FrSS
16
kHz
TSD
TSD
Thermal shutdown temperature
Thermal shutdown temperature
Shutdown temperature
Recovery temperature
170
158
°C
°C
(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to 0.6A
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
= 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C. VIN = 24 V.
30
10
29
9
28
8
27
7
26
25
24
23
22
21
20
6
5
4
3
2
25C
150C
-40C
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Shut
LMR3
EN = 0 V
VFB = 1 V
图7-2. Shutdown Supply Current
图7-1. Non-Switching Input Supply Current
1.5
1
0.8
0.6
0.4
0.2
0
1.3
1.1
0.9
0.7
0.5
-40
0
40 80
Temperature (°C)
120
150
-40
0
40 80
Temperatuer (°C)
120
150
ls-c
hs-c
VIN = 24 V
VIN = 24 V
图7-4. Low Side Current Limit
图7-3. High Side Current Limit
1.02
370
320
270
220
170
120
1.016
1.012
1.008
1.004
1
0.996
0.992
0.988
0.984
0.98
25C
150C
-40C
-40
0
40 80
Temperature (°C)
120
150
vref
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
LMR3
IOUT = 0 A
VOUT = 3.3 V
ƒSW = 2100 kHz
图7-5. Reference Voltage Drift
图7-6. IPEAK-MIN
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8 Detailed Description
8.1 Overview
The LMR36006-Q1 is a synchronous peak-current-mode buck regulator designed for a wide variety of
automotive applications. The regulator automatically switches modes between PFM and PWM, depending on
load. At heavy loads, the device operates in PWM at a constant switching frequency. At light loads, the mode
changes to PFMW with diode emulation allowing DCM. This reduces the input supply current and keeps
efficiency high. The device features internal loop compensation which reduces design time and requires fewer
external components than externally compensated regulators.
The LMR36006-Q1 is designed with a flip-chip or HotRod package technology, greatly reducing the parasitic
inductance of pins. In addition, the layout of the device allows for reduction in the radiated noise generated by
the switching action through partial cancellation of the current generated magnetic field. As a result, the switch-
node waveform exhibits less overshoot and ringing.
2V/div
50ns/div
BW:500MHz
图8-1. Switch Node Waveform
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8.2 Functional Block Diagram
VCC
VIN
INT. REG.
BIAS
OSCILLATOR
BOOT
ENABLE
LOGIC
HS CURRENT
SENSE
EN
ꢀ
1.0V
Reference
PWM
COMP.
ERROR
AMPLIFIER
+
-
CONTROL
LOGIC
DRIVER
SW
+
-
FB
LS CURRENT
SENSE
PFM MODE
CONTROL
PG
POWER GOOD
CONTROL
AGND PGND
8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36006-Q1 can be used to reset a system
microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault
conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents
false flag operation for short excursions of the output voltage, such as during line and load transients. Output
voltage excursions lasting less than tPG do not trip the power-good flag. Power-good operation can best be
understood by reference to 图 8-2 and 图 8-3. Note that during initial power-up, a delay of about 4 ms (typical) is
inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs
during start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤
4 mA.
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VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN
(105%)
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
图8-2. Static Power-Good Operation
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Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
<tPG
PG
tPG
tPG
tPG
图8-3. Power-Good-Timing Behavior
8.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see 节 9.2.1.2.9.1). Applying a voltage of ≥
VEN-VCC-H causes the device to enter standby mode, powering the internal VCC, but not producing an output
voltage. Increasing the EN voltage to VEN-OUT-H (VEN-H in 图 8-4) fully enables the device, allowing it to enter
start-up mode and starting the soft-start period. When the EN input is brought below VEN-OUT-H (VEN-H in 图 8-4)
by VEN-OUT-HYS (VEN-HYS in 图 8-4), the regulator stops running and enters standby mode. Further decrease in
the EN voltage to below VEN-VCC-L completely shuts down the device. This behavior is shown in 图 8-4. The EN
input can be connected directly to VIN if this feature is not needed. This input must not be allowed to float. The
values for the various EN thresholds can be found in 节7.5.
The LMR36006-Q1 utilizes a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. A typical start-up waveform is shown in 图 8-5 along with typical timings.
The rise time of the output voltage is about 4 ms.
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EN
VEN-H
VEN-H œ VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5 V
0
VOUT
VOUT
0
图8-4. Precision Enable Behavior
图8-5. Typical Start-up Behavior VIN = 24 V, VOUT = 3.3 V, IOUT = 0.6 A
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8.3.3 Current Limit and Short Circuit
The LMR36006-Q1 incorporates valley current limit for normal overloads and for short-circuit protection. In
addition, the high-side power MOSFET is protected from excessive current by a peak current limit circuit. Cycle-
by-cycle current limit is used for overloads, while hiccup mode is used for short circuits. Finally, a zero current
detector is used on the low-side power MOSFET to implement diode emulation mode (DEM) at light loads (see
节12.7).
During overloads, the low-side current limit, ILIMIT, determines the maximum load current that the LMR36006-Q1
can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not
fall below ILIMIT before the next turnon cycle, then that cycle is skipped, and the low-side MOSFET is left on until
the current falls below ILIMIT. This is somewhat different than the more typical peak current limit and results in 方
程式1 for the maximum load current.
(
V
IN - VOUT
)
∂
VOUT
IOUT
= ILIMIT
+
max
2∂ fSW ∂L
V
IN
(1)
where
• fSW = switching frequency
• L = inductor value
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
hiccup mode. In this mode, the device stops switching for tHC or about 94 ms, and then goes through a normal
re-start with soft start. If the short-circuit condition remains, the device runs in current limit for about 20 ms
(typical) and then shuts down again. This cycle repeats, as shown in 图 8-6 as long as the short-circuit condition
persists. This mode of operation helps to reduce the temperature rise of the device during a hard short on the
output. Of course, the output current is greatly reduced during hiccup mode. Once the output short is removed
and the hiccup delay is passed, the output voltage recovers normally as shown in 图8-6.
The high-side-current limit trips when the peak inductor current reaches ISC. This is a cycle-by-cycle current limit
and does not produce any frequency or load current foldback. It is meant to protect the high-side MOSFET from
excessive current. Under some conditions, such as high input voltages, this current limit can trip before the low-
side protection. Under this condition, ISC determines the maximum output current. Note that ISC varies with duty
cycle.
图8-6. Short-Circuit Transient and Recovery
8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR36006-Q1 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC
pin). When VCC reaches 3.8 V (typ.), the device receives the EN signal and starts switching. When VCC falls
below 3.3 V (typ.), the device shuts down, regardless of EN status. Because the LDO is in dropout during these
transitions, the previously mentioned values roughly represent the input voltage levels during the transitions.
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Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 170°C, the device shuts down; re-start occurs when the temperature falls to about
158°C.
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM.
In PWM, the regulator operates as a constant frequency, current mode, full synchronous converter using PWM
to regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency of
these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see
节12.7). This mode provides high light-load efficiency by reducing the amount of input supply current required to
regulate the output voltage at small loads. This trades off very good light-load efficiency for larger output voltage
ripple and variable switching frequency. Also, a small increase in output voltage occurs at light loads. The actual
switching frequency and output voltage ripple depend on the input voltage, output voltage, and load. Typical
switching waveforms in PFM and PWM are shown in 图8-7 and 图8-8.
图8-7. Typical PFM Switching Waveforms VIN = 24 图8-8. Typical PWM Switching Waveforms VIN = 24
V, VOUT = 5 V, IOUT = 30 mA
V, VOUT = 5 V, IOUT = 600 mA, ƒS = 400 kHz
8.4.2 Forced PWM Operation
The following select variant or variants are factory options made available for cases when constant frequency
operation is more important than light load efficiency.
表8-1. LMR36006-Q1 Device Variants with Fixed Frequency Operation at No Load
ORDERABLE PART NUMBER
LMR36006FSCQRNXTQ1
LMR36006FSCQRNXRQ1
LMR36006FSC3RNXTQ1
LMR36006FSC3RNXRQ1
OUTPUT VOLTAGE SPREAD SPECTRUM
FPWM
FSW
Adjustable
Adjustable
3.3-V fixed
3.3-V fixed
Yes
Yes
Yes
Yes
Yes
2.1 MHz
2.1 MHz
2.1 MHz
2.1 MHz
Yes
Yes
Yes
In FPWM operation, the diode emulation feature is turned off. This means that the device remains in CCM under
light loads. Under conditions where the device must reduce the on-time or off-time below the ensured minimum
to maintain regulation, the frequency reduces to maintain the effective duty cycle required for regulation. This
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occurs for very high and very low input/output voltage ratios. When in FPWM mode, a limited reverse current is
allowed through the inductor allowing power to pass from the output of the regulator to its input. Note that in
FPWM mode, larger currents pass through the inductor, if lightly loaded, than in auto mode. Once loads are
heavy enough to necessitate CCM operation, FPWM mode has no measurable effect on regulator operation.
8.4.3 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is
reduced to near the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
Beyond this point, the switching can become erratic, the output voltage falls out of regulation, or both. To avoid
this problem, the LMR36006-Q1 automatically reduces the switching frequency to increase the effective duty
cycle and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the
input and output voltage when the output has dropped by 1% of its nominal value. Under this condition, the
switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4-V short circuit
detection threshold is not activated when in dropout mode. Typical dropout characteristics can be found in 图8-9
and 图8-10.
4.5E+5
4E+5
3.5E+5
3E+5
2.5E+5
2E+5
1.5E+5
1E+5
5E+4
0
6
5.5
5
IOUT = 1.5 mA
IOUT = 300 mA
IOUT = 600 mA
4.5
4
IOUT = 300 mA
IOUT = 600 mA
3.5
3
5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Input Voltage (V)
6
4
4.2 4.4 4.6 4.8 5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
LMR3
LMR3
图8-10. Typical ƒSW vs Output Current ƒSW = 400
图8-9. Overall Dropout Characteristic VOUT = 5 V
kHz
8.4.4 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR36006-Q1 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before
frequency foldback occurs, is found in 方程式2. As the input voltage is increased, the switch on-time (duty cycle)
reduces to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops, while
the on-time remains fixed.
VOUT
V
Ç
IN
tON ∂ fSW
(2)
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2.4E+6
2.2E+6
2E+6
1.8E+6
1.6E+6
1.4E+6
1.2E+6
1E+6
8E+5
6E+5
4E+5
IOUT = 300 mA
IOUT = 600 mA
2E+5
0
10
15
20
25
30
35
40
Input Voltage (V)
45
50
55
60
Freq
图8-11. Switching Frequency vs Input Voltage VOUT = 3.3 V
8.4.5 Spread Spectrum Operation
The spread spectrum is a factory option in the select variants.
表8-2. LMR36006-Q1 Device Variant(s) with Spread Spectrum Operation
ORDERABLE PART NUMBER
LMR36006FSCQRNXTQ1
LMR36006FSCQRNXRQ1
LMR36006FSC3RNXTQ1
LMR36006FSC3RNXRQ1
OUTPUT VOLTAGE SPREAD SPECTRUM
FPWM
fSW
2.1 MHz
Adjustable
Adjustable
3.3-V Fixed
3.3-V Fixed
Yes
Yes
Yes
Yes
Yes
Yes
2.1 MHz
2.1 MHz
2.1 MHz
Yes
Yes
The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading
emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems
containing the LMR36006-Q1, low frequency conducted emissions from the first few harmonics of the switching
frequency can be easily filtered. A more difficult design criterion is reduction of emissions at higher harmonics
which fall in the FM band. These harmonics often couple to the environment through electric fields around the
switch node. The LMR36006-Q1 devices with a triangular spread spectrum use typically a ±4% spreading rate
with the modulation rate set at 16 kHz (typical). The spread spectrum is only available while the internal clock is
free running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off:
• At high input voltages/low output voltage ratio when the device operates at minimum on time the internal
clock is slowed disabling spread spectrum.
• The clock is slowed during dropout.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LMR36006-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 0.6 A. The following design procedure can be used to select
components for the LMR36006-Q1. Alternately, the WEBENCH® Design Tool may be used to generate a
complete design. This tool utilizes an iterative design procedure and has access to a comprehensive database
of components. This allows the tool to create an optimized design and allows the user to experiment with various
options.
备注
All of the capacitance values given in the following application information refer to effective values;
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and
temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with
an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and/or higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank should be made in
order to ensure that the minimum value of effective capacitance is provided.
9.2 Typical Application
图9-1 and 图9-2 show typical application circuits for the LMR36006-Q1. This device is designed to function over
a wide range of external components and system parameters. However, the internal compensation is optimized
for a certain range of external inductance and output capacitance. As a quick start guide, 表 9-1 provides typical
component values for a range of the most common output voltages.
L
VOUT
VIN
SW
VIN
VIN
CIN
CHF1
220 nF 220 nF
CHF2
CBOOT
4.7 µF
COUT
BOOT
EN
VPU
100 kΩ
0.1 µF
LMR36006-Q1
CFF
RFBT
100 kΩ
PG
FB
VCC
RFBB
CVCC
1 µF
PGND PGND
AGND
图9-1. Example Applications Circuit (Adjustable Output)
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L
VOUT
VIN
SW
VIN
VIN
CIN
CHF1
220 nF 220 nF
CHF2
CBOOT
4.7 µF
COUT
BOOT
EN
VPU
100 kΩ
0.1 µF
LMR36006-Q1
PG
FB
VCC
CVCC
1 µF
PGND PGND
AGND
图9-2. Example Applications Circuit (Fixed 3.3 V Output)
表9-1. Typical External Component Values
NOMINAL COUT
(RATED
MINIMUM COUT
(RATED
VOUT
ƒSW
(kHz)
L (µH)
CIN
CFF
RFBT (Ω) RFBB (Ω)
(V)
3.3
3.3
5
CAPACITANCE) (1)
CAPACITANCE) (2)
4.7 µF + 2 × 220
nF
400
2100
400
22
6.8
33
10
56
22
2 × 22µF
2 × 15 µF
2 × 22 µF
2 × 15 µF
2 × 22 µF
2 × 15 µF
1 × 22µF
1 × 15 µF
1 × 22 µF
1 × 15 µF
1 × 22 µF
1 × 15 µF
100 k
100 k
100 k
100 k
100 k
100 k
43.2 k
43.2 k
24.9 k
24.9 k
9.09 k
9.09 k
20 pF
20 pF
20 pF
20 pF
20 pF
20 pF
4.7 µF + 2 × 220
nF
4.7 µF + 2 × 220
nF
4.7 µF + 2 × 220
nF
2100
400
5
4.7 µF + 2 × 220
nF
12
12
4.7 µF + 2 × 220
nF
2100
(1) Optimized for superior load transient performance from 0 to 100% rated load.
(2) Optimized for size constrained end applications.
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9.2.1 Design 1: Low Power 24-V, 600-mA PFM Converter
9.2.1.1 Design Requirements
Example requirements for a typical 5-V or 3.3-V application. The input voltages are here for illustration purposes
only. See 节7 for the operating input voltage range.
表9-2. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
12 V to 24 V steady state, 4.2 V to 60-V transients
Output voltage
5 V/3.3 V
Maximum output current
Switching frequency
0 A to 0.6 A
400 kHz
Current consumption at 0-A load
Switching frequency at 0-A load
Critical: Need to ensure low current consumption to reduce battery drain
Not critical: Need fixed frequency operation at high load only
表9-3. List of Components for Design 1
VOUT
FREQUENCY
400 kHz
RFBB
COUT
L
U1
5 V
2 × 22 µF
2 × 22 µF
LMR36006AQRNXRQ1
LMR36006AQRNXRQ1
24.9 kΩ
43.3 kΩ
22 µH, 250 mΩ
22 µH, 250 mΩ
3.3 V
400 kHz
LMR36006FSCQRNXR
Q1
3.3 V
3.3 V
2100 kHz
2100 kHz
1 × 15 µF
1 × 15 µF
43.2 kΩ
43.2 kΩ
7.8 µH, 13.6 mΩ
7.8 µH, 13.6 mΩ
LMR36006FSCQRNXR
Q1
9.2.1.2 Detailed Design Procedure
The following design procedure applies to 图9-1 and 表9-2.
9.2.1.2.1 Custom Design With WEBENCH Tools
Click here to create a custom design using the LMR36006-Q1 device and the WEBENCH Power Designer.
1. Start by entering the input voltage, output voltage, and output current requirements
2. Optimize the design for key performance such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases the following features are available with this tool:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to help understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print full design reports in PDF.
Get more information at ti.com
9.2.1.2.2 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example, 400 kHz is used.
9.2.1.2.3 Setting the Output Voltage
For the fixed output voltage versions, FB is connected directly to the output voltage node. Preferably, near the
top of the output capacitor. If the feedback point is located further away from the output capacitors (that is,
remote sensing), then a small 100-nF capacitor may be needed at the sensing point.
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9.2.1.2.3.1 FB for Adjustable Output
The output voltage of LMR36006-Q1 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in the Electrical Characteristics table. The divider network is comprised of
RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter regulates the
output voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance
of the divider is a compromise between excessive noise pick-up and excessive loading of the output. Smaller
values of resistance reduce noise sensitivity but also reduce the light-load efficiency. The recommended value
for RFBT is 100 kΩ; with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a feed-forward
capacitor must be used across this resistor to provide adequate loop phase margin (see 节 9.2.1.2.9). Once
RFBT is selected, 方程式3 is used to select RFBB. VREF is nominally 1 V .
RFBT
RFBB
=
»
…
ÿ
VOUT
VREF
-1
Ÿ
⁄
(3)
For this 5-V example values are: RFBT = 100 kΩand RFBB = 24.9 kΩ.
9.2.1.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the
maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, use the the maximum device current. 方程式 4 can be used to
determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example,
K = 0.4 was chosen and an inductance of L = 16.4 µH was found; the standard value of 10 µH was selected.
(
V
IN - VOUT
)
VOUT
L =
∂
fSW ∂K ∂IOUTmax
V
IN
(4)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC
.
This ensures that the inductor does not saturate even during a short circuit on the output. When the inductor
core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated inductor
can cause the current to rise to high values very rapidly. This can lead to component damage; do not allow the
inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about
1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit, ILIMIT
.
To avoid subharmonic oscillation, the inductance value must not be less than that given in 方程式5:
VOUT
LMIN í 0.28 ∂
fSW
(5)
9.2.1.2.5 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements rather than the
output voltage ripple. 方程式 6 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
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K2
12
»
…
…
ÿ
DIOUT
fSW ∂ DVOUT ∂K
COUT
í
∂
(
1- D
)
∂
(
1+ K
)
+
∂
(
2 - D
)
Ÿ
Ÿ
⁄
(
2 + K
)
∂ DVOUT
ESR Ç
K2
1
»
ÿ
≈
’
2∂ DIOUT 1+ K +
∂∆1+
÷
÷
…
Ÿ
∆
12
(1- D)
…
«
◊Ÿ
⁄
VOUT
D =
V
IN
(6)
where
• ΔVOUT = output voltage transient
• ΔIOUT = output current transient
• K = ripple factor from 节9.2.1.2.4
Once the output capacitor and ESR have been calculated, 方程式 7 can be used to check the output voltage
ripple.
1
Vr @ DIL ∂ ESR2 +
2
8∂ fSW ∂COUT
(7)
where
• Vr = peak-to-peak output voltage ripple
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
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9.2.1.2.6 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7 µF is required on
the input of the LMR36006-Q1. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple, maintain the input voltage during load transients, or both. In addition, a small case size 220-nF
ceramic capacitor must be used at the input as close a possible to the regulator. This provides a high frequency
bypass for the control circuits internal to the device. For this example, a 4.7-µF, 100-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 100 V with an X7R dielectric. The VQFN package
provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the
input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the
effectiveness of the input bypassing. In this example, place two 220-nF ceramic capacitors at each VIN-PGND
location.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
RMS value of this current can be calculated from 方程式 8 and should be checked against the manufacturers'
maximum ratings.
IOUT
IRMS
@
2
(8)
9.2.1.2.7 CBOOT
The LMR36006-Q1 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This
capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic
capacitor of 100 nF and at least 16 V is required.
9.2.1.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this
output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for
the power-good function (see 节 8.3.1). A value in the range of 10 kΩ to 100 kΩ is a good choice in this case.
The nominal output voltage on VCC is 5 V.
9.2.1.2.9 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. 方程式 9 can be used to estimate the value of CFF.
The value found with 方程式 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
VOUT ∂COUT
CFF
<
VREF
VOUT
120 ∂RFBT
∂
(9)
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9.2.1.2.9.1 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in 图9-3 can be used. The input voltage at which the device turns on is
designated VON; while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100
kΩand then 方程式10 is used to calculate RENT and VOFF
.
VIN
RENT
EN
RENB
图9-3. Setup for External UVLO Application
≈
∆
∆
«
’
÷
◊
VON
÷
RENT
=
-1 ∂RENB
VEN-H
≈
’
÷
÷
◊
VEN-HYS
VEN
∆
VOFF = VON ∂ 1-
∆
«
(10)
where
• VON = VIN turnon voltage
• VOFF = VIN turnoff voltage
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9.2.1.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR36006-Q1 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA of the device, and PCB combination. The maximum internal die temperature for the LMR36006-Q1 must
be limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. 方程式 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC
Package Thermal Metrics application report, the values given in are not valid for design purposes and must not
be used to estimate the thermal performance of the application. The values reported in that table were measured
under a specific set of conditions that are rarely obtained in an actual application.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(11)
where
• η= efficiency
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement; to mention just a few. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP
is not available. This means that this package exhibits a somewhat greater RθJA. A typical example of RθJA vs
copper board area can be found in 图 9-4. Note that the data given in this graph is for illustration purposes only,
and the actual performance in any given application depends on all of the factors mentioned above.
70
65
60
55
50
45
RNX, 4L
60
40
0
10
20
30
40
50
70
Copper Area (cm2)
C005
图9-4. RθJA versus Copper Board Area for the VQFN (RNX) Package
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given
application environment:
• Thermal Design by Insight not Hindsight Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Using New Thermal Metrics Application Report
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9.2.1.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 24 V, TA = 25°C. The circuit is shown in 图 9-1,
with the appropriate BOM from 表9-3.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
8 VIN
6 VIN
12 VIN
24 VIN
48 VIN
60 VIN
12 VIN
24 VIN
48 VIN
60 VIN
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Output Current (A)
Output Current (A)
3p3V
5Vou
VOUT = 5 V
400 kHz
VOUT = 3.3 V
400 kHz
图9-5. Efficiency
图9-6. Efficiency
5.04
5.03
5.02
5.01
5
3.335
3.33
6 VIN
8 VIN
12 VIN
24 VIN
48 VIN
60 VIN
12 VIN
24 VIN
48 VIN
60 VIN
3.325
3.32
3.315
3.31
3.305
3.3
4.99
4.98
4.97
4.96
3.295
3.29
3.285
3.28
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
0.6
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
0.6
LMR3
5vou
VOUT = 3.3 V
400 kHz
VOUT = 5 V
400 kHz
图9-8. Load Regulation
图9-7. Load Regulation
4.5E+5
4E+5
3.5E+5
3E+5
2.5E+5
2E+5
1.5E+5
1E+5
5E+4
0
6
5.5
5
IOUT = 1.5 mA
IOUT = 300 mA
IOUT = 600 mA
4.5
4
IOUT = 300 mA
IOUT = 600 mA
3.5
3
5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Input Voltage (V)
6
4
4.2 4.4 4.6 4.8 5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
LMR3
LMR3
VOUT = 5 V
400 kHz
VOUT = 5 V
400 kHz
图9-10. Frequency Dropout Characteristic
图9-9. Overall Dropout Characteristic
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50
45
40
35
30
25
20
225
200
175
150
125
100
75
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
LMR3
iq-v
VOUT = 3.3 V
400 kHz
VOUT = 3.3 V
IOUT= 0 A
RFBT= 100 kΩ
图9-12. Mode Change Thresholds
图9-11. Input Supply Current
VOUT = 5 V
400 kHz
VOUT = 5 V
400 kHz
图9-14. Start-Up Waveform
图9-13. Start-Up Waveform
VOUT = 5 V
400 kHz
ILOAD= 0 A - 0.3 A
VOUT = 3.3 V
400 kHz
ILOAD= 0 A - 0.3 A
Slew Rate=1µs/A
Slew Rate = 1 µs/A
图9-15. Load Transient
图9-16. Load Transient
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VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 150kHz to 30 MHz
Frequency Tested: 30 MHz to 108 MHz
图9-17. Conducted EMI vs. CISPR25 Limits
(Yellow: Peak Signal, Blue: Average Signal)
图9-18. Conducted EMI vs. CISPR25 Limits
(Yellow: Peak Signal, Blue: Average Signal)
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 150 kHz to 30 MHz
Frequency Tested: 30 MHz to 200 MHz
图9-19. Radiated EMI Rod vs. CISPR25 Limits
图9-20. Radiated EMI Bicon Vertical vs. CISPR25
Limits
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 30 MHz to 200 MHz
Frequency Tested: 200 MHz to 1 GHz
图9-21. Radiated EMI Bicon Horizontal vs.
图9-22. Radiated EMI Log Vertical vs. CISPR25
CISPR25 Limits
Limits
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VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 200 MHz to 1 GHz
Frequency Tested: 1.83 GHz to 2.5 GHz
图9-23. Radiated EMI Log Horizontal vs. CISPR25
图9-24. Radiated EMI Horn Vertical vs. CISPR25
Limits
Limits
83H9652
VIN
IN+
FB1
+
CD = 100 uF
GND
INœ
CF2 = 0.1 uF
CF1 = 4.7 uF
CF3 = 4.7 uF
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 1.8 GHz to 2.5 GHz
图9-25. Radiated EMI Horn Horizontal vs. CISPR25
Limits
图9-26. Recommended Input EMI Filter
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9.2.2 Design 2: High Density 12-V, 600-mA FPWM Converter
9.2.2.1 Design Requirements
Example requirements for a typical 3.3-V application. The input voltages are here for illustration purposes only.
See 节7 for the operating input voltage range.
表9-4. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
6-V to 18-V steady state, 4.2-V to 60-V transients
3.3 V
Output voltage
Maximum output current
Switching frequency
0 A to 600 mA
2100 kHz
Current consumption at 0-A load
Switching frequency at 0-A load
Not critical: < 100 mA acceptable
Critical: Need fixed frequency operation
表9-5. List of Components for Design 2
VOUT
3.3 V
FREQUENCY
RFBB
COUT
L
U1
2100 kHz
1 × 15 µF
LMR36006FSCQRNXRQ1
43.2 kΩ
7.8 µH, 13.6 mΩ
9.2.2.2 Detailed Design Procedure
See 节9.2.1.2.
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9.2.2.3 Application Curves
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
3.38
3.36
3.34
3.32
3.3
3.28
3.26
3.24
3.22
6 VIN
12 VIN
18 VIN
6 VIN
12 VIN
18 VIN
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
0.6
0
0.1
0.2
0.3
Output Current (A)
0.4
0.5
0.6
D007
D009
VOUT = 3.3 V
2100 kHz
VOUT = 3.3 V
2100 kHz
图9-27. Efficiency
图9-28. Load Regulation
2.4E+6
24
23
22
21
20
19
18
17
16
15
2.2E+6
2E+6
1.8E+6
1.6E+6
1.4E+6
1.2E+6
1E+6
8E+5
6E+5
4E+5
2E+5
0
IOUT = 300 mA
IOUT = 600 mA
10
15
20
25
30
35
40
Input Voltage (V)
45
50
55
60
14
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
Freq
iqvi
图9-29. Switching Frequency vs Input Voltage
VOUT = 3.3 V
IOUT= 0 A
RFBT= 100 kΩ
图9-30. Input Supply Current
VOUT = 3.3 V
2100 kHz
VOUT = 3.3 V
2100 kHz
ILOAD= 0 A - 0.3 A
Slew Rate = 1 µs/A
图9-31. Start-Up Waveform
图9-32. Load Transient
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VOUT = 3.3 V
Slew Rate = 1 µs/A
2100 kHz
ILOAD= 0 A - 0.6 A
图9-33. Load Transient
9.3 What to Do and What Not to Do
• Don't: Exceed the Absolute Maximum Ratings.
• Don't: Exceed the ESD Ratings.
• Don't: Allow the EN input to float.
• Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
• Don't: Use the thermal data given in the Thermal Information table to design your application.
• Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Support Resources).
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with 节 7 found in this data sheet. In addition, the
input supply must be capable of delivering the required input current to the loaded regulator. The average input
current can be estimated with 方程式12.
VOUT ∂IOUT
IIN
=
VIN ∂ h
(12)
where
• ηis the efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shutdown, reset, or both. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator, use an aluminum or tantalum input capacitor in parallel with the
ceramics, or both. The moderate ESR of these types of capacitors help to damp the input resonant circuit and
reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and
help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DCDC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power
ground, as shown in 图 11-1. This loop carries large transient currents that can cause large transient voltages
when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. 图 11-2 shows a recommended layout for the critical components of the
LMR36006-Q1.
1. Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. VIN and GND
pins are adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the
BOOT and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as
a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in 节9.2.1.2.10, enough copper area must be
used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. The
top and bottom PCB layers must be made with two ounce copper; and no less than one ounce. If the PCB
design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner
layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
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VIN
CIN
SW
GND
图11-1. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground
plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control
circuitry. Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors.
PGND pins are connected directly to the source of the low-side MOSFET switch and also connected directly to
the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can
bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one
side of the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes.
Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1
oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding, and lower thermal resistance.
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11.2 Layout Example
VOUT
VOUT
INDUCTOR
COUT
COUT
COUT
COUT
GND
GND
CIN
CIN
CHF
CHF
12
1
11
10
9
2
3
4
VIN
EN
PGOOD
VIN
8
5
6
7
CVCC
RFBB
GND
GND
HEATSINK
HEATSINK
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
VIN Strap on Inner Layer
VIA to Signal Layer
VIA to GND Planes
VIA to VIN Strap
Top
Inner GND Plane
VIN Strap and
GND Plane
Signal
traces and
GND Plane
Trace on Signal Layer
图11-2. Example Layout
Copyright © 2022 Texas Instruments Incorporated
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LMR36006-Q1
ZHCSIN5D –AUGUST 2018 –REVISED AUGUST 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
• Two-Stage Power Supply Reference Design for Field Transmitters
• Wide Vin Power Supply Reference Design for Space-Constrained Industrial Sensors
• Automotive ADAS camera power supply reference design optimized for solution size and low noise
• How a DC/DC converter package and pinout design can enhance automotive EMI performance
• Introduction to Buck Converters Features: UVLO, Enable, Soft Start, Power Good
• Introduction to Buck Converters: Understanding Mode Transitions
• Introduction to Buck Converters: Minimum On-time and Minimum Off-time Operation
• Introduction to Buck Converters: Understanding Quiescent Current Specifications
• Trade-offs between thermal performance and small solution size with DC/DC converters
• Reduce EMI and shrink solution size with Hot Rod packaging
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR36006-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Designing High-Performance, Low-EMI Automotive Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Application Report
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
Copyright © 2022 Texas Instruments Incorporated
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LMR36006-Q1
ZHCSIN5D –AUGUST 2018 –REVISED AUGUST 2022
www.ti.com.cn
12.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LMR36006-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR36006AQRNXRQ1
LMR36006AQRNXTQ1
LMR36006BQRNXRQ1
LMR36006FSC3RNXRQ1
LMR36006FSC3RNXTQ1
LMR36006FSCQRNXRQ1
LMR36006FSCQRNXTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNX
RNX
RNX
RNX
RNX
RNX
RNX
12
12
12
12
12
12
12
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
NH06AQ
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU
NH06AQ
NH06BQ
NH6C3Q
NH6C3Q
NH06CQ
NH06CQ
3000 RoHS & Green
3000 RoHS & Green
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
NIPDAU | SN
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMR36006-Q1 :
Catalog : LMR36006
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR36006AQRNXRQ1 VQFN-
HR
RNX
RNX
RNX
RNX
RNX
RNX
RNX
12
12
12
12
12
12
12
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.25
2.25
2.25
2.25
2.25
2.25
2.25
3.25
3.25
3.25
3.25
3.25
3.25
3.25
1.05
1.05
1.05
1.05
1.05
1.05
1.05
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LMR36006AQRNXTQ1 VQFN-
HR
LMR36006BQRNXRQ1 VQFN-
HR
3000
3000
250
LMR36006FSC3RNXRQ1 VQFN-
HR
LMR36006FSC3RNXTQ1 VQFN-
HR
LMR36006FSCQRNXRQ1 VQFN-
HR
3000
250
LMR36006FSCQRNXTQ1 VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMR36006AQRNXRQ1
LMR36006AQRNXTQ1
LMR36006BQRNXRQ1
LMR36006FSC3RNXRQ1
LMR36006FSC3RNXTQ1
LMR36006FSCQRNXRQ1
LMR36006FSCQRNXTQ1
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNX
RNX
RNX
RNX
RNX
RNX
RNX
12
12
12
12
12
12
12
3000
250
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RNX 12
2 x 3 mm, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224286/A
PACKAGE OUTLINE
RNX0012B
VQFN-HR - 0.9 mm max height
SCALE 4.500
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.9
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1
SYMM
(0.2) TYP
5
7
4X 0.5
8
4
2X
0.675
PKG
2X
1.725
1.525
2X
1.125
0.65
A
A
11
1
12
0.3
0.2
0.1
PIN 1 ID
11X
0.3
0.2
C B A
C
0.5
0.3
11X
0.05
4223969/C 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNX0012B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.25)
12
11X (0.6)
11X
1
2X (0.65)
11
(0.25)
(1.825)
(0.788)
2X
(1.125)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
(R0.05) TYP
5
7
SYMM
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
PADS 1, 2, 10-12
(PREFERRED)
SOLDER MASK DETAILS
4223969/C 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RNX0012B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.25)
2X (0.812)
12
11X (0.6)
11X (0.25)
1
11
2X
(0.65)
(1.294)
EXPOSED METAL
PKG
2X
(1.125)
(0.282)
2X (0.675)
4X (0.5)
8
(1.4)
4
(R0.05) TYP
5
7
SYMM
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR PAD 12
87.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4223969/C 10/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RNX0012C
A
2.1
1.9
B
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1
PKG
(0.2) TYP
5
7
(0.16)
4X 0.5
8
4
2X
0.675
PKG
2X
1.125
1.725
1.525
2X
0.65
A
A
11
1
12
PIN 1 ID
0.3
0.2
0.3
0.2
11X
0.5
0.3
0.1
C A B
C
11X
0.05
4225021/C 05/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RNX0012C
(0.25)
11X (0.6)
12
11X (0.25)
2X (0.65)
11
1
(1.825)
2X
(1.125)
(0.7875)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
5
7
PKG
(1.8)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE: 20X
0.075 MAX
ALL AROUND
0.075 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225021/C 05/2022
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RNX0012C
2X (0.25)
2X (0.812)
11X (0.6)
11X (0.25)
12
2X (0.65)
1
11
EXPOSED
METAL
2X
(1.125)
(1.294)
(0.281)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
5
7
PKG
(1.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
FOR PAD 12
87.7% PRINTED COVERAGE BY AREA
SCALE: 20X
4225021/C 05/2022
NOTES: (continued)
5.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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