LMR36015SFBRNXR [TI]
LMR36015S 4.2-V to 60-V, 1.5-A Buck Converter with -55°C Junction Temperature;
| 型号： | LMR36015SFBRNXR |
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TEXAS INSTRUMENTS |
| 描述： | LMR36015S 4.2-V to 60-V, 1.5-A Buck Converter with -55°C Junction Temperature |
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LMR36015S
SNVSBV9 – JANUARY 2021
LMR36015S 4.2-V to 60-V, 1.5-A Buck Converter with -55°C Junction Temperature
1 Features
2 Applications
•
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Designed for reliable and rugged applications
– Input transient protection up to 66 V
– Junction temperature range –55°C to +150°C
– 0.4-V dropout with 1.5-A load (typical)
Suited for scalable industrial power supplies
– Pin compatible with:
•
•
•
•
•
Aerospace and defense
Field transmitters and sensors, PLC modules
Thermostats, video surveillance, HVAC systems
AC and servo drives, rotary encoders
Industrial transport, asset tracking
•
3 Description
The LMR36015S regulator is an easy-to-use,
synchronous, step-down DC/DC converter. With
integrated high-side and low-side power MOSFETs,
up to 1.5 A of output current is delivered over a wide
input voltage range of 4.2 V to 60 V. Tolerance goes
up to 66 V. The transient tolerance reduces the
necessary design effort to protect against
overvoltages and meets the surge immunity
requirements of IEC 61000-4-5.
•
•
•
LMR36006 (60 V, 0.6 A)
LMR33620/LMR33630 (36 V, 2 A, or 3 A)
– 400-kHz, 1-MHz frequency options
Small, 2-mm × 3-mm HotRod™ package
Low power dissipation across load spectrum
– 90% efficiency at 400 kHz (24 VIN, 5 VOUT, 1 A)
– 93% efficiency at 400 kHz (12 VIN, 5 VOUT, 1 A)
– Increased light load efficiency in PFM
– Low operating quiescent current of 26 µA
Solution with few external components
Optimized for ultra low EMI requirements
– Meets CISPR25 class 5 standard
– HotRod package minimizes switch node ringing
– Parallel input path minimizes parasitic
inductance
– Spread spectrum reduces peak emissions
Create a custom design using the LMR36015S
with the WEBENCH® Power Designer
•
•
The LMR36015S uses peak-current-mode control to
provide optimal efficiency and output voltage
accuracy. Load transient performance is improved
with FPWM feature in the 1-MHz regulator. Precision
enable gives flexibility by enabling a direct connection
to the wide input voltage or precise control over
device start-up and shutdown. The power-good flag,
with built-in filtering and delay, offers a true indication
of system status eliminating the requirement for an
external supervisor.
•
•
Device Information
•
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LMR36015S
VQFN-HR (12)
2.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
BOOT
VIN
VIN
CBOOT
EN
CIN
SW
VOUT
L1
COUT
PGND
VCC
LMR36015S
PG
FB
RFBT
CVCC
RFBB
AGND
VOUT = 5 V
400 kHz
Simplified Schematic
Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR36015S
SNVSBV9 – JANUARY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 2
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 5
8.1 Absolute Maximum Ratings ....................................... 5
8.2 ESD Ratings .............................................................. 5
8.3 Recommended Operating Conditions ........................5
8.4 Thermal Information ...................................................6
8.5 Electrical Characteristics ............................................6
8.6 Timing Requirements .................................................7
8.7 System Characteristics .............................................. 8
8.8 Typical Characteristics................................................9
9 Detailed Description......................................................10
9.1 Overview...................................................................10
9.2 Functional Block Diagram......................................... 11
9.3 Feature Description...................................................11
9.4 Device Functional Modes..........................................16
10 Application and Implementation................................18
10.1 Application Information........................................... 18
10.2 Typical Application.................................................. 18
10.3 What to Do and What Not to Do............................. 32
11 Power Supply Recommendations..............................33
12 Layout...........................................................................34
12.1 Layout Guidelines................................................... 34
12.2 Layout Example...................................................... 36
13 Device and Documentation Support..........................37
13.1 Device Support....................................................... 37
13.2 Documentation Support.......................................... 37
13.3 Receiving Notification of Documentation Updates..37
13.4 Support Resources................................................. 37
13.5 Trademarks.............................................................38
13.6 Electrostatic Discharge Caution..............................38
13.7 Glossary..................................................................38
14 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
January 2021
*
Initial release
5 Description (continued)
The LMR36015S is in a HotRod package which enables low noise, higher efficiency, and the smallest package
to die ratio. The device requires few external components and has a pinout designed for simple PCB layout. The
small solution size and feature set of the LMR36015S are designed to simplify implementation for a wide range
of end equipment, including space critical applications of ultra-small field transmitters and vision sensors.
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6 Device Comparison Table
ORDERABLE PART
NUMBER
OUTPUT VOLTAGE
FPWM
fSW
PACKAGE QUANTITY
LMR36015SARNXR
LMR36015SFBRNXR
LMR36015SBRNXR
Adjustable
Adjustable
Adjustable
No
Yes
No
400 kHz
1 MHz
1 MHz
3000
3000
3000
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7 Pin Configuration and Functions
SW
12
1
2
11 PGND
10 VIN
PGND
VIN
9
3
4
EN
NC
PG
8
BOOT
6
7
5
AGND
VCC
FB
Figure 7-1. 12-Pin VQFN-HR RNX Package (Top View)
Table 7-1. Pin Functions
NO.
NAME
PGND
VIN
TYPE
DESCRIPTION
1, 11
2, 10
G
P
Power ground terminal. Connect to system ground and AGND. Connect to CIN with short wide traces.
Input supply to regulator. Connect to CIN with short wide traces.
Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT capacitor to the
SW pin. This pin has no internal connection to the regulator.
3
4
NC
—
P
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this
pin to the SW pin. Connect the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin.
BOOT
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
GND.
5
VCC
P
Analog ground for regulator and system. Ground reference for internal references and logic. All electrical
parameters are measured with respect to this pin. Connect to system ground on PCB.
6
7
AGND
FB
G
A
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not
ground.
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. Goes low when EN = Low. Can be open or grounded when
not used.
8
PG
A
9
EN
A
P
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float.
Regulator switch node. Connect to power inductor. Connect the SW pin to NC on the PCB. This
simplifies the connection from the CBOOT capacitor to the SW pin.
12
SW
A = Analog, P = Power, G = Ground
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8 Specifications
8.1 Absolute Maximum Ratings
Over operating junction temperature range of -55°C to 150°C (unless otherwise noted)(1)
MIN
MAX
66
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
Output voltage
Output voltage
VIN to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–0.3
-55
EN to AGND
66.3
5.5
V
FB to AGND
V
PG to AGND
22
V
AGND to PGND
SW to PGND
0.3
V
66.3
66.3
5.5
V
SW to PGND less than 10-ns transients
CBOOT to SW
V
V
VCC to AGND
5.5
V
Junction Temperature TJ
Storage temperature, Tstg
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
UNIT
Electrostatic
discharge
V(ESD)
Human-body model (HBM) per ANSI/ESDA/JEDEC JS-001(1)
±2500
V
Electrostatic
discharge
V(ESD)
Charged-device model (CDM) per JEDEC specification JESD22-C101(2)
±750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –55℃ to 150℃ (unless otherwise noted)(1)
MIN
4.2
0
MAX
UNIT
VIN to PGND
EN to PGND(2)
PG to PGND(2)
IOUT
60
60
V
V
V
A
Input voltage
0
18
Output current
0
1.5
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
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UNIT
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8.4 Thermal Information
LMR36015S
THERMAL METRIC(1)
RNX (VQFN-HR)
12 PINS
72.5
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
35.9
23.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.8
ψJB
23.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –55°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating quiescent current (non-
switching)(2)
IQ-nonSW
ISD
VEN = 3.3 V (PFM variant only)
VEN = 0 V
18
26
5
36
µA
µA
Shutdown quiescent current;
measured at VIN pin
ENABLE (EN PIN)
VEN-VCC-H
VEN-VCC-L
VEN-VOUT-H
Enable input high level for VCC output VENABLE rising
1.14
1.3
V
V
Enable input low level for VCC output
Enable input high level for VOUT
VENABLE falling
0.3
VENABLE rising
1.157
1.231
110
V
VEN-VOUT-HYS Enable input hysteresis for VOUT
ILKG-EN Enable input leakage current
INTERNAL LDO (VCC PIN)
Hysteresis below VENABLE-H; falling
VEN = 3.3V
mV
nA
0.2
VCC
Internal VCC voltage
6 V ≤ VIN ≤ 60 V
VCC rising
4.75
3.6
5
5.25
4.0
V
V
VCC-UVLO-
Internal VCC undervoltage lockout
Internal VCC undervoltage lockout
3.8
Rising
VCC-UVLO-
VCC falling
3.1
3.3
3.5
V
Falling
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
0.985
1
1.015
V
ILKG-FB
Feedback leakage current
FB = 1 V
0.2
nA
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(3)
2
2.4
1.8
2.8
A
A
A
A
A
ILS-LIMIT
IL-ZC
IPEAK-MIN
IL-NEG
Low-side current limit(3)
1.55
2.07
Zero cross detector threshold
Minimum inductor peak current(3)
Negative current limit(3)
PFM variants only
FPWM variant only
0.02
0.45
–1.4
–1.8
–0.9
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Limits apply over operating junction temperature (TJ ) range of –55°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
VPG-LOW-DN
Power-Good upper threshold - rising
% of FB voltage
105%
90%
107%
93%
110%
95%
Power-Good lower threshold - falling
% of FB voltage
% of FB voltage
Power-Good hysteresis (rising &
falling)
VPG-HYS
TPG
2%
Power-Good rising/falling edge
deglitch delay
80
140
200
2
µs
V
Minimum input voltage for proper
Power-Good function
VPG-VALID
RPG
Power-Good on-resistance
Power-Good on-resistance
VEN = 2.5 V
VEN = 0 V
80
35
165
90
Ω
Ω
RPG
OSCILLATOR
FOSC
Internal oscillator frequency
Internal oscillator frequency
1-MHz variant
0.85
340
1
1.15
460
MHz
kHz
FOSC
400-kHz variant
400
MOSFETS
RDS-ON-HS
RDS-ON-LS
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
IOUT = 0.5 A
IOUT = 0.5 A
225
150
435
280
mΩ
mΩ
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
8.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –55°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
MIN
NOM
MAX
83
73
12
6
UNIT
tON-MIN
tOFF-MIN
tON-MAX
tSS
Minimum switch on-time
Minimum switch off-time
Maximum switch on-time
Internal soft-start time
55
ns
53
ns
7
µs
3
4.5
ms
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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8.7 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –55℃ to 150℃. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
4.2
60
V
Adjustable output voltage
regulation(1)
VOUT
PFM operation
–1.5%
–1.5%
2.5%
1.5%
Adjustable output voltage
regulation(1)
VOUT
FPWM operation
Input supply current when in
regulation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
ISUPPLY
DMAX
VHC
26
98%
0.4
µA
Maximum switch duty cycle(2)
FB pin voltage required to trip short-
circuit hiccup mode
V
Time between current-limit hiccup
burst
tHC
94
ms
tD
Switch voltage dead time
2
170
158
ns
°C
°C
TSD
TSD
Thermal shutdown temperature
Thermal shutdown temperature
Shutdown temperature
Recovery temperature
(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to 1.5 A
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
= 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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8.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C. VIN = 24 V.
VFB = 1 V
EN = 0 V
Figure 8-1. Non-Switching Input Supply Current
Figure 8-2. Shutdown Supply Current
VIN = 24 V
VIN = 24 V
Figure 8-3. High Side Current Limit
Figure 8-4. Low Side Current Limit
IOUT = 0 A
VOUT = 3.3 V
ƒSW = 400 kHz
Figure 8-6. IPEAK-MIN
Figure 8-5. Reference Voltage Drift
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9 Detailed Description
9.1 Overview
The LMR36015S is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial
applications. The regulator automatically switches modes between PFM and PWM, depending on load. At heavy
loads, the device operates in PWM at a constant switching frequency. At light loads, the mode changes to PFM
with diode emulation allowing DCM. This reduces the input supply current and keeps efficiency high. The device
features internal loop compensation which reduces design time and requires fewer external components than
externally compensated regulators.
The LMR36015S is designed with a flip-chip or HotRod technology, greatly reducing the parasitic inductance of
pins. In addition, the layout of the device allows for reduction in the radiated noise generated by the switching
action through partial cancellation of the current generated magnetic field. As a result, the switch-node waveform
exhibits less overshoot and ringing.
2V/div
50ns/div
BW:500MHz
Figure 9-1. Switch Node Waveform
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9.2 Functional Block Diagram
VCC
VIN
INT. REG.
BIAS
OSCILLATOR
BOOT
ENABLE
LOGIC
HS CURRENT
SENSE
EN
ꢀ
1.0V
Reference
PWM
COMP.
ERROR
AMPLIFIER
+
-
CONTROL
LOGIC
DRIVER
SW
+
-
FB
LS CURRENT
SENSE
PFM MODE
CONTROL
PG
POWER GOOD
CONTROL
AGND PGND
9.3 Feature Description
9.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36015S can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by reference
to Figure 9-2 and Figure 9-3. Note that during initial power up, a delay of about 4 ms (typical) is inserted from the
time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up
and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4
mA.
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VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN
(105%)
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
Figure 9-2. Static Power-Good Operation
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Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
<tPG
PG
tPG
Figure 9-3. Power-Good-Timing Behavior
tPG
tPG
9.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see Section 10.2.1.2.9.1). Applying a voltage
of ≥ VEN-VCC-H causes the device to enter standby mode, powering the internal VCC, but not producing an output
voltage. Increasing the EN voltage to VEN-OUT-H (VEN-H in Figure 9-4) fully enables the device, allowing it to enter
start-up mode and starting the soft-start period. When the EN input is brought below VEN-OUT-H (VEN-H in Figure
9-4) by VEN-OUT-HYS (VEN-HYS in Figure 9-4), the regulator stops running and enters standby mode. Further
decrease in the EN voltage to below VEN-VCC-L completely shuts down the device. This behavior is shown in
Figure 9-4. The EN input can be connected directly to VIN if this feature is not needed. This input must not be
allowed to float. The values for the various EN thresholds can be found in Section 8.5.
The LMR36015S uses a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. A typical start-up waveform is shown in Figure 9-5 along with typical
timings. The rise time of the output voltage is about 4 ms.
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EN
VEN-H
VEN-H œ VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5 V
0
VOUT
VOUT
0
Figure 9-4. Precision Enable Behavior
Figure 9-5. Typical Start-up Behavior VIN = 24 V, VOUT = 3.3 V, IOUT = 1.5 A
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9.3.3 Current Limit and Short Circuit
The LMR36015S incorporates valley current limit for normal overloads and for short-circuit protection. In
addition, the high-side power MOSFET is protected from excessive current by a peak current limit circuit. Cycle-
by-cycle current limit is used for overloads, while hiccup mode is used for short circuits. Finally, a zero current
detector is used on the low-side power MOSFET to implement diode emulation mode (DEM) at light loads (see
Section 13.7).
During overloads, the low-side current limit, ILIMIT, determines the maximum load current that the LMR36015S
can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not
fall below ILIMIT before the next turnon cycle, then that cycle is skipped, and the low-side MOSFET is left on until
the current falls below ILIMIT. This is somewhat different than the more typical peak current limit and results in
Equation 1 for the maximum load current.
(
V
IN - VOUT
)
∂
VOUT
IOUT
= ILIMIT
+
max
2∂ fSW ∂L
V
IN
(1)
where
•
•
fSW = switching frequency
L = inductor value
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
hiccup mode. In this mode, the device stops switching for tHC or about 94 ms, and then goes through a normal
re-start with soft start. If the short-circuit condition remains, the device runs in current limit for about 20 ms
(typical) and then shuts down again. This cycle repeats, as shown in Figure 9-6, as long as the short-circuit
condition persists. This mode of operation helps reduce the temperature rise of the device during a hard short on
the output. Of course, the output current is greatly reduced during hiccup mode. Once the output short is
removed and the hiccup delay is passed, the output voltage recovers normally as shown in Figure 9-6.
The high-side-current limit trips when the peak inductor current reaches ISC. This is a cycle-by-cycle current limit
and does not produce any frequency or load current foldback. It is meant to protect the high-side MOSFET from
excessive current. Under some conditions, such as high input voltages, this current limit can trip before the low-
side protection. Under this condition, ISC determines the maximum output current. Note that ISC varies with duty
cycle.
Figure 9-6. Short-Circuit Transient and Recovery
9.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR36015S incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC
pin). When VCC reaches 3.8 V (typ.), the device receives the EN signal and starts switching. When VCC falls
below 3.3 V (typ.), the device shuts down, regardless of EN status. Since the LDO is in dropout during these
transitions, the previously mentioned values roughly represent the input voltage levels during the transitions.
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Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 170°C, the device shuts down; restart occurs when the temperature falls to about
158°C.
9.4 Device Functional Modes
9.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM.
In PWM, the regulator operates as a constant frequency, current mode, full synchronous converter using PWM
to regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency of
these bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see
Section 13.7). This mode provides high light-load efficiency by reducing the amount of input supply current
required to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger
output voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light
loads. The actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and
load. Typical switching waveforms in PFM and PWM are shown in Figure 9-7 and Figure 9-8. See Section 10.2.2
for output voltage variation with load in auto mode.
Figure 9-7. Typical PFM Switching Waveforms VIN = Figure 9-8. Typical PWM Switching Waveforms VIN
24 V, VOUT = 5 V, IOUT = 200 mA
= 24 V, VOUT = 5 V, IOUT = 1.5 A, ƒS = 400 kHz
9.4.2 Forced PWM Operation
The following select variant or variants are factory options made available for cases when constant frequency
operation is more important than light load efficiency.
Table 9-1. LMR36015S Device Variants with Fixed Frequency Operation at No Load
ORDERABLE PART NUMBER
OUTPUT VOLTAGE
FPWM
fSW
LMR36015SFBRNXR
Adjustable
Yes
1 MHz
In FPWM operation, the diode emulation feature is turned off. This means that the device remains in CCM under
light loads. Under conditions where the device must reduce the on-time or off-time below the ensured minimum
to maintain regulation, the frequency reduces to maintain the effective duty cycle required for regulation. This
occurs for very high and very low input/output voltage ratios. When in FPWM mode, a limited reverse current is
allowed through the inductor allowing power to pass from the output of the regulator to its input. Note that in
FPWM mode, larger currents pass through the inductor, if lightly loaded, than in auto mode. Once loads are
heavy enough to necessitate CCM operation, FPWM mode has no measurable effect on regulator operation.
9.4.3 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is
reduced to near the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
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Beyond this point, the switching can become erratic, the output voltage falls out of regulation, or both. To avoid
this problem, the LMR36015S automatically reduces the switching frequency to increase the effective duty cycle
and maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the input
and output voltage when the output has dropped by 1% of its nominal value. Under this condition, the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4-V short circuit detection
threshold is not activated when in dropout mode. Typical dropout characteristics can be found in Figure 9-9 and
Figure 9-10.
4.5E+5
4E+5
3.5E+5
3E+5
2.5E+5
2E+5
1.5E+5
1E+5
5E+4
0
6
5.5
5
4.5
4
IOUT = 0.75 A
IOUT = 1.5 A
IOUT = 0.0015 A
IOUT = 0.75 A
IOUT = 1.5 A
3.5
3
5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Input Voltage (V)
6
4
4.2 4.4 4.6 4.8 5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
LMR3
LMR3
Figure 9-10. Frequency Dropout Characteristics
ƒSW = 400 kHz
Figure 9-9. Overall Dropout Characteristic
VOUT = 5 V
9.4.4 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle and, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR36015S automatically reduces the switching frequency when the
minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before
frequency foldback occurs, is found in Equation 2. As the input voltage is increased, the switch on-time (duty
cycle) reduces to regulate the output voltage. When the on-time reaches the limit, the switching frequency drops,
while the on-time remains fixed.
VOUT
V
Ç
IN
tON ∂ fSW
(2)
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The LMR36015S step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 1.5 A. The following design procedure can be used to select
components for the LMR36015S. Alternately, the WEBENCH® Design Tool can be used to generate a complete
design. This tool utilizes an iterative design procedure and has access to a comprehensive database of
components. This allows the tool to create an optimized design and allows the user to experiment with various
options.
Note
All of the capacitance values given in the following application information refer to effective values;
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and
temperature; not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with
an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and/or higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank should be made in
order to ensure that the minimum value of effective capacitance is provided.
10.2 Typical Application
Figure 10-1 shows a typical LMR36015S application circuit. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick start guide, Table 10-1 provides typical
component values for a range of the most common output voltages.
L
VOUT
VIN
SW
VIN
VIN
CIN
CHF1
220 nF 220 nF
CHF2
CBOOT
4.7 µF
COUT
BOOT
EN
VPU
100 k
0.1 µF
LMR36015S
CFF
RFBT
100 kΩ
PG
FB
VCC
RFBB
CVCC
1 µF
PGND
PGND
AGND
Figure 10-1. Example Applications Circuit
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Table 10-1. Typical External Component Values
NOMINAL COUT
(RATED
MINIMUM COUT
(RATED
ƒSW
(kHz)
VOUT
L (µH)
RFBT (Ω) RFBB (Ω)
CIN
CFF
(V)
3.3
3.3
5
CAPACITANCE) (1)
CAPACITANCE) (2)
4.7 µF + 2 × 220
nF
400
1000
400
10
6.8
15
10
27
22
2 × 47 µF
3 × 15 µF
3 × 22 µF
3 × 15 µF
3 × 22 µF
2 × 22 µF
2 × 22 µF
2 × 15 µF
2 × 22 µF
2 × 15 µF
2 × 22 µF
2 × 15 µF
100 k
100 k
100 k
100 k
100 k
100 k
43.2 k
43.2 k
24.9 k
24.9 k
9.09 k
9.09 k
20 pF
20 pF
20 pF
20 pF
20 pF
20 pF
4.7 µF + 2 × 220
nF
4.7 µF + 2 × 220
nF
4.7 µF + 2 × 220
nF
1000
400
5
4.7 µF + 2 × 220
nF
12
12
4.7 µF + 2 × 220
nF
1000
(1) Optimized for superior load transient performance from 0 to 100% rated load.
(2) Optimized for size constrained end applications.
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10.2.1 Design 1: Low Power 24-V, 1.5-A PFM Converter
10.2.1.1 Design Requirements
Example requirements for a typical 5-V or 3.3-V application. The input voltages are here for illustration purposes
only. See Section 8 for the operating input voltage range.
Table 10-2. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
12 V to 24 V steady state, 4.2 V to 60-V transients
Output voltage
5 V/3.3 V
Maximum output current
Switching frequency
0 A to 1.5 A
400 kHz
Current consumption at 0-A load
Switching frequency at 0-A load
Critical: Need to ensure low current consumption to reduce battery drain
Not critical: Need fixed frequency operation at high load only
Table 10-3. List of Components for Design 1
VOUT
FREQUENCY
400 kHz
RFBB
COUT
L
U1
5 V
24.9 kΩ
43.3 kΩ
2 × 22 µF
2 × 22 µF
10 µH, 45 mΩ
10 µH, 45 mΩ
LMR36015SARNXR
LMR36015SARNXR
3.3 V
400 kHz
10.2.1.2 Detailed Design Procedure
The following design procedure applies to Figure 10-1 and Table 10-2.
10.2.1.2.1 Custom Design With WEBENCH Tools
Click here to create a custom design using the LMR36015S device and the WEBENCH Power Designer.
1. Start by entering the input voltage, output voltage, and output current requirements
2. Optimize the design for key performance such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases the following features are available with this tool:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to help understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print full design reports in PDF.
Get more information at ti.com
10.2.1.2.2 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example, 400 kHz is used.
10.2.1.2.3 Setting the Output Voltage
The output voltage of LMR36015S is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in Section 8.5. The divider network is comprised of RFBT and RFBB, and
closes the loop between the output voltage and the converter. The converter regulates the output voltage by
holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the divider is a
compromise between excessive noise pickup and excessive loading of the output. Smaller values of resistance
reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for RFBT is 100 kΩ,
with a maximum value of 1 MΩ. If 1 MΩ is selected for RFBT, then a feedforward capacitor must be used across
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this resistor to provide adequate loop phase margin (see Section 10.2.1.2.9). Once RFBT is selected, Equation 3
is used to select RFBB. VREF is nominally 1 V.
RFBT
RFBB
=
»
…
ÿ
VOUT
VREF
-1
Ÿ
⁄
(3)
For this 5-V example, values are: RFBT = 100 kΩ and RFBB = 24.9 kΩ.
10.2.1.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the
maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, use the the maximum device current. Equation 4 can be used
to determine the value of inductance. The constant K is the percentage of inductor current ripple. For this
example, K = 0.4 was chosen and an inductance of L = 16 µH was found; the standard value of 10 µH was
selected.
(
V
IN - VOUT
)
VOUT
L =
∂
fSW ∂K ∂IOUTmax
V
IN
(4)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC
.
This ensures that the inductor does not saturate even during a short circuit on the output. When the inductor
core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated inductor
can cause the current to rise to high values very rapidly. This can lead to component damage; do not allow the
inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about
1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit, ILIMIT
To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 5:
.
VOUT
LMIN í 0.28 ∂
fSW
(5)
10.2.1.2.5 Output Capacitor Selection
The value of the output capacitor and its ESR determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements rather than the
output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
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K2
12
»
…
…
ÿ
DIOUT
fSW ∂ DVOUT ∂K
COUT
í
∂
(
1- D
)
∂
(
1+ K
)
+
∂
(
2 - D
)
Ÿ
Ÿ
⁄
(
2 + K
)
∂ DVOUT
ESR Ç
K2
1
»
ÿ
≈
’
2∂ DIOUT 1+ K +
∂∆1+
÷
÷
…
Ÿ
∆
12
(1- D)
…
«
◊Ÿ
⁄
VOUT
D =
V
IN
(6)
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Section 10.2.1.2.4
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the output voltage
ripple.
1
Vr @ DIL ∂ ESR2 +
2
8∂ fSW ∂COUT
(7)
where
Vr = peak-to-peak output voltage ripple
•
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
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10.2.1.2.6 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7 µF is required on
the input of the LMR36015S. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple, maintain the input voltage during load transients, or both. In addition, a small case size 220-nF
ceramic capacitor must be used at the input as close a possible to the regulator. This provides a high frequency
bypass for the control circuits internal to the device. For this example, a 4.7-µF, 100-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 100 V with an X7R dielectric. The VQFN package
provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the
input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the
effectiveness of the input bypassing. In this example, place two 220-nF ceramic capacitors at each VIN-PGND
location.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
RMS value of this current can be calculated from Equation 8 and should be checked against the manufacturers'
maximum ratings.
IOUT
IRMS
@
2
(8)
10.2.1.2.7 CBOOT
The LMR36015S requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This
capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic
capacitor of 100 nF and at least 16 V is required.
10.2.1.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this
output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for
the power-good function (see Section 9.3.1). A value in the range of 10 kΩ to 100 kΩ is a good choice in this
case. The nominal output voltage on VCC is 5 V.
10.2.1.2.9 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feed-forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
VOUT ∂COUT
CFF
<
VREF
VOUT
120 ∂RFBT
∂
(9)
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10.2.1.2.9.1 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 10-2 can be used. The input voltage at which the device turns
on is designated VON while the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to
100 kΩ and then Equation 10 is used to calculate RENT and VOFF
.
VIN
RENT
EN
RENB
Figure 10-2. Setup for External UVLO Application
≈
∆
∆
«
’
÷
◊
VON
÷
RENT
=
-1 ∂RENB
VEN-H
≈
’
÷
÷
◊
VEN-HYS
VEN
∆
VOFF = VON ∂ 1-
∆
«
(10)
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
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10.2.1.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR36015S dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA of the device, and PCB combination. The maximum internal die temperature for the LMR36015S must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, then interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC
Package Thermal Metrics Application Report, the values given in Section 8.4 are not valid for design purposes
and must not be used to estimate the thermal performance of the application. The values reported in that table
were measured under a specific set of conditions that are rarely obtained in an actual application.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(11)
where
η = efficiency
•
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement, to mention just a few. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP
is not available. This means that this package exhibits a somewhat greater RθJA. A typical example of RθJA
versus copper board area can be found in Figure 10-3. Note that the data given in this graph is for illustration
purposes only, and the actual performance in any given application depends on all of the factors mentioned
above.
70
65
60
55
50
45
RNX, 4L
60
40
0
10
20
30
40
50
70
Copper Area (cm2)
C005
Figure 10-3. RθJA versus Copper Board Area for the VQFN (RNX) Package
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application
environment:
•
•
•
•
Thermal Design by Insight not Hindsight Application Report
Semiconductor and IC Package Thermal Metrics Application Report
Thermal Design Made Simple with LM43603 and LM43602 Application Report
Using New Thermal Metrics Application Report
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10.2.2 Application Curves
Unless otherwise specified the following conditions apply: VIN = 24 V, TA = 25°C. The circuit is shown in Figure
10-1, with the appropriate BOM from Table 10-3.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
8 VIN
6 VIN
12 VIN
24 VIN
48 VIN
60 VIN
12 VIN
24 VIN
48 VIN
60 VIN
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Output Current (A)
1
2
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Output Current (A)
1
2
LMR3
LMR3
VOUT = 5 V
400 kHz
VOUT = 3.3 V
400 kHz
Figure 10-4. Efficiency
Figure 10-5. Efficiency
5.08
5.06
5.04
5.02
5
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.3
8 VIN
6 VIN
12 VIN
24 VIN
48 VIN
60 VIN
12 VIN
24 VIN
48 VIN
60 VIN
4.98
4.96
3.29
0
0.25
0.5 0.75
Output Current (A)
1
1.25
1.5
0
0.25
0.5 0.75
Output Current (A)
1
1.25
1.5
LMR3
LMR3
VOUT = 5 V
400 kHz
VOUT = 3.3 V
400 kHz
Figure 10-6. Load Regulation
Figure 10-7. Load Regulation
5.5
5
4
3.5
3
4.5
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
IOUT = 0.0015 A
IOUT = 0.75 A
IOUT = 1.5 A
IOUT = 0.0015 A
IOUT = 0.75 A
IOUT = 1.5 A
0.5
0
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
LMR3
LMR3
VOUT = 5 V
400 kHz
VOUT = 3.3 V
400 kHz
Figure 10-8. Line Regulation
Figure 10-9. Line Regulation
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6
4.5E+5
4E+5
3.5E+5
3E+5
2.5E+5
2E+5
1.5E+5
1E+5
5E+4
0
5.5
5
4.5
4
IOUT = 0.0015 A
IOUT = 0.75 A
IOUT = 1.5 A
3.5
3
IOUT = 0.75 A
IOUT = 1.5 A
4
4.2 4.4 4.6 4.8
5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Input Voltage (V)
6
LMR3
LMR3
VOUT = 5 V
400 kHz
VOUT = 5 V
400 kHz
Figure 10-10. Overall Dropout Characteristic
Figure 10-11. Frequency Dropout Characteristic
45
500
450
400
350
300
250
200
150
40
35
30
25
20
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
LMR3
LMR3
VOUT = 3.3 V
IOUT= 0 A
RFBT= 100 kΩ
VOUT = 3.3 V
400 kHz
Figure 10-12. Input Supply Current
Figure 10-13. Mode Change Thresholds
VOUT = 5 V
400 kHz
VOUT = 3.3 V
400 kHz
Figure 10-14. Start-Up Waveform
Figure 10-15. Start-Up Waveform
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VOUT = 5 V
400 kHz
VOUT = 3.3 V
400 kHz
ILOAD= 10 mA - 0.75 A
Slew Rate = 1 µs/A
ILOAD= 10 mA - 0.75 A
Slew Rate = 1 µs/A
Figure 10-16. Load Transient
Figure 10-17. Load Transient
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 150 kHz to 30 MHz
Frequency Tested: 30 MHz to 108 MHz
Figure 10-18. Conducted EMI vs. CISPR25 Limits
(Yellow: Peak Signal, Blue: Average Signal)
Figure 10-19. Conducted EMI vs. CISPR25 Limits
(Yellow: Peak Signal, Blue: Average Signal)
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 150 kHz to 30 MHz
Frequency Tested: 30 MHz to 200 MHz
Figure 10-20. Radiated EMI Rod vs. CISPR25 Limits
Figure 10-21. Radiated EMI Bicon Vertical vs.
CISPR25 Limits
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VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 30 MHz to 200 MHz
Frequency Tested: 200 MHz to 1 GHz
Figure 10-22. Radiated EMI Bicon Horizontal vs.
CISPR25 Limits
Figure 10-23. Radiated EMI Log Vertical vs.
CISPR25 Limits
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 200 MHz to 1 GHz
Frequency Tested: 1.83 GHz to 2.5 GHz
Figure 10-24. Radiated EMI Log Horizontal vs.
CISPR25 Limits
Figure 10-25. Radiated EMI Horn Vertical vs.
CISPR25 Limits
83H9652
VIN
IN+
FB1
+
CD = 100 uF
GND
INœ
CF2 = 0.1 uF
CF3 = 4.7 uF
CF1 = 4.7 uF
VIN = 13.5 V
VOUT = 5 V
IOUT = 1.5 A
Frequency Tested: 1.8 GHz to 2.5 GHz
Figure 10-27. Recommended Input EMI Filter
Figure 10-26. Radiated EMI Horn Horizontal vs.
CISPR25 Limits
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10.2.3 Design 2: High Density 24-V, 1.5-A FPWM Converter
10.2.3.1 Design Requirements
Example requirements for a typical 5-V application. The input voltages are here for illustration purposes only.
See Section 8 for the operating input voltage range.
Table 10-4. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
8-V to 24-V steady state, 4.2-V to 60-V transients
5 V
Output voltage
Maximum output current
Switching frequency
0 A to 1.5 A
1000 kHz
Current consumption at 0-A load
Switching frequency at 0-A load
Not critical: < 100 mA acceptable
Critical: Need fixed frequency operation
Table 10-5. List of Components for Design 2
VOUT
5 V
FREQUENCY
RFBB
COUT
L
U1
1000 KHz
24.9 kΩ
2 × 15 µF
8.5 µH, 30.5 mΩ
LMR36015SFBRNXR
10.2.3.2 Detailed Design Procedure
See Section 10.2.1.2.
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10.2.3.3 Application Curves
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
5.08
5.06
5.04
5.02
5
6 VIN
6 VIN
12 VIN
24 VIN
48 VIN
60 VIN
12 VIN
24 VIN
48 VIN
60 VIN
4.98
4.96
0
0.25
0.5 0.75
Output Current (A)
1
1.25
1.5
0
0.25
0.5 0.75
Output Current (A)
1
1.25
1.5
LMR3
LMR3
VOUT = 5 V
1000 kHz
VOUT = 5 V
1000 kHz
Figure 10-28. Efficiency
Figure 10-29. Load Regulation
6
5.5
5
1.2E+6
1.1E+6
1E+6
9E+5
8E+5
7E+5
6E+5
5E+5
4E+5
3E+5
2E+5
1E+5
0
4.5
4
IOUT = 0 A
IOUT = 0.75 A
IOUT = 1.5 A
IOUT = 0.0015 A
IOUT = 0.75 A
IOUT = 1.5 A
3.5
3
5
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9
Input Voltage (V)
6
4
4.2 4.4 4.6 4.8 5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
LMR3
LMR3
VOUT = 5 V
1000 kHz
VOUT = 5 V
1000 kHz
Figure 10-31. Frequency Dropout Characteristic
Figure 10-30. Overall Dropout Characteristic
22
21
20
19
18
17
16
15
14
13
12
11
10
9
5
10 15 20 25 30 35 40 45 50 55 60
Input Voltage (V)
iq-v
VOUT = 5 V
IOUT= 0 A
RFBT= 100 kΩ
VOUT = 5 V
1000 kHz
Figure 10-32. Input Supply Current
Figure 10-33. Start-Up Waveform
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VOUT = 5 V
1000 kHz
ILOAD= 0 A – 0.75 A
VOUT = 5 V
Slew Rate = 1 µs/A 1000 kHz
Slew Rate = 1 µs/A
ILOAD= 0 A – 1.5 A
Figure 10-34. Load Transient
Figure 10-35. Load Transient
10.3 What to Do and What Not to Do
•
•
•
•
•
•
Don't: Exceed the Abolsute Maximum Ratings.
Don't: Exceed the ESD Ratings.
Don't: Allow the EN input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the thermal data given in the Thermal Information table to design your application.
Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Support Resources).
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11 Power Supply Recommendations
The characteristics of the input supply must be compatible with Section 8 found in this data sheet. In addition,
the input supply must be capable of delivering the required input current to the loaded regulator. The average
input current can be estimated with Equation 12.
VOUT ∂IOUT
IIN
=
VIN ∂ h
(12)
where
•
η is the efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shutdown, reset, or both. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator, use an aluminum or tantalum input capacitor in parallel with the
ceramics, or both. The moderate ESR of these types of capacitors help to damp the input resonant circuit and
reduce any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and
help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DCDC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
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12 Layout
12.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power
ground, as shown in Figure 12-1. This loop carries large transient currents that can cause large transient
voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper
operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as
small as possible to reduce the parasitic inductance. Figure 12-2 shows a recommended layout for the critical
components of the LMR36015S.
1. Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. VIN and GND
pins are adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT
and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed
near any noise source (such as the SW node) that can capacitively couple into the feedback path of the
regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as a
heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any
voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in Section 10.2.1.2.10, enough copper area
must be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature.
The top and bottom PCB layers must be made with two ounce copper; and no less than one ounce. If the
PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the
inner layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
•
•
•
•
Layout Guidelines for Switching Power Supplies Application Report
Simple Switcher PCB Layout Guidelines Application Report
Construction Your Power Supply- Layout Considerations Seminar
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
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VIN
CIN
SW
GND
Figure 12-1. Current Loops with Fast Edges
12.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground
plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control
circuitry. Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors.
PGND pins are connected directly to the source of the low-side MOSFET switch and also connected directly to
the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can
bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one
side of the ground planes. The other side of the ground plane contains much less noise; use for sensitive routes.
Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1
oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding, and lower thermal resistance.
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12.2 Layout Example
VOUT
VOUT
INDUCTOR
COUT
COUT
COUT
COUT
GND
GND
CIN
CIN
CHF
CHF
12
1
11
10
9
2
3
4
VIN
EN
PGOOD
VIN
8
5
6
7
CVCC
RFBB
GND
GND
HEATSINK
HEATSINK
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
VIN Strap on Inner Layer
VIA to Signal Layer
VIA to GND Planes
VIA to VIN Strap
Top
Inner GND Plane
VIN Strap and
GND Plane
Signal
traces and
GND Plane
Trace on Signal Layer
Figure 12-2. Example Layout
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
•
•
•
•
•
•
•
•
•
•
Two-Stage Power Supply Reference Design for Field Transmitters
Wide Vin Power Supply Reference Design for Space-Constrained Industrial Sensors
Automotive ADAS camera power supply reference design optimized for solution size and low noise
How a DC/DC converter package and pinout design can enhance automotive EMI performance
Introduction to Buck Converters Features: UVLO, Enable, Soft Start, Power Good
Introduction to Buck Converters: Understanding Mode Transitions
Introduction to Buck Converters: Minimum On-time and Minimum Off-time Operation
Introduction to Buck Converters: Understanding Quiescent Current Specifications
Trade-offs between thermal performance and small solution size with DC/DC converters
Reduce EMI and shrink solution size with Hot Rod packaging
13.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR36015S device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
Texas Instruments, Designing High-Performance, Low-EMI Automotive Power Supplies Application Report
Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
Texas Instruments, Construction Your Power Supply- Layout Considerations Application Report
Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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13.5 Trademarks
HotRod™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR36015SARNXR
LMR36015SBRNXR
LMR36015SFBRNXR
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
RNX
RNX
RNX
12
12
12
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 150
-55 to 150
-55 to 150
ET15A
SN
SN
ET15B
ET15FB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jan-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR36015SARNXR
LMR36015SBRNXR
LMR36015SFBRNXR
VQFN-
HR
RNX
RNX
RNX
12
12
12
3000
3000
3000
180.0
180.0
180.0
8.4
8.4
8.4
2.3
2.3
2.3
3.2
3.2
3.2
1.0
1.0
1.0
4.0
4.0
4.0
8.0
8.0
8.0
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMR36015SARNXR
LMR36015SBRNXR
LMR36015SFBRNXR
VQFN-HR
VQFN-HR
VQFN-HR
RNX
RNX
RNX
12
12
12
3000
3000
3000
195.0
195.0
195.0
200.0
200.0
200.0
45.0
45.0
45.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RNX 12
2 x 3 mm, 0.5 mm pitch
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224286/A
PACKAGE OUTLINE
RNX0012B
VQFN-HR - 0.9 mm max height
SCALE 4.500
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.9
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1
SYMM
(0.2) TYP
5
7
4X 0.5
8
4
2X
0.675
PKG
2X
1.725
1.525
2X
1.125
0.65
A
A
11
1
12
0.3
0.2
0.1
PIN 1 ID
11X
0.3
0.2
C B A
C
0.5
0.3
11X
0.05
4223969/C 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNX0012B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.25)
12
11X (0.6)
11X
1
2X (0.65)
11
(0.25)
(1.825)
(0.788)
2X
(1.125)
PKG
2X
(0.675)
4X (0.5)
8
(1.4)
4
(R0.05) TYP
5
7
SYMM
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
PADS 1, 2, 10-12
(PREFERRED)
SOLDER MASK DETAILS
4223969/C 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNX0012B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.25)
2X (0.812)
12
11X (0.6)
11X (0.25)
1
11
2X
(0.65)
(1.294)
EXPOSED METAL
PKG
2X
(1.125)
(0.282)
2X (0.675)
4X (0.5)
8
(1.4)
4
(R0.05) TYP
5
7
SYMM
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR PAD 12
87.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4223969/C 10/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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