LMR36502F3RPER [TI]
具有 6μA IQ 的 3V 至 65V、150mA 超小型同步降压转换器 | RPE | 9 | -40 to 150;型号: | LMR36502F3RPER |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 6μA IQ 的 3V 至 65V、150mA 超小型同步降压转换器 | RPE | 9 | -40 to 150 转换器 |
文件: | 总50页 (文件大小:3717K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
LMR3650x 3V 至65V、100mA 和150mA 宽VIN 同步降压转换器(针对尺寸和轻
负载效率进行了优化)
1 特性
3 说明
• 提供功能安全
LMR3650x 是业内超小型 65V、150mA、100mA 同步
直流/直流降压转换器,采用 4mm2 HotRod 封装。这
款易于使用的转换器可处理高达 70V 的输入电压瞬
变,提供出色的 EMI 性能,并支持固定、3.3V、5V 和
其他可调输出电压。
– 可提供用于功能安全系统设计的文档
• 专用于条件严苛的工业应用:
– 结温范围:–40°C 至+150°C
– 高达70V 的输入瞬态保护
– 宽输入电压范围:3.0V(下降阈值)至65V
– 超低开关节点振铃以降低EMI
– 提供可调和固定输出3.3V 和5V 电压选项
• 适用于可扩展的工业电源:
LMR3650x 采用具有内部补偿的峰值电流模式控制架
构,用于维持稳定运行和超小的输出电容。LMR3650x
在RT 引脚与地之间选用合适的电阻器后,可通过外部
编程在200kHz 至2.2MHz 的宽范围内实现理想的开关
频率。借助精密 EN/UVLO 功能,可对器件启动和关断
进行精确控制。附带内置干扰滤波器和延迟释放功能的
PGOOD 标志可提供系统状态的真实指示,免去了使用
外部电压监控器的麻烦。LMR3650x 紧凑的解决方案
尺寸和丰富的功能集简化了各种工业应用的实施。
– 引脚与LMR36503(65V,300mA)和
LMR36506(65V,600mA)兼容
– 可调开关频率:200kHz 至
2.2MHz(采用RT 引脚型号时)
• 减小了解决方案尺寸并降低了成本:
– 超小型2mm x 2mm HotRod™ 封装
器件信息
封装(1)
• 在整个负载范围内具有高效率和低功率耗散:
封装尺寸(标称值)
器件型号
– 1MHz 时峰值效率大于80%
LMR36501
RPE(VQFN-HR,
9)
2.00mm × 2.00mm
(3.3V VOUT
)
LMR36502
RPE(VQFN-HR,
9)
2.00mm × 2.00mm
2 应用
• 工厂自动化:现场发送器和过程传感器
• 楼宇自动化:HVAC 和防火安全通知及探测器
• 电器:园艺和电动工具
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 便携式电子产品:耳机和耳塞
100
90
80
70
60
50
40
BOOT
VIN
CIN
VIN
CBOOT
LIND
EN/
VOUT
COUT
SW
UVLO
RT
VCC
PGOOD
FB
RFBT
CVCC
30
RFBB
VIN = 12 V
VIN = 24 V
GND
20
VIN = 36 V
VIN = 48 V
10
0
0.001
0.01
Load Current (A)
0.1 0.15
简化原理图
效率与输出电流间的关系
VOUT = 3.3V(固定值),1MHz,AUTO
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSC31
LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Application.................................................... 27
9.3 Best Design Practices...............................................36
9.4 Power Supply Recommendations.............................36
9.5 Layout....................................................................... 36
10 Device and Documentation Support..........................39
10.1 Device Support....................................................... 39
10.2 Documentation Support.......................................... 39
10.3 接收文档更新通知................................................... 39
10.4 支持资源..................................................................39
10.5 Trademarks.............................................................39
10.6 静电放电警告.......................................................... 40
10.7 术语表..................................................................... 40
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD (Commercial) Ratings.........................................5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 System Characteristics............................................... 9
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
Information.................................................................... 41
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (March 2023) to Revision A (May 2023)
Page
• 包含了功能安全要点........................................................................................................................................... 1
• 删除了有关超高功率密度的要点.........................................................................................................................1
• 删除了 LMR36501 的预发布说明....................................................................................................................... 1
• 将说明 部分的引用更改为100mA 器件.............................................................................................................. 1
• 将效率图更新为 AUTO 模式运行........................................................................................................................1
• Included LMR36502FS5RPER...........................................................................................................................3
• Included LMR36502P3RPER............................................................................................................................. 3
• Included LMR36502PS5RPER...........................................................................................................................3
• Included LMR36501F3RPER............................................................................................................................. 3
• Included LMR36501F5RPER............................................................................................................................. 3
• Included LMR36501P3RPER............................................................................................................................. 3
• Included LMR36501P5RPER............................................................................................................................. 3
• Corrected LMR36501F5RPE to LMR36501F5RPER to signify the reel information..........................................3
• Corrected LMR36502F3RPE to LMR36502F3RPER to signify the reel information..........................................3
• Removed preview note from LMR36501F5RPE.................................................................................................3
• Removed preview note from 100-mA current limits............................................................................................5
• Corrected frequency from 1.1 MHz to 1 MHz when RT is tied to Vcc...............................................................14
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNVSC31
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LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
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5 Device Comparison Table
ORDERABLE PART NUMBER
RATED
CURRENT
OUTPUT
VOLTAGE
EXTERNAL SYNC
FSW
SPREAD SPECTRUM
(1)
No
(Default PFM at light
load)
Fixed 3.3-V /
Adjustable
Adjustable
with RT resistor
LMR36501P3RPER
LMR36501P5RPER
LMR36501F3RPER
LMR36501F5RPER
LMR36502P3RPER
LMR36502PS5RPER
LMR36502F3RPER
LMR36502FS5RPER
100 mA
No
No
(Default PFM at light
load)
Fixed 5-V /
Adjustable
Adjustable
with RT resistor
100 mA
100 mA
100 mA
150 mA
150 mA
150 mA
150 mA
No
No
No
No
Yes
No
Yes
No
Fixed 3.3-V /
Adjustable
Adjustable
with RT resistor
(Default FPWM at
light load)
No
Fixed 5-V /
Adjustable
Adjustable
with RT resistor
(Default FPWM at
light load)
No
(Default PFM at light
load)
Fixed 3.3-V /
Adjustable
Adjustable
with RT resistor
No
Fixed 5-V /
Adjustable
Adjustable
with RT resistor
(Default FPWM at
light load)
No
Fixed 3.3-V /
Adjustable
Adjustable
with RT resistor
(Default FPWM at
light load)
No
Fixed 5-V /
Adjustable
Adjustable
with RT resistor
(Default FPWM at
light load)
(1) For more information on device orderable part numbers, see 节10.1.1. Contact TI for details and availability of other device options.
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SNVSC31
LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
www.ti.com.cn
6 Pin Configuration and Functions
GND
9
RT
VOUT/FB
1
8
PGOOD
VCC
2
3
7
6
EN/UVLO
BOOT
VIN
SW
4
5
图6-1. 9-Pin (2 mm × 2 mm) VQFN-HR RPE Package (Top View)
表6-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
The switching frequency can be adjusted from 200 kHz to 2.2 MHz by selecting the appropriate
valued resistor from this pin to GND. See 节8.3.2 for more details. Do not float this pin.
1
RT
A
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. This pin goes low when EN = low. This pin can be
open or grounded when not used.
2
3
PGOOD
EN/UVLO
A
A
Enable input to regulator. High = ON, Low = OFF. Can be connected directly to VIN.
Do not float this pin.
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin
and GND.
4
5
6
VIN
SW
P
P
P
Regulator switch node. Connect to power inductor.
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 0.1-μF capacitor from
this pin to the SW pin.
BOOT
Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this
pin to GND.
7
VCC
P
Fixed output options and adjustable output options are available with the VOUT/FB pin variant.
Connect to the output voltage node for fixed VOUT. Connect to tap point of feedback voltage divider
for adjustable VOUT. See Output Voltage Selection for how to select feedback resistor divider
values. Check Device Comparison Table for more details.
8
9
VOUT/FB
GND
A
Do not float this pin.
G
Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces.
A = Analog, P = Power, G = Ground
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English Data Sheet: SNVSC31
LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
PARAMETER
MIN
–0.3
–0.3
–0.3
0
MAX
70
UNIT
V
VIN to GND
EN to GND
70
V
SW to GND
PGOOD to GND
70.3
20
V
V
VOUT/FB to GND
16
V
Voltage
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–65
BOOT to SW
5.5
5.5
5.5
5.5
150
150
V
VCC to GND
V
RT to GND (RT variant)
MODE/SYNC to GND (MODE/SYNC variant)
Junction temperature
Storage temperature
V
V
TJ
°C
°C
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD (Commercial) Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001 (1)
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per ANSI/ESDA/
JEDEC JS-002 (2)
±750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) (1) (2)
MIN
3.6
1
TYP
MAX UNIT
Input voltage
Input voltage range after startup
65
16
V
V
Output voltage
Output voltage range for adjustable output variants
LMR36501 load current range (3)
0
100 mA
150 mA
2.2 MHz
2.2 MHz
150 °C
Output current
LMR36502 load current range (3)
0
Frequency setting
External clock setting
Temperature
Selectable frequency range with RT (RT variant only)
External Sync CLK (MODE/SYNC variant only)
TJ juction temperature
0.2
0.2
-40
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics table.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125℃
(3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See
Application section for details.
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English Data Sheet: SNVSC31
LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
www.ti.com.cn
7.4 Thermal Information
The value of RθJA given in this table is only valid for comparison with other packages and cannot be used for design
purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do
not represent the performance obtained in an actual application.
LMR36501 / LMR36502
THERMAL METRIC (1)
VQFN (RPE)
9 Pins
85.7
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
64.7
28.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.0
27.7
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report. The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent
the performance obtained in an actual application. For design information see the Maximum Ambient Temperature section.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Minimum operating input voltage
(rising)
VIN_R
Rising threshold
3.4
3.0
0.5
1
3.55
V
V
Minimum operating input voltage
(falling)
VIN_F
Once operating; Falling threshold
VEN = 0 V; VIN = 13.5 V
2.45
Shutdown quiescent current; measured
at VIN pin (2)
ISD_13p5
ISD_24p0
IQ_13p5_Fixed
IQ_13p5_Adj
IQ_24p0_Fixed
IQ_24p0_Adj
IB_13p5
1.1 µA
1.6 µA
1.05 µA
22 µA
1.7 µA
22 µA
22 µA
22 µA
Shutdown quiescent current; measured
at VIN pin (2)
VEN = 0 V; VIN = 24 V
Non-switching input current; measured VIN = VEN = 13.5 V; VOUT/FB = 5.25 V, VRT = 0 V;
at VIN pin (2)
Fixed output
0.25 0.672
Non-switching input current; measured VIN = VEN = 13.5 V; VFB = 1.05 V, VRT = 0 V;
at VIN pin (2)
Adjustable output
14
0.8
14
14
14
17
1.2
18
17
18
Non-switching input current; measured VIN = VEN = 24 V; VOUT/FB = 5.25 V, VRT = 0 V;
at VIN pin (2)
Fixed output
Non-switching input current; measured VIN = VEN = 24 V; VFB = 1.05 V, VRT = 0 V;
at VIN pin (2)
Adjustable output
Current into VOUT/FB pin (not
switching) (2)
VIN = 13.5 V, VOUT/FB = 5.25 V, VRT = 0 V; Fixed
output
Current into VOUT/FB pin (not
switching) (2)
VIN = 24 V, VOUT/FB = 5.25 V, VRT = 0 V; Fixed
output
IB_24p0
ENABLE (EN PIN)
VEN-WAKE
VEN-VOUT
VEN-HYST
ILKG-EN
Enable wake-up threshold
0.4
V
Precision enable high level
Enable threshold hysteresis
Enable input leakage current
1.16 1.263
0.285 0.35 0.425
0.2
1.36
V
V
VEN = 3.3 V
8
nA
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNVSC31
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7.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INTERNAL LDO
VCC
Internal VCC voltage
Adjustable or fixed output; Auto mode
3.1
3.15
50
3.25
V
ICC
Bias regulator current limit
Internal VCC undervoltage lockout
120 mA
VCC-UVLO
VCC rising under voltage threshold
Hysteresis below VCC-UVLO
3
3.3
3.65
1.2
V
V
Internal VCC under voltage lock-out
hysteresis
VCC-UVLO-HYST
0.4
0.8
CURRENT LIMITS
ISC-100mA
Short circuit high side current limit (3)
Low side current limit (3)
100 mA version
100 mA version
140
99
167
116
200 mA
135 mA
ILS-LIMIT-100mA
PFM Operation, 100 mA version; Duty Cycle =
0%
IPEAK-MIN-100mA Minimum peak inductor current limit (3)
30
40
50 mA
ISC-150mA
Short circuit high side current limit (3)
Low side current limit (3)
150 mA version
150 mA version
210
150
250
175
298 mA
204 mA
ILS-LIMIT-150mA
PFM Operation, 150 mA version; Duty Cycle =
0%
IPEAK-MIN-150mA Minimum Peak Inductor Current (3)
55
70
85 mA
IZC
Zero cross current (3)
Auto mode
0
-200
-200
2.5
-175
-175
5 mA
IL-NEG-100mA
IL-NEG-150mA
POWER GOOD
Sink current limit (negative) (3)
Sink current limit (negative) (3)
FPWM mode
FPWM mode
-150 mA
-150 mA
% of FB (Adjustable output) or % of VOUT/FB
(Fixed output)
PG-OV
PGOOD upper threshold - rising
PGOOD lower threshold - falling
PGOOD hysteresis - rising/falling
106
93
107
94
110
96.5
1.8
2
%
%
%
V
% of FB (Adjustable output) or % of VOUT/FB
(Fixed output)
PG-UV
% of FB (Adjustable output) or % of VOUT/FB
(Fixed output)
PG-HYS
VPG-VALID
0.8
0.7
1.2
0.9
Minimum input voltage for proper PG
function
RPG-EN5p0
RPG-EN0
PGOOD pull down resistance
PGOOD pull down resistance
VEN = 5.0 V, 1 mA pull-up current
VEN = 0 V, 1 mA pull-up current
20
15
40
24
70
46
Ω
Ω
MOSFETS
RDSON-HS
RDSON-LS
VBOOT-UVLO
High-side MOSFET on-resistance
Low-side MOSFET on-resistance
BOOT - SW UVLO threshold (4)
Load = 100 mA
Load = 100 mA
2.2
1
Ω
Ω
V
2.14
2.3
2.42
VOLTAGE FEEDBACK (VOUT/FB PIN)
VOUT
VOUT
VREF
IFB
Output Voltage Accuracy for fixed VOUT VOUT = 3.3-V, VIN = 3.6 V to 65 V, FPWM
Output Voltage Accuracy for fixed VOUT VOUT = 5-V, VIN = 5.5 V to 65 V, FPWM
3.24
4.93
3.3
5
3.34
5.08
1.01
V
V
V
Internal reference voltage
FB input current
VIN = 3.6 V to 65 V, FPWM mode
Adjustable output, FB = 1 V
0.985
1
1
30 nA
THERMAL SHUTDOWN
TSD-R
Thermal shutdown rising
Shutdown threshold
158
8
168
10
180 °C
15 °C
TSD-HYS
Thermal shutdown hysteresis
SOFT START
Time from first SW pulse to VFB at 90%
of VREF
tSS
1.95
2.58
3.2 ms
VIN ≥3.6 V
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English Data Sheet: SNVSC31
LMR36501, LMR36502
ZHCSO70A –MARCH 2023 –REVISED MAY 2023
www.ti.com.cn
7.5 Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +150°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER GOOD
tRESET_FILTER
tPGOOD_ACT
Glitch filter time constant for PG
function
15
25
40 µs
Delay time to PG high signal
1.7 1.956
2.16 ms
PWM LIMITS (SW)
tON-MIN
tOFF-MIN
tON-MAX
Minimum switch on-time
VIN = 24 V, IOUT = 150 mA
40
40
55
60
9
80 ns
90 ns
9.8 µs
Minimum switch off-time
Maximum switch on-time
HS timeout in dropout
7.6
OSCILLATOR (RT)
fOSC_2p2MHz Internal oscillator frequency
fOSC_1p0MHz
RT = GND
RT = VCC
2.1
2.2
1
2.3 MHz
Internal oscillator frequency
0.93
1.05 MHz
Accuracy of external frequency, 400
kHz
fADJ_400kHz
0.34
0.4
0.46 MHz
RT = 39.2 kΩ
(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
(4) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor
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7.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STANDBY CURRENT AND DUTY RATIO
Input supply current when in
regulation
VIN = 13.5 V, VOUT/FB = 3.3 V, IOUT = 0 A,
PFM mode
ISUPPLY
6.5
4
µA
Input supply current when in
regulation
VIN = 24 V, VOUT/FB = 3.3 V, IOUT = 0 A,
PFM mode
ISUPPLY
µA
ns
tON-MIN
DMAX
Minimum switch on-time
Frequency foldback
30
Maximum switch duty cycle (1)
98%
OUTPUT VOLTAGE ACCURACY (VOUT/FB)
VOUT = 3.3-V, VIN = 3.6 V to 65 V,
VOUT_3p3V_ACC
FPWM mode
AUTO mode
FPWM mode
AUTO mode
1.5
2.5
1.5
2.5
%
%
%
%
–1.5
–1.5
–1.5
–1.5
IOUT = 0 A to full load (2)
VOUT = 3.3-V, VIN = 3.6 V to 65 V,
VOUT_3p3V_ACC
IOUT = 0 A to full load (2)
VOUT = 5-V, VIN = 5.5 V to 65 V,
VOUT_5p0V_ACC
IOUT = 0 A to full load (2)
VOUT = 5-V, VIN = 5.5 V to 65 V,
VOUT_5p0V_ACC
IOUT = 0 A to full load (2)
(1) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: fMIN
= 1 / (tON-MAX + TOFF-MIN). DMAX = (tON-MAX) / (tON-MAX + tOFF-MIN).
(2) Deviation is with respect to VIN = 13.5 V
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7.7 Typical Characteristics
Unless otherwise specified, the following conditions apply: TA = 25°C, VIN = 13.5 V.
100
80
60
40
20
0
1074
1072
1070
1068
1066
1064
1062
1060
1058
1056
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 48 V
1
10
100
200
-40 -20
0
20
40
60
80 100 120 140
Load Current (mA)
Temperature (°C)
LMR36502F3
VOUT = 3.3 V Fixed
1 MHz (FPWM)
图7-2. Typical Shutdown Current for 24-V VIN
图7-1. Efficiency
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8 Detailed Description
8.1 Overview
The LMR3650x is a wide input, low-quiescent current, synchronous buck converter that operates over a wide
range of duty ratio and switching frequencies, from 200 kHz to 2.2 MHz. During wide input transients, if the
minimum on time or the minimum off time cannot support the desired duty ratio at the higher switching frequency
settings, the switching frequency is reduced automatically, allowing the LMR3650x to maintain the output voltage
regulation. With an internally compensated design optimized for minimal output capacitors, the system design
process with the LMR3650x is simplified significantly compared to other buck regulators available in the market.
The device is designed to minimize external component cost and solution size while operating in all demanding
industrial environments. An internally compensated control loop simplifies the design procedure, and is
optimized to reduce the required output capacitance, reducing solution size and cost. The LMR3650x includes
variants that can be set up to operate over a wide switching frequency range, from 200 kHz to 2.2 MHz, with the
correct resistor selection from the RT pin to ground. To further reduce system cost, the PGOOD output feature
with built-in delayed release allows the elimination of the reset supervisor in many applications.
The LMR3650x comes in an ultra-small 2-mm × 2-mm (HotRod™) QFN package along with specially designed
corner anchor pins for reliable board level solder connections. Given that the package size is very small and the
increase reliability of solder connectivity due to corner anchor pins, the LMR3650x offers a reduced solution size
and high reliability for space constrained industrial applications.
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8.2 Functional Block Diagram
VCC
VOUT/FB
CLK
OSCILLATOR
LDO
VCC UVLO
TSD
RT
VIN
SLOPE
COMPENSATION
THERMAL
SHUTDOWN
FSW FOLDBACK
SYS ENABLE
EN
ENABLE
BOOT
HS
CURRENT
SENSE
VIN
ERROR
AMPLFIER
–
+
+
–
COMP
FB
DETECT
TSD
CLK
VOUT/
FB
+
MAX. and
MIN.
LIMITS
+
HS
–
SW
CURRENT
SYS ENABLE
SYS ENABLE
LMIT
CONTROL
LOGIC and
DRIVER
SOFT-
START
and
TSD
GND
VREF
LS
CURRENT
LMIT
BANDGAP
VCC UVLO
–
+
VOUT/FB
PGOOD
–
+
MIN.
LS CURRENT
LIMIT
GND
VOUT UV/OV
PGOOD
LOGIC
FPWM or AUTO
VOUT UV/OV
LS
CURRENT
SENSE
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8.3 Feature Description
8.3.1 Enable, Shutdown, and Start-up
The voltage at the EN/UVLO pin controls the start-up voltage and shutdown voltage of the LMR3650x. There are
three distinct modes set by the EN/UVLO pin; shut-down, standby and active. As long as the EN/UVLO pin
voltage is less than VEN-WAKE the device is shutdown mode. During shutdown mode, the input current drawn by
the device typically is 0.5 µA (VIN = 13.5 V). The internal LDO regulator is not operational. When the voltage at
the EN/UVLO pin is greater than the VEN-WAKE but less than VEN-VOUT the device enters the standby mode. In
standby mode, the internal LDO is enabled. As the EN/UVLO pin voltage increases above VEN-VOUT, the device
enters active mode starting the feedback resistor detection. After feedback detect is completed, soft-start
functionality is released to slowly increases the output voltage and switching starts. To stop switching and enter
standby mode the EN/UVLO pin must fall below (VEN-VOUT – VEN-HYST). Any further decrease in the EN/UVLO
pin voltage below VEN-WAKE the device is in shutdown. The various EN/UVLO threshold parameters and their
values are listed in 节 7.5. See 节 8.3.6 for information about feedback resistor detection. 图 8-1 shows the
precision enable behavior.
EN
VEN-VOUT
VEN-HYST
VEN-WAKE
VCC
3.15V
0
VOUT
VOUT
0
图8-1. Precision Enable Behavior
Remote precision undervoltage lockout can be implemented with this functionality as shown in 图 8-2. See 节
9.2.2.9 for component selection.
VIN
RENT
EN
RENB
AGND
图8-2. VIN Undervoltage Lockout
Using the EN/UVLO Pin
The high-voltage compliant EN/UVLO pin can be connected directly to the VIN input pin if remote precision
control is not needed. The EN/UVLO pin must not be allowed to float. The various EN threshold parameters are
listed in the 节 7.5. 图 8-1 shows the precision enable behavior. After EN/UVLO goes above VEN-VOUT with a
delay of about 1 ms, the output voltage begins to rise with a soft-start and reaches close to the final value in
about 2.58 ms (tss). After a delay of about 2 ms (tPGOOD_ACT), the PGOOD flag goes high. During startup, the
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device is not allowed to enter FPWM mode until the soft-start time has elapsed. Check 节 9.2.2.9 for component
selection.
8.3.2 Adjustable Switching Frequency (with RT)
The select variants in the LMR3650x family with the RT pin allow the power designers to set any desired
operating frequency between 200 kHz and 2.2 MHz in their applications. See 图 8-3 to determine the resistor
value needed for the desired switching frequency. See 表8-1 for selection on programming the RT pin.
表8-1. RT Pin Setting
RT INPUT
VCC
SWITCHING FREQUENCY
1 MHz
GND
2.2 MHz
RT to GND
Adjustable according to 图8-3
No Switching
Float (Not Recommended)
方程式1 can be used to calculate the value of RT for a desired frequency.
18286
RT =
Fsw1.021
(1)
where
• RT is the frequency setting resistor value (kΩ).
• FSW is the switching frequency (kHz).
80
70
60
50
40
30
20
10
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
图8-3. RT Values vs Frequency
8.3.3 Power-Good Output Operation
The power-good feature using the PGOOD pin of the LMR3650x can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output remains low under device fault
conditions, such as current limit and thermal shutdown, as well as during normal startup. A glitch filter prevents
false flag operation for any short duration excursions in the output voltage, such as during line and load
transients. Output voltage excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good
operation can best be understood in reference to 图 8-4. 表 8-2 gives a more detailed breakdown the PGOOD
operation. Here, VPG-UV is defined as the PG-UV scaled version of the VOUT-Reg (target regulated output voltage)
and VPG-HYS as the PG-HYS scaled version of the VOUT-Reg, where both PG-UV and PG-HYS are listed in 节7.5.
During the initial power up, a total delay of 5 ms (typical) is encountered from the time the VEN-VOUT is triggered
to the time that the power-good is flagged high. This delay only occurs during the device startup and is not
encountered during any other normal operation of the power-good function. When EN/UVLO is pulled low, the
power-good flag output is also forced low. With EN/UVLO low, power-good remains valid as long as the input
voltage (VPG-VALID is ≥1 V (typical)).
The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup
resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an
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appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit
the current into this pin to ≤4 mA.
Output
Voltage
Input
Voltage
Input Voltage
tRESET_FILTER
tPGOOD_ACT
tPGOOD_ACT
tRESET_FILTER
tRESET_FILTER
VPG-HYS
tRESET_FILTER
VPG-UV (falling)
VIN_R (rising)
VIN_F (falling)
VPG_VALID
GND
VOUT
PGOOD
Small glitches
do not cause
reset to signal
a fault
PGOOD may
not be valid if
input is below
VPG-VALID
Small glitches do not
reset tPGOOD_ACT timer
PGOOD may not
be valid if input is
below VPG-VALID
Startup
delay
图8-4. Power-Good Operation (OV Events Not Included)
表8-2. Fault Conditions for PGOOD (Pull Low)
FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS
BEFORE PGOOD OUTPUT IS RELEASED)
FAULT CONDITION INITIATED
Output voltage in regulation:
VPG-UV + VPG-HYS < VOUT < VPG-OV - VPG-HYS
VOUT < VPG-UV AND t > tRESET_FILTER
VOUT > VPG-OV AND t > tRESET_FILTER
TJ > TSD-R
EN < VEN-VOUT –VEN-HYST
VCC < VCC-UVLO –VCC-UVLO-HYST
Output voltage in regulation
TJ < TSD-F AND output voltage in regulation
EN > VEN-VOUT AND output voltage in regulation
VCC > VCC-UVLO AND output voltage in regulation
8.3.4 Internal LDO, VCC UVLO, and VOUT/FB Input
The LMR3650x uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin draws
power either from the VIN (in adjustable output variants) or the VOUT/FB depending on how the output voltage
is configured. In the fixed output configuration, after the LMR3650x is active but has yet to regulate, the VCC rail
continues to draw power from the VIN pin, until the VOUT/FB voltage reaches greater than 3.15 V (or when the
device has reached steady-state regulation post the soft start). The VCC rail typically measures 3.15 V in both
adjustable and fixed output variants. To prevent unsafe operation, VCC has an undervoltage lockout, which
prevents switching if the internal voltage is too low. See VVCC-UVLO and VVCC-UVLO-HYST in 节 7.5. During startup,
VCC momentarily exceeds the normal operating voltage until VVCC-UVLO is exceeded, then drops to the normal
operating voltage. Note that these undervoltage lockout values, when combined with the LDO dropout, drives
the minimum input voltage rising and falling thresholds.
8.3.5 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned on.
The capacitor connected between BOOT and SW works as a charge pump to boost voltage on the BOOT
terminal to (SW + VCC). The boot diode is integrated on the LMR3650x die to minimize physical solution size. TI
recommends a 100-nF capacitor rated for 10 V or higher for CBOOT. The BOOT rail has an UVLO setting. This
UVLO has a threshold of VBOOT-UVLO and is typically set at 2.3 V. If the CBOOT capacitor is not charged above
this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-side
switch before attempting to turn on the high-side device.
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8.3.6 Output Voltage Selection
In the LMR3650x, each variant can be configured as a fixed output voltage or an adjustable output voltage.
During device initialization the device configures the target output voltage to an internally selected value or an
adjustable version by detecting if feedback resistors are present. When configuring the output voltage to be fixed
value, simply connect the VOUT/FB pin to the system output voltage node. See 节 5 for the fixed output voltage
setting of each variant.
To configure an adjustable output voltage, external feedback resistors are required as shown in 图 8-5. By
connecting external feedback resistors with a parallel resistance greater than 5 kΩbut less than or equal to
10 kΩ(see 方程式 2) the output voltage is set according as needed. The internal voltage reference is 1 V. Refer
to 节9.2.2.2.1 for more details on how to adjust the output voltage.
When using the fixed-output configuration from the device family, simply connect the FB pin (identified as
VOUT/FB pin for fixed-output variants in the rest of the datasheet) to the system output voltage node. See 节 5
for more details.
VOUT
RFBT
FB
RFBB
AGND
图8-5. Setting Output Voltage for Adjustable Output Variant
5 kΩ < R
R
≤ 10 kΩ
(2)
FBT
FBB
• RFBT is the top resistor of the feedback divider
• RFBB is the bottom resistor of the feedback divider
When configured in adjustable output voltage mode, an addition feed-forward capacitor, CFF, in parallel with the
FBT, can be used to optimize the phase margin and transient response. See 节 9.2.2.8 for more details. No
R
additional resistor divider or feed-forward capacitor, CFF, is needed in fixed-output variants.
8.3.7 Soft Start and Recovery from Dropout
When designing with the LMR3650x, both soft start and recovery from dropout can cause slow rise in output
voltage and must be considered as a two separate operating conditions, as shown in 图 8-6 and 图 8-7. These
features ramp the output voltage at a controlled rate, keeping the output voltage from overshooting. See 节
8.3.7.1 and 节8.3.7.2 for more details.
8.3.7.1 Soft Start
The soft-start feature allows the converter to gradually reach the steady state output voltage, reducing the
startup stress in the system. Soft start is triggered by any of the following conditions:
• Voltage is applied to the VIN pin of the device, releasing undervoltage lockout.
• EN/UVLO voltage is sufficient to enter active mode.
• Recovery from shutdown due to over temperature protection.
After soft start is triggered, the internal reference is slowly ramped up. Assuming the output voltage is initially 0
V, the reference is ramped to 90% of the target output voltage in tSS. During the soft-start time the switching
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mode is set to AUTO mode. AUTO mode activates diode emulation for the low-side MOSFET, not allowing
negative inductor current. This allows the output voltage to be pre-biased, voltage already present on the output,
during startup without discharging the output capacitor. 图 8-6 shows the difference between a non biased soft
start and a pre-biased soft start.
If selected, FPWM
is enabled only
after completion of
tSS
If selected, FPWM
is enabled only
after completion of
tSS
Triggering event
Triggering event
tEN
tSS
tEN
tSS
V
V
VEN
VEN
VOUT Set
Point
VOUT Set
Point
VOUT
VOUT
90% of
VOUT Set
Point
90% of
VOUT Set
Point
t
t
0 V
0 V
Time
Time
图8-6. Soft Start with and Without Pre-biased Voltage
8.3.7.2 Recovery from Dropout
Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called
graceful recovery, differs from soft start in two important ways:
• The reference voltage is set to approximately 1% above what is needed to achieve the existing output
voltage.
• If the device mode is set to FPWM, the device mode continues to operate in that mode during its recovery
from dropout. If output voltage were to suddenly be pulled up by an external supply, the LMR3650x can pull
down on the output. Note that all protections that are present during normal operation are in place, preventing
any catastrophic failure if output is shorted to a high voltage or ground.
V
Load
current
VOUT Set
Point
and max
output
Slope
VOUT
the same
as during
soft start
current
t
Time
图8-7. Recovery from Dropout
Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall
below its set point is removed, the output climbs at the same speed as during start-up.
8.3.8 Current Limit and Short Circuit
The LMR3650x is protected from overcurrent conditions by cycle-by-cycle current limiting on both high-side and
low-side MOSFETs.
High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The
HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is
compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop
minus the slope compensation every switching cycle. Because the output of the internal error amplifier loop has
a maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased
duty factor if duty factor is typically above 35%.
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When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side
device, the low-side device has a turn-off commanded by the internal error amplifier loop. In the case of the low-
side device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new
switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be.
This limit is called the low-side current limit, IVALMAX in 图 8-8. If the LS current limit is exceeded, the LS
MOSFET stays on and the HS switch is not to be turned on. The LS switch is turned off after the LS current falls
below this limit and the HS switch is turned on again as long as at least one clock period has passed since the
last time the HS device has turned on.
VSW
VIN
tON < tON_MAX
0
t
Typically, tSW > Clock setting
iL
IPEAKMAX
IVALMAX
IOUT
t
0
图8-8. Current Limit Waveforms
Because the current waveform assumes values between IPEAKMAX and IVALMAX, the maximum output current is
very close to the average of these two values unless duty factor is very high. After operating in current limit,
hysteretic control is used and current does not increase as output voltage approaches zero.
If the duty factor is very high, current ripple must be very low to prevent instability. Because current ripple is low,
the part is able to deliver full current. The current delivered is very close to IVALMAX
.
IOUT
Rated
IVALMAX IPEAKMAX
VOUT
VOUT Setting
VIN > 2 × VOUT Setting
IN ≅ VOUT Setting
V
0
0
IOUT
Output Current
图8-9. Output Voltage versus Output Current
Under most conditions, current is limited to the average of IPEAKMAX and IVALMAX, which is approximately 1.3
times the maximum rated current. If input voltage is low, current can be limited to approximately IVALMAX. Also
note that the maximum output current does not exceed the average of IPEAKMAX and IVALMAX. After the overload
is removed, the part recovers as though in soft start.
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8.3.9 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction
temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal
shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to
approximately 158°C (typical). When the junction temperature falls below 158°C (typical), the LMR3650x
attempts another soft start.
While the LMR3650x is shut down due to high junction temperature, power continues to be provided to VCC. To
prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced
current limit while the part is disabled due to high junction temperature. The LDO only provides a few
milliamperes during thermal shutdown.
8.3.10 Input Supply Current
The LMR3650x is designed to have very low input supply current when regulating light loads. This low input
supply current is achieved by powering much of the internal circuitry from the output. When configured as a fixed
output voltage, the VOUT/FB pin is the input to the LDO that powers the majority of the control circuits. By
connecting the VOUT/FB input pin to the output node of the regulator, a small amount of current is drawn from
the output. This current is reduced at the input by the ratio of VOUT / VIN.
V
OUT
× V
I
= I + I + I ×
BIAS
(3)
Q_VIN
Q
EN
η
eff
IN
where
• IQ_VIN is the total standby (switching) current consumed by the operating (switching) buck converter when
unloaded.
• IQ is the current drawn from the VIN terminal. Check IQ_13p5_Fixed or IQ_24p0_Fixed in Electrical Characteristics
for IQ.
• IEN is current drawn by the EN terminal. Include this current if EN is connected to VIN. Check ILKG-EN in
Electrical Characteristics for IEN
.
• IBIAS is bias current drawn by the BIAS LDO. Check IB_13p5 or IB_24p0 in Electrical Characteristics for IBIAS
.
• ηeff is the light-load efficiency of the buck converter with IQ_VIN removed from the input current of the buck
converter. ηeff = 0.8 is a conservative value that can be used under normal operating conditions. This can be
traced back as the ISUPPLY in System Characteristics.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/UVLO pin provides electrical on and off control of the device. When the EN/UVLO pin voltage is below
0.4 V, the internal LDO is disabled and there is no switching of the internal Power MOSFETs. In shutdown mode,
the quiescent current drops to 0.5 µA, typically.
8.4.2 Standby Mode
When the EN/UVLO pin voltage is greater than the VEN-WAKE but less than VEN-VOUT, the internal LDO is
enabled. The precision enable circuitry, is enabled after VCC is above its undervoltage threshold (VCC-UVLO). The
internal power MOSFETs remain off unless the voltage on EN/UVLO pin voltage goes above its precision enable
threshold (VEN-VOUT).
8.4.3 Active Mode
The LMR3650x is in active mode whenever the EN/UVLO pin is above VEN-VOUT, VIN is high enough to satisfy
VIN_R, and no other fault conditions are present. The simplest way to enable the operation is to connect the EN/
UVLO pin to VIN, which allows self start-up when the applied input voltage exceeds the minimum VIN_R
.
In active mode, depending on the load current, input voltage, and output voltage, the LMR3650x is in one of five
modes:
• Continuous Conduction Mode (CCM) with fixed switching frequency when load current is above half of the
inductor current ripple
• AUTO Mode - Light Load Operation: PFM when switching frequency is decreased at very light load
• FPWM Mode - Light Load Operation: Continuous Conduction Mode (CCM) when the load current is lower
than half of the inductor current ripple
• Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to
maintain regulation.
• Dropout mode: When switching frequency is reduced to minimize voltage dropout.
8.4.3.1 CCM Mode
The following operating description of the LMR3650x refers to the Functional Block Diagram and to the
waveforms in 图 8-10. The LMR3650x has two behaviors while lightly loaded, AUTO mode and FPWM mode.
Regardless of the light load operation configuration, the converter operates in CCM when the load current is
greater than half the inductor ripple current.
In CCM, the LMR3650x supplies a regulated output voltage by turning on the internal high-side (HS) and low-
side (LS) switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, VSW, swings
up to approximately VIN, and the inductor current, iL, increases with a linear slope. The HS switch is turned off by
the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges
through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch.
The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of
the HS switch over the switching period:
D = TON / TSW
(4)
In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage:
D = VOUT / VIN
(5)
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tON
tSW
VOUT
VIN
VSW
D =
≈
VIN
tOFF
tON
0
t
- IOUT RDSON-LS
tSW
iL
IPEAK
IOUT
Iripple
t
0
图8-10. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
8.4.3.2 AUTO Mode - Light Load Operation
AUTO mode operation allows for seamless transition between normal current mode operation while heavily
loaded and highly efficient light load operation. The other behavior, called FPWM mode, maintains full frequency
even when unloaded. Which mode the LMR3650x operates in depends on which variant from this family is
selected. Note that all parts operate in FPWM mode when synchronizing frequency to an external signal.
The light load operation is employed in the LMR3650x only in the auto mode. The light load operation employs
two techniques to improve efficiency:
• Diode emulation, which allows DCM operation. See 图8-11.
• Frequency reduction. See 图8-12.
Note that while these two features operate together to improve light load efficiency, they operate independent of
each other.
8.4.3.2.1 Diode Emulation
Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to
regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.
With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to
maintain regulation.
tON
tSW
VOUT
VIN
VSW
D =
<
VIN
tOFF
tON
tHIGHZ
0
t
tSW
iL
IPEAK
IOUT
0
t
In auto mode, the low-side device is turned off after SW node current is near zero. As a result, after output current is less than half of
what inductor ripple is in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.
图8-11. PFM Operation
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The LMR3650x has a minimum peak inductor current setting (see IPEAK-MIN in 节 7.5) while in auto mode. After
current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then achieved by
adjusting frequency. This mode of operation is called PFM mode regulation.
8.4.3.2.2 Frequency Reduction
The LMR3650x reduces frequency whenever output voltage is high. This function is enabled whenever the
internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the
regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance
while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when
the part is completely unloaded.
VOUT
Current
Limit
1% Above
Set point
VOUT Set
Point
IOUT
Output Current
0
In auto mode, after output current drops below approximately 1/10th the rated current of the part, output resistance increases so that
output voltage is 1% high while the buck is completely unloaded.
图8-12. Steady State Output Voltage versus Output Current in Auto Mode
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a
dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.
8.4.3.3 FPWM Mode - Light Load Operation
In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is
allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see 节 7.5 for
reverse current limit values.
tON
tSW
VSW
VOUT
VIN
D =
≈
VIN
tOFF
tON
0
t
tSW
iL
IPEAK
IOUT
0
Iripple
t
In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple
.
图8-13. FPWM Mode Operation
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For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to
command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output
being pulled up.
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8.4.3.4 Minimum On-time Operation
The LMR3650x continues to regulate output voltage even if the input-to-output voltage ratio requires an on-time
less than the minimum. This action is accomplished using valley current control. At all times, the compensation
circuit dictates both a maximum peak inductor current and a maximum valley inductor current. If for any reason,
valley current is exceeded, the clock cycle is extended until valley current falls below that determined by the
compensation circuit. If the converter is not operating in current limit, the maximum valley current is set above
the peak inductor current, preventing valley control from being used unless there is a failure to regulate using
peak current only. If the input-to-output voltage ratio is too high, such that the inductor current peak value
exceeds the peak command dictated by compensation, the high-side device cannot be turned off quickly enough
to regulate output voltage. As a result, the compensation circuit reduces both peak and valley current. After a low
enough current is selected by the compensation circuit, valley current matches that being commanded by the
compensation circuit. Under these conditions, the low-side device is kept on and the next clock cycle is
prevented from starting until inductor current drops below the desired valley current. Because on-time is fixed at
its minimum value, this type of operation resembles that of a device using a Constant On-Time (COT) control
scheme; see 图8-14.
tON
VOUT
VIN
VSW
D =
≈
tSW
tON = tON_MIN
VIN
tOFF
0
- IOUT RDSON-LS
t
tSW > Clock setting
iL
IOUT
IVAL
Iripple
t
0
In valley control mode, minimum inductor current is regulated, not peak inductor current.
图8-14. Valley Current Mode Operation
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8.4.3.5 Dropout
Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the
required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. After this limit is
reached as shown in 图 8-16 if clock frequency is maintained, the output voltage falls. Instead of allowing the
output voltage to drop, the LMR36502 extends the high side switch on-time past the end of the clock cycle until
the needed peak inductor current is achieved. The clock is allowed to start a new cycle after peak inductor
current is achieved or after a pre-determined maximum on-time, tON-MAX, of approximately 9 µs passes. As a
result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the existence of a
minimum off-time, frequency drops to maintain regulation. As shown in 图 8-15 if input voltage is low enough so
that output voltage cannot be regulated even with an on-time of tON-MAX, output voltage drops to slightly below
the input voltage by VDROP. For additional information on recovery from dropout, refer back to 图8-7.
Input
Voltage
VOUT
VDROP
Output
Output
Setting
Voltage
VIN
0
Input Voltage
FSW
FSW-NOM
≅ 110 kHz
VIN
0
Input Voltage
Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC
reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,
input voltage tracks output voltage.
图8-15. Frequency and Output Voltage in Dropout
tON
tSW
VOUT
VIN
VSW
D =
VIN
tOFF = tOFF_MIN
tON < tON_MAX
0
- IOUT RDSON-LS
t
tSW > Clock setting
iL
IPEAK
IOUT
Iripple
t
0
Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,
frequency drops. This frequency drop is limited by tON-MAX
.
图8-16. Dropout Waveforms
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMR3650x step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 100 mA and 150 mA. The following design procedure can be used to
select components for the LMR3650x.
备注
All of the capacitance values given in the following application information refer to effective values
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and
temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with
an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This usage can also ease the RMS current requirements on a
single capacitor. A careful study of bias and temperature variation of any capacitor bank must be
made to ensure that the minimum value of effective capacitance is provided.
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9.2 Typical Application
图 9-1 shows a typical application circuit for the LMR36502. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick-start guide, 表 9-1 and 表 9-2 provide
typical component values for a range of the most common output voltages.
L
VOUT
VIN
SW
VIN
CIN
CHF
CBOOT
100 nF
2.2 µF
BOOT
COUT
EN
0.1 µF
LMR36502
RT (A)
CFF
RFBT
PG
FB
MODE/SYNC (B)
VCC
RFBB
CVCC
1 µF
GND
A. The RT pin is factory-set for externally adjustable switching frequency RT variants only. Tying this pin to GND results in 2.2-MHz or to
VCC results in 1.1-MHz switching frequency. See 节8.3.2 for details.
B. The MODE/SYNC pin is factory-set for fixed frequency frequency MODE/SYNC variants only. Tying this pin to GND results in AUTO
mode.
图9-1. Example Application Circuit
表9-1. Typical External Component Values for Adjustable Output LMR36502
NOMINAL COUT MINIMUM COUT
(1) (2)
FSW
VOUT
(V)
RFBT (Ω) (3)
RFBB (Ω)
L (µH)
(RATED
(RATED
CIN
CBOOT
CVCC
(kHz)
CAPACITANCE) CAPACITANCE)
400
1000
400
3.3
3.3
5
33
15
47
22
1 × 47 µF
2 × 22 µF
1 × 47 µF
2 × 22 µF
1 × 22 µF
1 × 22 µF
1 × 22 µF
1 × 22 µF
33.2 k
33.2 k
49.9 k
49.9 k
14.3 k
14.3 k
12.4 k
12.4 k
2.2 µF + 1 × 100 nF 100 nF
2.2 µF + 1 × 100 nF 100 nF
2.2 µF + 1 × 100 nF 100 nF
2.2 µF + 1 × 100 nF 100 nF
1 µF
1 µF
1 µF
1 µF
1000
5
(1) Inductor values are calculated based on typical VIN = 24 V.
(2) The switching frequencies listed here can be achieved in a number of ways depending on the device variant. For RT devices see 节
8.3.2. .
(3) For RFBT and RFBB values outside the range stated above, see 节9.2.2.2.1.
表9-2. Typical External Component Values for Fixed Output LMR36502
NOMINAL COUT MINIMUM COUT
(1) (2)
FSW
VOUT
(V)
RFBT (Ω)
RFBB (Ω) (3)
L (µH)
(RATED
CAPACITANCE) CAPACITANCE)
(RATED
CIN
CBOOT
CVCC
(kHz)
400
2200
400
3.3
3.3
5
68
10
82
15
1 × 47 µF
1 × 10 µF
1 × 47 µF
1 × 10 µF
1 × 22 µF
1 × 10 µF
1 × 22 µF
1 × 10 µF
0
0
0
0
DNP
DNP
DNP
DNP
2.2 µF + 1 × 100 nF 100 nF
2.2 µF + 1 × 100 nF 100 nF
2.2 µF + 1 × 100 nF 100 nF
2.2 µF + 1 × 100 nF 100 nF
1 µF
1 µF
1 µF
1 µF
2200
5
(1) Inductor values are calculated based on typical VIN = 13.5 V.
(2) The switching frequencies listed here can be achieved in a number of ways depending on the device variant. For RT devices see 节
8.3.2.
(3) DNP = Do Not Populate.
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9.2.1 Design Requirements
节9.2.2 provides a detailed design procedure based on 表9-3.
表9-3. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
24 V (6 V to 65 V)
3.3 V
Output voltage
Maximum output current
Switching frequency
0 A to 150 mA
1000 kHz
9.2.2 Detailed Design Procedure
The following design procedure applies to 图9-1 and 表9-2.
9.2.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more
compact design. For this example, 1000 kHz is used.
9.2.2.2 Setting the Output Voltage
VOUT / FB of the device can be either connected directly to the output capacitor or a midpoint of a feedback
resistor divider. When connected directly to the output capacitor, the device assumes that a fixed output voltage
of either 3.3 V or 5 V is desired. The 3.3-V or 5-V fixed output options are factory trimmed and it is unique to a
specific device. See 节5 for the selection of fixed output voltage versions.
9.2.2.2.1 VOUT / FB for Adjustable Output
If other voltages are desired, VOUT / FB can be connected to a feedback resistor divider network to set the output
voltage. The divider network is comprised of RFBT and RFBB, and closes the loop between the output voltage and
the converter. The converter regulates the output voltage by holding the voltage on the VOUT / FB pin equal to
the internal reference voltage, VREF. The converter determines whether fixed output voltage or adjustable output
voltage is required by sensing the resistance of the feedback path during start-up. To ensure that the converter
regulates to the desired output voltage, the typical minimum value for the parallel combination of RFBT and RFBB
is 5 kΩ while the typical maximum value is 10 kΩ as shown in 方程式 6. 方程式 7 can be used as a starting
point to determine the value of RFBT. Reference 表 9-4 for a list of acceptable resistor values for various output
voltages.
The resistance of the divider is a compromise between excessive noise pickup and excessive loading of the
output. Smaller values of resistance reduce noise sensitivity but also reduce the light-load efficiency. The
recommended maximum value for RFBT is 200 kΩ. For a 3.3-V example, LMR36502F3RPE output pin
(VOUT / FB) can connect directly to the output capacitor.
5 kΩ < R
R
≤ 10 kΩ
(6)
(7)
FBT
FBB
V
OUT
1 V
R
≤ 10 kΩ ×
FBT
表9-4. Recommended Feedback Resistor Values for Various Output Voltages
RFBT (1) (kΩ)
RFBB (1) (kΩ)
VOUT (V)
1.2
10.2
51.1
2.5
24.9
16.5
3.3
33.2
14.3
5
49.9
12.4
12
110
10
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表9-4. Recommended Feedback Resistor Values for Various Output Voltages (continued)
RFBT (1) (kΩ)
RFBB (1) (kΩ)
VOUT (V)
24
200
8.66
(1) RFBT and RFBB are based on 1% standard resistor values.
9.2.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the
maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, use the maximum device current. 方程式 8 can be used to
determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example,
choose K = 0.3 and find an inductance of L = 44 µH. Select the next standard value of L = 47 µH.
V
− V
V
OUT
IN
× K × I
OUT
L =
×
(8)
V
f
IN
SW
OUT max
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit,
PEAKMAX (see 节 7.5). The saturation current rating of the inductor being as large as the high-side switch current
I
limit ensures that the inductor does not saturate, even during a short circuit on the output. When the inductor
core material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, IVALMAX, is designed to reduce the risk of current runaway, a saturated inductor
can cause the current to rise to high values very rapidly. This high rise can lead to component damage. Do not
allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but
usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing
some relaxation in the current rating of the inductor. However, they have more core losses at frequencies above
about 1 MHz. In any case, the inductor saturation current must not be less than the maximum peak inductor
current at full load.
To avoid subharmonic oscillation, the inductance value must not be less than that given in 方程式9:
V
OUT
L
≥ 2.5 ×
(9)
MIN
f
sw
The maximum inductance is limited by the minimum current ripple for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device
maximum rated current under nominal conditions.
9.2.2.4 Output Capacitor Selection
The current mode control scheme of the LM36502 devices allows operation over a wide range of output
capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather
than the output voltage ripple. Please refer to 节 9.2 for typical output capacitor value for 3.3-V and 5-V output
voltages. Based on 表 9-2, for a 3.3-V output design, you can choose the recommended 1 × 22-µF ceramic
output capacitor for this example. For other designs with other output voltages, WEBENCH can be used as a
starting point for selecting the value of output capacitor.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of
1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
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as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
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9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 2.2 µF is required on
the input of the LMR36502. This capacitance must be rated for at least the maximum input voltage that the
application requires, preferably twice the maximum input voltage. This capacitance can be increased to help
reduce input voltage ripple and maintain the input voltage during load transients. In addition, a small case size
100-nF ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high
frequency bypass for the control circuits internal to the device. For this example a 2.2-µF, 100-V, X7R (or better)
ceramic capacitor is chosen. The 100 nF must also be rated at 100 V with an X7R dielectric.
Using an electrolytic capacitor on the input in parallel with the ceramics is desirable. This statement is especially
true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
RMS value of this current can be calculated from 方程式 10 and must be checked against the manufacturers'
maximum ratings.
IOUT
IRMS
@
2
(10)
9.2.2.6 CBOOT
The LMR36502 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 16 V is required.
9.2.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this
output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for
the power-good function (see 节 8.3.3). A value in the range of 10 kΩ to 100 kΩ is a good choice in this case.
The nominal output voltage on VCC is 3.15 V; see 节7.5 for limits.
9.2.2.8 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. The Optimizing Transient Response of Internally Compensated DC-DC
Converters with Feed forward Capacitor Application Report is helpful when experimenting with a feedforward
capacitor.
Due to the nature of the feedback detect circuitry, the value of CFF must be limited to ensure that the desired
output voltage is established when configuring for adjustable output voltages. Follow 方程式 11 to ensure CFF
remains below the maximum value.
V
OUT
C
< C
×
(11)
FF
OUT
1.2MΩ
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9.2.2.9 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. An input UVLO
level different than that provided internal to the device is can be accomplished by using the circuit shown in 图
9-2. The input voltage at which the device turns on is designated as VON while the turn-off voltage is VOFF. First,
a value for RENB is chosen in the range of 10 kΩto 100 kΩ, then 方程式 12and 方程式 13 are used to calculate
RENT and VOFF, respectively.
VIN
RENT
EN
RENB
图9-2. Setup for External UVLO Application
V
ON
R
V
=
– 1 ×R
(12)
(13)
ENT
ENB
V
EN − VOUT
V
EN − HYS
= V × 1 –
OFF
ON
V
ENVOUT
where
• VON is the VIN turn-on voltage.
• VOFF is the VIN turn-off voltage.
9.2.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR3650x dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum junction temperature for the LMR3650x must be
limited to 150°C. This limit establishes a limit on the maximum device power dissipation and, therefore, the load
current. 方程式 14 shows the relationships between the important parameters. Seeing that larger ambient
temperatures (TA) and larger values of RθJA reduce the maximum available output current is easy. The
converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating
conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. For more information, refer to the
Semiconductor and IC Package Thermal Metrics application report.
T − T
η
J
A
1
I
=
×
×
(14)
OUT MAX
R
1 − η
V
θJA
OUT
where
• ηis the efficiency.
The effective RθJA is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature and flow
• PCB area
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• Copper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement
The IC junction temperature can be estimated for a given operating condition using 方程式15.
TJ ≈TA + RθJA × IC Power Loss
(15)
where
• TJ is the IC junction temperature (°C).
• TA is the ambient temperature (°C).
• RθJA is the thermal resistance (°C/W)
• IC Power Loss is the power loss for the IC (W).
The IC Power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC
Resistance. The overall power loss can be approximated by using WEBENCH for a specific operating condition
and temperature.
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given
application environment:
• Thermal Design by Insight not Hindsight application report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application report
• Semiconductor and IC Package Thermal Metrics application report
• Thermal Design Made Simple with LM43603 and LM43602 application report
• PowerPAD™ Thermally Enhanced Package application report
• PowerPAD™ Made Easy application report
• Using New Thermal Metrics application report
• PCB Thermal Calculator
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9.2.3 Application Curves
100
3.2966
3.2964
3.2962
3.296
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 48 V
80
60
40
20
0
3.2958
3.2956
3.2954
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 48 V
0
25
50
75
100
125
150
1
10
100
200
Load Current (mA)
Load Current (mA)
LMR36502F3
VOUT = 3.3 V Fixed
1 MHz (FPWM)
LMR36502F3
VOUT = 3.3 V Fixed
1 MHz (FPWM)
图9-4. Line and Load Regulation
图9-3. Efficiency
3.3
3.3
3
IOUT = 0 mA
IOUT = 150 mA
IOUT = 0 A
IOUT = 150 mA
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Input Voltage (V)
Input Voltage (V)
LMR36502F3
VOUT = 3.3 V Fixed
1 MHz (FPWM)
LMR36502F3
VOUT = 3.3 V Fixed
1 MHz (FPWM)
图9-5. Dropout VIN High to Low
图9-6. Dropout VIN Low to High
VOUT (100 mV/DIV)
VOUT (100 mV/DIV)
IOUT (100 mA/DIV)
IOUT (100 mA/DIV)
200 µs/DIV
200 µs/DIV
LMR36502F3
VIN = 24 V
VOUT = 3.3 V Fixed
0 mA to 150 mA
1 MHz (FPWM)
LMR36502F3
VIN = 24 V
VOUT = 3.3 V Fixed
0 mA to 150 mA
1 MHz (FPWM)
COUT = 2 × 22 μF
COUT = 2 × 22 μF
图9-7. Load Transient
图9-8. Load Transient
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VIN (20 V/DIV)
SW (20 V/DIV)
VOUT (10 mV/DIV)
IL (200 mA/DIV)
VOUT (5 V/DIV)
2 µs/DIV
1 µs/DIV
LMR36502F3
VIN = 24 V
VOUT = 3.3 V Fixed
150 mA
1 MHz (FPWM)
LMR36502F3
VIN = 24 V
VOUT = 3.3 V Fixed
150 mA
1 MHz (FPWM)
COUT = 2 × 22 μF
COUT = 2 × 22 μF
图9-9. Steady State Waveforms
图9-10. Output Voltage Ripple
VOUT (2 V/DIV)
VOUT (2 V/DIV)
IOUT (100 mA/DIV)
IOUT (100 mA/DIV)
1 ms/DIV
1 ms/DIV
LMR36502F3
VIN = 24 V
VOUT = 3.3 V Fixed
1 MHz (FPWM)
LMR36502F3
VIN = 24 V
VOUT = 3.3 V Fixed
1 MHz (FPWM)
L = 15 μH
COUT = 2 × 22 μF
L = 15 μH
COUT = 2 × 22 μF
图9-11. Short Circuit Entry
图9-12. Short Circuit Exit
LMR36502F3
VIN = 48 V
VOUT = 3.3 V Fixed
150 mA
1 MHz (FPWM)
COUT = 2 × 22 μF
LMR36502F3
VIN = 36 V
VOUT = 3.3 V Fixed
150 mA
1 MHz (FPWM)
COUT = 2 × 22 μF
图9-14. Thermal Image
图9-13. Thermal Image
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9.3 Best Design Practices
• Do not exceed the Absolute Maximum Ratings.
• Do not exceed the Recommended Operating Conditions.
• Do not exceed the ESD specifications found in ESD (Commercial) Ratings.
• Do not allow the EN input to float.
• Do not allow the output voltage to exceed the input voltage, nor go below ground.
• Follow all the guidelines and suggestions found in this data sheet before committing the design to production.
TI application engineers are ready to help critique your design and PCB layout to help make your project a
success.
9.4 Power Supply Recommendations
The characteristics of the input supply must be compatible with 节 7 found in this data sheet. In addition, the
input supply must be capable of delivering the required input current to the loaded regulator. The average input
current can be estimated with 方程式16.
V
× I
OUT
OUT
V
I
=
(16)
IN
× η
IN
where
• ηis the efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shut down and reset. The best way to solve these kind of issues is to limit the distance
from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the
ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
9.5 Layout
9.5.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power
ground, as shown in 图 9-15. This loop carries large transient currents that can cause large transient voltages
when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
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to reduce the parasitic inductance. 图 9-16 shows a recommended layout for the critical components of the
LMR3650x.
1. Place the input capacitors as close as possible to the VIN and GND terminals.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the
BOOT and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat
dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in 节9.2.2.10, enough copper area must be
used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. The
top and bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB
design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner
layer heat-spreading ground planes.
8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies application report
• Simple Switcher PCB Layout Guidelines application report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report
VIN
CIN
SW
GND
图9-15. Current Loops with Fast Edges
9.5.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground
plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control
circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as
well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the
ground plane contains much less noise; use for sensitive routes.
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TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See
图 9-16 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom
layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting
from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout,
provides low current conduction impedance, proper shielding and lower thermal resistance.
9.5.2 Layout Example
RFBB
CFF
RFBT
CVCC
RENB
RENT
CIN
L1
CIN
COUT
GND
图9-16. Example Layout
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Device Nomenclature
图 10-1 shows the device naming nomenclature of the LMR3650x. See 节 5 for the availability of each variant.
Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order
quantities apply.
LMR3650 X X X X X RPER
OUTPUT CURRENT MAX
1: 100 mA
2: 150 mA
MODE TRIM OPTION
F: RT Trim (FPWM only)
P: RT Trim (Auto)
SPREAD SPECTRUM FIXED FSW
*: O
VOUT OPTION
A: 400 kHz 3: 3.3-V Fixed
PACKAGE
RPER = WQFN 9-pin large reel
S: On
B: 1 MHz
C: 2.2 MHz
5: 5-V Fixed
*No character
defaults to Spread
Spectrum is “O ”
*No
character
defaults to for ADJ voltage
RT Trim output
*Both variants
can be setup
图10-1. Device Naming Nomenclature
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Thermal Design by Insight not Hindsight application report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, Simple Switcher PCB Layout Guidelines application report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report
10.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
10.5 Trademarks
HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
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10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR36501F3RPER
LMR36501F5RPER
LMR36501P3RPER
LMR36501P5RPER
LMR36502F3RPER
LMR36502FS5RPER
LMR36502P3RPER
LMR36502PS5RPER
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPE
RPE
RPE
RPE
RPE
RPE
RPE
RPE
9
9
9
9
9
9
9
9
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
CL03
CL04
CL07
CL08
CL01
CL02
CL05
CL06
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
SN
SN
SN
SN
SN
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR36501F3RPER
LMR36501F5RPER
LMR36501P3RPER
LMR36501P5RPER
LMR36502F3RPER
LMR36502FS5RPER
LMR36502P3RPER
LMR36502PS5RPER
VQFN-
HR
RPE
RPE
RPE
RPE
RPE
RPE
RPE
RPE
9
9
9
9
9
9
9
9
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMR36501F3RPER
LMR36501F5RPER
LMR36501P3RPER
LMR36501P5RPER
LMR36502F3RPER
LMR36502FS5RPER
LMR36502P3RPER
LMR36502PS5RPER
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RPE
RPE
RPE
RPE
RPE
RPE
RPE
RPE
9
9
9
9
9
9
9
9
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RPE 9
2 x 2, 0.5 mm pitch
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227057/A
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PACKAGE OUTLINE
RPE0009B
VQFN-HR - 1.0 mm max height
S
C
A
L
E
6
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
4X (0.15)
(0.1) TYP
0.55
0.45
4X (0.15)
2X
0.275
4X
0.175
0.1
C A B
C
4
0.05
5
2X 0.738
2X 0.25
0.000 PKG
2X 0.25
1.1 0.05
2X 0.738
8
1
9
0.275
0.175
0.1
PIN 1 ID
4X
0.6
0.5
C A B
2X
0.05
C
0.4
0.3
0.45
0.35
4X
4227033/A 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
RPE0009B
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.75)
2X (0.4)
(0.35)
9
4X (0.225)
1
2X (0.575)
(1.3)
8
2X (0.738)
4X (0.6)
2X (0.25)
0.000 PKG
(0.55)
4X (0.25)
2X (0.25)
SEE SOLDER MASK
DETAILS
(R0.05) TYP
2X (0.738)
5
4
2X (0.575)
SYMM
(1.8)
2X (0.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4227033/A 08/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RPE0009B
VQFN-HR - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.75)
2X
2X (0.55)
9
2X (0.35)
(0.4)
2X (0.5)
4X (0.225)
(0.925)
(0.175)
1
8
2X (0.738)
4X (0.6)
2X (0.25)
4X (0.25)
0.000 PKG
2X (0.25)
(R0.05) TYP
2X (0.738)
5
4
2X (0.575)
SYMM
(1.8)
2X (0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
PADS 1 & 8:
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PAD 9:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
DWG_NO:5/REV:5 MM_YYYY:5
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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