LMR36503RS3QRPERQ1_技术文档

LMR36503-Q1

ZHCSKX8B –SEPTEMBER 2019 –REVISED SEPTEMBER 2020

LMR36503-Q1 3V 至65V、0.3A 针对尺寸和轻负载效率进行了优化的同步降压

转换器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

– 器件温度等级1：–40°C 至+125°C，T_A

• 提供功能安全

LMR36503-Q1 是业界超小型 65V、0.3A 同步降压直

流/直流转换器，采用 2mm x 2mm HotRod^™封装。这

款易于使用的转换器可处理高达 70V 的输入电压瞬

变，提供出色的 EMI 性能，并支持固定电压 3.3V、5V

和其他可调输出电压。

– 可帮助进行功能安全系统设计的文档

• 电流为5mA 时的效率大于70%

– 4µA 的I_Q（开关），在_输入电压为24V 和_输出电压

为3.3V（固定输出选项）时

• 微型解决方案尺寸和低组件成本

– 具有可湿性侧面的2mm × 2mm HotRod^™封装

– 内部补偿

LMR36503-Q1 采用具有内部补偿的峰值电流模式控制

架构，用于维持稳定运行和极小的输出电容。

LMR36503-Q1 的宽输入工作电压范围有助于其在深度

输入电压骤降条件下保持正常工作，因而是承受严苛冷

启动脉冲的汽车应用的理想选择。LMR36503-Q1 中的

PGOOD 标志可提供输出电压状态的精确指示，免去了

使用外部监控器的麻烦。从 FPWM 到 PFM 的无缝转

换以及超低的待机静态电流，这让 LMR36503-Q1 可

以在低输出负载下支持更高的系统效率。MODE/

SYNC 引脚型号有助于将 LMR36503-Q1 与外部时钟

同步。LMR36503-Q1 RT 引脚型号有合适的电阻器可

选，还可通过外部编程实现理想的开关频率。

LMR36503-Q1 丰富的功能集旨在简化各种汽车类终端

设备的实现。

• 专为汽车应用而设计：

– 结温范围：–40°C 至+150°C

– 假随机展频符合CISPR 25 EMI 标准

– 宽输入电压范围：3.0V（下降阈值）至65V

– 提供可调的3.3V 和5V 固定输出电压选项

– 可与MODE/SYNC 引脚型号同步

– 可调F_SW：200kHz 至2.2MHz（采用RT 引脚

型号时）

– 与LMR36506-Q1 引脚兼容（65V、600mA）

器件信息

封装⁽¹⁾

2 应用

器件型号

封装尺寸（标称值）

• 高级驾驶辅助系统(ADAS)

• 车身电子装置和照明

• 信息娱乐系统与仪表组

LMR36503-Q1

VQFN-HR (9)

2.00mm × 2.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

100

90

80

70

60

50

40

BOOT

V_IN

C_IN

VIN

C_BOOT

L_IND

EN/

V_OUT

C_OUT

SW

UVLO

MODE/

SYNC

VCC

PGOOD

FB

30

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

R_FBT

C_VCC

20

10

0

R_FBB

GND

10m

100m

1m 10m

Load Current (A)

100m

LMR3

效率与输出电流间的关系V_OUT= 3.3V（固定值），

简化版原理图

2.2MHz

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBB5

LMR36503-Q1

ZHCSKX8B –SEPTEMBER 2019 –REVISED SEPTEMBER 2020

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Table of Contents

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................23

9 Application and Implementation..................................29

9.1 Application Information............................................. 29

9.2 Typical Application.................................................... 30

9.3 What to Do and What Not to Do............................... 41

10 Power Supply Recommendations..............................41

11 Layout...........................................................................42

11.1 Layout Guidelines................................................... 42

11.2 Layout Example...................................................... 43

12 Device and Documentation Support..........................44

12.1 Documentation Support.......................................... 44

12.2 接收文档更新通知................................................... 44

12.3 支持资源..................................................................44

12.4 Trademarks.............................................................44

12.5 静电放电警告.......................................................... 44

12.6 术语表..................................................................... 44

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

Pin Functions.................................................................... 4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD (Automotive) Ratings .........................................5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................6

7.6 Timing Characteristics ................................................8

7.7 Switching Characteristics ...........................................8

7.8 System Characteristics .............................................. 8

7.9 Typical Characteristics..............................................10

8 Detailed Description......................................................11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram.........................................12

Information.................................................................... 45

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (December 2019) to Revision B (September 2020)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

• 更新了整个文档中的表、图和交叉参考的编号格式.............................................................................................1

2

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5 Device Comparison Table

ORDERABLE PART

OUTPUT VOLTAGE

EXTERNAL SYNC

F_SW

SPREAD SPECTRUM

NUMBER

Yes

Fixed

2.2 MHz

LMR36503MSCQRPERQ1

Adjustable

5-V Fixed

Yes

(PFM/FPWM Selectable)

Yes

Fixed

2.2 MHz

LMR36503MSC5RPERQ1

LMR36503MSC3RPERQ1

LMR36503RS3QRPERQ1

LMR36503RS5QRPERQ1

(PFM/FPWM Selectable)

Yes

Fixed

2.2 MHz

3.3-V Fixed

5-V Fixed

(PFM/FPWM Selectable)

No

Adjustable

with RT resistor

(Default PFM at light load)

No

Adjustable

with RT resistor

(Default PFM at light load)

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6 Pin Configuration and Functions

GND

9

RT⁽¹⁾

FB⁽⁴⁾

1

8

7

6

VOUT/BIAS⁽³⁾

MODE/SYNC⁽²⁾

2

3

PGOOD

VCC

EN/UVLO

BOOT

VIN

SW

4

5

A. See 节5 for more details. Pin 1 trimmed and factory-set for externally adjustable switching frequency RT variants only.

B. Pin 1 factory-set for fixed switching frequency MODE/SYNC variants only.

C. Pin 8 trimmed and factory-set for fixed output voltage VOUT/BIAS variants only.

D. Pin 8 factory-set for adjustable output voltage FB variants only.

图6-1. 9-Pin (2 mm x 2 mm) VQFN-HR RPE Package (Top View)

Pin Functions

I/O

DESCRIPTION

NO.

NAME

When part is trimmed as the RT variant, the switching frequency can be adjusted from 200 kHz to

2.2 MHz. When the part is trimmed as the MODE/SYNC variant, it can operate in user-selectable

PFM/FPWM mode and can be synchronized to an external clock.

Do not float this pin.

RT

1

A

or MODE/SYNC

Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting

resistor. High = power OK, low = power bad. It goes low when EN = low. It can be open or

grounded when not used.

2

3

PGOOD

A

Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float this

pin.

EN/UVLO

Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin

and GND.

4

5

6

VIN

SW

P

Regulator switch node. Connect to power inductor.

Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from

this pin to the SW pin.

BOOT

Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads.

Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this

pin to GND.

7

VCC

P

Fixed output options are available with the VOUT/BIAS pin variant. Connect to output voltage node

for fixed VOUT. Check 节5 for more details.

The FB pin variant can help adjust the output voltage. Connect to tap point of feedback voltage

divider. Do not float this pin.

8

9

VOUT/BIAS or FB

GND

A

G

Power ground terminal. Connect to system ground. Connect to C_INwith short, wide traces.

A = Analog, P = Power, G = Ground

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

PARAMETER

MIN

–0.3

0

MAX

70

UNIT

V

VIN to GND

EN to GND

70

V

SW to GND

PGOOD to GND

70.3

20

V

VOUT/BIAS to GND (Fixed output)

Voltage

16

V

–0.3

–40

–65

FB to GND - (Adjustable output)

16

V

BOOT to SW

5.5

150

V

VCC to GND

V

RT to GND (RT variant)

MODE/SYNC to GND (MODE/SYNC variant)

V

T_J

Junction temperature

Storage temperature

°C

T_stg

(1) Stresses beyond those listed under 节7.1 may cause permanent damage to the device. These are stress ratings only, which do not

imply functional operation of the device at these or any other conditions beyond those indicated under 节7.3. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD (Automotive) Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD classification level 2

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC

Q100-011 CDM ESD classification level C5

±750

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40 °C to 150 °C (unless otherwise noted)^{(1) (2)}

MIN

TYP

MAX

UNIT

Input

voltage

Input voltage range after startup

Load current range⁽³⁾

3.6

65

V

Output

current

0

0.3

2.2

A

Selectable frequency range with RT (RT variant only)

0.2

MHz

Frequency

setting

Set frequency value with RT connected to GND (RT variant only)

Set frequency value with RT connected to VCC (RT variant only)

2.2

1

External

clock

External Sync CLK (MODE/SYNC variant only)

0.2

2.2

MHz

setting

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics table.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125℃

(3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See

Application section for details.

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7.4 Thermal Information

The value of R_θJAgiven in this table is only valid for comparison with other packages and cannot be used for design

purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do

not represent the performance obtained in an actual application. For example, with a 4-layer PCB, a R_θJA= 58℃/W can be

achieved

LMR36503-Q1

THERMAL METRIC⁽¹⁾

VQFN (RPE)

9 Pins

84.4

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

47.5

26.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.9

25.9

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report. The value of R_ΘJAgiven in this table is only valid for comparison with other packages and can not be used for design

purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent

the performance obtained in an actual application. For design information see the Maximum Ambient Temperature section.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

Minimum operating input voltage

(rising)

V_{IN_R}

Rising threshold

3.4

3.0

3.5

V

Minimum operating input voltage

(falling)

V_{IN_F}

Once operating; Falling threshold

2.45

0.25

14

Non-switching input current;

measured at VIN pin⁽²⁾

V_IN= V_EN= 13.5V ; V_OUT/BIAS= 5.25V,

V_MODE/SYNC= V_RT= 0V; Fixed output

I_{Q_13p5_Fixed}

I_{Q_13p5_Adj}

0.672

17

1.05

22

µA

Non-switching input current;

measured at VIN pin⁽²⁾

V_IN= V_EN= 13.5V ; V_FB= 1.05V, V_MODE/

_SYNC= V_RT= 0V; Adjustable output

V_IN= V_EN= 24V ; V_OUT/BIAS

5.25V, V_MODE/SYNC= V_RT= 0V; Fixed

output

=

Non-switching input current;

measured at VIN pin(2)

I_{Q_24p0_Fixed}

0.8

1.2

1.7

µA

Non-switching input current;

measured at VIN pin⁽²⁾

V_IN= V_EN= 24V ; V_FB= 1.05V, V_MODE/

_SYNC= V_RT= 0V; Adjustable output

I_{Q_24p0_Adj}

I_{B_13p5}

14

18

17

18

0.5

1

22

µA

Current into VOUT/BIAS pin (not

switching)⁽²⁾

V_IN= 13.5V, V_OUT/BIAS= 5.25V, V_MODE/

_SYNC= V_RT= 0V; Fixed output

Current into VOUT/BIAS pin (not

switching)⁽²⁾

V_IN= 24V, V_OUT/BIAS= 5.25V, V_MODE/SYNC

= V_RT= 0V; Fixed output

I_{B_24p0}

22

Shutdown quiescent current;

measured at VIN pin⁽²⁾

I_{SD_13p5}

I_{SD_24p0}

V_EN= 0; V_IN= 13.5V

V_EN= 0; V_IN= 24V

1.1

1.6

Shutdown quiescent current;

measured at VIN pin⁽²⁾

ENABLE (EN PIN)

V_EN-WAKEEnable wake-up threshold

0.4

V

Precision enable high level for

VOUT

V_EN-VOUT

1.16

1.263

1.36

Enable threshold hysteresis below

V_{EN- VOUT}

V_EN-HYST

0.3

0.35

0.3

0.4

8

V

I_LKG-EN

Enable input leakage current

VEN = 3.3 V

nA

INTERNAL LDO

6

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Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

3.15

65

MAX

3.22

240

UNIT

V_CC

Internal VCC voltage

Bias regulator current limit

Adjustable or fixed output; Auto mode

3.125

V

I_CC

mA

V

V_CC-UVLO

Internal VCC undervoltage lockout VCC rising under voltage threshold

3

3.3

3.65

Internal VCC under voltage lock-

Hysteresis below V_CC-UVLO

out hysteresis

V_CC-UVLO-HYST

0.4

0.8

1.2

V

CURRENT LIMITS

Short circuit high side current

I_SC-0p3

0.3A Version

0.42

0.3

0.5

0.35

0.09

0.575

0.4

A

Limit⁽³⁾

I_LS-LIMIT-0p3

I_PEAK-MIN-0p3

Low side current limit⁽³⁾

PFM Operation, 0.3A Version; Duty

Factor = 0

Minimum peak inductor current⁽³⁾

0.067

0.11

I_ZC

Zero cross current⁽³⁾

Auto mode

0

0.01

0.7

0.022

0.8

A

I_L-NEG

Sink current limit (negative)⁽³⁾

FPWM mode

0.6

POWER GOOD

% of FB (Adjustable output) or % of

VOUT/BIAS (Fixed output)

PG-OV

PGOOD upper threshold - rising

PGOOD lower threshold - falling

PGOOD hysteresis - rising/falling

106

93

107

94

1.8

1

110

96.5

2.3

2

%

V

% of FB (Adjustable output) or % of

VOUT/BIAS (Fixed output)

PG-UV

% of FB (Adjustable output) or % of

VOUT/BIAS (Fixed output)

PG-HYS

V_PG-VALID

1.3

Minimum input voltage for proper

PG function

0.75

R_PG-EN5p0

R_PG-EN0

R_DS(ON)PGOOD output

VEN = 5.0V, 1mA pull-up current

VEN = 0 V, 1mA pull-up current

20

10

40

18

70

31

Ω

OSCILLATOR (MODE/SYNC)

Sync input and mode high level

threshold

V_{MODE_H}

V_SYNC-HYS

V_{MODE_L}

1.8

V

mV

V

Sync input hysteresis

230

300

380

0.8

Sync input and mode low level

threshold

MOSFETS

R_DS-ON-HS

R_DS-ON-LS

High-side MOSFET on-resistance Load = 0.3 A

560

280

2.3

920

460

mΩ

V

Low-side MOSFET on-resistance

Cboot - SW UVLO threshold⁽⁴⁾

Load = 0.3 A

V_CBOOT-UVLO

2.14

3.25

2.42

VOLTAGE REFERENCE

Initial VOUT voltage accuracy for

V_{OUT_Fixed3p3}

FPWM mode

3.3

5

3.34

5.07

V

3.3 V

Initial VOUT voltage accuracy for 5

V

V_{OUT_Fixed5p0}

4.93

V_REF

I_FB

Internal reference voltage

FB input current

V_IN= 3.6V to 65V, FPWM mode

Adjustable output, FB = 1V

0.985

1

1.01

110

V

85

nA

(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.

(4) When the voltage across the C_BOOTcapacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor

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7.6 Timing Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOFT START

Time from first SW pulse to V_FBat

90%, of V_REF

t_SS

1.95

2.58

3.2

ms

V_IN≥3.6 V

POWER GOOD

Glitch filter time constant for PG

t_{RESET_FILTER}

15

25

40

µs

function

t_{PGOOD_ACT}

Delay time to PG high signal

1.7

1.956

2.16

ms

OSCILLATOR (MODE/SYNC)

High duration needed to be

recognized as a pulse

t_{PULSE_H}

t_{PULSE_L}

t_SYNC

100

6

ns

µs

Low duration needed to be

recognized as a pulse

High/low signal duration in a valid

synchronization signal

9

12

Time at one level needed to indicate

FPWM or Auto Mode

t_MODE

18

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM LIMITS (SW)

t_ON-MIN

t_OFF-MIN

t_ON-MAX

Minimum switch on-time

Minimum switch off-time

Maximum switch on-time

I_OUT= 0.3 A

35

40

60

58

9

97

77

ns

µs

HS timeout in dropout

7.6

9.8

OSCILLATOR (RT)

f_{OSC_2p2MHz}

f_{OSC_1p0MHz}

f_{ADJ_400kHz}

Internal oscillator frequency

RT = GND

RT = VCC

2.1

0.93

0.34

2.2

1

2.3

1.05

0.46

MHz

0.4

RT = 39.2 kΩ

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.8 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 150°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STANDBY CURRENT AND DUTY RATIO

Input supply current when in

regulation

V_IN= 13.5 V, V_OUT/BIAS= 3.3 V, I_OUT

0 A, PFM mode

=

I_SUPPLY

6.5

4

µA

Input supply current when in

regulation

V_IN= 24 V, V_OUT/BIAS= 3.3 V, I_OUT= 0

A, PFM mode

I_SUPPLY

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The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 150°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D_MAX

Maximum switch duty cycle⁽¹⁾

98%

OUTPUT VOLTAGE ACCURACY (VOUT/BIAS)

V_OUT= 3.3 V, V_IN= 3.6 V to 65 V,

V_{OUT_3p3V_ACC}

FPWM mode

1.5

2.5

%

–1.5

I_OUT= 0 to full load⁽²⁾

V_OUT= 3.3 V, V_IN= 3.6V to 65 V,

V_{OUT_3p3V_ACC}

Auto mode

I_OUT= 0 A to full load⁽²⁾

SPREAD SPECTRUM

Frequency span of spread

f_SSS

spectrum operation - largest

Spread spectrum active

±2

%

deviation from center frequency

Spread spectrum pseudo random

pattern frequency

f_PSS

0.98

1.5

Hz

THERMAL SHUTDOWN

T_SD-R

Thermal shutdown rising

Shutdown threshold

Recovery threshold

158

150

8

168

158

10

180

165

15

°C

T_SD-F

Thermal shutdown falling

T_SD-HYS

Thermal shutdown hysteresis

(1) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: f_MIN

1 / (t_ON-MAX+ T_OFF-MIN). D_MAX= t_ON-MAX/(t_ON-MAX+ t_OFF-MIN).

=

(2) Deviation is with respect to V_IN=13.5 V

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7.9 Typical Characteristics

Unless otherwise specified, the following conditions apply: T_A= 25°C, V_IN= 13.5 V.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

1m

10m

Load Current (A)

100m

0.001

0.01

Load Current (A)

0.1

0.5

LMR3

V_OUT= 3.3 V Fixed

F_SW= 2.2 MHz (FPWM)

V_OUT= 5 V Fixed

F_SW= 2.2 MHz (FPWM)

图7-1. Efficiency 3.3-V Output, FPWM

图7-2. Efficiency 5-V Output, FPWM

100

90

80

70

60

50

40

18

3.3V

5V

16

14

12

10

8

30

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

6

20

4

10

0

2

5

10 15 20 25 30 35 40 45 50 55 60 65

Input Voltage (V)

10m

100m

1m 10m

Load Current (A)

100m

LMR3

V_OUT= 5 V Fixed

F_SW-NOM= 2.2 MHz (Auto)

图7-4. Typical Input Supply Current at No Load for

Fixed 3.3-V and 5-V Output

图7-3. Efficiency 5-V Output, Auto Mode

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

VOUT (1V/DIV)

VIN (1V/DIV)

Power-Down

Power-Up

IOUT (200mA/DIV)

0

1

2

3 4

Input Voltage (V)

5

6

7

D006

50ms/DIV

I_Load= 300 mA

V_OUT= 5 V Fixed F_SW-NOM= 2.2 MHz

(Auto)

图7-6. Typical Start-up and Shutdown at V_OUT= 5 V

图7-5. Dropout at Power-Up and Power-Down

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8 Detailed Description

8.1 Overview

The LMR36503-Q1 is a wide input, low-quiescent current, high-performance regulator that can operate over a

wide range of duty ratio and the switching frequencies, including sub-AM band at 400 kHz and above AM band

at 2.2 MHz. During wide input transients, if the minimum ON-time or the minimum OFF-time cannot support the

desired duty ratio at the higher switching frequency settings, the switching frequency is reduced automatically,

allowing the LMR36503-Q1 to maintain the output voltage regulation. With an internally-compensated design

optimized for minimal output capacitors, the system design process with the LMR36503-Q1 is simplified

significantly compared to other buck regulators available in the market.

The LMR36503-Q1 is designed to minimize external component cost and solution size while operating in all

demanding automotive environments. The LMR36503-Q1 family includes variants that can be set-up to operate

over a wide switching frequency range, from 200 kHz to 2.2 MHz, with the correct resistor selection from RT pin

to ground. To further reduce system cost, the PGOOD output feature with built-in delayed release allows the

elimination of the reset supervisor in many applications.

The LMR36503-Q1 family is designed to reduce EMI/EMC emissions. The design includes a pseudo-random

spread spectrum switching frequency dithering scheme, has no bond-wire flip-chip on the lead (HotRod™)

package, and is available with the MODE/SYNC feature (select variants), allowing synchronization to an external

clock, when available. Together, these features eliminate the need for any common-mode choke or shielding or

any elaborate input filter design scheme, greatly reducing the complexity and cost of the EMI/EMC mitigation

measures.

The LMR36503-Q1 comes in an ultra-small 2-mm x 2-mm QFN package with wettable flanks allowing for quick

optical inspection along with specially designed corner anchor pins for reliable board level solder connections.

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8.2 Functional Block Diagram

VCC

MODE/SYNC VARIANTS

FIXED

OUTPUT

VOLTAGE

VARIANTS

ONLY

MODE

CLOCK

SLOPE

VOUT/

BIAS

/SYNC

OSCILLATOR

RT

COMPENSATION

LDO

VCC UVLO

TSD

RT VARIANTS ONLY

VIN

THERMAL

SHUTDOWN

F_SWFOLDBACK

BOOT

SYS ENABLE

ENABLE

EN

HS

CURRENT

SENSE

VIN

ADJ. OUTPUT

VOLTAGE

VARIANTS ONLY

ERROR

+

œ

AMPLFIER

COMP

FB

TSD

œ

VOUT/

BIAS

+

MAX. &

MIN.

CLOCK

LIMITS

+

HS

FIXED OUTPUT

œ

SW

VOLTAGE

VARIANTS

ONLY

CURRENT

SYS ENABLE

LMIT

CONTROL

LOGIC &

DRIVER

SOFT-

START

&

TSD

GND

VREF

LS

BANDGAP

VCC UVLO

CURRENT

LMIT

œ

FIXED OUTPUT

VOLTAGE

ADJ. OUTPUT

+

VOLTAGE

VARIANTS

VARIANTS ONLY

ONLY

œ

VOUT/

MIN.

LS CURRENT

LIMIT

FB

BIAS

GND

+

PGOOD

FPWM or AUTO

VOUT UV/OV

PGOOD

LOGIC

LS

CURRENT

SENSE

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8.3 Feature Description

8.3.1 Enable, Start-up and Shutdown

Voltage at the EN pin controls the start-up or remote shutdown of the LMR36503-Q1 family of devices. The part

stays shut down as long as the EN pin voltage is less than V_EN-WAKE= 0.4 V. During the shutdown, the input

current drawn by the device typically drops down to 0.5 µA (VIN = 13.5 V). With the voltage at the EN pin greater

than the V_EN-WAKE, the device enters the device standby mode, the internal LDO powers up to generate VCC. As

the EN voltage increases further, approaching V_EN-VOUT, the device finally starts to switch, entering the start-up

mode, with a soft start. During the device shutdown process, when the EN input voltage measures less than

(V_EN-VOUT– V_EN-HYST), the regulator stops switching and re-enters the device standby mode. Any further

decrease in the EN pin voltage, below V_EN-WAKE, the device is then firmly shut down. The high-voltage compliant

EN input pin can be connected directly to the VIN input pin if remote precision control is not needed. The EN

input pin must not be allowed to float. The various EN threshold parameters and their values are listed in 节 7.5.

图 8-2 shows the precision enable behavior. 图 8-3 shows a typical remote EN start-up waveform in an

application. Once EN goes high, after a delay of about 1 ms, the output voltage begins to rise with a soft start

and reaches close to the final value in about 2.67 ms (t_ss). After a delay of about 2 ms (t_{PGOOD_ACT}), the PGOOD

flag goes high. During start-up, the device is not allowed to enter FPWM mode until the soft-start time has

elapsed. This time is measured from the rising edge of EN. Check 节9.2.2.8.1 for component selection.

V_IN

R_ENT

EN

R_ENB

AGND

图8-1. VIN UVLO Using the EN pin

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EN

V_EN-VOUT

V_EN-HYST

V_EN-WAKE

VCC

3.3V

0

VOUT

V_OUT

0

图8-2. Precision Enable Behavior

VIN (5V/DIV)

VOUT (5V/DIV)

EN (2V/DIV)

PGOOD (5V/DIV)

IOUT (0.5A/DIV)

1ms/DIV

图8-3. Enable Start-up V_IN= 12 V, V_OUT= 5 V, I_OUT= 300 mA

8.3.2 External CLK SYNC (with MODE/SYNC)

It is often desirable to synchronize the operation of multiple regulators in a single system, resulting in a well-

defined system level performance. The select variants in the LMR36503-Q1 with the MODE/SYNC pin allow the

power designer to synchronize the device to a common external clock. The LMR36503-Q1 implements an in-

phase locking scheme, where the rising edge of the clock signal, provided to the MODE/SYNC pin of the

LMR36503-Q1, corresponds to the turning on of the high-side device. The external clock synchronization is

implemented using a phase locked loop (PLL) eliminating any large glitches. The external clock fed into the

LMR36503-Q1 replaces the internal free-running clock, but does not affect any frequency foldback operation.

Output voltage continues to be well-regulated. The device remains in FPWM mode and operates in CCM for light

loads when synchronization input is provided.

The MODE/SYNC input pin in the LMR36503-Q1 can operate in one of three selectable modes:

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• Auto Mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation

prevents reverse current through the inductor. See 节8.4.3.2 for more details.

• FPWM Mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the

inductor. This allows operation at full frequency even without load current. See 节8.4.3.3 for more details.

• SYNC Mode: The internal clock locks to an external signal applied to the MODE/SYNC pin. As long as output

voltage can be regulated at full frequency and is not limited by minimum off-time or minimum on-time, clock

frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the device is in

SYNC mode, it operates as though in FPWM mode: diode emulation is disabled allowing the frequency

applied to the MODE/SYNC pin to be matched without a load.

8.3.2.1 Pulse-Dependent MODE/SYNC Pin Control

Most systems that require more than a single mode of operation from the LMR36503-Q1 are controlled by digital

circuitry such as a microprocessor. These systems can generate dynamic signals easily but have difficulty

generating multi-level signals. Pulse-Dependent MODE/SYNC pin control is useful with these systems. To initiate

Pulse-Dependent MODE/SYNC pin control, a valid sync signal must be applied. 表 8-1 shows a summary of the

pulse dependent mode selection settings.

表8-1. Pulse-Dependent Mode Selection Settings

MODE/SYNC INPUT

MODE

> V_{MODE_H}

FPWM with Spread Spectrum factory setting

Auto Mode with Spread Spectrum factory setting

SYNC Mode

< V_{MODE_L}

Synchronization Clock

图 8-4 shows the transition between AUTO Mode and FPWM Mode while in Pulse-Dependent MODE/SYNC

control. The LMR36503-Q1 transitions to a new mode of operation after the time, t_MODE. 图 8-4 and 图 8-5 show

the details.

Transition to new mode of operation

starts, spread spectrum turns on

> t_MODE

FPWM Mode

V_{MODE_H}

V_{MODE_L}

Auto Mode

图8-4. Transition from Auto Mode and FPWM Mode

If MODE/SYNC voltage remains constant longer than t_MODE, the LMR36503-Q1 enters either Auto mode or

FPWM mode with spread spectrum turned on (if factory setting is enabled) and MODE/SYNC continues to

operate in Pulse-Dependent scheme.

t_MODE

Now Auto Mode, Spread Spectrum on

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图8-5. Transition from SYNC Mode to Auto Mode

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t_MODE

< t_SYNC

Now FPWM Mode, Spread Spectrum on

V_{MODE_H}

V_{MODE_L}

> t_{PULSE_H}

< t_SYNC

> t_{PULSE_L}

图8-6. Transition from SYNC Mode to FPWM Mode

8.3.3 Adjustable Switching Frequency (with RT)

The select variants in the LMR36503-Q1 family with the RT pin allow the power designers to set any desired

operating frequency between 200 kHz and 2.2 MHz in their applications. See 图 8-7 to determine the resistor

value needed for the desired switching frequency. The RT pin and the MODE/SYNC pin variants share the same

pin location. The power supply designer can either use the RT pin variant and adjust the switching frequency of

operation as warranted by the application or use the MODE/SYNC variant and synchronize to an external clock

signal. See 表8-2 for selection on programming the RT pin.

表8-2. RT Pin Setting

RT INPUT

VCC

SWITCHING FREQUENCY

1 MHz

GND

2.2 MHz

RT to GND

Adjustable according to 图8-7

No Switching

Float (Not Recommended)

方程式1 can be used to calculate the value of RT for a desired frequency.

18286

RT =

Fsw^1.021

(1)

where

• RT = Frequency setting resistor value (kΩ)

• F_SW= Switching frequency (kHz)

80

70

60

50

40

30

20

10

0

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Switching Frequency (kHz)

RTvs

图8-7. RT Values vs Frequency

8.3.4 Power-Good Output Operation

The power-good feature using the PG pin of the LMR36503-Q1 can be used to reset a system microprocessor

whenever the output voltage is out of regulation. This open-drain output remains low under device fault

conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents

false flag operation for any short duration excursions in the output voltage, such as during line and load

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transients. Output voltage excursions lasting less than t_{RESET_FILTER}do not trip the power-good flag. Power-good

operation can best be understood in reference to 图 8-8. 表 8-3 gives a more detailed breakdown the PGOOD

operation. Here, V_PG-UVis defined as the PG-UV scaled version of the V_OUT-Reg(target regulated output voltage)

and V_PG-HYSas the PG-HYS scaled version of the V_OUT-Reg, where both PG-UV and PG-HYS are listed in 节7.5.

During the initial power up, a total delay of 5 ms (typ.) is encountered from the time the V_EN-VOUTis triggered to

the time that the power-good is flagged high. This delay only occurs during the device start-up and is not

encountered during any other normal operation of the power-good function. When EN is pulled low, the power-

good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage

(V_PG-VALIDis ≥1 V (typical).

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup

resistor connected to a suitable logic supply. It can also be pulled up to either V_CCor V_OUTthrough an

appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit

the current into this pin to ≤4 mA.

Output

Voltage

Input

Voltage

Input Voltage

t_{RESET_FILTER}

t_{PGOOD_ACT}

t_{RESET_FILTER}

V_PG-HYS

t_{RESET_FILTER}

V_PG-UV(falling)

V_{IN_R}(rising)

V_{IN_F}(falling)

V_{PG_VALID}

GND

VOUT

PGOOD

Small glitches

do not cause

reset to signal

a fault

PGOOD may

not be valid if

input is below

V_PG-VALID

Small glitches do not

reset t_{PGOOD_ACT}timer

PGOOD may not

be valid if input is

below V_PG-VALID

Startup

delay

图8-8. Power-Good Operation (OV Events Not Included)

表8-3. Fault Conditions for PGOOD (Pull Low)

FAULT CONDITION ENDS (AFTER WHICH t_{PGOOD_ACT}MUST PASS

BEFORE PGOOD OUTPUT IS RELEASED)

FAULT CONDITION INITIATED

Output voltage in regulation:

V_PG-UV+ V_PG-HYS< V_OUT< V_PG-OV- V_PG-HYS

V_OUT< V_PG-UVAND t > t_{RESET_FILTER}

V_OUT> V_PG-OVAND t > t_{RESET_FILTER}

T_J> T_SD-R

EN < V_EN-VOUT- V_EN-HYST

V_CC< V_CC-UVLO- V_CC-UVLO-HYST

Output voltage in regulation

T_J< T_SD-FAND output voltage in regulation

EN > V_EN-VOUTAND output voltage in regulation

V_CC> V_CC-UVLOAND output voltage in regulation

8.3.5 Internal LDO, VCC UVLO, and VOUT/BIAS Input

The LMR36503-Q1 uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin

draws power either from the VIN (in adjustable output variants) or the VOUT/BIAS (in fixed-output variants). In

the fixed output variants, once the LMR36503-Q1 is active but has yet to regulate, the VCC rail will continue to

draw power from the input voltage, VIN, until the VOUT/BIAS voltage reaches > 3.15 V (or when the device has

reached steady-state regulation post the soft start). The VCC rail typically measures 3.15 V in both adjustable

and fixed output variants. To prevent unsafe operation, VCC has an undervoltage lockout, which prevents

switching if the internal voltage is too low. See V_VCC-UVLOand V_{VCC-UVLO-HYST}in 节 7.5. During start-up, VCC

momentarily exceeds the normal operating voltage until V_VCC-UVLOis exceeded, then drops to the normal

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operating voltage. Note that these undervoltage lockout values, when combined with the LDO dropout, drives

the minimum input voltage rising and falling thresholds.

8.3.6 Bootstrap Voltage and V_CBOOT-UVLO(CBOOT Terminal)

The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned ON.

The capacitor connected between CBOOT and SW works as a charge pump to boost voltage on the CBOOT

terminal to (SW+VCC). The boot diode is integrated on the LMR36503-Q1 die to minimize physical solution size.

A 100-nF capacitor rated for 10 V or higher is recommended for CBOOT. The CBOOT rail has an UVLO setting.

This UVLO has a threshold of V_CBOOT-UVLOand is typically set at 2.3 V. If the CBOOT capacitor is not charged

above this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-

side switch before attempting to turn on the high-side device.

8.3.7 Output Voltage Selection

In the LMR36503-Q1 family, select variants with an adjustable output voltage option (see 节5), and you need an

external resistor divider connection between the output voltage node, the device FB pin, and the system GND,

as shown in 图 8-9. The variants with adjustable output voltage option in the LMR36503-Q1 family are designed

with a 1-V internal reference voltage.

R_FBT

R_FBB

=

V_OUTÅ 1

(2)

When using the fixed-output variants from the LMR36503-Q1 family, simply connect the FB pin (will be identified

as VOUT/BIAS pin for fixed-output variants in the rest of the data sheet) to the system output voltage node. See

节5 for more details.

V_OUT

R_FBT

FB

R_FBB

AGND

图8-9. Setting Output Voltage for Adjustable Output Variant

In adjustable output voltage variants, an addition feed-forward capacitor, C_FF, in parallel with the R_FBT, can be

used to optimize the phase margin and transient response. See 节9.2.2.8 for more details. No additional resistor

divider or feed-forward capacitor, C_FF, is needed in fixed-output variants.

8.3.8 Soft Start and Recovery from Dropout

When designing with the LMR36503-Q1, slow rise in output voltage due to recovery from dropout and soft start

should be considered as a two separate operating conditions, as shown in 图 8-10 and 图 8-11. Soft start is

triggered by any of the following conditions:

• Power is applied to the VIN pin of the device, releasing undervoltage lockout.

• EN is used to turn on the device.

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• Recovery from shutdown due to overtemperature protection.

Once soft start is triggered, the IC takes the following actions:

• The reference used by the IC to regulate output voltage is slowly ramped up. The net result is that output

voltage, if previously 0 V, takes t_SSto reach 90% of the desired value.

• Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side

MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already

present at the output during a pre-bias start-up.

If selected, FPWM

is enabled only

after completion of

t_SS

If selected, FPWM

is enabled only

after completion of

t_SS

Triggering event

t_EN

t_SS

t_EN

t_SS

V

V_EN

V_OUTSet

Point

V_OUTSet

Point

V_OUT

90% of

V_OUTSet

Point

90% of

V_OUTSet

Point

t

0 V

Time

图8-10. Soft Start With and Without Pre-bias Voltage

8.3.8.1 Recovery from Dropout

Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called

graceful recovery from dropout in this document, differs from soft start in two important ways:

• The reference voltage is set to approximately 1% above what is needed to achieve the existing output

voltage.

• If the device is set to FPWM, it will continue to operate in that mode during its recovery from dropout. If output

voltage were to suddenly be pulled up by an external supply, the LMR36503-Q1 can pull down on the output.

Note that all protections that are present during normal operation are in place, preventing any catastrophic

failure if output is shorted to a high voltage or ground.

V

Load

current

V_OUTSet

Point

and max

output

Slope

V_OUT

the same

as during

soft start

current

t

Time

图8-11. Recovery from Dropout

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VIN (2V/DIV)

8V

4V

VOUT (2V/DIV)

5V

Load Current (0.2A/DIV)

500µs/DIV

图8-12. Typical Output Recovery from Dropout from 8 V to 4 V

Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall

below its set point is removed, the output climbs at the same speed as during start-up. shows an example of this

behavior.

8.3.9 Current Limit and Short Circuit

The LMR36503-Q1 is protected from overcurrent conditions by cycle-by-cycle current limiting on both high-side

and low-side MOSFETs.

High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The

HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is

compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop

minus the slope compensation every switching cycle. Since the output of the internal error amplifier loop has a

maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased

duty factor if duty factor is typically above 35%.

When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side

device, the low-side device has a turnoff commanded by the internal error amplifier loop. In the case of the low-

side device, turnoff is prevented if the current exceeds this value, even if the oscillator normally starts a new

switching cycle. Also like the high-side device, there is a limit on how high the turnoff current is allowed to be.

This is called the low-side current limit, I_LS-LIMIT(or I_L-LSin 图 8-13). If the LS current limit is exceeded, the LS

MOSFET stays on and the HS switch is not to be turned on. The LS switch is turned off once the LS current falls

below this limit and the HS switch is turned on again as long as at least one clock period has passed since the

last time the HS device has turned on.

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V_SW

V_IN

t_ON< t_{ON_MAX}

0

t

Typically, t_SW> Clock setting

i_L

I_L-HS

I_L-LS

I_OUT

t

0

图8-13. Current Limit Waveforms

Since the current waveform assumes values between I_SC(or I_L-HSin 图 8-13) and I_LS-LIMIT, the maximum output

current is very close to the average of these two values unless duty factor is very high. Once operating in current

limit, hysteretic control is used and current does not increase as output voltage approaches zero.

If duty factor is very high, current ripple must be very low in order to prevent instability. Since current ripple is

low, the part is able to deliver full current. The current delivered is very close to I_LS-LIMIT

.

V_OUT

I_L-LS

I_OUTrated

I_L-HS

V_OUTSetting

V_IN> 2 ‡ V_OUTSetting

V_IN~ V_OUTSetting

I_OUT

0

Output Current

图8-14. Output Voltage versus Output Current

Under most conditions, current is limited to the average of I_L-HSand I_L-LS, which is approximately 1.3 times the

maximum-rated current. If input voltage is low, current can be limited to approximately I_L-LS. Also note that the

maximum output current does not exceed the average of I_L-HSand I_L-LS. Once the overload is removed, the part

recovers as though in soft start.

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VOUT (1V/DIV)

5V

Short Removed

Short Applied

VOUT (5V/DIV)

0V

Inductor Current (0.2A/DIV)

10ms/DIV

Load Current (0.2A/DIV)

2ms/DIV

图8-15. Short Circuit Waveform

图8-16. Overload Output Recovery

8.3.10 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction

temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal

shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to

approximately 158°C (typical). When the junction temperature falls below 158°C (typical), the LMR36503-Q1

attempts another soft start.

While the LMR36503-Q1 is shut down due to high junction temperature, power continues to be provided to VCC.

To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced

current limit while the part is disabled due to high junction temperature. The LDO only provides a few

milliamperes during thermal shutdown.

8.3.11 Input Supply Current

The LMR36503-Q1 is designed to have very low input supply current when regulating light loads. This is

achieved by powering much of the internal circuitry from the output. The VOUT/BIAS pin in the fixed-output

voltage variants is the input to the LDO that powers the majority of the control circuits. By connecting the VOUT/

BIAS input pin to the output node of the regulator, a small amount of current is drawn from the output. This

current is reduced at the input by the ratio of V_OUT/ V_IN.

V_OUT

I_{Q_VIN}= I_Q+ I_EN+ I_BIAS

¾

eff

x V_IN

(3)

where

• I_{Q_VIN}is the total standby (switching) current consumed by the operating (switching) buck converter when

unloaded.

• I_Qis the current drawn from the V_INterminal. Check I_{Q_13p5_Fixed}or I_{Q_24p0_Fixed}in 节7.5 for I_Q.

• I_ENis current drawn by the EN terminal. Include this current if EN is connected to VIN. Check I_LKG-ENin 节7.5

for I_EN

.

• I_BIASis bias current drawn by the BIAS input. Check I_{B_13p5}or I_{B_24p0}in 节7.5 for I_BIAS

.

• η_effis the light-load efficiency of the buck converter with I_{Q_VIN}removed from the input current of the buck

converter. η_eff= 0.8 is a conservative value that can be used under normal operating conditions. This can be

traced back as the I_SUPPLYin 节7.7.

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, both

the converter and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode,

the quiescent current drops to typically 0.5 µA.

8.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above

1.1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the

VCC voltage at 3.3 V typical. The precision enable circuitry is ON once VCC is above its UVLO. The internal

power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable

threshold. The LMR36503-Q1 also employs UVLO protection. If the VCC voltage is below its UVLO level, the

output of the converter is turned off.

8.4.3 Active Mode

The LMR36503-Q1 is in active mode whenever the EN pin is above V_EN-VOUT, V_INis high enough to satisfy

V_{IN_R}, and no other fault conditions are present. The simplest way to enable the operation is to connect the EN

pin to V_IN, which allows self start-up when the applied input voltage exceeds the minimum V_{IN_R}

.

In active mode, depending on the load current, input voltage, and output voltage, the LMR36503-Q1 is in one of

five modes:

• Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

inductor current ripple

• Auto Mode - Light Load Operation: PFM when switching frequency is decreased at very light load

• FPWM Mode - Light Load Operation: Discontinuous conduction mode (DCM) when the load current is lower

than half of the inductor current ripple

• Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to

maintain regulation.

• Dropout mode: When switching frequency is reduced to minimize voltage dropout.

8.4.3.1 CCM Mode

The following operating description of the LMR36503-Q1 refers to the 节 8.2 and to the waveforms in 图 8-17. In

CCM, the LMR36503-Q1 supplies a regulated output voltage by turning on the internal high-side (HS) and low-

side (LS) switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, V_SW, swings

up to approximately V_IN, and the inductor current, i_L, increases with a linear slope. The HS switch is turned off by

the control logic. During the HS switch off-time, t_OFF, the LS switch is turned on. Inductor current discharges

through the LS switch, which forces the V_SWto swing below ground by the voltage drop across the LS switch.

The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of

the HS switch over the switching period:

D = T_ON/ T_SW

(4)

In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage:

D = V_OUT/ V_IN

(5)

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

V_IN

t_OFF

t_ON

0

t

- I_OUT‡R_DSLS

t_SW

i_L

I_LPK

I_OUT

I_ripple

t

0

图8-17. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

8.4.3.2 Auto Mode - Light Load Operation

The LMR36503-Q1 can have two behaviors while lightly loaded. One behavior, called auto mode operation,

allows for seamless transition between normal current mode operation while heavily loaded and highly efficient

light load operation. The other behavior, called FPWM Mode, maintains full frequency even when unloaded.

Which mode the LMR36503-Q1 operates in depends on which variant from this family is selected. Note that all

parts operate in FPWM mode when synchronizing frequency to an external signal.

The light load operation is employed in the LMR36503-Q1 only in the auto mode. The light load operation

employs two techniques to improve efficiency:

• Diode emulation, which allows DCM operation. See 图8-18.

• Frequency reduction. See 图8-19.

Note that while these two features operate together to improve light load efficiency, they operate independent of

each other.

8.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to

regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.

With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to

maintain regulation.

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t_ON

V_OUT

V_IN

D =

V_SW

<

t_SW

V_IN

t_OFF

t_ON

t_HIGHZ

0

t

t_SW

i_L

I_LPK

I_OUT

0

t

In auto mode, the low-side device is turned off once SW node current is near zero. As a result, once output current is less than half of

what inductor ripple would be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.

图8-18. PFM Operation

The LMR36503-Q1 has a minimum peak inductor current setting (I_LPK(see I_PEAK-MINin 节 7.5) while in auto

mode. Once current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then

achieved by adjusting frequency. This mode of operation is called PFM mode regulation.

8.4.3.2.2 Frequency Reduction

The LMR36503-Q1 reduces frequency whenever output voltage is high. This function is enabled whenever the

internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the

regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance

while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when

the part is completely unloaded.

V_OUT

Current

Limit

1% Above

Set point

V_OUTSet

Point

I_OUT

Output Current

0

In auto mode, once output current drops below approximately 1/10th the rated current of the part, output resistance increases so that

output voltage is 1% high while the buck is completely unloaded.

图8-19. Steady State Output Voltage versus Output Current in Auto Mode

In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The

lower the frequency in PFM, the more DC offset is needed on V_OUT. If the DC offset on V_OUTis not acceptable, a

dummy load at V_OUTor FPWM Mode can be used to reduce or eliminate this offset.

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8.4.3.3 FPWM Mode - Light Load Operation

In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is

allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see 节 7.5 for

reverse current limit values.

V_SW

t_ON

V_OUT

V_IN

D =

≈

t_SW

V_IN

t_OFF

t_ON

0

t

t_SW

i_L

I_LPK

I_OUT

0

I_ripple

t

In FPWM mode, Continuous Conduction (CCM) is possible even if I_OUTis less than half of I_ripple

.

图8-20. FPWM Mode Operation

For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to

command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output

being pulled up.

8.4.3.4 Minimum On-time (High Input Voltage) Operation

The LMR36503-Q1 continues to regulate output voltage even if the input-to-output voltage ratio requires an on-

time less than the minimum on-time of the chip with a given clock setting. This is accomplished using valley

current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a

maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until

valley current falls below that determined by the compensation circuit. If the converter is not operating in current

limit, the maximum valley current is set above the peak inductor current, preventing valley control from being

used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high,

such that the inductor current peak value exceeds the peak command dictated by compensation, the high-side

device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit

reduces both peak and valley current. Once a low enough current is selected by the compensation circuit, valley

current matches that being commanded by the compensation circuit. Under these conditions, the low-side device

is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley

current. Since on-time is fixed at its minimum value, this type of operation resembles that of a device using a

Constant On-Time (COT) control scheme; see 图8-21.

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

V_IN

t_ON= t_{ON_MIN}

t_OFF

0

t

- I_OUT‡R_DSLS

t_SW> Clock setting

i_L

I_OUT

I_ripple

I_LVLY

t

0

In valley control mode, minimum inductor current is regulated, not peak inductor current.

图8-21. Valley Current Mode Operation

8.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the

required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. Once this limit is

reached as shown in 图 8-23 if clock frequency was to be maintained, the output voltage would fall. Instead of

allowing the output voltage to drop, the LMR36503-Q1 extends the high side switch on-time past the end of the

clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle once

peak inductor current is achieved or once a pre-determined maximum on-time, t_ON-MAX, of approximately 9 µs

passes. As a result, once the needed duty cycle cannot be achieved at the selected clock frequency due to the

existence of a minimum off-time, frequency drops to maintain regulation. As shown in 图 8-22 if input voltage is

low enough so that output voltage cannot be regulated even with an on-time of t_ON-MAX, output voltage drops to

slightly below the input voltage by V_DROP. For additional information on recovery from dropout, refer back to 图

8-11.

Input

Voltage

V_OUT

V_DROP

Output

Voltage

Output

Setting

V_IN

0

Input Voltage

F_SW

F_SW-NOM

~110kHz

0

V_IN

Input Voltage

Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC

reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,

input voltage tracks output voltage.

图8-22. Frequency and Output Voltage in Dropout

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

t_OFF= t_{OFF_MIN}

V_IN

t_ON< t_{ON_MAX}

0

t

- I_OUT‡R_DSLS

t_SW> Clock setting

i_L

I_LPK

I_OUT

I_ripple

t

0

Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,

frequency drops. This frequency drop is limited by t_ON-MAX

.

图8-23. Dropout Waveforms

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9 Application and Implementation

备注

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The LMR36503-Q1 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 0.3 A. The following design procedure can be used to select

components for the LMR36503-Q1.

备注

All of the capacitance values given in the following application information refer to effective values

unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and

temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with

an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage

coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance

drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help

mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective

capacitance up to the required value. This can also ease the RMS current requirements on a single

capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to

ensure that the minimum value of effective capacitance is provided.

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9.2 Typical Application

图 9-1 shows a typical application circuit for the LMR36503-Q1. This device is designed to function over a wide

range of external components and system parameters. However, the internal compensation is optimized for a

certain range of external inductance and output capacitance. As a quick-start guide, 表 9-1 provides typical

component values for a range of the most common output voltages.

L

V_OUT

V_IN

SW

VIN

EN

C_IN

C_HF

C_BOOT

100 nF

2.2 µF

C_OUT

BOOT

0.1 µF

LMR36503-Q1

C_FF

R_FBT

MODE

VCC

PG

FB

100 kΩ

R_FBB

C_VCC

1 µF

GND

图9-1. Example Application Circuit

表9-1. Typical External Component Values⁽¹⁾

NOMINAL C_OUTMINIMUM C_OUT

(RATED (RATED

CAPACITANCE) CAPACITANCE)

V_OUT

(V)

ƒ_SW

(kHz)

L (µH)

C_IN

C_BOOT

C_VCC

R_FBT(Ω)

R_FBB(Ω)

400

2200

400

3.3

5

68

10

82

15

1 x 47 µF

1 × 10 µF

1 x 47 µF

1 × 10 µF

1 x 22 µF

1 x 10 µF

1 × 22 µF

1 x 10 µF

100 k

43.2 k

24.9 k

2.2 µF + 1 × 100 nF

100 nF

1 µF

2200

5

(1) Inductor values are calculated based on typical V_IN= 13.5 V.

9.2.1 Design Requirements

节9.2.2 provides a detailed design procedure based on 表9-2.

表9-2. Detailed Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

13.5 V (6 V to 60 V)

5 V

Output voltage

Maximum output current

Switching frequency

0 A to 0.3 A

2200 kHz

9.2.2 Detailed Design Procedure

The following design procedure applies to 图9-1 and 表9-1.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more

compact design. For this example, 2200 kHz is used.

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9.2.2.2 Setting the Output Voltage

For the fixed output voltage versions, pin 8 (VOUT/BIAS) of the device must be connected directly to the output

voltage node. This output sensing point is normally located near the top of the output capacitor. If the sensing

point is located further away from the output capacitors (that is, remote sensing), then a small 100-nF capacitor

can be needed at the sensing point.

9.2.2.2.1 FB for Adjustable Output

In an adjustable output voltage version, pin 8 of the device is FB. The output voltage of LMR36503-Q1 is

externally adjustable using an external resistor divider network. The divider network is comprised of R_FBTand

R_FBB, and closes the loop between the output voltage and the converter. The converter regulates the output

voltage by holding the voltage on the FB pin equal to the internal reference voltage, V_REF. The resistance of the

divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller values of

resistance reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for R_FBTis

100 kΩ with a maximum value of 1 MΩ. Once R_FBTis selected, 方程式 6 is used to select R_FBB. V_REFis

nominally 1 V. See 节7.5.

R_FBT

R_FBB

=

»

…

ÿ

V_OUT

V_REF

-1

Ÿ

⁄

(6)

For this 5-V example, R_FBT= 100 kΩand R_FBB= 24.9 kΩis chosen.

9.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on

the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the

maximum output current. Experience shows that the best value for inductor ripple current is 30% of the

maximum load current. Note that when selecting the ripple current for applications with much smaller maximum

load than the maximum available from the device, use the maximum device current. 方程式 7 can be used to

determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example,

choose K = 0.4 and find an inductance of L = 11.9 µH. Select the next standard value of L = 15 µH.

(

V

_IN- V_OUT

)

V_OUT

L =

∂

f_SW∂K ∂I_OUTmax

V

IN

(7)

Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, I_SC

(see 节 7.5). This ensures that the inductor does not saturate, even during a short circuit on the output. When

the inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise

very rapidly. Although the valley current limit, I_LIMIT, is designed to reduce the risk of current runaway, a saturated

inductor can cause the current to rise to high values very rapidly. This can lead to component damage. Do not

allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but

usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing

some relaxation in the current rating of the inductor. However, they have more core losses at frequencies above

about 1 MHz. In any case, the inductor saturation current must not be less than the maximum peak inductor

current at full load.

To avoid subharmonic oscillation, the inductance value must not be less than that given in

V_OUT

L_MIN≥ 2.5 x

f_SW

(8)

The maximum inductance is limited by the minimum current ripple for the current mode control to perform

correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device

maximum rated current under nominal conditions.

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9.2.2.4 Output Capacitor Selection

The current mode control scheme of the LMR36503-Q1 devices allows operation over a wide range of output

capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather

than the output voltage ripple. Please refer to 节 9.2 for typical output capacitor value for 3.3-V and 5-V output

voltages. Based on this table, for a 5-V output design, you can choose the recommended 1 × 10-µF ceramic

output capacitor for this example. For other designs with other output voltages, WEBENCH can be used as a

starting point for selecting the value of output capacitor.

In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load

transient testing and bode plots are the best way to validate any given design and must always be completed

before the application goes into production. In addition to the required output capacitance, a small ceramic

placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1

nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.

Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever

is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well

as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load

and loop stability must be performed.

9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple

current and isolating switching noise from other circuits. A minimum ceramic capacitance of 2.2 µF is required on

the input of the LMR36503-Q1. This must be rated for at least the maximum input voltage that the application

requires, preferably twice the maximum input voltage. This capacitance can be increased to help reduce input

voltage ripple and maintain the input voltage during load transients. In addition, a small case size 100-nF

ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency

bypass for the control circuits internal to the device. For this example a 2.2-µF, 100-V, X7R (or better) ceramic

capacitor is chosen. The 100 nF must also be rated at 100 V with an X7R dielectric.

It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially

true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this

capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this

additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate

RMS value of this current can be calculated from 方程式 9 and must be checked against the manufacturers'

maximum ratings.

I_OUT

I_RMS

@

2

(9)

9.2.2.6 C_BOOT

The LMR36503-Q1 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This

capacitor stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic

capacitor of 100 nF and at least 16 V is required.

9.2.2.7 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output

requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this

output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for

the power-good function (see 节 8.3.4). A value in the range of 10 kΩ to 100 kΩ is a good choice in this case.

The nominal output voltage on VCC is 3.2 V; see 节7.5 for limits.

9.2.2.8 C_FFSelection

In some cases, a feedforward capacitor can be used across R_FBTto improve the load transient response or

improve the loop-phase margin. This is especially true when values of R_FBT> 100 kΩ are used. Large values of

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R_FBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes

with the loop stability. A C_FFcan help mitigate this effect. Use 方程式 10 to estimate the value of C_FF. The value

found with 方程式10 is a starting point; use lower values to determine if any advantage is gained by the use of a

C_FFcapacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with

Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.

V_OUT∂C_OUT

C_FF

<

V_REF

V_OUT

120 ∂R_FBT

∂

(10)

9.2.2.8.1 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be

accomplished by using the circuit shown in 图 9-2. The input voltage at which the device turns on is designated

as V_ONwhile the turnoff voltage is V_OFF. First, a value for R_ENBis chosen in the range of 10 kΩto 100 kΩ, then

方程式11 is used to calculate R_ENTand V_OFF

.

VIN

R_ENT

EN

R_ENB

图9-2. Setup for External UVLO Application

≈

∆

«

’

÷

◊

V_ON

÷

R_ENT

=

-1 ∂R_ENB

V_EN-H

≈

’

÷

◊

V_EN-HYS

V_EN

∆

V_OFF= V_ON∂ 1-

∆

«

(11)

where

• V_ONis the V_INturnon voltage.

• V_OFFis the V_INturnoff voltage.

9.2.2.9 Maximum Ambient Temperature

As with any power conversion device, the LMR36503-Q1 dissipates internal power while operating. The effect of

this power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal resistance,

R_θJA, of the device and PCB combination. The maximum junction temperature for the LMR36503-Q1 must be

limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load

current. 方程式 12 shows the relationships between the important parameters. It is easy to see that larger

ambient temperatures (T_A) and larger values of R_θJAreduce the maximum available output current. The

converter efficiency can be estimated by using the curves provided in this data sheet. If the desired operating

conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency.

Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be

measured directly. The correct value of R_θJAis more difficult to estimate. As stated in the Semiconductor and IC

Package Thermal Metrics Application Report, the values given in 节 7.4 are not valid for design purposes and

must not be used to estimate the thermal performance of the application. The values reported in that table were

measured under a specific set of conditions that are rarely obtained in an actual application.

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(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

MAX

(

)

V_OUT

(12)

where

• η= efficiency

The effective R_θJAis a critical parameter and depends on many factors such as the following:

• Power dissipation

• Air temperature/flow

• PCB area

• Copper heat-sink area

• Number of thermal vias under the package

• Adjacent component placement

A typical example of R_θJAversus copper board area can be found in 图 9-3. The copper area given in the graph

is for each layer. For a 4-layer PCB design, the top and bottom layers are 2-oz. copper each, while the inner

layers are 1 oz. For a 2-layer PCB design, the top and bottom layers are 2-oz. copper each. Note that the data

given in these graphs are for illustration purposes only, and the actual performance in any given application

depends on all of the factors mentioned above.

Using the value of R_θJAfrom 图9-3 for a given PCB copper area and Ψ_JTfrom 节7.4, one can approximate the

junction temperature of the IC for a given operating condition using 方程式13

T_J≈T_A+ R_θJAx IC Power Loss

(13)

where

• T_J= IC Junction Temperature (°C)

• T_A= Ambient Temperature (°C)

• R_θJA= Thermal Resistance (°C/W)

• IC Power Loss = Power loss for the IC (W)

The IC Power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC

Resistance. The overall power loss can be approximated from the efficiency curves in the 节 9.2.3 or by using

WEBENCH for a specific operating condition and temperature.

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220

200

180

160

140

120

100

80

2 Layer, 0.5W

4 Layer, 0.5W

60

40

0

1000

2000

3000

4000

5000

6000

PCB Copper Area (mm²)

Rthe

图9-3. R_θJAversus PCB Copper Area for the VQFN (RPE) Package

Use the following resources as guides to optimal thermal PCB design and estimating R_θJAfor a given

application environment:

• Thermal Design by Insight not Hindsight Application Report

• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report

• Semiconductor and IC Package Thermal Metrics Application Report

• Thermal Design Made Simple with LM43603 and LM43602 Application Report

• PowerPAD^™Thermally Enhanced Package Application Report

• PowerPAD^™Made Easy Application Report

• Using New Thermal Metrics Application Report

• PCB Thermal Calculator

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 13.5V, T_A= 25°C. 图 9-25 shows the circuit with the

appropriate BOM in 表9-3

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

10m

100m

1m 10m

Load Current (A)

100m

1m

10m

Load Current (A)

100m

LMR3

LMR36503MSC3 V_OUT= 3.3 V Fixed 2.2 MHz (AUTO)

LMR36503MSC3 V_OUT= 3.3 V Fixed 2.2 MHz (FPWM)

图9-4. Efficiency

图9-5. Efficiency

100

90

80

70

60

50

40

100

90

80

70

60

50

40

30

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

20

10

0

10

0

10m

100m

1m 10m

Load Current (A)

100m

0.001

0.01

Load Current (A)

0.1

0.5

LMR3

LMR36503MSC5

V_OUT= 5 V Fixed

2.2 MHz (AUTO)

LMR36503MSC5

V_OUT= 5 V Fixed

2.2 MHz (FPWM)

图9-6. Efficiency

图9-7. Efficiency

3.35

3.34

3.33

3.32

3.31

3.3

5.06

5.05

5.04

5.03

5.02

5.01

5

V_IN= 8V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

V_IN= 13.5V

V_IN= 24V

V_IN= 48V

3.29

4.99

0

0.05

0.1

0.15

Load Current (A)

0.2

0.25

0.3

0

0.05

0.1

0.15

Load Current (A)

0.2

0.25

0.3

LMR3

LMR36503MSC3 V_OUT= 3.3 V Fixed 2.2 MHz (AUTO)

LMR36503MSC5

V_OUT= 5 V Fixed

2.2 MHz (AUTO)

图9-8. Line and Load Regulation

图9-9. Line and Load Regulation

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3.45

3.3

5.5

5

3.15

3

4.5

4

2.85

2.7

3.5

3

I_OUT= 0A

I_OUT= 0.15A

I_OUT= 0.3A

I_OUT= 0A

I_OUT= 0.15A

I_OUT= 0.3A

2.55

2.4

3

2.5

3.25

3.5

3.75

4

Input Voltage (V)

4.25

4.5

4.75

5

3

3.5

4

4.5

5

5.5

Input Voltage (V)

6

6.5

7

Drop

LMR36503MSC3 V_OUT= 3.3 V Fixed 2.2 MHz (AUTO)

LMR36503MSC5

V_OUT= 5 V Fixed

2.2 MHz (AUTO)

图9-10. Dropout

图9-11. Dropout

AUTO MODE

VOUT (200mV/DIV)

3.3V

VOUT (100mV/DIV)

FPWM MODE

VOUT (200mV/DIV)

3.3V

Load Current (0.2A/DIV)

200µs/DIV

LMR36503MSC3 V_OUT= 3.3 V Fixed

2.2 MHz

LMR36503MSC3 V_OUT= 3.3 V Fixed

2.2 MHz

0.15 A to 0.3 A,1

A/µs

0 A to 0.3 A,1 A/µs

图9-12. Load Transient

图9-13. Load Transient

AUTO MODE

VOUT (200mV/DIV)

5V

FPWM MODE

VOUT (200mV/DIV)

VOUT (100mV/DIV)

5V

Load Current (0.2A/DIV)

200µs/DIV

LMR36503MSC5

0.15 A to 0.3 A,1

A/µs

V_OUT= 5 V Fixed

2.2 MHz

LMR36503MSC5

0 A to 0.3 A,1 A/µs

V_OUT= 5 V Fixed

2.2 MHz

图9-14. Load Transient

图9-15. Load Transient

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VOUT (20mV/DIV)

Inductor Current (200mA/DIV)

5ms/DIV

LMR36503MSC5

V_OUT= 5 V Fixed

No Load

LMR36503MSC3 V_OUT= 3.3 V Fixed

No Load

图9-17. Output Ripple

图9-16. Output Ripple

2250

2000

1750

1500

1250

1000

750

2250

2000

1750

1500

1250

1000

750

500

I_OUT= 0A

I_OUT= 0.3A

I_OUT= 0A

I_OUT= 0.3A

250

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Input Voltage (V)

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Input Voltage (V)

LMR3

LMR36503MSC3 V_OUT= 3.3 V Fixed

2200 kHz

FPWM

LMR36503MSC5

V_OUT= 5 V Fixed

2200 kHz

FPWM

图9-18. Switching Frequency over Input Voltage

图9-19. Switching Frequency over Input Voltage

10000

2500

2250

2000

1750

1500

1250

1000

750

1000

100

10

1

500

3.3V

5V

I_OUT= 0.15A

I_OUT= 0.3A

250

0

0.1

1E-5

0.0001

0.001 0.01

Load Current (A)

0.1

1

3

3.5

4

4.5

5

5.5

Input Voltage (V)

6

6.5

7

7.5

8

Swit

LMR36503MSC3 V_OUT= 3.3 V Fixed

LMR36503MSC5 V_OUT= 5 V Fixed

V_IN= 13.5 V

AUTO

LMR36503MSC5

V_OUT= 5 V Fixed

AUTO

图9-21. Switching Frequency during Dropout

图9-20. Switching Frequency over Load Current

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V_IN= 13.5 V

V_OUT= 5 V

Fsw = 2.2 MHz

Load = 0.3 A

V_IN= 13.5 V

V_OUT= 5 V

Fsw = 2.2 MHz

Load = 0.3 A

图9-22. Typical CISPR 25 Conducted EMI 150kHz - 图9-23. Typical CISPR 25 Conducted EMI 30MHz -

30MHz Yellow: Peak Detect, Blue = Average Detect

108MHz Yellow: Peak Detect, Blue = Average

Detect

Ferrite Bead

LISN +

VIN

+

C_D

1 …F

C_FILT1

C_FILT2

C_IN1

C_BULK

C_IN2

R_D

2 x 0.1 …F

2.2 …F

0.1 …F

22 …F

2.2 …F

4.99Ω

LISN -

GND

Ferrite Bead Part Number:

FBMH3225HM601NT

图9-24. Typical Input EMI Filter for 2.2 MHz

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L

V_OUT

V_IN

VIN

SW

C_IN

C_HF

C_BOOT

0.1 µF

2.2 µF

C_OUT

EN/

UVLO

BOOT

0.1 µF

U1

MODE/

SYNC

MODE

PGOOD

VOUT/

BIAS

VCC

C_VCC

1 µF

GND

图9-25. Schematic for Typical Application Curves

表9-3. BOM for Typical Application Curves

NOMINAL C_OUT

(RATED CAPACITANCE)

U1

V_OUT

L

ƒ_SW

LMR36503MSC3RPERQ1

LMR36503MSC5RPERQ1

2200 kHz

3.3 V

5 V

1 × 10 µF

15 µH. 260 mΩ

1 × 10 µF

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9.3 What to Do and What Not to Do

• Do not exceed the Absolute Maximum Ratings.

• Do not exceed the Recommended Operating Conditions.

• Do not exceed the ESD Ratings.

• Do not allow the EN input to float.

• Do not allow the output voltage to exceed the input voltage, nor go below ground.

• Follow all the guidelines and suggestions found in this data sheet before committing the design to production.

TI application engineers are ready to help critique your design and PCB layout to help make your project a

success.

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with 节 7 found in this data sheet. In addition, the

input supply must be capable of delivering the required input current to the loaded regulator. The average input

current can be estimated with 方程式14.

V_OUT∂I_OUT

I_IN

=

V_IN∂ h

(14)

where

• ηis the efficiency

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input

capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the

regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is

applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the

regulator to momentarily shut down and reset. The best way to solve these kind of issues is to limit the distance

from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the

ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce

any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to

hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple

Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when

designing an input filter for any switching regulator.

In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not

recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the

output voltage of the regulator, the output capacitors discharge through the device back to the input. This

uncontrolled current flow can damage the device.

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11 Layout

11.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout

can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad

PCB layout can mean the difference between a robust design and one that cannot be mass produced.

Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck

converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power

ground, as shown in 图 11-1. This loop carries large transient currents that can cause large transient voltages

when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the

converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible

to reduce the parasitic inductance. 图 11-2 shows a recommended layout for the critical components of the

LMR36503-Q1.

1. Place the input capacitors as close as possible to the VIN and GND terminals.

2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and

routed with short, wide traces to the VCC and GND pins.

3. Use wide traces for the C_BOOTcapacitor. Place C_BOOTclose to the device with short/wide traces to the

BOOT and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.

4. Place the feedback divider as close as possible to the FB pin of the device. Place R_FBB, R_FBT, and C_FF, if

used, physically close to the device. The connections to FB and GND must be short and close to those pins

on the device. The connection to V_OUTcan be somewhat longer. However, the latter trace must not be

routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of

the regulator.

5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat

dissipation path.

6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces

any voltage drops on the input or output paths of the converter and maximizes efficiency.

7. Provide enough PCB area for proper heat-sinking. As stated in 节9.2.2.9, enough copper area must be used

to ensure a low R_θJA, commensurate with the maximum load current and ambient temperature. The top and

bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design

uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer

heat-spreading ground planes.

8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as

possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

See the following PCB layout resources for additional important guidelines:

• Layout Guidelines for Switching Power Supplies Application Report

• Simple Switcher PCB Layout Guidelines Application Report

• Construction Your Power Supply- Layout Considerations Seminar

• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

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VIN

C_IN

SW

GND

图11-1. Current Loops with Fast Edges

11.1.1 Ground and Thermal Considerations

As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground

plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control

circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as

well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the

ground plane contains much less noise; use for sensitive routes.

TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See 图

11-2 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom

layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting

from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout,

provides low current conduction impedance, proper shielding and lower thermal resistance.

11.2 Layout Example

RFBB

CFF

RFBT

CVCC

RENB

RENT

CIN

L1

CIN

COUT

GND

图11-2. Example Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Thermal Design by Insight not Hindsight Application Report

• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

Application Report

• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report

• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report

• Texas Instruments, PowerPAD^™Thermally Enhanced Package Application Report

• Texas Instruments, PowerPAD^™Made Easy Application Report

• Texas Instruments, Using New Thermal Metrics Application Report

• Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report

• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report

• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar

• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

HotRod^™and are trademarks of TI.

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RPE 9

2 x 2, 0.5 mm pitch

VQFN-HR - 1.0 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4227057/A

www.ti.com

PACKAGE OUTLINE

RPE0009A

VQFN-HR - 1.0 mm max height

S

C

A

L

E

6

.

0

PLASTIC QUAD FLATPACK - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

2.1

1.9

0.1 MIN

(0.05)

A

-

A

4

0

.

0

SECTION A-A

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

4X (0.15)

0.55

0.45

(0.2) TYP

0.275

0.175

4X (0.15)

2X

4X

0.1

C A B

C

4

0.05

5

2X 0.738

2X 0.25

0.000 PKG

2X 0.25

A

1.1 0.05

2X 0.738

8

1

9

0.275

0.175

PIN 1 ID

0.6

0.5

4X

2X

0.1

C A B

0.4

0.3

0.05

C

0.45

0.35

4X

4224447/B 01/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RPE0009A

VQFN-HR - 1.0 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (0.75)

2X (0.4)

(0.35)

9

4X (0.225)

1

2X (0.575)

(1.3)

8

2X (0.738)

4X (0.6)

2X (0.25)

0.000 PKG

(0.55)

4X (0.25)

2X (0.25)

SEE SOLDER MASK

DETAILS

(R0.05) TYP

2X (0.738)

5

4

2X (0.575)

2X (0.35)

SYMM

(1.8)

2X (0.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 30X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224447/B 01/2022

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RPE0009A

VQFN-HR - 1.0 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (0.75)

2X

2X (0.55)

9

2X (0.35)

(0.4)

2X (0.5)

4X (0.225)

(0.925)

(0.175)

1

8

2X (0.738)

4X (0.6)

2X (0.25)

4X (0.25)

0.000 PKG

2X (0.25)

(R0.05) TYP

2X (0.738)

5

4

2X (0.575)

SYMM

(1.8)

2X (0.35)

2X (0.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 30X

PADS 1 & 8:

90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PAD 9:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

DWG_NO:5/REV:5 MM_YYYY:5

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	LMR36503RS3QRPERQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 3V 至 65V、0.3A 降压转换器，针对尺寸和轻负载效率进行了优化 \| RPE \| 9 \| -40 to 150 转换器
文件：	总54页 (文件大小：2878K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMR36503RS3QRPERQ1 [TI]

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