LMR36506MSCQRPERQ1_技术文档

LMR36506

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SNVSBB6A – DECEMBER 2019 – REVISED DECEMBER 2020

LMR36506 3-V to 65-V, 0.6-A Ultra-Small Synchronous Buck Converter with 4 µA I_Q

1 Features

3 Description

•

Designed for rugged industrial applications:

– Junction temperature range –40°C to +150°C

– Input transient protection up to 70 V

– Wide input voltage range: 3.0 V (falling

threshold) to 65 V

– Low EMI and minimized switch node ringing

– Adjustable fixed output voltage options

available

The LMR36506 is the industry's smallest 65 V, 0.6 A

synchronous step-down DC/DC converter in 2-mm x

2-mm HotRod^™package. This easy-to-use converter

can handle input voltage transients up to 70 V,

provide excellent EMI performance and support fixed

3.3 V and other adjustable output voltages. The

transient tolerance reduces the necessary design

effort to protect against input overvoltage and meets

the surge immunity requirements of IEC 61000-4-5.

•

Suited for scalable industrial power supplies:

– Pin compatible with LMR36503 (65 V, 300 mA)

– Adjustable switching frequency: 200 kHz to 2.2

MHz with RT pin variant

Minimized solution size and cost:

– Highest power density with internal

compensation and reduced external component

count

The LMR36506 uses the peak current mode control

architecture with internal compensation to maintain

stable operation with minimal output capacitance. The

LMR36506 with the right resistor selection from the

RT pin to ground can be externally programmed to

any desired switching frequency of operation over a

wide range from 200 kHz to 2.2 MHz. The precision

EN/UVLO feature allows precise control of the device

during the start-up and shutdown. The power-good

flag, with built-in glitch filter and delayed release,

offers a true indication of the system status,

eliminating the requirement for an external supervisor.

The compact solution size and rich feature set of

LMR36506 simplifies implementation for a wide range

of industrial applications.

– Ultra-small, 2-mm × 2-mm HotRod^™package

with wettable flanks

High efficiency across load range with low power

dissipation:

– 93% peak efficiency at 400 kHz (12 V_IN, 3.3

V_OUTfixed)

– 90% peak efficiency at 400 kHz (24 V_IN, 3.3

V_OUTfixed)

•

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

Ultra-low operating quiescent current at no load

– 4 µA at 24 V_INto 3.3 V_OUT(fixed output option)

LMR36506

VQFN-HR (9)

2.00 mm × 2.00 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Factory automation: field transmitters and process

sensors

•

Building automation: HVAC and fire safety

Appliances: garden and power tools

100

90

80

70

60

50

BOOT

V_IN

C_IN

VIN

C_BOOT

L_IND

EN/

V_OUT

C_OUT

SW

UVLO

RT

40

VCC

PGOOD

FB

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

30

R_FBT

C_VCC

20

R_FBB

10

GND

0

10m

100m

1m 10m

Load Current (A)

100m

LMR3

Efficiency versus Output Current V_OUT= 5 V (Fix),

1 MHz

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SNVSBB6A – DECEMBER 2019 – REVISED DECEMBER 2020

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings ....................................... 5

7.2 ESD Ratings .............................................................. 5

7.3 Recommended Operating Conditions ........................5

7.4 Thermal Information ...................................................6

7.5 Electrical Characteristics ............................................6

7.6 Timing Characteristics ................................................8

7.7 Switching Characteristics ...........................................8

7.8 System Characteristics .............................................. 8

7.9 Typical Characteristics..............................................10

8 Detailed Description......................................................11

8.1 Overview................................................................... 11

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................13

8.4 Device Functional Modes..........................................22

9 Application and Implementation..................................28

9.1 Application Information............................................. 28

9.2 Typical Application.................................................... 29

9.3 What to Do and What Not to Do............................... 38

10 Power Supply Recommendations..............................38

11 Layout...........................................................................39

11.1 Layout Guidelines................................................... 39

11.2 Layout Example...................................................... 40

12 Device and Documentation Support..........................41

12.1 Documentation Support.......................................... 41

12.2 Receiving Notification of Documentation Updates..41

12.3 Support Resources................................................. 41

12.4 Trademarks.............................................................41

12.5 Electrostatic Discharge Caution..............................41

12.6 Glossary..................................................................41

13 Mechanical, Packaging, and Orderable

Information.................................................................... 42

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (December 2019) to Revision A (December 2020)

Page

•

Changed device status from Advance Information to Production Data.............................................................. 1

Updated the numbering format for tables, figures and cross-references throughout the document...................1

2

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5 Device Comparison Table

ORDERABLE PART

OUTPUT VOLTAGE

EXTERNAL SYNC

F_SW

SPREAD SPECTRUM

NUMBER

No

(Default FPWM at light

load)

Adjustable

with RT resistor

LMR36506RFRPER

Adjustable

3.3-V Fixed

No

Adjustable

with RT resistor

LMR36506R3RPER

LMR36506RF3RPER

(Default PFM at light load)

No

(Default FPWM at light

load)

Adjustable

with RT resistor

No

Adjustable

with RT resistor

LMR36506RRPER

LMR36506R5RPER

Adjustable

5-V Fixed

No

(Default PFM at light load)

No

Adjustable

with RT resistor

(Default PFM at light load)

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6 Pin Configuration and Functions

GND

RT

VOUT/BIAS

VCC

RT

PGOOD

FB

1

2

3

9

8

7

6

1

2

3

9

8

7

6

PGOOD

VCC

BOOT

EN/UVLO

BOOT

EN/UVLO

VIN

SW

VIN

SW

4

5

4

5

Figure 6-1. RPE Package 9-Pin (2 mm x 2 mm) VQFN-HR Top View

Table 6-1. Pin Functions

NAME

I/O

DESCRIPTION

NO.

When part is trimmed as the RT variant, the switching frequency can be adjusted from 200 kHz to

2.2 MHz. Do not float this pin.

1

RT

A

Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting

resistor. High = power OK, low = power bad. It goes low when EN = low. It can be open or

grounded when not used.

2

3

PGOOD

EN/UVLO

A

Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float this

pin.

Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin

and GND.

4

5

6

VIN

SW

P

Regulator switch node. Connect to power inductor.

Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from

this pin to the SW pin.

BOOT

Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads.

Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this

pin to GND.

7

VCC

P

Fixed output options are available with the VOUT/BIAS pin variant. Connect to output voltage node

for fixed VOUT. Check Section 5 for more details.

The FB pin variant can help adjust the output voltage. Connect to tap point of feedback voltage

divider. Do not float this pin.

8

9

VOUT/BIAS or FB

GND

A

G

Power ground terminal. Connect to system ground. Connect to C_INwith short, wide traces.

A = Analog, P = Power, G = Ground

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range⁽¹⁾

PARAMETER

MIN

–0.3

0

MAX

70

UNIT

V

VIN to GND

EN to GND

70

V

SW to GND

PGOOD to GND

70.3

20

V

VOUT/BIAS to GND (Fixed output)

Voltage

–0.3

–40

–65

16

V

FB to GND - (Adjustable output)

16

V

BOOT to SW

5.5

150

V

VCC to GND

V

RT to GND (RT variant)

MODE/SYNC to GND (MODE/SYNC variant)

V

T_J

Junction temperature

Storage temperature

°C

T_stg

(1) Stresses beyond those listed under Section 7.1 may cause permanent damage to the device. These are stress ratings only, which do

not imply functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 . Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

±2000

V

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC

specification JESD22-C101⁽²⁾

±750

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40 °C to 150 °C (unless otherwise noted)^{(1) (2)}

MIN

TYP

MAX

UNIT

Input

voltage

Input voltage range after startup

Load current range⁽³⁾

3.6

65

V

Output

current

0

0.6

2.2

A

Selectable frequency range with RT (RT variant only)

0.2

MHz

Frequency

setting

Set frequency value with RT connected to GND (RT variant only)

Set frequency value with RT connected to VCC (RT variant only)

2.2

1

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For ensured specifications, see Electrical Characteristics table.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125℃

(3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See

Application section for details.

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7.4 Thermal Information

The value of R_θJAgiven in this table is only valid for comparison with other packages and cannot be used for design

purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do

not represent the performance obtained in an actual application. For example, with a 4-layer PCB, a R_θJA= 58℃/W can be

achieved

LMR36506

THERMAL METRIC⁽¹⁾

VQFN (RPE)

9 Pins

84.4

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

47.5

26.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.9

Ψ_JB

25.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report. The value of R_ΘJAgiven in this table is only valid for comparison with other packages and can not be used for design purposes.

This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent the

performance obtained in an actual application. For design information see the Maximum Ambient Temperature section.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

Minimum operating input voltage

(rising)

V_{IN_R}

Rising threshold

3.4

3.0

0.672

17

3.5

V

Minimum operating input voltage

(falling)

V_{IN_F}

Once operating; Falling threshold

2.45

0.25

14

V

Non-switching input current;

measured at VIN pin⁽²⁾

V_IN= V_EN= 13.5V ; V_OUT/BIAS= 5.25V,

V_RT= 0V; Fixed output

I_{Q_13p5_Fixed}

I_{Q_13p5_Adj}

I_{Q_24p0_Fixed}

I_{Q_24p0_Adj}

I_{B_13p5}

1.05

22

µA

Non-switching input current;

measured at VIN pin⁽²⁾

V_IN= V_EN= 13.5V ; V_FB= 1.05V, V_RT

0V; Adjustable output

=

Non-switching input current;

measured at VIN pin(2)

V_IN= V_EN= 24V ; V_OUT/BIAS= 5.25V, V_RT

= 0V; Fixed output

0.8

14

1.2

18

1.7

22

Non-switching input current;

measured at VIN pin⁽²⁾

V_IN= V_EN= 24V ; V_FB= 1.05V, V_RT= 0V;

Adjustable output

Current into VOUT/BIAS pin (not

switching)⁽²⁾

V_IN= 13.5V, V_OUT/BIAS= 5.25V, V_RT= 0V;

Fixed output

14

17

22

Current into VOUT/BIAS pin (not

switching)⁽²⁾

V_IN= 24V, V_OUT/BIAS= 5.25V, V_RT= 0V;

Fixed output

I_{B_24p0}

14

18

22

Shutdown quiescent current;

measured at VIN pin⁽²⁾

I_{SD_13p5}

I_{SD_24p0}

V_EN= 0; V_IN= 13.5V

V_EN= 0; V_IN= 24V

0.5

1

1.1

1.6

Shutdown quiescent current;

measured at VIN pin⁽²⁾

ENABLE (EN PIN)

V_EN-WAKEEnable wake-up threshold

0.4

V

Precision enable high level for

VOUT

V_EN-VOUT

1.16

1.263

1.36

Enable threshold hysteresis below

V_{EN- VOUT}

V_EN-HYST

0.3

0.35

0.3

0.4

8

V

I_LKG-EN

Enable input leakage current

VEN = 3.3 V

nA

INTERNAL LDO

6

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Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

3.15

65

MAX

3.22

240

UNIT

V_CC

Internal VCC voltage

Bias regulator current limit

Adjustable or fixed output; Auto mode

3.125

V

I_CC

mA

V

V_CC-UVLO

Internal VCC undervoltage lockout VCC rising under voltage threshold

3

3.3

3.65

Internal VCC under voltage lock-

Hysteresis below V_CC-UVLO

out hysteresis

V_CC-UVLO-HYST

0.4

0.8

1.2

V

CURRENT LIMITS

Short circuit high side current

I_SC-0p3

0.3A Version

0.42

0.3

0.5

0.35

0.09

0.575

0.4

A

Limit⁽³⁾

I_LS-LIMIT-0p3

I_PEAK-MIN-0p3

Low side current limit⁽³⁾

PFM Operation, 0.3A Version; Duty

Factor = 0

Minimum peak inductor current⁽³⁾

0.067

0.11

Short circuit high side current

Limit⁽³⁾

I_SC-0p6

0.87

1

1.11

A

I_LS-LIMIT-0p6

I_PEAK-MIN-0p6

I_ZC

Low side current limit⁽³⁾

0.6

0.127

0

0.7

0.19

0.01

0.7

0.752

0.227

0.022

0.8

A

Minimum Peak Inductor Current⁽³⁾Auto Mode, duty factor = 0

Zero cross current⁽³⁾

Auto mode

I_L-NEG

Sink current limit (negative)⁽³⁾

FPWM mode

0.6

POWER GOOD

% of FB (Adjustable output) or % of

VOUT/BIAS (Fixed output)

PG-OV

PGOOD upper threshold - rising

PGOOD lower threshold - falling

PGOOD hysteresis - rising/falling

106

93

107

94

1.8

1

110

96.5

2.3

2

%

V

% of FB (Adjustable output) or % of

VOUT/BIAS (Fixed output)

PG-UV

% of FB (Adjustable output) or % of

VOUT/BIAS (Fixed output)

PG-HYS

V_PG-VALID

1.3

Minimum input voltage for proper

PG function

0.75

R_PG-EN5p0

R_PG-EN0

R_DS(ON)PGOOD output

VEN = 5.0V, 1mA pull-up current

VEN = 0 V, 1mA pull-up current

20

10

40

18

70

31

Ω

MOSFETS

R_DS-ON-HS

R_DS-ON-LS

V_CBOOT-UVLO

High-side MOSFET on-resistance Load = 0.3 A

560

280

2.3

920

460

mΩ

V

Low-side MOSFET on-resistance

Cboot - SW UVLO threshold⁽⁴⁾

Load = 0.3 A

2.14

3.25

2.42

VOLTAGE REFERENCE

Initial VOUT voltage accuracy for

V_{OUT_Fixed3p3}

FPWM mode

3.3

5

3.34

5.07

V

3.3 V

Initial VOUT voltage accuracy for 5

V

V_{OUT_Fixed5p0}

4.93

V_REF

I_FB

Internal reference voltage

FB input current

V_IN= 3.6V to 65V, FPWM mode

Adjustable output, FB = 1V

0.985

1

1.01

110

V

85

nA

(1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.

(4) When the voltage across the C_BOOTcapacitor falls below this voltage, the low side MOSFET is turn to recharge the boot capacitor

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7.6 Timing Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOFT START

Time from first SW pulse to V_FBat

90%, of V_REF

t_SS

V_IN≥ 3.6 V

1.95

2.58

3.2

ms

POWER GOOD

Glitch filter time constant for PG

t_{RESET_FILTER}

15

25

40

µs

function

t_{PGOOD_ACT}

Delay time to PG high signal

1.7

1.956

2.16

ms

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated.

Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 24 V.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PWM LIMITS (SW)

t_ON-MIN

t_OFF-MIN

t_ON-MAX

Minimum switch on-time

Minimum switch off-time

Maximum switch on-time

VIN =24 V, I_OUT= 0.6 A

40

57

58

9

80

77

ns

µs

HS timeout in dropout

7.6

9.8

OSCILLATOR (RT)

f_{OSC_2p2MHz}

f_{OSC_1p0MHz}

f_{ADJ_400kHz}

Internal oscillator frequency

RT = GND

RT = VCC

2.1

0.93

0.34

2.2

1

2.3

1.05

0.46

MHz

RT = 39.2 kΩ

0.4

(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation

usingStatistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

7.8 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 150°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STANDBY CURRENT AND DUTY RATIO

Input supply current when in

regulation

V_IN= 13.5 V, V_OUT/BIAS= 3.3 V, I_OUT

0 A, PFM mode

=

I_SUPPLY

6.5

µA

Input supply current when in

regulation

V_IN= 24 V, V_OUT/BIAS= 3.3 V, I_OUT= 0

A, PFM mode

I_SUPPLY

4

D_MAX

Maximum switch duty cycle⁽¹⁾

98%

OUTPUT VOLTAGE ACCURACY (VOUT/BIAS)

V_OUT= 3.3 V, V_IN= 3.6 V to 65 V,

V_{OUT_3p3V_ACC}

FPWM mode

Auto mode

–1.5

1.5

2.5

%

I_OUT= 0 to full load⁽²⁾

V_OUT= 3.3 V, V_IN= 3.6V to 65 V,

V_{OUT_3p3V_ACC}

I_OUT= 0 A to full load⁽²⁾

THERMAL SHUTDOWN

8

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The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the

typical (TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the

case of typical components over the temperature range of T_J= –40°C to 150°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

Shutdown threshold

Recovery threshold

MIN

158

150

8

TYP

168

158

10

MAX

180

165

15

UNIT

T_SD-R

Thermal shutdown rising

Thermal shutdown falling

Thermal shutdown hysteresis

°C

T_SD-F

°C

T_SD-HYS

°C

(1) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: f_MIN

1 / (t_ON-MAX+ T_OFF-MIN). D_MAX= t_ON-MAX/(t_ON-MAX+ t_OFF-MIN).

=

(2) Deviation is with respect to V_IN=13.5 V

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7.9 Typical Characteristics

Unless otherwise specified, the following conditions apply: T_A= 25°C, V_IN= 13.5 V.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

1m

10m

100m

1

10m

100m

1m 10m

Load Current (A)

100m

1

Load Current (A)

LMR3

V_OUT= 3.3 V Fixed

F_SW= 1 MHz (FPWM)

V_OUT= 3.3 V Fixed

F_SW= 1 MHz (Auto)

Figure 7-1. Efficiency 3.3-V Output, FPWM

Figure 7-2. Efficiency 3.3-V Output, Auto Mode

100

90

80

70

60

50

100

90

80

70

60

50

40

V_IN= 12V

V_IN= 24V

V_IN= 12V

V_IN= 24V

30

V_IN= 36V

V_IN= 48V

V_IN= 54V

V_IN= 36V

V_IN= 48V

V_IN= 54V

20

10

0

10m

100m

1m 10m

Load Current (A)

100m

10m

100m

1m 10m

Load Current (A)

100m

1

LMR3

V_OUT= 5 V Fixed

F_SW-NOM= 1 MHz (Auto)

V_OUT= 5 V Fixed

F_SW-NOM= 400 kHz (Auto)

Figure 7-4. Efficiency 5-V Output, Auto Mode

Figure 7-3. Efficiency 5-V Output, Auto Mode

18

3.3V

5V

16

14

12

10

8

VOUT (1V/DIV)

6

4

VIN (1V/DIV)

IOUT (200mA/DIV)

2

5

10 15 20 25 30 35 40 45 50 55 60 65

Input Voltage (V)

Inpu

50ms/DIV

Figure 7-5. Typical Input Supply Current at No

Load for Fixed 3.3-V and 5-V Output

Figure 7-6. Typical Start-up and Shutdown at V_OUT

= 5 V

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8 Detailed Description

8.1 Overview

The LMR36506 is a wide input, low-quiescent current, high-performance regulator that can operate over a wide

range of duty ratio and the switching frequencies, including sub-AM band at 400 kHz and above AM band at 2.2

MHz. During wide input transients, if the minimum ON-time or the minimum OFF-time cannot support the desired

duty ratio at the higher switching frequency settings, the switching frequency is reduced automatically, allowing

the LMR36506 to maintain the output voltage regulation. With an internally-compensated design optimized for

minimal output capacitors, the system design process with the LMR36506 is simplified significantly compared to

other buck regulators available in the market.

The LMR36506 is designed to minimize external component cost and solution size while operating in all

demanding industrial environments. The LMR36506 family includes variants that can be set-up to operate over a

wide switching frequency range, from 200 kHz to 2.2 MHz, with the correct resistor selection from RT pin to

ground. To further reduce system cost, the PGOOD output feature with built-in delayed release allows the

elimination of the reset supervisor in many applications.

The LMR36506 comes in an ultra-small 2-mm x 2-mm QFN package with wettable flanks allowing for quick

optical inspection along with specially designed corner anchor pins for reliable board level solder connections.

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8.2 Functional Block Diagram

VCC

FIXED

OUTPUT

VOLTAGE

VARIANTS

ONLY

CLOCK

SLOPE

VOUT/

BIAS

RT

OSCILLATOR

COMPENSATION

LDO

VCC UVLO

TSD

VIN

THERMAL

SHUTDOWN

F_SWFOLDBACK

BOOT

SYS ENABLE

ENABLE

EN

HS

CURRENT

SENSE

VIN

ADJ. OUTPUT

VOLTAGE

VARIANTS ONLY

ERROR

+

œ

AMPLFIER

COMP

FB

TSD

œ

VOUT/

BIAS

+

MAX. &

MIN.

CLOCK

LIMITS

+

HS

FIXED OUTPUT

œ

SW

VOLTAGE

VARIANTS

ONLY

CURRENT

SYS ENABLE

LMIT

CONTROL

LOGIC &

DRIVER

SOFT-

START

&

TSD

GND

VREF

LS

BANDGAP

VCC UVLO

CURRENT

LMIT

œ

FIXED OUTPUT

VOLTAGE

ADJ. OUTPUT

+

VOLTAGE

VARIANTS

VARIANTS ONLY

ONLY

œ

VOUT/

MIN.

LS CURRENT

LIMIT

FB

BIAS

GND

+

PGOOD

FPWM or AUTO

VOUT UV/OV

PGOOD

LOGIC

LS

CURRENT

SENSE

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8.3 Feature Description

8.3.1 Enable, Start-up, and Shutdown

Voltage at the EN pin controls the start-up or remote shutdown of the LMR36506 family of devices. The part

stays shut down as long as the EN pin voltage is less than V_EN-WAKE= 0.4 V. During the shutdown, the input

current drawn by the device typically drops down to 0.5 µA (VIN = 13.5 V). With the voltage at the EN pin greater

than the V_EN-WAKE, the device enters the device standby mode, the internal LDO powers up to generate VCC. As

the EN voltage increases further, approaching V_EN-VOUT, the device finally starts to switch, entering the start-up

mode, with a soft start. During the device shutdown process, when the EN input voltage measures less than

(V_EN-VOUT– V_EN-HYST), the regulator stops switching and re-enters the device standby mode. Any further

decrease in the EN pin voltage, below V_EN-WAKE, the device is then firmly shut down. The high-voltage compliant

EN input pin can be connected directly to the VIN input pin if remote precision control is not needed. The EN

input pin must not be allowed to float. The various EN threshold parameters and their values are listed in Section

7.5. Figure 8-2 shows the precision enable behavior. Figure 8-3 shows a typical remote EN start-up waveform in

an application. Once EN goes high, after a delay of about 1 ms, the output voltage begins to rise with a soft start

and reaches close to the final value in about 2.67 ms (t_ss). After a delay of about 2 ms (t_{PGOOD_ACT}), the PGOOD

flag goes high. During start-up, the device is not allowed to enter FPWM mode until the soft-start time has

elapsed. This time is measured from the rising edge of EN. Check Section 9.2.2.8.1 for component selection.

V_IN

R_ENT

EN

R_ENB

AGND

Figure 8-1. VIN UVLO Using the EN pin

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EN

V_EN-VOUT

V_EN-HYST

V_EN-WAKE

VCC

3.3V

0

VOUT

V_OUT

0

Figure 8-2. Precision Enable Behavior

VIN (5V/DIV)

VOUT (5V/DIV)

EN (2V/DIV)

PGOOD (5V/DIV)

IOUT (1A/DIV)

1ms/DIV

Figure 8-3. Enable Start-up V_IN= 12 V, V_OUT= 5 V, I_OUT= 600 mA

8.3.2 Adjustable Switching Frequency (with RT)

The select variants in the LMR36506 family with the RT pin allow the power designers to set any desired

operating frequency between 200 kHz and 2.2 MHz in their applications. See Figure 8-4 to determine the resistor

value needed for the desired switching frequency. See Table 8-1 for selection on programming the RT pin.

Table 8-1. RT Pin Setting

RT INPUT

VCC

SWITCHING FREQUENCY

1 MHz

GND

2.2 MHz

RT to GND

Adjustable according to Figure 8-4

No Switching

Float (Not Recommended)

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Equation 1 can be used to calculate the value of RT for a desired frequency.

18286

RT =

Fsw^1.021

(1)

where

•

RT is the frequency setting resistor value (kΩ).

F_SWis the switching frequency (kHz).

80

70

60

50

40

30

20

10

0

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

Switching Frequency (kHz)

RTvs

Figure 8-4. RT Values vs Frequency

8.3.3 Power-Good Output Operation

The power-good feature using the PG pin of the LMR36506 can be used to reset a system microprocessor

whenever the output voltage is out of regulation. This open-drain output remains low under device fault

conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents

false flag operation for any short duration excursions in the output voltage, such as during line and load

transients. Output voltage excursions lasting less than t_{RESET_FILTER}do not trip the power-good flag. Power-good

operation can best be understood in reference to Figure 8-5. Table 8-2 gives a more detailed breakdown the

PGOOD operation. Here, V_PG-UVis defined as the PG-UV scaled version of the V_OUT-Reg(target regulated output

voltage) and V_PG-HYSas the PG-HYS scaled version of the V_OUT-Reg, where both PG-UV and PG-HYS are listed

in Section 7.5. During the initial power up, a total delay of 5 ms (typ.) is encountered from the time the V_EN-VOUT

is triggered to the time that the power-good is flagged high. This delay only occurs during the device start-up and

is not encountered during any other normal operation of the power-good function. When EN is pulled low, the

power-good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage

(V_PG-VALIDis ≥ 1 V (typical).

The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup

resistor connected to a suitable logic supply. It can also be pulled up to either V_CCor V_OUTthrough an

appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit

the current into this pin to ≤ 4 mA.

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Output

Voltage

Input

Voltage

Input Voltage

t_{RESET_FILTER}

t_{PGOOD_ACT}

t_{RESET_FILTER}

V_PG-HYS

t_{RESET_FILTER}

V_PG-UV(falling)

V_{IN_R}(rising)

V_{IN_F}(falling)

V_{PG_VALID}

GND

VOUT

PGOOD

Small glitches

do not cause

reset to signal

a fault

PGOOD may

not be valid if

input is below

V_PG-VALID

Small glitches do not

reset t_{PGOOD_ACT}timer

PGOOD may not

be valid if input is

below V_PG-VALID

Startup

delay

Figure 8-5. Power-Good Operation (OV Events Not Included)

Table 8-2. Fault Conditions for PGOOD (Pull Low)

FAULT CONDITION ENDS (AFTER WHICH t_{PGOOD_ACT}MUST PASS

BEFORE PGOOD OUTPUT IS RELEASED)

FAULT CONDITION INITIATED

Output voltage in regulation:

V_PG-UV+ V_PG-HYS< V_OUT< V_PG-OV- V_PG-HYS

V_OUT< V_PG-UVAND t > t_{RESET_FILTER}

V_OUT> V_PG-OVAND t > t_{RESET_FILTER}

T_J> T_SD-R

EN < V_EN-VOUT- V_EN-HYST

V_CC< V_CC-UVLO- V_CC-UVLO-HYST

Output voltage in regulation

T_J< T_SD-FAND output voltage in regulation

EN > V_EN-VOUTAND output voltage in regulation

V_CC> V_CC-UVLOAND output voltage in regulation

8.3.4 Internal LDO, VCC UVLO, and VOUT/BIAS Input

The LMR36506 uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin draws

power either from the VIN (in adjustable output variants) or the VOUT/BIAS (in fixed-output variants). In the fixed

output variants, once the LMR36506 is active but has yet to regulate, the VCC rail will continue to draw power

from the input voltage, VIN, until the VOUT/BIAS voltage reaches > 3.15 V (or when the device has reached

steady-state regulation post the soft start). The VCC rail typically measures 3.15 V in both adjustable and fixed

output variants. To prevent unsafe operation, VCC has an undervoltage lockout, which prevents switching if the

internal voltage is too low. See V_VCC-UVLOand V_{VCC-UVLO-HYST}in Section 7.5. During start-up, VCC momentarily

exceeds the normal operating voltage until V_VCC-UVLOis exceeded, then drops to the normal operating voltage.

Note that these undervoltage lockout values, when combined with the LDO dropout, drives the minimum input

voltage rising and falling thresholds.

8.3.5 Bootstrap Voltage and V_CBOOT-UVLO(CBOOT Terminal)

The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned ON.

The capacitor connected between CBOOT and SW works as a charge pump to boost voltage on the CBOOT

terminal to (SW+VCC). The boot diode is integrated on the LMR36506 die to minimize physical solution size. A

100-nF capacitor rated for 10 V or higher is recommended for CBOOT. The CBOOT rail has an UVLO setting.

This UVLO has a threshold of V_CBOOT-UVLOand is typically set at 2.3 V. If the CBOOT capacitor is not charged

above this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-

side switch before attempting to turn on the high-side device.

8.3.6 Output Voltage Selection

In the LMR36506 family, select variants with an adjustable output voltage option (see Section 5), and you need

an external resistor divider connection between the output voltage node, the device FB pin, and the system

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GND, as shown in Figure 8-6. The variants with adjustable output voltage option in the LMR36506 family are

designed with a 1-V internal reference voltage.

R_FBT

R_FBB

=

V_OUTÅ 1

(2)

When using the fixed-output variants from the LMR36506 family, simply connect the FB pin (will be identified as

VOUT/BIAS pin for fixed-output variants in the rest of the data sheet) to the system output voltage node. See

Section 5 for more details.

V_OUT

R_FBT

FB

R_FBB

AGND

Figure 8-6. Setting Output Voltage for Adjustable Output Variant

In adjustable output voltage variants, an addition feed-forward capacitor, C_FF, in parallel with the R_FBT, can be

used to optimize the phase margin and transient response. See Section 9.2.2.8 for more details. No additional

resistor divider or feed-forward capacitor, C_FF, is needed in fixed-output variants.

8.3.7 Soft Start and Recovery from Dropout

When designing with the LMR36506, slow rise in output voltage due to recovery from dropout and soft start

should be considered as a two separate operating conditions, as shown in Figure 8-7 and Figure 8-8. Soft start

is triggered by any of the following conditions:

•

Power is applied to the VIN pin of the device, releasing undervoltage lockout.

EN is used to turn on the device.

Recovery from shutdown due to overtemperature protection.

Once soft start is triggered, the IC takes the following actions:

•

The reference used by the IC to regulate output voltage is slowly ramped up. The net result is that output

voltage, if previously 0 V, takes t_SSto reach 90% of the desired value.

•

Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side

MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already

present at the output during a pre-bias start-up.

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If selected, FPWM

Triggering event

is enabled only

after completion of

t_SS

is enabled only

after completion of

t_SS

t_EN

t_SS

t_EN

t_SS

V

V_EN

V_OUTSet

Point

V_OUTSet

Point

V_OUT

90% of

V_OUTSet

Point

90% of

V_OUTSet

Point

t

0 V

Time

Figure 8-7. Soft Start With and Without Pre-bias Voltage

8.3.7.1 Recovery from Dropout

Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called

graceful recovery from dropout in this document, differs from soft start in two important ways:

•

The reference voltage is set to approximately 1% above what is needed to achieve the existing output

voltage.

•

If the device is set to FPWM, it will continue to operate in that mode during its recovery from dropout. If output

voltage were to suddenly be pulled up by an external supply, the LMR36506 can pull down on the output.

Note that all protections that are present during normal operation are in place, preventing any catastrophic

failure if output is shorted to a high voltage or ground.

V

Load

current

V_OUTSet

Point

and max

output

Slope

V_OUT

the same

as during

soft start

current

t

Time

Figure 8-8. Recovery from Dropout

VIN (2V/DIV)

8V

5V

4V

VOUT (2V/DIV)

Load Current (0.2A/DIV)

500µs/DIV

Figure 8-9. Typical Output Recovery from Dropout from 8 V to 4 V

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Whether output voltage falls due to high load or low input voltage, once the condition that causes output to fall

below its set point is removed, the output climbs at the same speed as during start-up. shows an example of this

behavior.

8.3.8 Current Limit and Short Circuit

The LMR36506 is protected from overcurrent conditions by cycle-by-cycle current limiting on both high-side and

low-side MOSFETs.

High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The

HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is

compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop

minus the slope compensation every switching cycle. Since the output of the internal error amplifier loop has a

maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased

duty factor if duty factor is typically above 35%.

When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side

device, the low-side device has a turnoff commanded by the internal error amplifier loop. In the case of the low-

side device, turnoff is prevented if the current exceeds this value, even if the oscillator normally starts a new

switching cycle. Also like the high-side device, there is a limit on how high the turnoff current is allowed to be.

This is called the low-side current limit, I_LS-LIMIT(or I_L-LSin Figure 8-10). If the LS current limit is exceeded, the

LS MOSFET stays on and the HS switch is not to be turned on. The LS switch is turned off once the LS current

falls below this limit and the HS switch is turned on again as long as at least one clock period has passed since

the last time the HS device has turned on.

V_SW

V_IN

t_ON< t_{ON_MAX}

0

t

Typically, t_SW> Clock setting

i_L

I_L-HS

I_L-LS

I_OUT

t

0

Figure 8-10. Current Limit Waveforms

Since the current waveform assumes values between I_SC(or I_L-HSin Figure 8-10) and I_LS-LIMIT, the maximum

output current is very close to the average of these two values unless duty factor is very high. Once operating in

current limit, hysteretic control is used and current does not increase as output voltage approaches zero.

If duty factor is very high, current ripple must be very low in order to prevent instability. Since current ripple is

low, the part is able to deliver full current. The current delivered is very close to I_LS-LIMIT

.

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V_OUT

I_L-LS

I_OUTrated

I_L-HS

V_OUTSetting

V_IN> 2 ‡ V_OUTSetting

V_IN~ V_OUTSetting

I_OUT

0

Output Current

Figure 8-11. Output Voltage versus Output Current

Under most conditions, current is limited to the average of I_L-HSand I_L-LS, which is approximately 1.3 times the

maximum-rated current. If input voltage is low, current can be limited to approximately I_L-LS. Also note that the

maximum output current does not exceed the average of I_L-HSand I_L-LS. Once the overload is removed, the part

recovers as though in soft start.

VOUT (2V/DIV)

5V

Short Removed

Short Applied

VOUT (5V/DIV)

0V

Inductor Current (0.5A/DIV)

750mA

Load Current (0.2A/DIV)

100mA

10ms/DIV

2ms/DIV

Figure 8-12. Short Circuit Waveform

Figure 8-13. Overload Output Recovery (100 mA to

750 mA)

8.3.9 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction

temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal

shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to

approximately 158°C (typical). When the junction temperature falls below 158°C (typical), the LMR36506

attempts another soft start.

While the LMR36506 is shut down due to high junction temperature, power continues to be provided to VCC. To

prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced

current limit while the part is disabled due to high junction temperature. The LDO only provides a few

milliamperes during thermal shutdown.

8.3.10 Input Supply Current

The LMR36506 is designed to have very low input supply current when regulating light loads. This is achieved

by powering much of the internal circuitry from the output. The VOUT/BIAS pin in the fixed-output voltage

variants is the input to the LDO that powers the majority of the control circuits. By connecting the VOUT/BIAS

input pin to the output node of the regulator, a small amount of current is drawn from the output. This current is

reduced at the input by the ratio of V_OUT/ V_IN.

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V_OUT

x V_IN

I_{Q_VIN}= I_Q+ I_EN+ I_BIAS

¾

eff

(3)

where

•

I_{Q_VIN}is the total standby (switching) current consumed by the operating (switching) buck converter when

unloaded.

•

I_Qis the current drawn from the V_INterminal. Check I_{Q_13p5_Fixed}or I_{Q_24p0_Fixed}in Section 7.5 for I_Q.

I_ENis current drawn by the EN terminal. Include this current if EN is connected to VIN. Check I_LKG-ENin

Section 7.5 for I_EN

.

•

I_BIASis bias current drawn by the BIAS input. Check I_{B_13p5}or I_{B_24p0}in Section 7.5 for I_BIAS

.

η_effis the light-load efficiency of the buck converter with I_{Q_VIN}removed from the input current of the buck

converter. η_eff= 0.8 is a conservative value that can be used under normal operating conditions. This can be

traced back as the I_SUPPLYin Section 7.7.

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8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.4 V, both

the converter and the internal LDO have no output voltage and the part is in shutdown mode. In shutdown mode,

the quiescent current drops to typically 0.5 µA.

8.4.2 Standby Mode

The internal LDO has a lower EN threshold than the output of the converter. When the EN pin voltage is above

1.1 V (maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the

VCC voltage at 3.3 V typical. The precision enable circuitry is ON once VCC is above its UVLO. The internal

power MOSFETs of the SW node remain off unless the voltage on EN pin goes above its precision enable

threshold. The LMR36506 also employs UVLO protection. If the VCC voltage is below its UVLO level, the output

of the converter is turned off.

8.4.3 Active Mode

The LMR36506 is in active mode whenever the EN pin is above V_EN-VOUT, V_INis high enough to satisfy V_{IN_R}

and no other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to

V_IN, which allows self start-up when the applied input voltage exceeds the minimum V_{IN_R}

,

.

In active mode, depending on the load current, input voltage, and output voltage, the LMR36506 is in one of five

modes:

•

Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the

inductor current ripple

•

Auto Mode - Light Load Operation: PFM when switching frequency is decreased at very light load

FPWM Mode - Light Load Operation: Discontinuous conduction mode (DCM) when the load current is lower

than half of the inductor current ripple

•

Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to

maintain regulation.

Dropout mode: When switching frequency is reduced to minimize voltage dropout.

8.4.3.1 CCM Mode

The following operating description of the LMR36506 refers to Section 8.2 and to the waveforms in Figure 8-14.

In CCM, the LMR36506 supplies a regulated output voltage by turning on the internal high-side (HS) and low-

side (LS) switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, V_SW, swings

up to approximately V_IN, and the inductor current, i_L, increases with a linear slope. The HS switch is turned off by

the control logic. During the HS switch off-time, t_OFF, the LS switch is turned on. Inductor current discharges

through the LS switch, which forces the V_SWto swing below ground by the voltage drop across the LS switch.

The converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on-time of

the HS switch over the switching period:

D = T_ON/ T_SW

(4)

In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inversely

proportional to the input voltage:

D = V_OUT/ V_IN

(5)

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

V_IN

t_OFF

t_ON

0

t

- I_OUT‡R_DSLS

t_SW

i_L

I_LPK

I_OUT

I_ripple

t

0

Figure 8-14. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

8.4.3.2 Auto Mode - Light Load Operation

The LMR36506 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows

for seamless transition between normal current mode operation while heavily loaded and highly efficient light

load operation. The other behavior, called FPWM Mode, maintains full frequency even when unloaded. Which

mode the LMR36506 operates in depends on which variant from this family is selected. Note that all parts

operate in FPWM mode when synchronizing frequency to an external signal.

The light load operation is employed in the LMR36506 only in the auto mode. The light load operation employs

two techniques to improve efficiency:

•

Diode emulation, which allows DCM operation. See Figure 8-15.

Frequency reduction. See Figure 8-16.

Note that while these two features operate together to improve light load efficiency, they operate independent of

each other.

8.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to

regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced.

With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to

maintain regulation.

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t_ON

V_OUT

V_IN

D =

V_SW

<

t_SW

V_IN

t_OFF

t_ON

t_HIGHZ

0

t

t_SW

i_L

I_LPK

I_OUT

0

t

In auto mode, the low-side device is turned off once SW node current is near zero. As a result, once output current is less than half of

what inductor ripple would be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.

Figure 8-15. PFM Operation

The LMR36506 has a minimum peak inductor current setting (I_LPK(see I_PEAK-MINin Section 7.5) while in auto

mode. Once current is reduced to a low value with fixed input voltage, on-time is constant. Regulation is then

achieved by adjusting frequency. This mode of operation is called PFM mode regulation.

8.4.3.2.2 Frequency Reduction

The LMR36506 reduces frequency whenever output voltage is high. This function is enabled whenever the

internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the

regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance

while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when

the part is completely unloaded.

V_OUT

Current

Limit

1% Above

Set point

V_OUTSet

Point

I_OUT

Output Current

0

In auto mode, once output current drops below approximately 1/10th the rated current of the part, output resistance increases so that

output voltage is 1% high while the buck is completely unloaded.

Figure 8-16. Steady State Output Voltage versus Output Current in Auto Mode

In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The

lower the frequency in PFM, the more DC offset is needed on V_OUT. If the DC offset on V_OUTis not acceptable, a

dummy load at V_OUTor FPWM Mode can be used to reduce or eliminate this offset.

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8.4.3.3 FPWM Mode - Light Load Operation

In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is

allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see Section 7.5

for reverse current limit values.

V_SW

t_ON

V_OUT

V_IN

D =

≈

t_SW

V_IN

t_OFF

t_ON

0

t

t_SW

i_L

I_LPK

I_OUT

0

I_ripple

t

In FPWM mode, Continuous Conduction (CCM) is possible even if I_OUTis less than half of I_ripple

.

Figure 8-17. FPWM Mode Operation

For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to

command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output

being pulled up.

8.4.3.4 Minimum On-time (High Input Voltage) Operation

The LMR36506 continues to regulate output voltage even if the input-to-output voltage ratio requires an on-time

less than the minimum on-time of the chip with a given clock setting. This is accomplished using valley current

control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum

valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley

current falls below that determined by the compensation circuit. If the converter is not operating in current limit,

the maximum valley current is set above the peak inductor current, preventing valley control from being used

unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high, such

that the inductor current peak value exceeds the peak command dictated by compensation, the high-side device

cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit reduces

both peak and valley current. Once a low enough current is selected by the compensation circuit, valley current

matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept

on and the next clock cycle is prevented from starting until inductor current drops below the desired valley

current. Since on-time is fixed at its minimum value, this type of operation resembles that of a device using a

Constant On-Time (COT) control scheme; see Figure 8-18.

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

V_IN

t_ON= t_{ON_MIN}

t_OFF

0

t

- I_OUT‡R_DSLS

t_SW> Clock setting

i_L

I_OUT

I_ripple

I_LVLY

t

0

In valley control mode, minimum inductor current is regulated, not peak inductor current.

Figure 8-18. Valley Current Mode Operation

8.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the

required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. Once this limit is

reached as shown in Figure 8-20 if clock frequency was to be maintained, the output voltage would fall. Instead

of allowing the output voltage to drop, the LMR36506 extends the high side switch on-time past the end of the

clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle once

peak inductor current is achieved or once a pre-determined maximum on-time, t_ON-MAX, of approximately 9 µs

passes. As a result, once the needed duty cycle cannot be achieved at the selected clock frequency due to the

existence of a minimum off-time, frequency drops to maintain regulation. As shown in Figure 8-19 if input voltage

is low enough so that output voltage cannot be regulated even with an on-time of t_ON-MAX, output voltage drops

to slightly below the input voltage by V_DROP. For additional information on recovery from dropout, refer back to

Figure 8-8.

Input

Voltage

V_OUT

V_DROP

Output

Voltage

Output

Setting

V_IN

0

Input Voltage

F_SW

F_SW-NOM

~110kHz

0

V_IN

Input Voltage

Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC

reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz, input

voltage tracks output voltage.

Figure 8-19. Frequency and Output Voltage in Dropout

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t_ON

V_OUT

V_IN

V_SW

D =

≈

t_SW

t_OFF= t_{OFF_MIN}

V_IN

t_ON< t_{ON_MAX}

0

t

- I_OUT‡R_DSLS

t_SW> Clock setting

i_L

I_LPK

I_OUT

I_ripple

t

0

Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,

frequency drops. This frequency drop is limited by t_ON-MAX

.

Figure 8-20. Dropout Waveforms

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LMR36506 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC

voltage with a maximum output current of 0.6 A. The following design procedure can be used to select

components for the LMR36506.

Note

All of the capacitance values given in the following application information refer to effective values

unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and

temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with

an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage

coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance

drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help

mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective

capacitance up to the required value. This can also ease the RMS current requirements on a single

capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to

ensure that the minimum value of effective capacitance is provided.

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9.2 Typical Application

Figure 9-1 shows a typical application circuit for the LMR36506. This device is designed to function over a wide

range of external components and system parameters. However, the internal compensation is optimized for a

certain range of external inductance and output capacitance. As a quick-start guide, Table 9-1 provides typical

component values for a range of the most common output voltages.

L

V_OUT

V_IN

SW

VIN

EN

C_IN

C_HF

C_BOOT

100 nF

2.2 µF

C_OUT

BOOT

0.1 µF

LMR36506

C_FF

R_FBT

RT

PG

FB

100 kΩ

VCC

R_FBB

C_VCC

1 µF

GND

Figure 9-1. Example Application Circuit

Table 9-1. Typical External Component Values ⁽¹⁾

NOMINAL C_OUTMINIMUM C_OUT

(RATED (RATED

CAPACITANCE) CAPACITANCE)

ƒ_SW

(kHz)

V_OUT

(V)

L (µH)

R_FBT(Ω)

R_FBB(Ω)

C_IN

C_BOOT

C_VCC

400

1000

400

3.3

5

33

15

47

22

1 x 47 µF

2 x 22 µF

1 x 47 µF

2 x 22 µF

1 x 22 µF

100 k

43.2 k

24.9 k

2.2 µF + 1 × 100 nF

100 nF

1 µF

1000

5

(1) Inductor values are calculated based on typical V_IN= 24 V.

9.2.1 Design Requirements

Section 9.2.2 provides a detailed design procedure based on Table 9-2.

Table 9-2. Detailed Design Parameters

DESIGN PARAMETER

Input voltage

EXAMPLE VALUE

24 V (6 V to 65 V)

Output voltage

5 V

Maximum output current

Switching frequency

0 A to 0.6 A

1000 kHz

9.2.2 Detailed Design Procedure

The following design procedure applies to Figure 9-1 and Table 9-1.

9.2.2.1 Choosing the Switching Frequency

The choice of switching frequency is a compromise between conversion efficiency and overall solution size.

Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.

However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more

compact design. For this example, 1000 kHz is used.

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9.2.2.2 Setting the Output Voltage

For the fixed output voltage versions, pin 8 (VOUT/BIAS) of the device must be connected directly to the output

voltage node. This output sensing point is normally located near the top of the output capacitor. If the sensing

point is located further away from the output capacitors (that is, remote sensing), then a small 100-nF capacitor

can be needed at the sensing point.

9.2.2.2.1 FB for Adjustable Output

In an adjustable output voltage version, pin 8 of the device is FB. The output voltage of LMR36506 is externally

adjustable using an external resistor divider network. The divider network is comprised of R_FBTand R_FBB, and

closes the loop between the output voltage and the converter. The converter regulates the output voltage by

holding the voltage on the FB pin equal to the internal reference voltage, V_REF. The resistance of the divider is a

compromise between excessive noise pickup and excessive loading of the output. Smaller values of resistance

reduce noise sensitivity but also reduce the light-load efficiency. The recommended value for R_FBTis 100 kΩ with

a maximum value of 1 MΩ. Once R_FBTis selected, Equation 6 is used to select R_FBB. V_REFis nominally 1 V. See

Section 7.5.

R_FBT

R_FBB

=

»

…

ÿ

V_OUT

V_REF

-1

Ÿ

⁄

(6)

For this 5-V example, R_FBT= 100 kΩ and R_FBB= 24.9 kΩ is chosen.

9.2.2.3 Inductor Selection

The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on

the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the

maximum output current. Experience shows that the best value for inductor ripple current is 30% of the

maximum load current. Note that when selecting the ripple current for applications with much smaller maximum

load than the maximum available from the device, use the maximum device current. Equation 7 can be used to

determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example,

choose K = 0.3 and find an inductance of L = 22 µH. Select the next standard value of L = 22 µH.

(

V

_IN- V_OUT

)

V_OUT

L =

∂

f_SW∂K ∂I_OUTmax

V

IN

(7)

Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, I_SC

(see Section 7.5). This ensures that the inductor does not saturate, even during a short circuit on the output.

When the inductor core material saturates, the inductance falls to a very low value, causing the inductor current

to rise very rapidly. Although the valley current limit, I_LIMIT, is designed to reduce the risk of current runaway, a

saturated inductor can cause the current to rise to high values very rapidly. This can lead to component damage.

Do not allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation

characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft

saturation, allowing some relaxation in the current rating of the inductor. However, they have more core losses at

frequencies above about 1 MHz. In any case, the inductor saturation current must not be less than the maximum

peak inductor current at full load.

To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 8:

V_OUT

L_MIN≥ 1.5 x

f_SW

(8)

The maximum inductance is limited by the minimum current ripple for the current mode control to perform

correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device

maximum rated current under nominal conditions.

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9.2.2.4 Output Capacitor Selection

The current mode control scheme of the LMR36506 devices allows operation over a wide range of output

capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather

than the output voltage ripple. Please refer to Section 9.2 for typical output capacitor value for 3.3-V and 5-V

output voltages. Based on , for a 5-V output design, you can choose the recommended ceramic output capacitor

for this example. For other designs with other output voltages, WEBENCH can be used as a starting point for

selecting the value of output capacitor.

In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load

transient testing and bode plots are the best way to validate any given design and must always be completed

before the application goes into production. In addition to the required output capacitance, a small ceramic

placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1

nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.

Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever

is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well

as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load

and loop stability must be performed.

9.2.2.5 Input Capacitor Selection

The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple

current and isolating switching noise from other circuits. A minimum ceramic capacitance of 2.2 µF is required on

the input of the LMR36506. This must be rated for at least the maximum input voltage that the application

requires, preferably twice the maximum input voltage. This capacitance can be increased to help reduce input

voltage ripple and maintain the input voltage during load transients. In addition, a small case size 100-nF

ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency

bypass for the control circuits internal to the device. For this example a 2.2-µF, 100-V, X7R (or better) ceramic

capacitor is chosen. The 100 nF must also be rated at 100 V with an X7R dielectric.

It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially

true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this

capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this

additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate

RMS value of this current can be calculated from Equation 9 and must be checked against the manufacturers'

maximum ratings.

I_OUT

I_RMS

@

2

(9)

9.2.2.6 C_BOOT

The LMR36506 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor

stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of

100 nF and at least 16 V is required.

9.2.2.7 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output

requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this

output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for

the power-good function (see Section 8.3.3). A value in the range of 10 kΩ to 100 kΩ is a good choice in this

case. The nominal output voltage on VCC is 3.2 V; see Section 7.5 for limits.

9.2.2.8 C_FFSelection

In some cases, a feedforward capacitor can be used across R_FBTto improve the load transient response or

improve the loop-phase margin. This is especially true when values of R_FBT> 100 kΩ are used. Large values of

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R_FBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes

with the loop stability. A C_FFcan help mitigate this effect. Use Equation 10 to estimate the value of C_FF. The

value found with Equation 10 is a starting point; use lower values to determine if any advantage is gained by the

use of a C_FFcapacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with

Feedforward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.

V_OUT∂C_OUT

C_FF

<

V_REF

V_OUT

120 ∂R_FBT

∂

(10)

9.2.2.8.1 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This can be

accomplished by using the circuit shown in Figure 9-2. The input voltage at which the device turns on is

designated as V_ONwhile the turnoff voltage is V_OFF. First, a value for R_ENBis chosen in the range of 10 kΩ to

100 kΩ, then Equation 11 is used to calculate R_ENTand V_OFF

.

VIN

R_ENT

EN

R_ENB

Figure 9-2. Setup for External UVLO Application

≈

∆

«

’

÷

◊

V_ON

÷

R_ENT

=

-1 ∂R_ENB

V_EN-H

≈

’

V_EN-HYS

V_EN

∆

÷

◊

V_OFF= V_ON∂ 1-

∆

«

(11)

where

•

V_ONis the V_INturnon voltage.

V_OFFis the V_INturnoff voltage.

9.2.2.9 Maximum Ambient Temperature

As with any power conversion device, the LMR36506 dissipates internal power while operating. The effect of this

power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal resistance,

R_θJA, of the device and PCB combination. The maximum junction temperature for the LMR36506 must be limited

to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load current.

Equation 12 shows the relationships between the important parameters. It is easy to see that larger ambient

temperatures (T_A) and larger values of R_θJAreduce the maximum available output current. The converter

efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions

cannot be found in one of the curves, interpolation can be used to estimate the efficiency. Alternatively, the EVM

can be adjusted to match the desired application requirements and the efficiency can be measured directly. The

correct value of R_θJAis more difficult to estimate. As stated in the Semiconductor and IC Package Thermal

Metrics Application Report, the values given in Section 7.4 are not valid for design purposes and must not be

used to estimate the thermal performance of the application. The values reported in that table were measured

under a specific set of conditions that are rarely obtained in an actual application.

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(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

MAX

(

)

V_OUT

(12)

where

η is the efficiency.

The effective R_θJAis a critical parameter and depends on many factors such as the following:

•

Power dissipation

Air temperature/flow

PCB area

Copper heat-sink area

Number of thermal vias under the package

Adjacent component placement

A typical example of R_θJAversus copper board area can be found in Figure 9-3 . The copper area given in the

graph is for each layer. For a 4-layer PCB design, the top and bottom layers are 2-oz. copper each, while the

inner layers are 1 oz. For a 2-layer PCB design, the top and bottom layers are 2-oz. copper each. Note that the

data given in these graphs are for illustration purposes only, and the actual performance in any given application

depends on all of the factors mentioned above.

Using the value of R_θJAfrom Figure 9-3 for a given PCB copper area and Ψ_JTfrom Section 7.4, one can

approximate the junction temperature of the IC for a given operating condition using Equation 13

T_J≈ T_A+ R_θJAx IC Power Loss

(13)

where

•

T_Jis the IC junction temperature (°C).

T_Ais the ambient temperature (°C).

R_θJAis the thermal resistance (°C/W)

IC Power Loss is the power loss for the IC (W).

The IC Power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC

Resistance. The overall power loss can be approximated from the efficiency curves in the Application Curves or

by using WEBENCH for a specific operating condition and temperature.

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220

200

180

160

140

120

100

80

2 Layer, 0.5W

4 Layer, 0.5W

60

40

0

1000

2000

3000

4000

5000

6000

PCB Copper Area (mm²)

Rthe

Figure 9-3. R_θJAversus PCB Copper Area for the VQFN (RPE) Package

Use the following resources as guides to optimal thermal PCB design and estimating R_θJAfor a given application

environment:

•

Thermal Design by Insight not Hindsight Application Report

A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report

Semiconductor and IC Package Thermal Metrics Application Report

Thermal Design Made Simple with LM43603 and LM43602 Application Report

PowerPAD^™Thermally Enhanced Package Application Report

PowerPAD^™Made Easy Application Report

Using New Thermal Metrics Application Report

PCB Thermal Calculator

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 24V, T_A= 25°C.

100

90

80

70

60

50

40

30

20

10

0

3.34

3.335

3.33

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

3.325

3.32

3.315

3.31

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

3.305

3.3

0

0.1

0.2

0.3

LoadSetPoint(A)

0.4

0.5

0.6

10m

100m

1m 10m

Load Current (A)

100m

1

Load

LMR3

LMR36506R

V_OUT= 3.3 V Fixed

1 MHz (AUTO)

LMR36506R3

V_OUT= 3.3 V Fixed

1 MHz (AUTO)

Figure 9-5. Line and Load Regulation

Figure 9-4. Efficiency

100

90

80

70

60

50

40

30

20

10

5.1

5.09

5.08

5.07

5.06

5.05

5.04

5.03

5.02

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

0

0.1

0.2

0.3

Load Current (A)

0.4

0.5

0.6

10m

100m

1m 10m

Load Current (A)

100m

1

Load

LMR3

LMR36506R

V_OUT= 5 V

400 kHz (AUTO)

LMR36506R

V_OUT= 5 V

400 kHz (AUTO)

Figure 9-7. Line and Load Regulation

Figure 9-6. Efficiency

100

90

80

70

60

50

40

30

20

10

0

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

5

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

V_IN= 12V

V_IN= 24V

V_IN= 36V

V_IN= 48V

V_IN= 54V

10m

100m

1m 10m

Load Current (A)

100m

0

0.1

0.2

0.3

Load Current (A)

0.4

0.5

0.6

LMR3

Load

LMR36506R5

V_OUT= 5 V Fixed

1 MHz (AUTO)

LMR36506R5

V_OUT=5 V

1 MHz (AUTO)

Figure 9-8. Efficiency

Figure 9-9. Line and Load Regulation

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3.45

3.30

3.15

3.00

2.85

2.70

5.5

5.0

4.5

4.0

3.5

3.0

2.5

I_OUT= 0A

I_OUT= 0.3A

I_OUT= 0.6A

I_OUT= 0A

I_OUT= 0.3A

I_OUT= 0.6A

2.55

2.40

3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00

Input Voltage (V)

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage (V)

6.0

6.5

7.0

Drop

LMR36506R3

V_OUT= 3.3 V Fixed

1 MHz (AUTO)

LMR36506R

V_OUT= 5 V

400 kHz (AUTO)

Figure 9-10. Dropout

Figure 9-11. Dropout

VOUT (100mV/DIV)

VOUT (200mV/DIV)

3.3V

Load Current (0.5A/DIV)

200µs/DIV

LMR36506R3

V_OUT= 3.3 V Fixed

1 MHz

LMR36506R3

V_OUT= 3.3 V Fixed

1 MHz

0.3 A to 0.6 A,1

A/µs

0 A to 0.6 A,1 A/µs

Figure 9-12. Load Transient

Figure 9-13. Load Transient

5V

VOUT (200mV/DIV)

VOUT (100mV/DIV)

5V

Load Current (0.5A/DIV)

200µs/DIV

LMR36506R

V_OUT= 5 V Fixed

400 kHz

LMR36506R

V_OUT= 5 V Fixed

400 kHz

0 A to 0.6 A,1 A/µs

0.3 A to 0.6 A,1

A/µs

Figure 9-14. Load Transient

Figure 9-15. Load Transient

36

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VOUT (20mV/DIV)

VOUT (10mV/DIV)

Inductor Current (200mA/DIV)

Inductor Current (500mA/DIV)

5ms/DIV

2µs/DIV

LMR36506R

V_OUT= 5V

Load = 0.6A

400kHz

LMR36506R3

V_OUT= 3.3V Fixed

No Load

Figure 9-16. Output Ripple

Figure 9-17. Output Ripple

L

V_OUT

V_IN

SW

VIN

C_IN

C_HF

C_BOOT

100 nF

EN

2.2 µF

C_OUT

BOOT

0.1 µF

LMR36506

R_FBT

RT

PG

FB

R_T

VCC

R_FBB

C_VCC

1 µF

GND

Figure 9-18. Schematic for Typical Application Curves

Table 9-3. BOM for Typical Application Curves

NOMINAL C_OUT

(RATED CAPACITANCE)

U1

ƒ_SW

V_OUT

L

RT pin

R_FBT

R_FBB

15 µH, 260

mΩ

Short to

VCC

LMR36506R3RPER

LMR36506RRPER

LMR36506R5RPER

1000 kHz 3.3 V (Fixed)

2 × 22 µF

0 Ω

Open

24.9 kΩ

Open

47 µH, 68.4

mΩ

400 kHz

5 V

2× 22 µF

2 x 22 µF

39.2 kΩ 100 kΩ

22 µH, 99.65

mΩ

Short to

0 Ω

1000 kHz

5 V (Fixed)

VCC

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9.3 What to Do and What Not to Do

•

Do not exceed the Absolute Maximum Ratings.

Do not exceed the Recommended Operating Conditions.

Do not exceed the ESD Ratings.

Do not allow the EN input to float.

Do not allow the output voltage to exceed the input voltage, nor go below ground.

Follow all the guidelines and suggestions found in this data sheet before committing the design to production.

TI application engineers are ready to help critique your design and PCB layout to help make your project a

success.

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with Section 7 found in this data sheet. In addition,

the input supply must be capable of delivering the required input current to the loaded regulator. The average

input current can be estimated with Equation 14.

V_OUT∂I_OUT

I_IN

=

V_IN∂ h

(14)

where

•

η is the efficiency

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input

capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the

regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is

applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the

regulator to momentarily shut down and reset. The best way to solve these kind of issues is to limit the distance

from the input supply to the regulator or plan to use an aluminum or tantalum input capacitor in parallel with the

ceramics. The moderate ESR of these types of capacitors help dampen the input resonant circuit and reduce

any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to

hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple

Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when

designing an input filter for any switching regulator.

In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not

recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the

output voltage of the regulator, the output capacitors discharge through the device back to the input. This

uncontrolled current flow can damage the device.

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11 Layout

11.1 Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout

can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad

PCB layout can mean the difference between a robust design and one that cannot be mass produced.

Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck

converter, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power

ground, as shown in Figure 11-1. This loop carries large transient currents that can cause large transient

voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper

operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as

small as possible to reduce the parasitic inductance. Figure 11-2 shows a recommended layout for the critical

components of the LMR36506.

1. Place the input capacitors as close as possible to the VIN and GND terminals.

2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and

routed with short, wide traces to the VCC and GND pins.

3. Use wide traces for the C_BOOTcapacitor. Place C_BOOTclose to the device with short/wide traces to the BOOT

and SW pins. Route the SW pin to the N/C pin and used to connect the BOOT capacitor to SW.

4. Place the feedback divider as close as possible to the FB pin of the device. Place R_FBB, R_FBT, and C_FF, if

used, physically close to the device. The connections to FB and GND must be short and close to those pins

on the device. The connection to V_OUTcan be somewhat longer. However, the latter trace must not be routed

near any noise source (such as the SW node) that can capacitively couple into the feedback path of the

regulator.

5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat

dissipation path.

6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any

voltage drops on the input or output paths of the converter and maximizes efficiency.

7. Provide enough PCB area for proper heat-sinking. As stated in Section 9.2.2.9, enough copper area must be

used to ensure a low R_θJA, commensurate with the maximum load current and ambient temperature. The top

and bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design

uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer

heat-spreading ground planes.

8. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as

possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

See the following PCB layout resources for additional important guidelines:

•

Layout Guidelines for Switching Power Supplies Application Report

Simple Switcher PCB Layout Guidelines Application Report

Construction Your Power Supply- Layout Considerations Seminar

Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

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VIN

C_IN

SW

GND

Figure 11-1. Current Loops with Fast Edges

11.1.1 Ground and Thermal Considerations

As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground

plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control

circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as

well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the

ground plane contains much less noise; use for sensitive routes.

TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See Figure

11-2 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom

layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting

from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout,

provides low current conduction impedance, proper shielding and lower thermal resistance.

11.2 Layout Example

RFBB

CFF

RFBT

CVCC

RENB

RENT

CIN

L1

CIN

COUT

GND

Figure 11-2. Example Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Thermal Design by Insight not Hindsight Application Report

Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages

Application Report

•

Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report

Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report

Texas Instruments, PowerPAD^™Thermally Enhanced Package Application Report

Texas Instruments, PowerPAD^™Made Easy Application Report

Texas Instruments, Using New Thermal Metrics Application Report

Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report

Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report

Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar

Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

HotRod^™, are trademarks of TI.

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMR36506MSCQRPERQ1
厂家：	TEXAS INSTRUMENTS
描述：	3V 至 65V、0.6A 降压转换器，拥有出色的尺寸和轻负载效率 \| RPE \| 9 \| -40 to 150 转换器
文件：	总45页 (文件大小：1697K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMR36506MSCQRPERQ1 [TI]

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