LMR36520 [TI]
具有 26uA IQ 的 SIMPLE SWITCHER® 4.2V 至 65V、2A 同步降压转换器;
| 型号： | LMR36520 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 26uA IQ 的 SIMPLE SWITCHER® 4.2V 至 65V、2A 同步降压转换器 转换器 |
| 文件： | 总40页 (文件大小：1529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
LMR36520 SIMPLE SWITCHER ®4.2V 至 65V、2A 同步降压转换器
1 特性
3 说明
1
•
专为可靠耐用的应用 设计
LMR36520 稳压器是一款易于使用的同步降压直流/直
流 SIMPLE SWITCHER 转换器。借助集成式高侧和低
侧功率 MOSFET，在 4.2V 至 65V 宽输入电压范围内
的输出电流可高达 2A。高达 70V 的瞬态电压耐受能力
有助于缩小解决方案尺寸和降低成本，以提供过压保护
并满足 IEC 61000-4-5 的浪涌抗扰度要求。
–
–
高达 70V 的输入瞬态保护
保护 功能：热关断、输入欠压锁定、逐周期电
流限制和断续短路保护
•
非常适合可扩展的工业电源
–
与以下器件引脚兼容：
–
–
LMR36510（65V、1A）
LMR36520 采用峰值电流模式控制机制来提供出色的
效率和输出电压精度。利用精密使能功能，您可以灵活
地直接连接到宽输入电压，或对器件启动和关断进行精
确控制。附带内置滤波和延迟功能的电源正常状态标志
可提供系统状态的真实指示，免去了使用外部监控器的
麻烦。
LMR33610/LMR33620/LMR33630/
LMR33640（36V、1A、2A、3A 或 4A）
–
–
内部补偿有助于减小解决方案尺寸、降低成本和
设计复杂性
频率为 400kHz
•
•
宽转换范围
–
–
输入电压范围：4.2V 至 65V
输出电压范围：1V 至 95% 的 VIN
通过集成和内部补偿，该器件减少了很多外部组件，并
提供专为实现简单 PCB 布局而设计的引脚排列方式。
该器件的功能集旨在简化各种终端设备的实施。
LMR36520 与 LMR36510（65V、1A）、
在整个负载范围内具有低功率耗散
–
在 400kHz（24VIN、5VOUT、1A）下效率为
90%
LMR33610、LMR33620、LMR33630 和 LMR33640
（36V、1A/2A/3A/4A）引脚对引脚兼容，完善了
SIMPLE SWITCHER 转换器的最新系列。这提高了宽
输入电压转换器在各种常用电压和电流额定值范围内的
易用性和可扩展性，无需重新设计电路板布局。因此，
不仅降低了总体成本和设计工作量，而且缩短了上市时
间。 LMR36510 与 LMR36520（65V、2A）、
LMR33610、LMR33620、LMR33630 和 LMR33640
（36V、1A/2A/3A/4A）引脚对引脚兼容，完善了
SIMPLE SWITCHER 转换器的最新系列。
–
–
在 PFM 模式中提高了轻负载效率
低至 26µA 的工作静态电流
•
具有滤波器和延迟释放功能的电源正常状态输出
2 应用
•
•
•
•
•
•
IP 网络摄像头
模拟安防摄像头
HVAC 阀门和传动器控制
交流驱动器和伺服驱动控制模块
模拟输入模块和混合 I/O 模块
通用宽输入电压电源
LMR36520 采用 8 引脚 HSOIC 封装。
器件信息(1)
器件型号
LMR36520
封装
HSOIC (8)
封装尺寸（标称值）
5.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
效率与输出电流间的关系
VOUT = 5V，400kHz
简化原理图
BOOT
100
90
VIN
CIN
VIN
EN
CBOOT
L1
VOUT
COUT
SW
80
PGND
VCC
70
PG
FB
60
RFBT
VIN = 12V
CVCC
VIN = 24V
VIN = 36V
VIN = 48V
50
RFBB
40
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Load (A)
1
2
Effi
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBF0
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
目录
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
9.3 What to Do and What Not to Do ............................. 26
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 7
7.7 Switching Characteristics.......................................... 7
7.8 System Characteristics ............................................. 8
7.9 Typical Characteristics.............................................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
9
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 30
12 器件和文档支持 ..................................................... 31
12.1 器件支持 ............................................................... 31
12.2 文档支持................................................................ 31
12.3 接收文档更新通知 ................................................. 31
12.4 支持资源................................................................ 31
12.5 商标....................................................................... 31
12.6 静电放电警告......................................................... 31
12.7 Glossary................................................................ 31
13 机械、封装和可订购信息....................................... 31
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (September 2019) to Revision A
Page
•
将器件状态从“预告信息”更改为“生产数据” ............................................................................................................................. 1
2
Copyright © 2019–2020, Texas Instruments Incorporated
LMR36520
www.ti.com.cn
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
5 Device Comparison Table
ORDERABLE PART
CURRENT
FPWM
fSW
AVAILABILITY
NUMBER
LMR36520ADDAR
LMR36520FADDAR
2 A
2 A
No
400 kHz
400 kHz
Now
No
Yes
Copyright © 2019–2020, Texas Instruments Incorporated
3
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
6 Pin Configuration and Functions
DDA Package
8-Pin HSOIC
Top View
PGND
VIN
1
2
3
4
8
7
6
5
SW
BOOT
VCC
FB
THERMAL PAD
EN
PG
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Power and analog ground terminal. Connect to bypass capacitor with short, wide traces. Ground
PGND
1
G
reference for internal references and logic. All electrical parameters are measured with respect to this
pin.
Input supply to regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin and
PGND.
VIN
EN
2
3
P
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN; Do not float.
Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. Flag pulls low when EN = Low. Can be left open when
not used.
PG
4
5
6
A
A
P
Feedback input to regulator. Connect to tap point of feedback voltage divider. Do not float. Do not
ground.
FB
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to external loads.
Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to
PGND.
VCC
Bootstrap supply voltage for internal high-side driver. Connect a high-quality 100-nF capacitor from this
pin to the SW pin.
BOOT
SW
7
8
P
P
Regulator switch node. Connect to a power inductor.
THERMAL Therm Major heat dissipation path of the device. A direct thermal connection to a ground plane is required.
PAD al The PAD is not meant as an electrical interconnect. Electrical characteristics are not ensured.
PAD
A = Analog, P = Power, G = Ground
4
Copyright © 2019–2020, Texas Instruments Incorporated
LMR36520
www.ti.com.cn
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of -40°C to 150°C (unless otherwise noted)(1)
MIN
MAX
70
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
Output voltage
Output voltage
VIN to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–0.3
-40
EN to PGND
70.3
5.5
V
FB to PGND
V
PG to PGND
20
V
SW to PGND
70.3
70
V
SW to PGND less than 10-ns transients
CBOOT to SW
V
5.5
V
VCC to PGND
5.5
V
Junction Temperature TJ
Storage temperature, Tstg
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human-body model (HBM)(1)
Charged-device model (CDM)(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 ℃ to 125 ℃ (unless otherwise noted)(1)
MIN
4.2
0
MAX
UNIT
VIN to PGND
EN to PGND(2)
PG to PGND(2)
VOUT
65
65
18
28
2
V
V
V
V
A
Input voltage
0
Output voltage
Output current
1
IOUT
0
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
Copyright © 2019–2020, Texas Instruments Incorporated
5
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
7.4 Thermal Information
LMR36520
DDA (HSOIC)
8 PINS
42.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
54
13.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.3
ψJB
13.8
RθJC(bot)
4.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating quiescent current (non-
IQ-nonSW
ISD
VEN = 3.3 V (PFM variant only)
VEN = 0 V
26
36
µA
µA
switching)(2)
Shutdown quiescent current;
measured at VIN pin
5.3
ENABLE (EN PIN)
VEN-VCC-H
VEN-VCC-L
VEN-VOUT-H
Enable input high level for VCC output VENABLE rising
1.14
1.3
V
V
Enable input low level for VCC output
Enable input high level for VOUT
VENABLE falling
0.3
VENABLE rising
1.157
1.231
110
V
VEN-VOUT-HYS Enable input hysteresis for VOUT
ILKG-EN Enable input leakage current
INTERNAL LDO (VCC PIN)
Hysteresis below VENABLE-H; falling
VEN = 3.3V
mV
nA
2.7
VCC
Internal VCC voltage
6 V ≤ VIN ≤ 65 V
4.75
3.6
5
5.25
4.0
V
V
VCC-UVLO-
Rising
Internal VCC undervoltage lockout
Internal VCC undervoltage lockout
VCC rising
3.8
VCC-UVLO-
Falling
VCC falling
FB = 1 V
3.1
3.3
3.5
V
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
0.985
1
1.015
V
ILKG-FB
Feedback leakage current
2.1
nA
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(3)
Low-side current limit(3)
2.4
1.8
3
2.3
3.6
2.8
A
A
A
A
A
ILS-LIMIT
IL-ZC
IPEAK-MIN
IL-NEG
Zero cross detector threshold
Minimum inductor peak current(3)
Negative current limit(3)
PFM variants only
FPWM variant only
0.04
0.59
–1.7
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
6
Copyright © 2019–2020, Texas Instruments Incorporated
LMR36520
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ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
Electrical Characteristics (continued)
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD (PGOOD PIN)
VPG-HIGH-UP
VPG-LOW-DN
Power-Good upper threshold - rising
% of FB voltage
105%
90%
107%
93%
110%
95%
Power-Good lower threshold - falling
% of FB voltage
Power-Good hysteresis (rising &
falling)
VPG-HYS
% of FB voltage
1.5%
Minimum input voltage for proper
Power-Good function
VPG-VALID
2
V
RPG
Power-Good on-resistance
Power-Good on-resistance
VEN = 2.5 V
VEN = 0 V
80
35
165
90
Ω
Ω
RPG
MOSFETS
RDS-ON-HS
RDS-ON-LS
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
IOUT = 0.5 A
IOUT = 0.5 A
245
165
465
310
mΩ
mΩ
7.6 Timing Requirements
Limits apply over operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions
apply: VIN = 24 V.
MIN
NOM
MAX
UNIT
tON-MIN
tOFF-MIN
tON-MAX
tSS
Minimum switch on-time
Minimum switch off-time
Maximum switch on-time
Internal soft-start time
92
ns
80
102
12
6
ns
7
µs
3
4.5
ms
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
7.7 Switching Characteristics
TJ = -40°C to 125°C, VIN = 24 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OSCILLATOR
FOSC
Internal oscillator frequency
400-kHz variant
340
400
460
kHz
Copyright © 2019–2020, Texas Instruments Incorporated
7
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
7.8 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃ to 125℃. These specifications are not ensured by production
testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
Adjustable output voltage regulation(1)
Adjustable output voltage regulation(1)
4.2
65
V
VOUT
VOUT
PFM operation
–1.5%
–1.5%
2.5%
1.5%
FPWM operation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
ISUPPLY
DMAX
VHC
Input supply current when in regulation
Maximum switch duty cycle(2)
26
98%
0.4
µA
V
FB pin voltage required to trip short-circuit
hiccup mode
tD
Switch voltage dead time
2
170
158
ns
°C
°C
TSD
TSD
Thermal shutdown temperature
Thermal shutdown temperature
Shutdown temperature
Recovery temperature
(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
=
8
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LMR36520
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ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
7.9 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 24 V.
12
10
8
850
800
750
700
650
600
550
6
4
25èC
125èC
-40èC
25èC
125èC
-40èC
2
5
10 15 20 25 30 35 40 45 50 55 60 65
Input Voltage (V)
5
10 15 20 25 30 35 40 45 50 55 60 65
Input Voltage (V)
Shut
Imin
EN = 0 V
IOUT = 0 A
VOUT = 3.3 V
ƒSW = 400 kHz
See 图 32
图 1. Shutdown Supply Current
图 2. IPEAK-MIN
版权 © 2019–2020, Texas Instruments Incorporated
9
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
The LMR36520 is a synchronous peak-current mode buck regulator designed for a wide variety of industrial
applications. The regulator automatically switches modes between PFM and PWM, depending on load. At heavy
loads, the device operates in PWM at a constant switching frequency. At light loads, the mode changes to PFM
with diode emulation, allowing DCM. This reduces the input supply current and keeps efficiency high. The device
features internal loop compensation, which reduces design time and requires fewer external components than
externally compensated regulators.
8.2 Functional Block Diagram
VCC
VIN
INT. REG.
BIAS
BOOT
OSCILLATOR
ENABLE
LOGIC
HS CURRENT
SENSE
EN
ꢀ
1.0 V
Reference
PWM
COMP
ERROR
AMPLIFIER
+
CONTROL
LOGIC
DRIVER
SW
œ
+
FB
œ
PFM
MODE
CONTROL
LS CURRENT
SENSE
PG
POWER GOOD
CONTROL
PGND
8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36520 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by
referencing 图 3 and 图 4. Note that during initial power-up, a delay of about 4 ms (typical) is inserted from the
time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up
and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor, as desired. If this function
is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4
mA.
10
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LMR36520
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ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
Feature Description (接下页)
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
<TPG
PG
TPG
TPG
TPG
图 3. Static Power-Good Operation
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP
(95%)
VPG-LOW-DN (93%)
<tPG
PG
tPG
tPG
tPG
图 4. Power-Good Timing Behavior
8.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see the External UVLO section). Applying a
voltage of ≥ VEN-VCC_H causes the device to enter standby mode, powering the internal VCC, but not producing
an output voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter start-up mode
and begin the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the regulator stops running
and enters standby mode. If the EN voltage decreases below VEN-VCC-L, the device shuts down. 图 5 shows this
behavior. The EN input can be connected directly to VIN if this feature is not needed. This input must not be
allowed to float. The values for the various EN thresholds can be found in the Electrical Characteristics table.
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LMR36520
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Feature Description (接下页)
The LMR36520 utilizes a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up.
EN
VEN-H
VEN-H œ VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5 V
0
VOUT
VOUT
0
图 5. Precision Enable Behavior
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Feature Description (接下页)
PGOOD (5V/DIV)
VOUT (2V/DIV)
EN (5V/DIV)
IOUT (2A/DIV)
2ms/DIV
图 6. Typical Start-up Behavior
VIN = 24 V, VOUT = 5 V, IOUT = 2 A
8.3.3 Current Limit and Short Circuit
The LMR36520 incorporates valley current limit for normal overloads and for short-circuit protection. In addition,
the high-side power MOSFET is protected from excessive current by a peak-current limit circuit. Cycle-by-cycle
current limit is used for overloads while hiccup mode is used for short circuits. Finally, a zero current detector is
used on the low-side power MOSFET to implement diode emulation at light loads (see the Glossary).
During overloads, the low-side current limit, ILIMIT, determines the maximum load current that the LMR36520 can
supply. When the low-side switch turns on, the inductor current begins to ramp down. If the current does not fall
below ILIMIT before the next turnon cycle, then that cycle is skipped, and the low-side MOSFET is left on until the
current falls below ILIMIT. This is somewhat different than the more typical peak-current limit and results in 公式 1
for the maximum load current.
(
V
IN - VOUT
)
∂
VOUT
IOUT
= ILIMIT
+
max
2∂ fSW ∂L
V
IN
where
•
•
fSW = switching frequency
L = inductor value
(1)
If, during current limit, the voltage on the FB input falls below about 0.4 V due to a short circuit, the device enters
into hiccup mode. In this mode, the device stops switching for tHC, or about 94 ms, and then goes through a
normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for about 20
ms (typical) and then shuts down again. This cycle repeats as long as the short-circuit condition persists. This
mode of operation reduces the temperature rise of the device during a hard short on the output. Of course, the
output current is greatly reduced during hiccup mode. Once the output short is removed and the hiccup delay is
passed, the output voltage recovers normally.
The high-side current limit trips when the peak inductor current reaches ISC. This is a cycle-by-cycle current limit
and does not produce any frequency or load current foldback. It is meant to protect the high-side MOSFET from
excessive current. Under some conditions, such as high input voltages, this current limit can trip before the low-
side protection. Under this condition, ISC determines the maximum output current. Note that ISC varies with duty
cycle.
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Feature Description (接下页)
Short removed
Short applied
Output Voltage (5V/DIV)
Inductor Current (2A/DIV)
Inductor Current (1A/DIV)
20ms/DIV
50ms/DIV
图 7. Short-Circuit Transient and Recovery
图 8. Inductor Current Burst in Short Circuit Mode
8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR36520 incorporates an undervoltage lockout feature on the output of the internal LDO at the VCC pin.
When VCC reaches about 3.7 V, the device is ready to receive an EN signal and start up. When VCC falls below
about 3 V, the device shuts down, regardless of EN status. Because the LDO is in dropout during these
transitions, the previously mentioned values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 170°C, the device shuts down; re-start occurs when the temperature falls to about
158°C. For safe operation, the device must not be allowed to go into a short circuit condition while in thermal
shutdown.
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM.
In PWM, the regulator operates as a constant frequency, current mode, full-synchronous converter using PWM to
regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency of these
bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency (see the Glossary).
This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate
the output voltage at small loads. This trades off very good light-load efficiency for larger output voltage ripple
and variable switching frequency. Also, a small increase in output voltage occurs at light loads. The actual
switching frequency and output voltage ripple depend on the input voltage, output voltage, and load.
14
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Device Functional Modes (接下页)
Switch Node (10V/DIV)
Switch Node (10V/DIV)
Inductor Current (1A/DIV)
Inductor Current (0.5A/DIV)
5µs/DIV
1µs/DIV
图 9. Typical PFM Switching Waveforms
图 10. Typical PWM Switching Waveforms
VIN = 24 V, VOUT = 5 V, IOUT = 50 mA
VIN = 24 V, VOUT = 5 V, IOUT = 1 A, ƒS = 400 kHz
8.4.2 Forced PWM Operation
The following select variant is a factory option made available for cases when constant frequency operation is
more important than light load efficiency.
表 1. LMR36520 Device Variants with Fixed Frequency Operation at No Load
ORDERABLE PART NUMBER
OUTPUT CURRENT
FPWM
fSW
LMR36520FADDAR
2 A
Yes
400 kHz
In FPWM operation, the diode emulation feature is turned off. This means that the device remains in CCM under
light loads. Under conditions where the device must reduce the on-time or off-time below the ensured minimum
to maintain regulation, the frequency reduces to maintain the effective duty cycle required for regulation. This
occurs for very high and very low input and output voltage ratios. In FPWM mode, a limited reverse current is
allowed through the inductor, allowing power to pass from the output of the regulator to the input of the regulator.
Note that in FPWM mode, larger currents pass through the inductor, if lightly loaded, than in auto mode. Once
loads are heavy enough to necessitate CCM operation, FPWM mode has no measurable effect on regulator
operation.
8.4.3 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is
reduced to the output voltage, the off-time of the high-side MOSFET starts to approach the minimum value.
Beyond this point, the switching can become erratic and the output voltage falls out of regulation. To avoid this
problem, the LMR36520 automatically reduces the switching frequency to increase the effective duty cycle and
maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the input and
output voltage when the output has dropped by 1% of the nominal value. Under this condition, the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V short circuit detection
threshold is not activated when in dropout mode.
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500
450
400
350
300
250
200
150
100
6
5.5
5
IOUT = 1 A
IOUT = 2 A
4.5
4
IOUT = 0.5 A
IOUT = 1 A
IOUT = 2 A
3.5
3
4
4.2 4.4 4.6 4.8
5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
4.5 4.75
5
5.25 5.5 5.75 6
Input Voltage (V)
6.25 6.5 6.75
7
Drop
Freq
图 11. Overall Dropout Characteristic
图 12. Frequency Dropout Characteristics
VOUT = 5 V
ƒSW = 400 kHz
8.4.4 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle, therefore, a minimum conversion
ratio. The constraint is encountered at high input voltages and low output voltages. To help extend the minimum
controllable duty cycle, the LMR36520 automatically reduces the switching frequency when the minimum on-time
limit is reached. This way, the converter can regulate the lowest programmable output voltage at the maximum
input voltage. An estimate for the approximate input voltage, for a given output voltage, before frequency
foldback occurs is found in 公式 2. As the input voltage is increased, the switch on-time (duty cycle) reduces to
regulate the output voltage. When the on-time reaches the limit, the switching frequency drops, while the on-time
remains fixed.
VOUT
V
Ç
IN
tON ∂ fSW
(2)
16
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR36520 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 2 A. The following design procedure can be used to select components
for the LMR36520.
注
All of the capacitance values given in the following application information refer to effective
values; unless otherwise stated. The effective value is defined as the actual capacitance
under DC bias and temperature, not the rated or nameplate values. Use high-quality, low-
ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value
ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. Under DC bias, the capacitance drops considerably. Large case sizes
and higher voltage ratings are better in this regard. To help mitigate these effects, multiple
capacitors can be used in parallel to bring the minimum effective capacitance up to the
required value. This can also ease the RMS current requirements on a single capacitor. A
careful study of bias and temperature variation of any capacitor bank must be made in
order to ensure that the minimum value of effective capacitance is provided.
9.2 Typical Application
shows a typical application circuit for the LMR36520. This device is designed to function over a wide range of
external components and system parameters. However, the internal compensation is optimized for a certain
range of external inductance and output capacitance. As a quick-start guide, 图 13 provides typical component
values for a range of the most common output voltages.
L
VOUT
VIN
SW
VIN
EN
CIN
CHF
CBOOT
220 nF
4.7 µF
COUT
BOOT
VPU
100 kΩ
0.1 µF
LMR36520
CFF
RFBT
PG
FB
VCC
RFBB
CVCC
1 µF
PGND
图 13. Example Application Circuit
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Typical Application (接下页)
表 2. Typical External Component Values
NOMINAL COUT
(RATED
MINIMUM COUT
(RATED
ƒSW
(kHz)
VOUT (V)
L (µH)
RFBT (Ω)
RFBB (Ω)
CIN
CFF
CAPACITANCE) CAPACITANCE)
(1)
(2)
400
400
400
3.3
5
6.8
10
33
3 × 22 µF
2 × 22 µF
4 × 10 µF
3 × 22 µF
2 × 22 µF
4 × 10 µF
100 k
100 k
100 k
43.2 k
24.9 k
9.09 k
2 × 4.7 µF + 220 nF
2 × 4.7 µF + 220 nF
2 × 4.7 µF + 220 nF
None
None
None
12
(1) Optimized for superior load transient performance from 0 to 100% rated load.
(2) Optimized for size constrained end applications.
9.2.1 Design 1: Low Power 24-V, 2-A Buck Converter
9.2.1.1 Design Requirements
The following are example requirements for a typical 5-V or 3.3-V application. The input voltages are here for
illustration purposes only. See the Specifications for the operating input voltage range.
表 3. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
12 V to 24 V steady state, 4.2 V to 60-V transients
Output voltage
5 V
Maximum output current
Switching frequency
0 A to 2 A
400 kHz
Current consumption at 0-A load
Switching frequency at 0-A load
Critical: Need to ensure low current consumption to reduce battery drain
Not critical: Need fixed frequency operation at high load only
表 4. List of Components for Design 1
VOUT
FREQUENCY
400 kHz
RFBB
COUT
L
U1
5 V
24.9 kΩ
43.2 kΩ
2 × 22 µF
3 × 22 µF
10 µH
6.8 µH
LMR36520
LMR36520
3.3 V
400 kHz
9.2.1.2 Detailed Design Procedure
The following design procedure applies to 图 13 and 表 3.
9.2.1.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size. The
LMR36520 switching frequency is fixed internal to the IC, therefore, a value of 400 kHz is used in this design.
9.2.1.2.2 Setting the Output Voltage
The output voltage of LMR36520 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in the Recommended Operating Conditions. The divider network is
comprised of RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter
regulates the output voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF
.
The resistance of the divider is a compromise between excessive noise pickup and excessive loading of the
output. Smaller values of resistance reduce noise sensitivity but also reduce the light-load efficiency. The
recommended value for RFBT is 100 kΩ with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a
feedforward capacitor must be used across this resistor to provide adequate loop phase margin (see the CFF
Selection section). Once RFBT is selected, use 公式 3 to select RFBB. VREF is nominally 1 V.
RFBT
RFBB
=
»
…
ÿ
VOUT
VREF
-1
Ÿ
⁄
(3)
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For this 5-V example, values are: RFBT = 100 kΩ and RFBB = 24.9 kΩ.
9.2.1.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum
output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load
current. Note that when selecting the ripple current for applications with much smaller maximum load than the
maximum available from the device, use the maximum device current. 公式 4 can be used to determine the value
of inductance. The constant K is the percentage of inductor current ripple. This example uses K = 0.4 and with
input voltage of 24 V, you can calculate an inductance of L = 12.37 µH. The standard value of 10 µH is selected.
(
V
IN - VOUT
)
VOUT
L =
∂
fSW ∂K ∂IOUTmax
V
IN
(4)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit, ISC
.
This ensures that the inductor does not saturate even during a short circuit on the output. When the inductor core
material saturates, the inductance falls to a very low value, causing the inductor current to rise very rapidly.
Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated inductor can
cause the current to rise to high values very rapidly. This can lead to component damage. Do not allow the
inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but usually
have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing some
relaxation in the current rating of the inductor. However, they have more core losses at frequencies above about
1 MHz. In any case, the inductor saturation current must not be less than the device low-side current limit, ILIMIT
.
In order to avoid subharmonic oscillation, the inductance value must not be less than that given in 公式 5:
VOUT
LMIN í M∂
fSW
where
•
•
•
LMIN = minimum inductance (H)
M = 0.42
fsw = switching frequency (Hz)
(5)
9.2.1.2.4 Output Capacitor Selection
The value of the output capacitor and the respective ESR determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements rather than the
output voltage ripple. 公式 6 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR that is required to meet a specified load transient.
K2
»
…
…
ÿ
DIOUT
fSW ∂ DVOUT ∂K
COUT
í
∂
(
1- D
)
∂
(
1+ K
)
+
∂
(
2 - D
)
Ÿ
12
Ÿ
⁄
(
2 + K
)
∂ DVOUT
ESR Ç
K2
1
»
ÿ
≈
’
2∂ DIOUT 1+ K +
∂∆1+
÷
÷
…
Ÿ
∆
12
(1- D)
…
«
◊Ÿ
⁄
VOUT
D =
V
IN
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = ripple factor from Inductor Selection
(6)
Once the output capacitor and ESR have been calculated, 公式 7 can be used to check the output voltage ripple.
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1
Vr @ DIL ∂ ESR2 +
2
8∂ fSW ∂COUT
where
•
Vr = peak-to-peak output voltage ripple
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high frequency noise. Small case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
9.2.1.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7-µF is required on
the input of the LMR36520. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. In addition, a small case size 220-nF ceramic
capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency bypass
for the control circuits internal to the device. For this example, a 1 x 4.7-µF, 100-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 100-V with an X7R dielectric.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitors. The approximate RMS value of
this current can be calculated from 公式 8 and must be checked against the manufacturer's maximum ratings.
IOUT
IRMS
@
2
(8)
9.2.1.2.6 CBOOT
The LMR36520 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 16 V is required.
9.2.1.2.7 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this output
must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see the Power-Good Flag Output section). A value in the range of 10 kΩ to 100 kΩ is a
good choice in this case. The nominal output voltage on VCC is 5 V.
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9.2.1.2.8 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help mitigate this effect. 公式 9 can be used to estimate the value of CFF. The
value found with 公式 9 is a starting point; use lower values to determine if any advantage is gained by the using
a CFF capacitor. The Optimizing Transient Response of Internally Compensated DC-DC Converters with Feed-
forward Capacitor Application Report is helpful when experimenting with a feedforward capacitor.
VOUT ∂COUT
CFF
<
VREF
VOUT
120 ∂RFBT
∂
(9)
9.2.1.2.9 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in 图 14. The input voltage at which the device turns on is designated
VON and the turnoff voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100 kΩ and then 公
式 10 is used to calculate RENT and VOFF
.
VIN
RENT
EN
RENB
图 14. Setup for External UVLO Application
≈
∆
∆
«
’
÷
◊
VON
÷
RENT
=
-1 ∂RENB
VEN-H
≈
’
÷
÷
◊
VEN-HYS
VEN
∆
VOFF = VON ∂ 1-
∆
«
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
(10)
9.2.1.2.10 Maximum Ambient Temperature
As with any power conversion device, the LMR36520 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
R
θJA, of the device and PCB combination. The maximum internal die temperature for the LMR36520 must be
limited to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load
current. 公式 11 shows the relationships between the important parameters. It is easy to see that larger ambient
temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated using the curves provided in this data sheet. If the desired operating conditions
cannot be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal
Metrics Application Report, the values given in Thermal Information are not valid for design purposes and must
not be used to estimate the thermal performance of the application. The values reported in that table were
measured under a specific set of conditions that are rarely obtained in an actual application.
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(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
where
•
η = efficiency
(11)
The effective RθJA is a critical parameter and depends on many factors such as the following:
•
•
•
•
•
•
Power dissipation
Air temperature/flow
PCB area
Cooper heat-sink area
Number of thermal vias under the package
Adjacent component placement
A typical example of RθJA versus copper board area can be found in 图 15. Note that the data given in this graph
is for illustration purposes only, and the actual performance in any given application depends on all of the factors
mentioned above.
55
4Layer
2Layer
50
45
40
35
30
25
5
10 15 20 25 30 35 40 45 50 55 60
Copper Area (cm2)
Ther
图 15. RθJA versus Copper Board Area
Use the following resources as guides to optimal thermal PCB design and estimate RθJA for a given application
environment:
•
•
•
•
Thermal Design by Insight not Hindsight Application Report
Semiconductor and IC Package Thermal Metrics Application Report
Thermal Design Made Simple with LM43603 and LM43602 Application Report
Using New Thermal Metrics Application Report
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9.2.2 Application Curves
Unless otherwise specified, the following conditions apply: VIN = 24 V, TA = 25°C. 图 32 shows the circuit with the
appropriate BOM from 表 5.
100
90
80
70
60
50
40
30
3.35
3.34
3.33
3.32
3.31
3.3
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
3.29
0.001
0.005
0.005
0.005
0.02 0.05 0.1 0.20.3 0.5
Load Current (A)
1
2
0
0.25
0.5
0.75
1
Load Current (A)
1.25
1.5
1.75
2
Effi
Load
LMR36520A
VOUT = 3.3 V
400 kHz
LMR36520A
VOUT = 3.3 V
400 kHz
图 16. Efficiency
图 17. Load Regulation
100
90
80
70
60
50
40
5.03
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
5.02
5.01
5
VIN = 12V
VIN = 24V
VIN = 36V
VIN = 48V
4.99
4.98
0.001
0.02 0.05 0.1 0.20.3 0.5
Load (A)
1
2
0
0.25
0.5
0.75 1
Load Current (A)
1.25
1.5
1.75
2
Effi
Load
LMR36520A
VOUT = 5 V
400 kHz
LMR36520A
VOUT = 5 V
400 kHz
图 18. Efficiency
图 19. Load Regulation
100
95
90
85
80
75
70
65
60
12.02
12
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 48V
11.98
11.96
11.94
11.92
11.9
VIN = 18V
VIN = 24V
VIN = 36V
VIN = 48V
0.001
0.02 0.05 0.1 0.20.3 0.5
Load Current (A)
1
2
0
0.25
0.5
0.75 1
Load Current (A)
1.25
1.5
1.75
2
Effi
Load
LMR36520A
VOUT = 12 V
400 kHz
LMR36520A
VOUT = 12 V
400 kHz
图 20. Efficiency
图 21. Load Regulation
版权 © 2019–2020, Texas Instruments Incorporated
23
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
13
12.5
12
6
5.5
5
11.5
11
4.5
4
10.5
10
IOUT = 0.5 A
IOUT = 1 A
IOUT = 2 A
IOUT = 0.5 A
IOUT = 1 A
IOUT = 2 A
3.5
3
9.5
9
4
4.2 4.4 4.6 4.8
5
Input Voltage (V)
5.2 5.4 5.6 5.8
6
10
10.5
11
11.5
12
Input Voltage (V)
12.5
13
13.5
14
Drop
Drop
VOUT = 5 V
400 kHz
VOUT = 12 V
400 kHz
图 22. Dropout Characteristic
图 23. Dropout Characteristic
10
36
34
32
30
28
26
24
22
20
VIN = 12V
VIN = 24V
1
0.1
RFBT = 100kW
RFBT = 1MW
0.01
5
10 15 20 25 30 35 40 45 50 55 60 65
Input Voltage (V)
0.1
1
Output Current (mA)
10
VIN_
Iout
VOUT = 3.3 V
RFBT = 100 kΩ
VOUT = 3.3 V
IOUT = 0 A
图 25. Input Supply Current versus Load Current
图 24. Input Supply Current
PGOOD (5V/DIV)
VOUT (2V/DIV)
EN (5V/DIV)
PGOOD (5V/DIV)
VOUT (2V/DIV)
EN (5V/DIV)
IOUT (2A/DIV)
IOUT (2A/DIV)
2ms/DIV
50µs/DIV
VIN = 24 V
VOUT = 3.3 V
ILOAD = 2 A
VIN = 24 V
VOUT = 3.3 V
ILOAD = 2 A
图 26. Enable Start-Up Waveform
图 27. Enable Shutdown Waveform
24
版权 © 2019–2020, Texas Instruments Incorporated
LMR36520
www.ti.com.cn
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
VOUT (100mV/DIV)
IOUT (1A/DIV)
VOUT (200mV/DIV)
IOUT (1A/DIV)
3.3V
5V
100µs/DIV
100µs/DIV
VOUT = 3.3 V
400 kHz
ILOAD = 0.5 A - 2 A
VOUT = 5 V
400 kHz
ILOAD = 0.5 A - 2 A
Slew Rate = 1 A/µs
Slew Rate = 1 A/µs
图 28. Load Transient
图 29. Load Transient
Output Voltage (20mV/DIV)
Output Voltage (50mV/DIV)
Inductor Current (1A/DIV)
Inductor Current (0.5A/DIV)
2µs/DIV
5ms/DIV
VIN = 24 V
VOUT = 5 V
ILOAD = 0 A
VIN = 24 V
VOUT = 5 V
图 31. Output Ripple at 1 A
ILOAD = 1 A
图 30. Output Ripple at No load
版权 © 2019–2020, Texas Instruments Incorporated
25
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
L
VOUT
VIN
SW
VIN
CIN
CHF
CBOOT
4.7 µF
220 nF
COUT
BOOT
EN
0.1 µF
LMR36520
CFF
RFBT
PG
FB
VCC
RFBB
CVCC
1 µF
PGND
图 32. Circuit for Typical Application Curves
表 5. BOM for Typical Application Curves
VOUT
FREQUENCY
L
COUT
RFBT
46.4 kΩ
RFBB
CFF
IC
3.3 V
5 V
400 kHz
400 kHz
400 kHz
6.8 µH, 29.45 mΩ
10 µH, 29.82 mΩ
33 µH, 57 mΩ
3 x 22 µF, 25V
2 x 22 µF, 25V
3 x 22 µF, 25V
20.0 kΩ
20.0 kΩ
9.09 kΩ
None
None
None
LMR36520A
LMR36520A
LMR36520A
34.0 kΩ + 46.4 kΩ
100 kΩ
12 V
9.3 What to Do and What Not to Do
•
•
•
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Do not use the thermal data given in the Thermal Information table to design your application.
26
版权 © 2019–2020, Texas Instruments Incorporated
LMR36520
www.ti.com.cn
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Specifications found in this data sheet. In
addition, the input supply must be capable of delivering the required input current to the loaded regulator. The
average input current can be estimated with 公式 12.
VOUT ∂IOUT
IIN
=
VIN ∂ h
where
•
η is the efficiency
(12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an underdamped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip can cause the
regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162 Simple
Success With Conducted EMI From DC/DC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device and back into the input. This
uncontrolled current flow can damage the device.
版权 © 2019–2020, Texas Instruments Incorporated
27
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Poor PCB layout
can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad
PCB layout can mean the difference between a robust design and one that cannot be mass produced.
Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck
converter, the most critical PCB feature is the loop formed by the input capacitors and power ground, as shown
in 图 33. This loop carries large transient currents that can cause large transient voltages when reacting with the
trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of
this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic
inductance. 图 34 shows a recommended layout for the critical components of the LMR36520.
1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place the bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short, wide traces to the
BOOT and SW pins. Route the SW pin to the N/C pin and used it to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as
a heat dissipation path.
6. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
7. Provide enough PCB area for proper heat-sinking. As stated in the Maximum Ambient Temperature section,
enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and
ambient temperature. The top and bottom PCB layers must be made with two ounce copper; and no less
than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also
be connected to the inner layer heat-spreading ground planes.
8. Keep the switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide
as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
•
•
•
•
Layout Guidelines for Switching Power Supplies Application Report
Simple Switcher PCB Layout Guidelines Application Report
Constructing Your Power Supply- Layout Considerations Seminar
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
28
版权 © 2019–2020, Texas Instruments Incorporated
LMR36520
www.ti.com.cn
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
Layout Guidelines (接下页)
VIN
CIN
SW
GND
图 33. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control circuitry.
Connect the PGND pin to the ground planes using vias next to the bypass capacitors. The PGND pin is
connected directly to the source of the low-side MOSFET switch and is also connected directly to the grounds of
the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to
load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the
ground planes. The other side of the ground plane contains much less noise; use it for sensitive routes.
Use as much copper as possible for the system ground plane, on the top and bottom layers for the best heat
dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1
oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current
conduction impedance, proper shielding, and lower thermal resistance.
版权 © 2019–2020, Texas Instruments Incorporated
29
LMR36520
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
www.ti.com.cn
11.2 Layout Example
GND
HEATSINK
INDUCTOR
VOUT
COUT
COUT
COUT
CHF
GND
VIN
CIN
EN
PGOOD
CVCC
RFBB
GND
GND
HEATSINK
VIA
Ground Plane
VIA
Bottom
Top Trace
Bottom Trace
图 34. Example Layout
30
版权 © 2019–2020, Texas Instruments Incorporated
LMR36520
www.ti.com.cn
ZHCSKA2A –SEPTEMBER 2019–REVISED FEBRUARY 2020
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
•
•
•
•
•
•
•
《直流/直流转换器封装和引脚排列设计如何提高汽车 EMI 性能》 博客文章
降压转换器简介 特性：UVLO、启用、软启动和电源正常状态 培训视频
降压转换器简介：了解模式转换 培训视频
降压转换器简介：最小导通时间和最小关闭时间运行 培训视频
降压转换器简介：了解静态电流规格 培训视频
直流/直流转换器热性能与小解决方案尺寸之间的折衷 培训视频
利用 HotRod 封装降低 EMI 并减小解决方案尺寸 培训视频
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
德州仪器 (TI)，《设计高性能、低 EMI 的汽车电源》 应用报告
德州仪器 (TI)，《Simple Switcher PCB 布局指南》 应用报告
德州仪器 (TI)，《构建电源之布局注意事项》 研讨会
德州仪器 (TI)，《使用 LM4360x 与 LM4600x 简化低辐射 EMI 布局》 应用报告
德州仪器 (TI)，《半导体和 IC 封装热指标》 应用报告
德州仪器 (TI)，《通过 LM43603 和 LM43602 简化热设计》 应用报告
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 商标
E2E is a trademark of Texas Instruments.
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019–2020, Texas Instruments Incorporated
31
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR36520ADDAR
LMR36520FADDAR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 125
36520A
36520F
Samples
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
Addendum-Page 2
PACKAGE OUTLINE
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.34
2.24
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.34
2.24
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(2.34)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
8X (1.55)
1
8
8X (0.6)
(2.34)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
0.125
0.150
0.175
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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