LMR38020_V01 [TI]
LMR38020 SIMPLE SWITCHER® 4.2-V to 80-V, 2-A Synchronous Buck Converter with 40-μA IQ;
| 型号： | LMR38020_V01 |
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TEXAS INSTRUMENTS |
| 描述： | LMR38020 SIMPLE SWITCHER® 4.2-V to 80-V, 2-A Synchronous Buck Converter with 40-μA IQ |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR38020
SNVSC40B – AUGUST 2021 – REVISED NOVEMBER 2021
LMR38020 SIMPLE SWITCHER® 4.2-V to 80-V, 2-A Synchronous Buck Converter with
40-µA IQ
1 Features
3 Description
•
•
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Configured for rugged industrial applications
– Input voltage range: 4.2 V to 80 V
– 2-A continuous output current
– Ultra-low 40-µA operating quiescent current
– > 1.5-mm distance between VIN and GND pin
– Adjustable switching frequency from 200 kHz to
2.2 MHz
– Frequency synchronization to external clock
– Spread spectrum option for reduced EMI
– 97% maximum duty cycle
– Support start-up with pre-biased output
– ±1.0% tolerance voltage reference at room
temperature
The LMR38020 synchronous buck converter is
designed to regulate over a wide input voltage range,
minimizing the need for external surge suppression
components. The LMR38020 operates during input
voltage dips as low as 4.2 V, at nearly 100% duty
cycle if needed, making it an excellent choice for wide
input industrial applications and MHEV/EV systems.
The LMR38020 uses precision enable to provide
flexibility by enabling a direct connection to the
wide input voltage or precise control over device
start-up and shutdown. The power-good flag, with
built-in filtering and delay, offers a true indication of
system status, eliminating the need for an external
supervisor. The device incorporates pseudo-random
spread spectrum form minimal EMI and switching
frequency can be configured between 200 kHz and
2.2 MHz to avoid noise sensitive frequency bands. In
addition, the frequency can be selected for improved
efficiency at low operating frequency or smaller
solution size at high operating frequency.
– Precision enable
– Easy to use with low BOM count
– Integrated synchronous rectification
– Internal compensation for ease of use
– 8-pin HSOIC with PowerPAD™ package
– PFM and forced PWM (FPWM) options
Create a custom design using the LMR38020 with
the WEBENCH® Power Designer
The device has built-in protection features, such as
cycle-by-cycle current limit, hiccup mode short-circuit
protection, and thermal shutdown in case of excessive
power dissipation. The LMR38020 is available in a
8-pin HSOIC PowerPAD™ package.
•
2 Applications
•
•
•
•
Industrial transport
Wireless infrastructure and networking
Power delivery
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
LMR38020
HSOIC (8)
4.89 mm × 3.90 mm
Factory automation and control
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
BOOT
VIN
CIN
VIN
EN
CBOOT
VOUT
COUT
SW
L1
PGND
PG
FB
RT/SYNC
RFBT
RT
RFBB
Simplified Schematic
Efficiency vs Output Current VOUT = 5 V, 400 kHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR38020
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SNVSC40B – AUGUST 2021 – REVISED NOVEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
ESD Ratings..................................................................... 4
7.2 Recommended Operating Conditions.........................4
7.3 Thermal Information....................................................5
7.4 Electrical Characteristics.............................................5
7.5 System Characteristics............................................... 7
7.6 Typical Characteristics................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................16
9 Application and Implementation..................................18
9.1 Application Information............................................. 18
9.2 Typical Application.................................................... 19
9.3 What to Do and What Not to Do............................... 26
10 Power Supply Recommendations..............................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 29
12 Device and Documentation Support..........................30
12.1 Device Support....................................................... 30
12.2 Receiving Notification of Documentation Updates..30
12.3 Support Resources................................................. 30
12.4 Trademarks.............................................................30
12.5 Electrostatic Discharge Caution..............................30
12.6 Glossary..................................................................30
13 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2021) to Revision B (November 2021)
Page
•
Changed document status from Advance Information to Production Data.........................................................1
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5 Device Comparison Table
ORDERABLE PART NUMBER
CURRENT
FPWM
No
SPREAD SPECTRUM
LMR38020SDDAR
2 A
2 A
2 A
1 A
1 A
1 A
Yes
No
LMR38020FDDAR(1)
LMR38020FSDDAR(1)
LMR38010SDDAR(1)
LMR38010FDDAR(1)
LMR38010FSDDAR(1)
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
(1) In Preview
6 Pin Configuration and Functions
GND
EN
1
2
3
4
8
7
6
5
SW
BOOT
PG
EP
VIN
RT/SYNC
FB
Figure 6-1. 8-Pin SO PowerPAD DDA Package (Top View)
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
EN
NO.
1
Power and analog ground terminal. All electrical parameters are measured with respect to this pin.
Connect a high-quality bypass capacitor directly to this pin and VIN with short and wide traces.
G
A
P
2
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN. Do not float.
Input supply to the regulator. Connect a high-quality bypass capacitor or capacitors directly to this pin
and GND with short and wide traces.
VIN
3
Resistor timing or external clock input. An internal amplifier holds this pin at a fixed voltage when
using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal
amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges
stop, the internal amplifier is re-enabled and the operating mode returns to frequency programming
by resistor.
RT/SYNC
4
A
Feedback input to the regulator. Connect to tap point of the feedback voltage divider. Do not float. Do
not ground.
FB
5
6
A
A
Open-drain power-good flag output. Connect to a suitable voltage supply through a current limiting
resistor. High = power OK, low = power bad. The flag pulls low when EN = low. Can be left open
when not used.
PG
Bootstrap supply voltage for the internal high-side driver. Connect a high-quality 100-nF capacitor
from this pin to the SW pin.
BOOT
SW
7
8
P
P
Regulator switch node. Connect to a power inductor.
THERMAL
PAD
EP
Thermal Connect to system ground. Connect to GND and CIN with short, wide traces.
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7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of -40°C to 150°C (unless otherwise noted)(1)
MIN
MAX
85
UNIT
VIN to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–3.5
–0.3
–40
V
V
EN to PGND
VIN+0.3
5.5
Input voltage
FB to PGND
V
RT/SYNC to PGND
CBOOT to SW
5.5
V
5.5
V
SW to PGND
85
V
Output voltage
SW to PGND less than 10-ns transients
PGOOD to PGND
85.3
20
V
V
Junction Temperature TJ
Storage temperature, Tstg
150
150
°C
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
–2000
2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM),
–500
500
per ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
Frequency
Input voltage range after start-up
EN to PGND
4.2
80
VIN
5
V
RT to PGND
V
PGOOD to PGND
20
V
SW to PGND
80
V
Output voltage range for adjustable version (2)
Frequency adjustment range
Synchronization frequency range
Output DC current range (LMR38010)(3)
Output DC current range (LMR38020)(3)
Operating junction temperature TJ range (4)
1
200
300
0
75
V
2200
2100
1
kHz
kHz
A
Sync frequency
Load current
Load current
Temperature
0
2
A
–40
150
°C
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For compliant specifications, see the Electrical Characteristics table.
(2) Under no conditions should the output voltage be allowed to fall below zero volts.
(3) Maximum continuous DC current may be derated when operating with high switching frequency, high ambient temperature, or both.
See the Application and Implementation section for details.
(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 150℃.
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7.3 Thermal Information
LMR38020-Q1
THERMAL METRIC(1)
DDA (HSOIC)
UNIT
8 PINS
42.9
29
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA(Effecitve)
RθJC(top)
RθJB
Junction-to-ambient thermal resistance with TI EVM board
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
54
13.6
4.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
13.8
4.3
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT
Needed to start up
4.2
3.8
V
V
VIN_OPERATE Input operating voltage
Once operating
IQ-SW
ISD
Operating quiescent current
VEN = 3.3 V (PFM variant only)
40
3
µA
Shutdown quiescent current;
measured at VIN pin
VEN = 0 V
10
µA
ENABLE
VEN-H
Enable input high level
Enable input low level
VENABLE rising
VENABLE falling
VEN = 3.3 V
1.1
1.25
1.10
5.0
1.4
V
V
VEN-L
0.95
1.22
ILKG-EN
Enable input leakage current
nA
VOLTAGE REFERENCE (FB PIN)
VREF
Feedback reference voltage
VIN = 4.2 V to 80 V, TJ = 25°C, FPWM
0.99
1
1
1.01
V
V
VREF
Feedback reference voltage
Feedback leakage current
FPWM
0.985
1.015
ILKG-FB
FB = 1.2 V
2.1
nA
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(2)
2-A version
2.6
1.8
1.3
0.9
3.2
2.3
3.8
2.8
1.9
1.5
A
A
A
A
A
A
A
A
A
ILS-LIMIT
ISC
ILS-LIMIT
IL-ZC
Low-side current limit(2)
2-A version
High-side current limit(2)
1-A version
1.6
Low-side current limit(2)
1-A version
1.2
Zero cross detector threshold
Minimum inductor peak current(2)
Minimum inductor peak current(2)
Negative current limit(2)
PFM variants only
0.01
0.5
IPEAK-MIN
IPEAK-MIN
IL-NEG
IL-NEG
2-A version, PFM variants only
1-A version, PFM variants only
2-A version, FPWM variant only
1-A version, FPWM variant only
0.25
–0.9
–0.5
Negative current limit(2)
POWER STAGE
RDS-ON-HS
RDS-ON-LS
tON-MIN
High-side MOSFET ON-resistance
303
133
80
mΩ
mΩ
ns
Low-side MOSFET ON-resistance
Minimum switch on time(3)
Minimum switch off time
VIN = 24 V, IOUT = 1 A
131
300
tOFF-MIN
190
ns
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Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 24 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tON-MAX
Maximum switch on time
5
μs
SWITCHING FREQUENCY AND SYNCHRONIZATION
FOSC
Switching frequency
RT = 49.9 kΩ
430
525
650
8%
2
kHz
Spread of internal oscillator with
spread
spectrum enabled
FSPREAD
VSYNC_HI
–8%
SYNC clock high level threshold
V
V
VSYNC_LO SYNC clock low level threshold
0.6
High duration needed to be recognized
as a pulse
tPULSE_H
50
ns
μs
Time needed for clock to lock to a valid
CLOCK
230
synchronization signal in sync cycles
STARTUP AND TRACKING
tSS
POWER GOOD
VPG-HIGH-UP
VPG-LOW-DN
Internal soft-start time
4
ms
Power-good upper threshold — rising % of FB voltage
Power-good lower threshold — falling % of FB voltage
110%
90%
112%
92%
114%
94%
Power-good hysteresis (rising and
% of FB voltage
VPG-HYS
2.2%
falling)
Minimum input voltage for proper
power-good function
VPG-VALID
2
V
RPG
RPG
Power-good on-resistance
Power-good on-resistance
VEN = 0 V
140
92
Ω
Ω
VEN = 3.3 V
Glitch filter time constant for
PGOOD function
tPGDFLT(fall)
40
μs
THERMAL SHUTDOWN
(1)
TSD-Rising
Thermal shutdown
Thermal shutdown
Shutdown threshold
Recovery threshold
163
150
℃
℃
(1)
TSD-Falling
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
(3) Not production tested. Specified by correlation by design at 1-A load.
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7.5 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃ only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the
case of typical components over the temperature range of TJ = –40℃ to 150℃. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
Adjustable output voltage regulation(1)
Adjustable output voltage regulation(1)
4.2
80
V
VOUT
VOUT
PFM operation
–1.5%
–1.5%
2.5%
1.5%
FPWM operation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
ISUPPLY
DMAX
VHC
Input supply current when in regulation
Maximum switch duty cycle(2)
40
97%
0.4
µA
V
FB pin voltage required to trip short-circuit
hiccup mode
tD
Switch voltage dead time
5
163
150
ns
°C
°C
TSD
TSD
Thermal shutdown temperature
Thermal shutdown temperature
Shutdown temperature
Recovery temperature
(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
= 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.6 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 24 V, fSW=400 kHz.
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
200
150
100
50
PFM, VIN=24V
PFM, VIN=36V
PFM, VIN=48V
PFM, VIN=64V
FPWM, VIN=24V
FPWM, VIN=36V
FPWM, VIN=48V
FPWM, VIN=64V
0
0.001
0.005
0.02 0.05 0.1 0.20.3 0.5
Load Current (A)
1
2
0
20
40
60
80
Input Voltage (V)
FSW = 400 kHz
VOUT = 12.0 V
VOUT = 5 V
RFBB = 100 k
L = 15 μH
Figure 7-1. Efficiency vs Load Current
Figure 7-2. No Load Input Current vs Input Voltage
6
5
4
3
2
1.01
1.005
1
0.995
IOUT = 0A
IOUT = 0.5A
IOUT = 1A
IOUT = 2A
0.99
3
4
5
6
7
8
-50
-25
0
25
50
75
100 125 150 175
FPWM version
Input Voltage (V)
Temperature (oC)
IOUT = 2 A
A.
FSW = 400 kHz
VOUT = 5.0 V
PFM version
Input voltage = 48
V
Figure 7-3. 5-V Dropout
Figure 7-4. Reference Voltage vs Temperature
4
3.5
3
5
UVLO Down (VIN)
UVLO Up (VIN)
4.6
4.2
3.8
3.4
3
2.5
HS Current Limit
LS Current Limit
2
-50
0
50
100
150
Temperature (oC)
-50
0
50
100
150
VOUT = 3.3 V
FPM version
Temperature (oC)
Figure 7-5. High-Side and Low-Side Current Limit
vs Temperature
Figure 7-6. VIN UVLO vs Temperature
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8 Detailed Description
8.1 Overview
The LMR38020 converter is an easy-to-use synchronous step-down DC-DC converter that operates from a
4.2-V to 80-V supply voltage. It is capable of delivering up to 2-A DC load current in a small solution size.
The LMR38020 employs peak-current mode control. The device enters PFM mode at light load to achieve high
efficiency for PFM version. A FPWM version is provided to achieve low output voltage ripple, tight output voltage
regulation, and constant switching frequency at light load. The device is internally compensated, which reduces
design time, and requires few external components.
Additional features, such as precision enable and internal soft start, provide a flexible and easy-to-use solution
for a wide range of applications. Protection features include thermal shutdown, VIN undervoltage lockout, cycle-
by-cycle current limit, and hiccup mode short-circuit protection.
The family requires very few external components and has a pinout designed for a simple, optimum PCB layout.
8.2 Functional Block Diagram
EN
VCC
Enable
LDO
VIN
Precision
Enable
BOOT
Internal
SS
HS I Sense
EA
REF
Rc
Cc
TSD
UVLO
PG
PWM CONTROL LOGIC
PFM
SW
Detector
OV/UV
Detector
FB
Slope
Comp
Freq
Foldback
Zero
Cross
HICCUP
Detector
RT/SYNC
Oscillator with PLL
LS I Sense
FB
PGND
8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The LMR38020 is a step-down synchronous buck converter with integrated high-side (HS) and low-side (LS)
switches (synchronous rectifier). The LMR38020 supplies a regulated output voltage by turning on the high-side
and low-side NMOS switches with controlled duty cycle. During high-side switch on time, the SW pin voltage
swings up to approximately VIN, and the inductor current, iL, increases with a linear slope (VIN – VOUT) / L. When
the high-side switch is turned off by the control logic, the low-side switch is turned on after an anti-shoot-through
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dead time. Inductor current discharges through the low-side switch with a slope of –VOUT / L. The control
parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch on time
and TSW is the switching period. The converter control loop maintains a constant output voltage by adjusting the
duty cycle D. In an ideal buck converter where losses are ignored, D is proportional to the output voltage and
inversely proportional to the input voltage: D = VOUT / VIN.
The LMR38020 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
on time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, making it easy to design and providing stable operation with almost any combination of
output capacitors. The converter operates with fixed switching frequency at normal load condition. At light-load
condition, the LMR38020 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for
low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).
8.3.2 Adjustable Output Voltage
A precision 1.0-V reference voltage (VREF) is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from the output voltage to the FB
pin. It is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select
the bottom-side resistor RFBB for the desired divider current and use Equation 1 to calculate the top-side resistor
RFBT. RFBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be
used if static loading is desired to reduce VOUT offset in PFM operation. Lower RFBT reduces efficiency at very
light load. Less static current goes through a larger RFBT and can be more desirable when light-load efficiency
is critical. RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible
to noise. Larger RFBT values require more carefully designed feedback path on the PCB. The tolerance and
temperature variation of the resistor dividers affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
Figure 8-1. Output Voltage Setting
VOUT - VREF
RFBT
=
× RFBB
VREF
(1)
8.3.3 Enable
The voltage on the EN pin controls the ON or OFF operation of the LMR38020. A voltage of less than 0.95
V shuts down the device, while a voltage of more than 1.4 V is required to start the converter. The EN pin is
an input and cannot be left open or floating. The simplest way to enable the operation of the LMR38020 is to
connect the EN to VIN. This allows self-start-up of the LMR38020 when VIN is within the operating range.
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 8-2) to establish
a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, making sure the user has reliable operation or
supply protection, such as a battery discharge level. An external logic signal can also be used to drive EN input
for system sequencing and protection. Note that the EN pin voltage must never be higher than VIN + 0.3 V. It is
not recommended to apply EN voltage when VIN is 0 V.
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VIN
RENT
EN
RENB
Figure 8-2. System UVLO by Enable Divider
8.3.4 Switching Frequency and Synchronization (RT/SYNC)
The switching frequency of the LMR38020 can be programmed by the resistor RT from the RT/SYNC pin and
GND pin. The RT/SYNC pin cannot be left floating or shorted to ground. To determine the timing resistance for
a given switching frequency, use Equation 2 or the curve in Figure 8-3. Table 8-1 gives typical RT values for a
given fSW
.
-1 . 027
R
k Ω = 30970 × f
kHz
SW
(2)
T
Figure 8-3. RT Versus Frequency Curve
Table 8-1. Typical Frequency Setting RT Resistance
fSW (kHz)
RT (kΩ)
200
400
133
64.9
52.3
34.8
25.5
16.9
12.7
11.5
500
750
1000
1500
2000
2200
The LMR38020 switching action can also be synchronized to an external clock from 300 kHz to 2.1 MHz.
Connect a square wave to the RT/SYNC pin through either circuit network shown in Figure 8-4. The internal
oscillator is synchronized by the falling edge of external clock. The recommendations for the external clock
include: high level no lower than 2.0 V, low level no higher than 0.6 V, and have a pulse width greater than 50
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ns. When using a low impedance signal source, the frequency setting resistor RT is connected in parallel with an
AC coupling capacitor, CCOUP, to a termination resistor, RTERM (for example, 50 Ω). The two resistors in series
provide the default frequency setting resistance when the signal source is turned off. A 10-pF ceramic capacitor
can be used for CCOUP
.
C
COUP
PLL
RT/SYNC
PLL
RT/SYNC
R
T
Lo-Z
Clock
Hi-Z
Clock
Source
Source
R
T
R
TERM
Figure 8-4. Synchronizing to an External Clock
8.3.5 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR38020 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than tPG do not trip the power-good flag. Note that during initial power up, a delay of approximately
4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This
delay only occurs during start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT, through a 100-kΩ resistor, as desired. If this function
is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With
EN low, power good remains valid as long as the input voltage is greater than or equal to 2 V (typical). Limit
the current into the power-good flag pin to less than 5-mA D.C. The maximum current is internally limited to
approximately 35 mA when the device is enabled and approximately 65 mA when the device is disabled. The
internal current limit protects the device from any transient currents that can occur when discharging a filter
capacitor connected to this output.
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VOUT
VPG-HIGH_UP (112%)
VPG-HIGH-UP – VPG-HYS
VPG-LOW-DN + VPG-HYS
VPG-LOW-DN (92%)
PG
High = Power Good
Low = Fault
Figure 8-5. Static Power-Good Operation
Glitches do not cause false opera on nor reset mer
VOUT
VPG-LOW-DN + VPG-HYS
VPG-LOW-DN (92%)
< tPG
PG
tPG
tPG
tPG
Figure 8-6. Power-Good-Timing Behavior
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8.3.6 Minimum On Time, Minimum Off Time, and Frequency Foldback
Minimum on time (TON_MIN) is the smallest duration of time that the high-side switch can be on. TON_MIN is
typically 75 ns in the LMR38020. Minimum off time (TOFF_MIN) is the smallest duration that the high-side switch
can be off. TOFF_MIN is typically 190 ns. In CCM operation, TON_MIN and TOFF_MIN limit the voltage conversion
range without switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is:
DMIN = TON_MIN × fSW
(3)
(4)
The maximum duty cycle without frequency foldback allowed is:
DMAX = 1 - TOFF_MIN × fSW
Given a required output voltage, the maximum VIN without frequency foldback can be found by:
VOUT
VIN_MAX
=
fSW × TON_MIN
(5)
(6)
The minimum VIN without frequency foldback can be calculated by:
VOUT
VIN_MIN
=
1- fSW × TOFF_MIN
In the LMR38020, a frequency foldback scheme is employed once the TON_MIN or TOFF_MIN is triggered, which
can extend the maximum duty cycle or lower the minimum duty cycle.
The on time decreases while VIN voltage increases. Once the on time decreases to TON_MIN, the switching
frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in
regulation according to Equation 3.
The frequency foldback scheme also works once larger duty cycle is needed under low VIN condition. The
frequency decreases once the device hits its TOFF_MIN, which extends the maximum duty cycle according to
Equation 4. In such condition, the frequency can be as low as approximately 133 kHz minimum. Wide range of
frequency foldback allows the LMR38020 output voltage stay in regulation with a much lower supply voltage VIN,
which leads to a lower effective dropout.
The fixed frequency operation at FPWM mode with switching frequency greater than 1.2 MHz, is maintained
with minimum load current about 100 mA for wider input voltage range. And for very light load and switching
frequency over 1.2 MHz, frequency drop can be expected during mintoff frequency foldback.
With frequency foldback, VIN_MAX is raised, and VIN_MIN is lowered by decreased fSW
.
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1450
1250
1150
1050
950
1300
1150
1000
850
850
700
750
6.5
50
60
70
80
7
7.5
8
8.5
9
Input Voltage (V)
VOUT = 5 V
Input Voltage (V)
FSW = 1.1 MHz
IOUT = 2 A
FSW = 1.1 MHz
VOUT = 5 V
IOUT = 2 A
Figure 8-7. Typical Frequency Foldback at TON_MIN
Figure 8-8. Typical Frequency Foldback at TOFF_MIN
8.3.7 Bootstrap Voltage
The LMR38020 provides an integrated bootstrap voltage converter. A small capacitor between the CB and SW
pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the bootstrap capacitor
is 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher is
recommended for stable performance over temperature and voltage.
8.3.8 Overcurrent and Short Circuit Protection
The LMR38020 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and
valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch
current is compared to the output of the error amplifier (EA) minus slope compensation every switching cycle.
The peak current of high-side switch is limited by a clamped maximum peak current threshold, Ihigh side_LIMIT
which is constant.
,
The current going through low-side MOSFET is also sensed and monitored. When the low-side switch turns on,
the inductor current begins to ramp down. The low-side switch is turned OFF at the end of a switching cycle if its
current is above the low-side current limit, ILS_LIMIT. The low-side switch is kept on so that inductor current keeps
ramping down until the inductor current ramps below the ILS_LIMIT. Then the low-side switch is turned OFF and
the high-side switch is turned on after a dead time. This is somewhat different to the more typical peak current
limit and results in Equation 7 for the maximum load current.
V
- VOUT
VOUT
VIN
(
)
×
IN
IOUT_MAX = ILS
+
2 × fSW × L
(7)
If the feedback voltage is lower than 40% of the VREF, the current of the low-side switch triggers ILS_LIMIT for 256
consecutive cycles, hiccup current protection mode is activated. In hiccup mode, the converter shuts down and
stays off for a period of hiccup, THICCUP (76-ms typical), before the LMR38020 tries to start again. If overcurrent
or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode reduces
power dissipation under severe overcurrent conditions and prevents overheating and potential damage to the
device.
For FPWM version, the inductor current is allowed to go negative. When this current exceeds the low-side
negative current limit, ILS_NEG, the low-side switch is turned off and high-side switch is turned on immediately.
This is used to protect the low-side switch from excessive negative current.
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8.3.9 Soft Start
The integrated soft-start circuit prevents input inrush current impacting the LMR38020 and the input power
supply. Soft start is achieved by slowly ramping up the target regulation voltage when the device is first enabled
or powered up. The typical soft-start time is 4.0 ms.
The LMR38020 also employs overcurrent protection blanking time, TOCP_BLK (18-ms typical) at the beginning of
power up. Without this feature, in applications with a large amount of output capacitors and high VOUT, the inrush
current is large enough to trigger the current-limit protection, which can make the device enter into Hiccup mode.
The device tries to restart after the hiccup period, then hits the current limit and enters into Hiccup mode again,
so VOUT cannot ramp up to the setting voltage ever. By introducing OCP blanking feature, the hiccup protection
function is disabled during TOCP_BLK, and LMR38020 charges the VOUT with its maximum limited current, which
maximizes the output current capacity during this period. Note that the peak current limit (IHS_LIMIT) and valley
current limit (ILS_LIMIT) protection functions are still available during TOCP_BLK, so there is no concern of inductor
current running away.
8.3.10 Thermal Shutdown
The LMR38020 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 163°C. Both high-side and low-side FETs stop switching in thermal shutdown. Once the die
temperature falls below 150°C, the device reinitiates the power-up sequence controlled by the internal soft-start
circuitry.
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode, the device moves between PWM and PFM as the load changes. At light loads, the regulator
operates in PFM. At higher loads, the mode changes to PWM.
In PWM, the regulator operates as a constant frequency, current mode, full-synchronous converter using PWM
to regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load.
The duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency
of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency (see the
Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required
to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger output
voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light loads.
The actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and load.
8.4.2 Forced PWM Operation
The forced PWM option is choiced for cases when constant frequency operation is more important than light-
load efficiency.
In FPWM operation, the diode emulation feature is turned off. This means that the device remains in CCM under
light loads. Under conditions where the device must reduce the on time or off time below the compliant minimum
to maintain regulation, the frequency reduces to maintain the effective duty cycle required for regulation. This
occurs for very high and very low input and output voltage ratios. In FPWM mode, a limited reverse current is
allowed through the inductor, allowing power to pass from the output of the regulator to the input of the regulator.
Note that in FPWM mode, larger currents pass through the inductor, if lightly loaded, than in Auto mode. Once
loads are heavy enough to necessitate CCM operation, FPWM mode has no measurable effect on regulator
operation.
8.4.3 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage
is reduced to the output voltage, the off time of the high-side MOSFET starts to approach the minimum value.
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Beyond this point, the switching can become erratic and the output voltage falls out of regulation. To avoid this
problem, the LMR38020 automatically reduces the switching frequency to increase the effective duty cycle and
maintain regulation. In this data sheet, the dropout voltage is defined as the difference between the input and
output voltage when the output has dropped by 1% of the nominal value. Under this condition, the switching
frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4-V short circuit detection
threshold is not activated when in dropout mode.
8.4.4 Minimum Switch On Time
Every switching regulator has a minimum controllable on time dictated by the inherent delays and blanking
times associated with the control circuits. This imposes a minimum switch duty cycle, therefore, a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR38020 automatically reduces the switching frequency when the
minimum on-time limit is reached. This way, the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage for a given output voltage, before
frequency foldback occurs, is found in Equation 8. As the input voltage is increased, the switch on time (duty
cycle) reduces to regulate the output voltage. When the on time reaches the limit, the switching frequency drops,
while the on time remains fixed.
VOUT
V
Ç
IN
tON ∂ fSW
(8)
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMR38020 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum output current of 2 A. The following design procedure can be used to select
components for the LMR38020. Alternately, use the WEBENCH Design Tool to generate a complete design. This
tool utilizes an iterative design procedure and has access to a comprehensive database of components. This
allows the tool to create an optimized design and allows the user to experiment with various options.
Note
All of the capacitance values given in the following application information refer to effective values
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias
and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors
with an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to
ensure that the minimum value of effective capacitance is provided.
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9.2 Typical Application
Figure 9-1 show a typical application circuit for the LMR38020. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick-start guide, Table 9-1 provides typical
component values for a range of the most common output voltages.
L
VOUT
VIN
SW
VIN
EN
CIN
CHF
CBOOT
100 nF
4.7 µF
COUT
BOOT
VPU
0.1 µF
LMR38020
100 kΩ
RFBT
PG
FB
RT/SYNC
RFBB
RT
GND
Figure 9-1. Example Application Circuit
Table 9-1. Typical External Component Values for 2-A Output Current
VIN (V)
ƒSW
(kHz)
NOMINAL COUT (RATED MINIMUM COUT (RATED
VOUT (V)
L (µH)
RFBT (Ω)
RFBB (Ω)
CAPACITANCE)
CAPACITANCE)
Typical
400
1000
400
48
24
48
24
48
5
15
6.8
33
10
47
3 × 22 µF
2 × 22 µF
1× 22 µF
2 × 10 µF
1 × 22 µF
2 × 22 µF
2 × 15 µF
1 × 15 µF
1 × 10 µF
1 × 15 µF
100 k
100 k
100 k
100 k
100 k
24.9 k
24.9 k
9.09 k
9.09 k
4.32 k
5
12
12
24
1000
500
9.2.1 Design Requirements
Section 9.2.2 provides a detailed design procedure based on Table 9-2.
Table 9-2. Detailed Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
6 V to 80 V
5 V
Output voltage
Maximum output current
Switching frequency
0 A to 2 A
400 kHz
9.2.2 Detailed Design Procedure
The following design procedure applies to Figure 9-1 and Table 9-1.
9.2.2.1 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, hence, a more
compact design. For this example, 400 kHz is used.
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9.2.2.2 FB for Adjustable Output
In an adjustable output voltage version, pin 5 of the device is FB. The output voltage of the LMR38020 is
externally adjustable using an external resistor divider network. The divider network is comprised of RFBT and
RFBB, and closes the loop between the output voltage and the converter. The converter regulates the output
voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF. The resistance of the
divider is a compromise between excessive noise pickup and excessive loading of the output. Smaller values of
resistance reduce noise sensitivity, but also reduce the light-load efficiency. The recommended value for RFBT
is 100 kΩ with a maximum value of 1 MΩ. Once RFBT is selected, Equation 9 is used to select RFBB. VREF is
nominally 1 V.
RFBT
RFBB
=
»
…
ÿ
VOUT
VREF
-1
Ÿ
⁄
(9)
For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ is chosen.
9.2.2.3 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based
on the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of
the maximum output current. Experience shows that the best value for inductor ripple current is 30% of the
maximum load current. Note that when selecting the ripple current for applications with much smaller maximum
load than the maximum available from the device, use the maximum device current. Equation 10 can be used to
determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example,
choose K = 0.4 and find an inductance of L = 14 µH. Select the next standard value of L = 15 µH.
(
V
IN - VOUT
)
VOUT
L =
∂
fSW ∂K ∂IOUTmax
V
IN
(10)
Ideally, the saturation current rating of the inductor is at least as large as the high-side switch current limit,
ISC. This makes sure that the inductor does not saturate, even during a short circuit on the output. When the
inductor core material saturates, the inductance falls to a very low value, causing the inductor current to rise very
rapidly. Although the valley current limit, ILIMIT, is designed to reduce the risk of current runaway, a saturated
inductor can cause the current to rise to high values very rapidly. This can lead to component damage. Do not
allow the inductor to saturate. Inductors with a ferrite core material have very hard saturation characteristics, but
usually have lower core losses than powdered iron cores. Powered iron cores exhibit a soft saturation, allowing
some relaxation in the current rating of the inductor. However, they have more core losses at frequencies above
approximately 1 MHz. In any case, the inductor saturation current must not be less than the maximum peak
inductor current at full load.
To avoid subharmonic oscillation, the inductance value must not be less than that given in Equation 11:
VOUT
LMIN í M∂
fSW
(11)
where
•
•
•
LMIN = minimum inductance (H)
M = 0.25 for a 2-A device
ƒSW = switching frequency (Hz)
The maximum inductance is limited by the minimum current ripple for the current mode control to perform
correctly. As a rule-of-thumb, the minimum inductor ripple current must be no less than about 10% of the device
maximum rated current under nominal conditions.
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9.2.2.4 Output Capacitor Selection
The current mode control scheme of the LMR38020 devices allows operation over a wide range of output
capacitance. The output capacitor bank is usually limited by the load transient requirements and stability rather
than the output voltage ripple. Refer to Table 9-1 for typical output capacitor value for 5-V to 24-V output
voltages. For a 5-V output design, 3 × 22-µF ceramic output capacitors are recommended for this example. For
other designs with other output voltages, WEBENCH can be used as a starting point for selecting the value of
output capacitor.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help reduce high-frequency noise. Small-case size ceramic capacitors in the range of 1
nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
Limit the maximum value of total output capacitance to approximately 10 times the design value, or 1000
µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of
start-up at full load and loop stability must be performed.
9.2.2.5 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum ceramic capacitance of 4.7 µF is required
on the input of the LMR38020. This must be rated for at least the maximum input voltage that the application
requires, preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and maintain the input voltage during load transients. In addition, a small case size 100-nF to
220-nF ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high
frequency bypass for the control circuits internal to the device. For this example a 4.7-µF, 100-V, X7R (or better)
ceramic capacitor is chosen. The 100-nF must also be rated at 100-V with an X7R dielectric.
It is often desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is especially
true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor or capacitors. The approximate
RMS value of this current can be calculated from Equation 12 and must be checked against the manufacturers'
maximum ratings.
IOUT
IRMS
@
2
(12)
9.2.2.6 CBOOT
The LMR38020 requires a bootstrap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 16 V is required.
9.2.2.7 External UVLO
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 9-2. The turn-on voltage is designated as VON while the
turn-off voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩ to 100 kΩ, then Equation 13 is
used to calculate RENT and VOFF
.
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VIN
RENT
EN
RENB
Figure 9-2. Setup for External UVLO Application
≈
∆
«
’
VON
RENT = RENB
∂
-1
÷
◊
VEN-H
≈
’
÷
VON
VOFF = VEN-L
∂
∆
«
VEN-H ◊
(13)
where
•
•
VON = VIN turn-on voltage
VOFF = VIN turn-off voltage
9.2.2.8 Maximum Ambient Temperature
As with any power conversion device, the device dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal resistance,
RθJA, of the device and PCB combination. The maximum junction temperature for the LMR38020 must be limited
to 150°C. This establishes a limit on the maximum device power dissipation and, therefore, the load current.
Equation 14 shows the relationships between the important parameters. It is easy to see that larger ambient
temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
cannot be found in one of the curves, interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in the Semiconductor and IC Package Thermal
Metrics Application Report, the values given in the Thermal Information are not valid for design purposes and
must not be used to estimate the thermal performance of the application. The values reported in that table were
measured under a specific set of conditions that are rarely obtained in an actual application.
(
TJ - TA
RqJA
)
∂
h
1- h
1
IOUT
=
∂
MAX
VOUT
(14)
where
η = efficiency
The effective RθJA is a critical parameter and depends on many factors such as the following:
•
•
•
•
•
•
•
Power dissipation
Air temperature/flow
PCB area
Copper heat-sink area
Number of thermal vias under the package
Adjacent component placement
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application
environment:
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•
•
•
•
•
Thermal Design by Insight not Hindsight Application Report
A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
Semiconductor and IC Package Thermal Metrics Application Report
How to Properly Evaluate Junction Temperature with Thermal Metrics Application Report
Using New Thermal Metrics Application Report
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 48 V, L = 15 µH, TA = 25°C.
LMR38020
VOUT = 5 V
400 kHz
LMR38020
VOUT = 5 V
400 kHz
Figure 9-3. Start-Up by VIN
Figure 9-4. Start-Up by EN
LMR38020
VOUT = 5 V
No Load
LMR38020
VOUT = 5 V
400 kHz
AC Coupled
AC Coupled
Figure 9-5. PFM Switching
Figure 9-6. Full Load Switching
LMR38020
VOUT = 5 V
Short Recovery
LMR38020
VOUT = 5 V
2 A to Short
Figure 9-8. Short Circuit Recovery
Figure 9-7. Short Circuit Applied
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LMR38020
VOUT = 5 V
400 kHz
LMR38020F
VOUT = 5 V
Bias to 3 V
No Load
Figure 9-10. Frequency Synchronization
Figure 9-9. Start-Up with Prebias
LMR38020
VOUT = 5 V
400 kHz
LMR38020
VOUT = 5 V
400 kHz
(AC Coupled)
(AC Coupled)
200 mA to 1.8 A at 200 mA/µs
10 V to 70 V at 200 V/ms
Figure 9-11. Load Transient
Figure 9-12. Line Transient
5.3
5.2
5.1
5
12.3
12.2
12.1
12
VIN=24V
VIN=36V
VIN=48V
VIN=64V
VIN=24V
VIN=36V
VIN=48V
VIN=64V
11.9
11.8
4.9
4.8
0
0.4
0.8
1.2
1.6
2
0
0.4
0.8
1.2
1.6
2
Output Current (A)
Output Current (A)
LMR38020
VOUT = 12 V
400 kHz
LMR38020
VOUT = 5 V
400 kHz
PFM Version
PFM Version
Figure 9-14. 12-V Load Regulation
Figure 9-13. 5-V Load Regulation
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9.3 What to Do and What Not to Do
•
•
•
•
•
•
Do not exceed the Absolute Maximum Ratings.
Do not exceed the Recommended Operating Conditions.
Do not exceed the ESD Ratings.
Do not allow the EN input to float.
Do not allow the output voltage to exceed the input voltage, nor go below ground.
Follow all the guidelines and suggestions found in this data sheet before committing the design to production.
TI application engineers are ready to help critique your design and PCB layout to help make your project a
success.
10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and
Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable
of delivering the required input current to the loaded regulator. The average input current can be estimated with
Equation 15.
VOUT ∂IOUT
IIN
=
VIN ∂ h
(15)
where
•
η = efficiency
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to
the regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient
is applied to the output. If the application is operating close to the minimum input voltage, this dip can cause
the regulator to momentarily shutdown and reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator, use an aluminum or tantalum input capacitor in parallel with the
ceramics, or both. The moderate ESR of these types of capacitors help damp the input resonant circuit and
reduce any overshoots. A value in the range of 22 µF to 68 µF is usually sufficient to provide input damping and
help to hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead
to instability, as well as some of the effects mentioned above, unless it is designed carefully. The AN-2162
Simple Success With Conducted EMI From DCDC Converters User's Guide provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases, a transient voltage suppressor (TVS) is used on the input of regulators. One class of this
device has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than
the output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow can damage the device.
The input voltage must not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors discharges through the internal parasitic diode found between the VIN and SW pins of
the device. During this condition, the current can become uncontrolled, possibly causing damage to the device. If
this scenario is considered likely, then a Schottky diode between the input supply and the output should be used.
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter,
the most critical PCB feature is the loop formed by the input capacitor or input capacitors, and power ground,
as shown in Figure 11-1. This loop carries large transient currents that can cause large transient voltages when
reacting with the trace inductance. These unwanted transient voltages will disrupt the proper operation of the
converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. Figure 11-2 shows a recommended layout for the critical components of the
LMR38020.
•
•
•
Place the input capacitor or capacitors as close as possible to the VIN and GND terminals. VIN and GND
pins are adjacent, simplifying the input capacitor placement.
Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the BOOT
and SW pins.
Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed
near any noise source (such as the SW node) that can capacitively couple into the feedback path of the
regulator.
•
•
Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as a
heat dissipation path.
Connect the thermal pad to the ground plane. The SOIC package has a thermal pad (PAD) connection that
must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an electrical
ground connection for the regulator. The integrity of this solder connection has a direct bearing on the total
effective RθJA of the application.
•
•
Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any
voltage drops on the input or output paths of the converter and maximizes efficiency.
Provide enough PCB area for proper heat sinking. Enough copper area must be used to keep a low RθJA
commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB
layers with two-ounce copper; and no less than one ounce. With the SOIC package, use an array of
,
heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB
design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer
heat-spreading ground planes.
•
Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node should be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
•
•
•
•
Layout Guidelines for Switching Power Supplies
Simple Switcher PCB Layout Guidelines
Construction Your Power Supply- Layout Considerations
Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
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VIN
KEEP
CURRENT
LOOP
CIN
SW
SMALL
GND
Figure 11-1. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. PGND pins are connected directly to the source of the low-side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
TI recommends providing adequate device heat sinking by utilizing the thermal pad (PAD) of the device as the
primary thermal path. Use a minimum 4 × 3 array of 10-mil thermal vias to connect the PAD to the system
ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible,
for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with
the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with
enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding, and
lower thermal resistance.
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11.2 Layout Example
GND
HEATSINK
INDUCTOR
VOUT
COUT
COUT
COUT
GND
CHF
EN
CIN
PGOOD
VIN
RT
RFBB
GND
GND
HEATSINK
VIA
Ground Plane
Top Trace
Bo om Trace
VIA Bo om
Figure 11-2. Example Layout for HSOIC (DDA) Package
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PLMR38020FDDAR
ACTIVE SO PowerPAD
DDA
8
75
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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