LMR51430XDDCR [TI]

具有 40µA IQ 的 SIMPLE SWITCHER® 4.5V 至 36V、3A 同步降压转换器

| DDC | 6 | -40 to 150;


型号：	LMR51430XDDCR
厂家：	TEXAS INSTRUMENTS
描述：	具有 40µA IQ 的 SIMPLE SWITCHER® 4.5V 至 36V、3A 同步降压转换器 \| DDC \| 6 \| -40 to 150 转换器
文件：	总33页 (文件大小：1719K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMR51430

ZHCSMO2A –JUNE 2022 –REVISED NOVEMBER 2022

采用SOT-23 封装的LMR51430 SIMPLE SWITCHER^®电源转换器4.5V 至36V、3A

同步降压转换器

1 特性

3 说明

• 功能安全型

LMR51430 是一款简单易用的宽 V_INSIMPLE

SWITCHER^®电源转换器同步降压转换器，能够驱动

高达3A 的负载电流。该器件具有4.5 V 至36V 的宽输

入范围，适用于从非稳压源进行电源调节的各种工业应

用。

– 有助于进行功能安全系统设计的文档

• 专用于条件严苛的工业应用

– 4.5V 至36V 输入电压范围

– 3A 持续输出电流

– 最短打开时间：70 ns

LMR51430 以 500kHz 和 1.1MHz 的开关频率运行，

支持使用相对较小的电感器，以实现更好的解决方案尺

寸。该器件具有可在轻负载时实现高效率的 PFM 版本

和实现恒定频率的 FPWM 版本，并可在整个负载范围

内实现低输出电压纹波。软启动和补偿电路在内部实

现，从而更大限度地减少了器件所用的外部元件。

– 500kHz 和1.1MHz 的固定开关频率选项

– -40°C 至150°C 的结温范围

– 98% 最大占空比

– 带预偏置输出的启动

– 具有断续模式的内部短路保护

– ±1.5% 容差电压基准

– 精密使能

该器件内置保护功能，例如逐周期电流限制、断续模式

短路保护以及功耗过大情况下的热关断功能。

LMR51430 采用6 引脚SOT-23 封装。

• 解决方案小巧且易于使用

– 集成同步整流

– 内置补偿功能，便于使用

– SOT-23 封装

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

• 与TPS54202 和TPS54302 引脚对引脚兼容

• 提供PFM 和强制PWM (FPWM) 选项

• 使用LMR51430 并借助WEBENCH^®Power

Designer 创建定制设计方案

LMR51430

DBV (SOT-23, 6)

2.90mm × 1.60mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 电器

• 楼宇自动化

• 电机驱动

• 通用宽输入电压电源

100

V_INup to 36 V

VIN

C_IN

C_BOOT

V_OUT

R_FBT

PFM, V_IN=8V

PFM, V_IN=12V

PFM, V_IN=24V

PFM, V_IN=36V

FPWM, V_IN=8V

FPWM, V_IN=12V

GND

C_OUT

R_FBB

FPWM, V_IN=24V

FPWM, V_IN=36V

简化原理图

0.001

0.005

0.02 0.05 0.1 0.2

Load Current (A)

0.5

2 3

D003_SLUSEF4.grf

效率与输出电流间的关系，V_OUT= 5V，500kHz

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSEF4

LMR51430

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ZHCSMO2A –JUNE 2022 –REVISED NOVEMBER 2022

Table of Contents

8.3 Feature Description...................................................10

8.4 Device Functional Modes..........................................15

9 Application and Implementation..................................16

9.1 Application Information............................................. 16

9.2 Typical Application.................................................... 16

9.3 Power Supply Recommendations.............................21

9.4 Layout....................................................................... 21

10 Device and Documentation Support..........................24

10.1 Device Support....................................................... 24

10.2 Documentation Support.......................................... 24

10.3 接收文档更新通知................................................... 24

10.4 支持资源..................................................................24

10.5 Trademarks.............................................................24

10.6 Electrostatic Discharge Caution..............................24

10.7 术语表..................................................................... 25

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 Recommended Operating Conditions.........................4

7.4 Thermal Information ...................................................5

7.5 Electrical Characteristics.............................................5

7.6 System Characteristics............................................... 6

7.7 Typical Characteristics................................................7

8 Detailed Description........................................................9

8.1 Overview.....................................................................9

8.2 Functional Block Diagram.........................................10

Information.................................................................... 25

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (June 2022) to Revision A (November 2022)

Page

• 在SIMPLE SWITCHER^®商标后添加了“电源转换器”....................................................................................1

• 已切换“效率与输出电流间的关系，V_OUT= 5V、500kHz”中的“PFM”和“FPWM”曲线标签.................... 1

• Switched the "PFM" and "FPWM" curve label in Figure7-1, Figure7-2, and Figure 7-3..................................... 7

• Changed the t_hiccup in Overcurrent and Short-Circuit Protection to 135 ms.................................................14

• Added 表9-2 ....................................................................................................................................................16

• Changed the quoted equation number in the design example as "Equation 12," "Equation 13," and "Equation

14".....................................................................................................................................................................18

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5 Device Comparison Table

Orderable Part Number

LMR51430XDDCR

LMR51430XFDDCR

LMR51430YDDCR

LMR51430YFDDCR

Frequency

500 kHz

1.1 MHz

PFM OR FPWM

PFM

Output

Adjustable

FPWM

PFM

FPWM

6 Pin Configuration and Functions

GND

VIN

图6-1. 6-Pin SOT-23 DBV Package (Top View)

表6-1. Pin Functions

Type⁽¹⁾

Description

Name

NO.

Power ground terminals. This pin connects to the source of the low-side FET internally. Connect to

system ground, and the ground side of CIN and COUT. The path to CIN must be as short as possible.

GND

Switching output of the converter. This pin connects to the source of the high-side FET and drain of

the low-side FET. Connect this pin to the power inductor.

VIN

Supply input terminal to internal bias LDO and high-side FET. Connect this pin to the input supply and

input bypass capacitors, C_IN. Input bypass capacitors must be directly connected to this pin and GND.

Feedback input to the converter. Connect a resistor divider to set the output voltage. Never short this

pin to ground during operation.

Precision enable input to the converter. Do not float. High = on, low = off. This pin can be tied to VIN.

Precision enable input allows adjustable UVLO by an external resistor divider. If the EN pin is left

floating, the device is disabled.

Bootstrap capacitor connection for the high-side FET driver. Connect a high quality 100-nF capacitor

from this pin to the SW pin.

(1) A = Analog, P = Power, G = Ground

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–3.0

–0.3

–40

MAX

UNIT

VIN

Input voltage

V_IN+ 0.3

5.5

SW, DC

SW, transient < 20 ns

Output voltage

43.5

5.5

CB to SW

Junction temperature, T_J

Storage temperature, T_stg

150

°C

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

Electrostatic

discharge

V_(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted)⁽¹⁾

MIN

4.5

NOM

MAX

UNIT

VIN to GND

EN⁽²⁾

Input voltage

V_IN

4.5

(3)

Output voltage V_OUT

Output current Iout⁽⁴⁾

0.6

95% of V_IN

T_J

Operating junction temperature⁽⁵⁾

+150

°C

–40

(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific

performance limits. For compliant specifications, see the Electrical Characteristics table.

(2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.

(3) Under no conditions must the output voltage be allowed to fall below 0 V.

(4) Maximum continuous DC current can be derated when operating with high switching frequency, high ambient temperature, or both.

See Application and Implementation section for details.

(5) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 150℃.

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7.4 Thermal Information

The value of R_θJAgiven in this table is only valid for comparison with other packages and cannot be used for design

purposes. These values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do

not represent the performance obtained in an actual application. For example, with a 2-layer PCB, a R_θJA= 80℃/W can be

achieved. For design information, see Maximum Output Current Versus Ambient Temperature.

DDC (SOT-23-6)

THERMAL METRIC⁽¹⁾

UNIT

6 PINS

107.8

52.4

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

23.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

9.3

23.0

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

Limits apply over operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated. Minimum and

maximum limits⁽¹⁾are specified through test, design or statistical correlation. Typical values represent the most likely

parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 4.5 V to 36 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

I_Q(VIN)

VIN quiescent current (non-switching)⁽²⁾V_EN= 3 V, PFM variant only

µA

I_SD(VIN)

VIN shutdown supply current

V_EN= 0 V

UVLO

VIN_UVLO(R)

VIN_UVLO(F)

VIN_UVLO(H)

ENABLE

V_EN(R)

VIN UVLO rising threshold

VIN UVLO falling threshold

VIN UVLO hysteresis

V_INrising

V_INfalling

3.89

3.58

0.3

4.5

3.35

EN voltage rising threshold

EN voltage falling threshold

EN rising, enable switching

EN falling, disable switching

1.1

1.227

1.08

1.36

1.22

V_EN(F)

0.95

EN pin sourcing current post EN rising

threshold

I_EN(P2)

V_EN= 3 V

200

REFERENCE VOLTAGE

Vfb

Reference voltage

FB input leakage current

0.591

0.6

0.8

0.609

I_FB(LKG)

V_FB= 1.2 V

SWITCHING FREQUENCY

f_SW1(CCM)

f_SW2(CCM)

STARTUP

t_SS

Switching frequency, CCM operation

500-kHz trim option

1.1-MHz trim option

450

500

1.1

560

kHz

Switching frequency, CCM operation

0.95

1.25

MHz

Internal fixed soft-start time

3.2

4.0

5.4

POWER STAGE

R_DSON(HS)

R_DSON(LS)

t_ON(min)

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

Minimum ON pulse width

0.12

0.07

T_J= 25℃

µs

V_IN= 12 V, I_OUT= 3 A

V_IN= 4.5 V

t_ON(max)

Maximum ON pulse width

6.76

150

t_OFF(min)

Minimum OFF pulse width

OVERCURRENT PROTECTION

I_{HS_PK(OC)}

High-side peak current limit⁽³⁾

LM51430

3.67

4.76

6.68

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7.5 Electrical Characteristics (continued)

Limits apply over operating junction temperature (T_J) range of –40°C to +150°C, unless otherwise stated. Minimum and

maximum limits⁽¹⁾are specified through test, design or statistical correlation. Typical values represent the most likely

parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: V_IN= 4.5 V to 36 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{LS_V(OC)}

I_LS(NOC)

I_ZC

Low-side valley current limit⁽³⁾

Low-side negative current limit

Zero-cross detection current threshold

LM51430

2.75

3.5

4.2

LM51430 FPWM Only

Temperature rising

–1.6

0.02

THERMAL SHUTDOWN

T_J(SD)

Thermal shutdown threshold⁽⁴⁾

Thermal shutdown hysteresis⁽⁴⁾

163

°C

T_J(HYS)

(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using

Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application

(4) Specified by design

7.6 System Characteristics

The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical

(TYP) column apply to T_J= 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case

of typical components over the temperature range of T_J= –40°C to 150°C. These specifications are not ensured by

production testing.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Operating input voltage range

4.5

V_OUT

Adjustable output voltage regulation⁽¹⁾PFM operation

2.5%

–1.5%

V_IN=12 V, V_OUT= 3.3 V, I_OUT= 0 A,

R_FBT= 1 MΩ, PFM variant

I_SUPPLY

D_MAX

V_HC

VIN quiescent current (non-switching)

Maximum switch duty cycle⁽²⁾

98%

0.24

µA

FB pin voltage required to trip short-

circuit hiccup mode

t_D

Switch voltage dead-time

6.5

163

141

°C

T_SD

Thermal shutdown temperature

Shutdown temperature

Recovery temperature

(1) Deviation in V_OUTfrom nominal output voltage value at V_IN= 24 V, I_OUT= 0 A to full load

(2) In dropout, the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: f_MIN

1 / (t_ON-MAX+ t_OFF-MIN). D_MAX= t_ON-MAX/ (t_ON-MAX+ t_OFF-MIN).

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7.7 Typical Characteristics

V_IN= 12 V, f_SW= 500 kHz ,T_A= 25°C, unless otherwise specified.

100

PFM, V_IN=8V

PFM, V_IN=12V

PFM, V_IN=24V

PFM, V_IN=36V

FPWM, V_IN=8V

FPWM, V_IN=12V

FPWM, V_IN=24V

FPWM, V_IN=36V

PFM, V_IN=8V

PFM, V_IN=12V

PFM, V_IN=24V

FPWM, V_IN=8V

PFM, V_IN=12V

PFM, V_IN=24V

0.001

0.005

0.02 0.05 0.1 0.2

Load Current (A)

0.5

2 3

0.001

0.005

0.02 0.05 0.1 0.2

Load Current (A)

0.5

2 3

D005_SLUSEF4.grf

V_OUT= 5 V

D004_SLUSEF4.grf

V_OUT= 3.3 V

f_SW= 1.1 MHz

f_SW= 500 kHz

图7-2. 5-V Efficiency vs Load Current

图7-1. 3.3-V Efficiency vs Load Current

100

PFM, V_IN=8V

PFM, V_IN=12V

PFM, V_IN=24V

PFM, V_IN=36V

FPWM, V_IN=8V

FPWM, V_IN=12V

FPWM, V_IN=24V

FPWM, V_IN=36V

0.001

0.005

0.02 0.05 0.1 0.2

Load Current (A)

0.5

2 3

D006_SLUSEF4.grf

V_OUT= 3.3 V

f_SW= 500 kHz

V_OUT= 5 V

PFM version

f_SW= 1.1 MHz

图7-4. 5-V Load Regulation

图7-3. 3.3-V Efficiency vs Load Current

3.34

5.6

5.2

4.8

4.4

VIN=8V

VIN=12V

VIN=24V

VIN=36V

3.33

3.32

3.31

3.3

3.6

3.2

2.8

2.4

3.29

3.28

3.27

I_OUT=0A

I_OUT=0.5A

I_OUT=1A

I_OUT=2A

I_OUT=3A

0.5

1.5

I_OUT(A)

2.5

4.5

5.5

6.5

7.5

V_IN(V)

D008_SLUSEF4.grf

PFM version

D009_SLUSEF4.grf

V_OUT= 5 V PFM version

f_SW= 500 kHz

V_OUT= 3.3 V

f_SW= 500 kHz

图7-5. 3.3-V Load Regulation

图7-6. 5-V Dropout

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4.1

3.9

3.8

3.7

3.6

3.5

3.4

UVLO Rising

UVLO Falling

-50 -30 -10 10

90 110 130 150

Termperature(^oC)

D0013_SLUSEF6.grf

图7-8. V_INUVLO vs Temperature

图7-7. I_Qvs Temperature

4.8

4.6

4.4

4.2

HS Current Limit

LS Current Limit

3.8

3.6

-40

-20

100 120 140

Temperature (^oC)

D0012_SLUSEF4.grf

图7-9. Reference Voltage vs Temperature

图7-10. HS and LS Current Limit vs Temperature

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8 Detailed Description

8.1 Overview

The LMR51430 is an easy-to-use synchronous step-down DC-DC converter operating from a 4.5-V to 36-V

supply voltage. The device is capable of delivering up to 3-A DC load current in a very small solution size. The

family has multiple versions applicable to various applications. See 节5 for detailed information.

The LMR51430 employs fixed-frequency peak-current mode control. The PFM version enters PFM mode at light

load to achieve high efficiency. A FPWM version is provided to achieve low output voltage ripple, tight output

voltage regulation, and constant switching frequency at light load. The device is internally compensated, which

reduces design time and requires few external components.

Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for

a wide range of applications. Protection features include the following:

• Thermal shutdown

• V_INundervoltage lockout

• Cycle-by-cycle current limit

• Hiccup mode short-circuit protection

This family of devices requires very few external components and has a pinout designed for simple, optimal PCB

layout.

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8.2 Functional Block Diagram

VCC

Enable

LDO

VIN

Precision

Enable

HSI Sense

Internal

REF

R_C

C_C

TSD

UVLO

PWM CONTROL LOGIC

PFM

Detector

Slope

Comp

Ton_min/Toff_min

Detector

Freq

Foldback

HICCUP

Detector

Zero

Cross

LSI Sense

Oscillator

GND

8.3 Feature Description

8.3.1 Fixed Frequency Peak Current Mode Control

The following operating description of the LMR51430 refers to 节 8.2 and to the waveforms in 图 8-1. The

LMR51430 is a step-down synchronous buck converter with integrated high-side (HS) and low-side (LS)

switches (synchronous rectifier). The LMR51430 supplies a regulated output voltage by turning on the high-side

and low-side NMOS switches with controlled duty cycle. During the high-side switch on time, the SW pin voltage

swings up to approximately V_IN, and the inductor current, i_L, increases with a linear slope of (V_IN– V_OUT) / L.

When the high-side switch is turned off by the control logic, the low-side switch is turned on after an anti-shoot–

through dead time. Inductor current discharges through the low-side switch with a slope of –V_OUT/ L. The

control parameter of a buck converter is defined as:

Duty Cycle D = t_ON/ t_SW

(1)

where

• t_ONis the high-side switch on time.

• t_SWis the switching period.

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The converter control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck

converter where losses are ignored, and D is proportional to the output voltage and inversely proportional to the

input voltage:

D = V_OUT/ V_IN

(2)

V_SW

V_IN

D = t_ON/ T_SW

t_ON

t_OFF

T_SW

i_L

I_LPK

I_OUT

∆i_L

图8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LMR51430 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get

accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak

inductor current is sensed from the high-side switch and compared to the peak current threshold to control the

on time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer

external components, making designing easy and providing stable operation when using a variety of output

capacitors. The converter operates with fixed switching frequency at normal load conditions. During light-load

condition, the LMR51430 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for

low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).

8.3.2 Adjustable Output Voltage

A precision 0.6-V reference voltage (V_REF) is used to maintain a tightly regulated output voltage over the entire

operating temperature range. The output voltage is set by a resistor divider from V_OUTto the FB pin. TI

recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the

bottom-side resistor, R_FBB, for the desired divider current and use 方程式 3 to calculate the top-side resistor,

R_FBT. The recommend range for R_FBTis 10 kΩ to 100 kΩ. A lower R_FBTvalue can be used if pre-loading is

desired to reduce V_OUToffset in PFM operation. Lower R_FBTreduces efficiency at very light load. Less static

current goes through a larger R_FBTand can be more desirable when light-load efficiency is critical. However, TI

does not recommend R_FBTlarger than 1 MΩ because it makes the feedback path more susceptible to noise.

Larger R_FBTvalues require a more carefully designed feedback path trace from the feedback resistors to the

feedback pin of the device. The tolerance and temperature variation of the resistor divider network affect the

output voltage regulation.

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V_OUT

R_FBT

R_FBB

图8-2. Output Voltage Setting

V_OUT- V_REF

R_FBT

× R_FBB

V_REF

(3)

8.3.3 Enable

The voltage on the EN pin controls the ON and OFF operation of the LMR51430. A voltage of less than 0.95 V

shuts down the device, while a voltage of greater than 1.36 V is required to start the converter. The EN pin is an

input and cannot be left open or floating. The simplest way to enable the operation of the LMR51430 is to

connect EN to VIN. This allows self-start–up of the LMR51430 when V_INis within the operating range.

Many applications benefit from the employment of an enable divider R_ENTand R_ENB(图 8-3) to establish a

precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility

power as well as battery power. System UVLO can also be used for sequencing, ensuring reliable operation, or

supplying protection, such as a battery discharge level. An external logic signal can also be used to drive EN

input for system sequencing and protection.

备注

The EN pin voltage must not to be greater than V_IN+ 0.3 V. Do not apply EN voltage when V_INis 0 V.

VIN

R_ENT

R_ENB

图8-3. System UVLO by an Enable Divider

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8.3.4 Minimum On Time, Minimum Off Time, and Frequency Foldback

Minimum on time (t_{ON_MIN}) is the shortest duration of time that the high-side switch can be turned on. t_{ON_MIN}is

typically 70 ns for the LMR51430. Minimum off time (t_{OFF_MIN}) is the shortest duration of time that the high-side

switch can be off. t_{OFF_MIN}is typically 150 ns. In CCM operation, t_{ON_MIN}and t_{OFF_MIN}limit the voltage

conversion range without switching frequency foldback.

The minimum duty cycle without frequency foldback allowed is:

D_MIN= t_{ON_MIN}× f_SW

(4)

(5)

The maximum duty cycle without frequency foldback allowed is:

D_MAX= 1 - t_{OFF_MIN}× f_SW

Given a required output voltage, the maximum V_INwithout frequency foldback can be found by:

V_OUT

V_{IN_MAX}

f_SW× T_{ON_MIN}

(6)

(7)

The minimum V_INwithout frequency foldback can be calculated by:

V_OUT

V_{IN_MIN}

1- f_SW× T_{OFF_MIN}

In the LMR51430, a frequency foldback scheme is employed after t_{ON_MIN}or t_{OFF_MIN}is triggered, which can

extend the maximum duty cycle or lower the minimum duty cycle.

The on time decreases while V_INvoltage increases. After the on time decreases to t_{ON_MIN}, the switching

frequency starts to decrease while V_INcontinues to increase, which lowers the duty cycle further to keep V_OUTin

regulation according to 方程式4.

The frequency foldback scheme also works after larger duty cycle is needed under low V_INcondition. The

frequency decreases after the device reaches t_{OFF_MIN}, which extends the maximum duty cycle according to 方

程式 5. In such condition, the frequency can be as low as approximately 133 kHz. A wide range of frequency

foldback allows for the LMR51430 output voltage to stay in regulation with a much lower supply voltage V_IN,

which leads to a lower effective dropout.

With frequency foldback while maintaining a regulated output voltage, V_{IN_MAX}is raised, and V_{IN_MIN}is lowered

by decreased f_SW

1400

1300

1100

900

1200

1000

800

700

500

600

300

400

4.5

9.5

Input Voltage (V)

D0015_SLUSEF4.grf

D0014_SLUSEF6.grf

V_OUT= 5.0 V

f_SW= 1.1 MHz

I_OUT= 3.0 A

V_OUT= 1.8 V

f_SW= 1.1 MHz

I_OUT= 3.0 A

图8-5. Frequency Foldback at t_{ON_MIN}

图8-4. Frequency Foldback at t_{ON_MIN}

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8.3.5 Bootstrap Voltage

The LMR51430 provides an integrated bootstrap voltage converter. A small capacitor between the CB and SW

pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the

high-side MOSFET is off and the low-side switch is on. The recommended value of the bootstrap capacitor is 0.1

µF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or

higher for stable performance over temperature and voltage.

8.3.6 Overcurrent and Short-Circuit Protection

The LMR51430 incorporates both peak and valley inductor current limit to provide protection to the device from

overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current

runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum

output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for

sustained short circuits.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The

high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch

current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle.

See Functional Block Diagram for more details. The peak current of high-side switch is limited by a clamped

maximum peak current threshold, I_sc(see the Electrical Characteristics), which is constant.

The current going through the low-side MOSFET is also sensed and monitored. When the low-side switch turns

on, the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching

cycle if its current is above the low-side current limit, I_{LS_LIMIT}(see the Electrical Characteristics). The low-side

switch is kept ON so that inductor current keeps ramping down until the inductor current ramps below I_{LS_LIMIT}

Then, the low-side switch is turned OFF and the high-side switch is turned on after a dead-time. After I_{LS_LIMIT}is

achieved, peak and valley current limit controls the max current deliver and it can be calculated using 方程式8.

I_{LS_LIMIT}+I_SC

I_OUT

max

(8)

If the feedback voltage is lower than 40% of V_REF, the current of the low-side switch triggers I_{LS_LIMIT}for 256

consecutive cycles and hiccup current protection mode is activated. In hiccup mode, the converter shuts down

and keeps off for a period of hiccup, t_HICCUP(135-ms typical), before the LMR51430 tries to start again. If an

overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup

mode reduces power dissipation under severe overcurrent conditions, preventing overheating and potential

damage to the device.

For FPWM version, the inductor current is allowed to go negative. When this current exceeds the low-side

negative current limit, I_{LS_NEG}, the low-side switch is turned off and high-side switch is turned on immediately.

This is used to protect the low-side switch from excessive negative current.

8.3.7 Soft Start

The integrated soft-start circuit prevents input inrush current impacting the LMR51430 and the input power

supply. Soft start is achieved by slowly ramping up the internal reference voltage when the device is first enabled

or powered up. The typical soft-start time is 4.0 ms.

The LMR51430 also employs overcurrent protection blanking time, t_{OCP_BLK}(33 ms typical), at the beginning of

power up. Without this feature, in applications with a large amount of output capacitors and high V_OUT, the inrush

current is large enough to trigger the current-limit protection, which can cause a false start as the device enters

into hiccup mode. This action results in a continuous recycling of soft start without raising up to the programmed

output voltage. The LMR51430 is able to charge the output capacitor to the programmed V_OUTby controlling the

average inductor current during the start-up sequence in the blanking time, t_{OCP_BLK}

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8.3.8 Thermal Shutdown

The LMR51430 provides an internal thermal shutdown to protect the device when the junction temperature

exceeds 163°C. Both high-side and low-side FETs stop switching in thermal shutdown. After the die temperature

falls below 141°C, the device reinitiates the power-up sequence controlled by the internal soft-start circuitry.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides electrical ON and OFF control for the LMR51430. When V_ENis below 0.95 V, the device is

in shutdown mode. The LMR51430 also employs V_INundervoltage lockout protection (UVLO). If V_INvoltage is

below its UVLO threshold of 3.58 V, the converter is turned off.

8.4.2 Active Mode

The LMR51430 is in active mode when both V_ENand V_INare above their respective operating threshold. The

simplest way to enable the LMR51430 is to connect the EN pin to VIN pin. This allows self-start–up when the

input voltage is in the operating range of 4.5 V to 36 V. See 节8.3.3 for details on setting these operating levels.

In active mode, depending on the load current, the LMR51430 is in one of four modes:

• Continuous conduction mode (CCM) with fixed switching frequency when load current is greater than half of

the peak-to-peak inductor current ripple (for both PFM and FPWM versions)

• Discontinuous conduction mode (DCM) with fixed switching frequency when load current is less than half of

the peak-to-peak inductor current ripple(only for PFM version)

• Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for

PFM version)

• Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for

FPWM version)

8.4.3 CCM Mode

Continuous conduction mode (CCM) operation is employed in the LMR51430 when the load current is greater

than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output

voltage ripple is at a minimum in this mode and the maximum output current of 3 A can be supplied by the

LMR51430.

8.4.4 Light-Load Operation (PFM Version)

For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the

LMR51430 operates in discontinuous conduction mode (DCM), also known as diode emulation mode (DEM). In

DCM operation, the low-side switch is turned off when the inductor current drops to I_ZC(20 mA typical) to

improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced PWM

operation at light load.

During light-load operation, pulse frequency modulation (PFM) mode is activated to maintain high efficiency

operation. When either the minimum high-side switch on time, t_{ON_MIN}, or the minimum peak inductor current,

I_{PEAK_MIN}(0.48 A typical), is reached, the switching frequency decreases to maintain regulation. In PFM mode,

switching frequency is decreased by the control loop to maintain output voltage regulation when load current

reduces. Switching loss is further reduced in PFM operation due to a significant drop in effective switching

frequency.

8.4.5 Light-Load Operation (FPWM Version)

For FPWM version, the LMR51430 is locked in PWM mode at full load range. This operation is maintained, even

in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off

reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching

frequency.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The LMR51430 is a step-down DC-to-DC converter. The device is typically used to convert a higher input

voltage to a lower output DC voltage with a maximum output current of 3 A. The following design procedure can

be used to select components for the LMR51430. Alternately, the WEBENCH^®software can be used to generate

complete designs. When generating a design, the WEBENCH software uses iterative design procedure and

accesses comprehensive databases of components. Go to ti.com for more details.

9.2 Typical Application

The LMR51430 only requires a few external components to convert from a wide voltage range supply to a fixed

output voltage. 图9-1 shows a basic schematic.

V_IN12 V

C_BOOT

0.1 µF

VIN

C_IN

2.2 µF

6.8 µH

V_OUT5 V

R_FBT

100 k

C_OUT

44 µF

GND

R_FBB

13.7 k

图9-1. Application Circuit

The external components have to fulfill the needs of the application and the stability criteria of the control loop of

the device. 表9-1 can be used to simplify the output filter component selection.

表9-1. L and C_OUTTypical Values

f_SW(kHz)

V_OUT(V)

L (µH)

C_OUT(µF) ⁽¹⁾

2 × 22 µF / 25 V

3 × 22 µF / 25 V

R_FBT(kΩ)

100

R_FBB(kΩ)

22.1

3.3

5.6

500

6.8

100

13.7

100

5.23

表9-2. L and C_OUTTypical Values

f_SW(kHz)

V_OUT(V)

L (µH)

C_OUT(µF) ⁽¹⁾

2 × 10 µF / 25 V

3 × 10 µF / 25 V

R_FBT(kΩ)

100

R_FBB(kΩ)

22.1

3.3

2.2

1100

3.3

100

13.7

6.8

100

5.23

(1) A ceramic capacitor is used in this table.

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9.2.1 Design Requirements

The detailed design procedure is described based on a design example. For this design example, use the

parameters listed in 表9-3 as the input parameters.

表9-3. Design Example Parameters

Parameter

Value

Input voltage, V_IN

12 V typical, range from 6 V to 36 V

Output voltage, V_OUT

5 V ±3%

3 A

Maximum output current, I_{OUT_MAX}

Output overshoot and undershoot 0.5 A to 2 A

Output voltage ripple

0.5%

Operating frequency

500 kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR51430 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Output Voltage Set-Point

The output voltage of the LMR51430 device is externally adjustable using a resistor divider network. The divider

network is comprised of a top feedback resistor R_FBTand bottom feedback resistor R_FBB. 方程式 9 is used to

determine the output voltage of the converter:

V_OUT- V_REF

R_FBT

× R_FBB

V_REF

(9)

Choose the value of R_FBBto be 13.7 kΩ. With the desired output voltage set to 5 V and the V_REF= 0.6 V, the

R_FBTvalue can then be calculated using 方程式 9. The formula yields a value 100.4 kΩ. A standard value of 100

kΩ is selected.

9.2.2.3 Switching Frequency

The higher switching frequency allows for lower-value inductors and smaller output capacitors, which result in a

smaller solution size and lower component cost. However, higher switching frequency brings more switching

loss, making the solution less efficient and produce more heat. The switching frequency is also limited by the

minimum on time of the following as mentioned in 节8.3.4:

• Integrated power switch

• Input voltage

• Output voltage

• Frequency shift limitation

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For this example, a switching frequency of 500 kHz is selected.

9.2.2.4 Inductor Selection

The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The

inductance is based on the desired peak-to-peak ripple current, Δi_L. Because the ripple current increases with

the input voltage, the maximum input voltage is always used to calculate the minimum inductance, L_MIN. Use 方

程式 11 to calculate the minimum value of the output inductor. K_INDis a coefficient that represents the amount of

inductor ripple current relative to the maximum output current of the device. A reasonable value of K_INDmust be

20% to 60% of maximum I_OUTsupported by the converter. During an instantaneous overcurrent operation event,

the RMS and peak inductor current can be high. The inductor saturation current must be higher than peak

current limit level.

V_OUT

- V_OUT

IN_MAX

(

)

ûi_L=

V_{IN_MAX}× L × f_SW

(10)

(11)

V_{IN_MAX}- V_OUT

V_OUT

L_MIN

I_OUT× K _IND

V_{IN_MAX}× f_SW

In general, choose lower inductance in switching power supplies because it usually corresponds to faster

transient response, smaller DCR, and reduced size for more compact designs. Too low of an inductance can

generate too large of an inductor current ripple such that overcurrent protection at the full load can be falsely

triggered and generates more inductor core loss because the current ripple is larger. Larger inductor current

ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control,

ensure there is an adequate amount of inductor ripple current. A larger inductor ripple current improves the

comparator signal-to-noise ratio.

For this design example, choose K_IND= 0.3. The minimum inductor value is calculated to be 6.48 µH. Choose

the nearest standard 6.8-µH ferrite inductor with a capability of 4-A RMS current and 5-A saturation current.

9.2.2.5 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters. Minimize the output capacitance to keep cost

and size down. The output capacitor or capacitors, C_OUT, must be chosen with care because it directly affects

the steady state output voltage ripple, loop stability, and output voltage overshoot and undershoot during load

current transient. The output voltage ripple is essentially composed of two parts. One part is caused by the

inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the output capacitors:

ûV_{OUT_ESR}= ûi_L× ESR = K_IND×I_OUT× ESR

(12)

The other part is caused by the inductor current ripple charging and discharging the output capacitors:

ûi_L

K_IND×I_OUT

ûV_{OUT_C}

8×f_SW× C_OUT8×f_SW× C_OUT

(13)

The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than

the sum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage

regulation with presence of large current steps and fast slew rates. When a large load step occurs, output

capacitors provide the required charge before the inductor current can slew to an appropriate level. The control

loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new

load level during this time. The output capacitance must be large enough to supply the current difference for

eight clock cycles to maintain the output voltage within the specified range. 方程式14 shows the minimum output

capacitance needed for a specified V_OUTovershoot and undershoot.

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8 × I_OH-I_OL

(

)

C_OUT

f_SW× ûV_{OUT_SHOOT}

(14)

where

• K_INDis the ripple ratio of the inductor current (Δi_L/ I_OUT).

• I_OLis the low level output current during load transient.

• I_OHis the high level output current during load transient.

• V_{OUT_SHOOT}is the target output voltage overshoot or undershoot.

For this design example, the target output ripple is 30 mV. Assuming ΔV_{OUT_ESR}= ΔV_{OUT_C}= 30 mV, choose

K_IND= 0.3. Equation 12 yields ESR no larger than 75 mΩ and Equation 13 yields C_OUTno smaller than 14 µF.

For the target overshoot and undershoot limitation of this design, ΔV_{OUT_SHOOT}= 5% × V_OUT= 250 mV. The

C_OUTcan be calculated to be no less than 48 µF by Equation 14. In summary, the most stringent criterion for the

output capacitor is 48 µF. For this design, two 22-µF, 25-V, X7R ceramic capacitors with 5-mΩ ESR are used.

9.2.2.6 Input Capacitor Selection

The LMR51430 device requires a high frequency input decoupling capacitor or capacitor. The typical

recommended value for the high frequency decoupling capacitor is 4.7 µF or higher. TI recommends a high-

quality ceramic type X5R or X7R with a sufficient voltage rating. The voltage rating must be greater than the

maximum input voltage. To compensate the derating of ceramic capacitors, TI recommends a voltage rating of

twice the maximum input voltage. For this design, two 4.7-µF, X7R dielectric capacitor rated for 50 V are used for

the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ and the current

rating is 1 A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as

possible to the device pins.

9.2.2.7 Bootstrap Capacitor

Every LMR51430 design requires a bootstrap capacitor, C_BOOT. The recommended bootstrap capacitor is 0.1 µF

and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The

bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature

stability.

9.2.2.8 Undervoltage Lockout Set-Point

The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of R_ENTand

R_ENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down

or brownouts when the input voltage is falling. 方程式15 can be used to determine the V_INUVLO level.

R_ENT+ R_ENB

V_{IN_RISING}= V_ENH

R_ENB

(15)

The EN rising threshold (V_ENH) for the LMR51430 is set to be 1.23 V (typical). Choose a value of 200 kΩ for

R_ENBto minimize input current from the supply. If the desired V_INUVLO level is at 6.0 V, then the value of R_ENT

can be calculated using 方程式16:

≈

’

◊

V_{IN_RISING}

R_ENT

-1 × R

∆

ENB

V_ENH

(16)

The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling

UVLO threshold, equals 5.3 V, can be calculated by 方程式 17 where EN hysteresis voltage, V_{EN_HYS}, is 0.13 V

(typical).

R_ENT+ R_ENB

V_{IN_FALLING}= V

(

- V_{EN_HYS}×

)

ENH

R_ENB

(17)

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9.2.3 Application Curves

Unless otherwise specified the following conditions apply: V_IN= 12 V, V_OUT= 5 V, f_SW= 500 kHz, L = 6.8 µH,

C_OUT= 44 µF, T = 25°C.

V_SW[5V/div]

V_OUT(AC) [10mV/div]

I_L[2A/div]

V_OUT(AC) [20mV/div]

I_L[500mA/div]

Time [2us/div]

Time [4ms/div]

图9-2. Ripple at No Load

图9-3. Ripple at Full Load

V_EN[2V/div]

V_OUT[2V/div]

I_L[2A/div]

V_IN[5V/div]

V_OUT[2V/div]

I_L[2A/div]

Time [2ms/div]

图9-4. Start-Up by V_IN

图9-5. Start-Up by EN

V_IN[10V/div]

V_OUT(AC) [200mV/div]

V_OUT[2V/div]

I_L[2A/div]

I_o[1A/div]

Time [400us/div]

Time [800us/div]

图9-6. Load Transient

图9-7. Line Transient

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V_OUT[2V/div]

I_L[2A/div]

Time [100ms/div]

图9-8. Short Protection

图9-9. Short Recovery

9.3 Power Supply Recommendations

The LMR51430 is designed to operate from an input voltage supply range between 4.5 V and 36 V. This input

supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the LMR51430 supply voltage that can cause a false UVLO fault triggering and system reset. If

the input supply is located more than a few inches from the LMR51430 additional bulk capacitance can be

required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 10-µF

or 22-µF electrolytic capacitor is a typical choice.

9.4 Layout

9.4.1 Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with

the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

• The input bypass capacitor C_INmust be placed as close as possible to the VIN and GND pins. Grounding for

both the input and output capacitors must consist of localized top-side planes that connect to the GND pin.

• Minimize trace length to the FB pin net. Both feedback resistors, R_FBTand R_FBB, must be located close to the

FB pin. If V_OUTaccuracy at the load is important, make sure V_OUTsense is made at the load. Route V_OUT

sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.

• Use the ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.

• Make V_IN, V_OUT, and ground bus connections as wide as possible, which reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

• Provide adequate device heat-sinking. GND, VIN, and SW pins provide the main heat dissipation path. Make

the GND, VIN, and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top

side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these

thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area

is used for heat-sinking to keep the junction temperature below 125°C.

9.4.1.1 Compact Layout for EMI Reduction

Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass

capacitors at the input side provide a primary path for the high di/dt components of the pulsing current. Placing a

ceramic bypass capacitor or capacitors as close as possible to the VIN and GND pins is the key to EMI

reduction.

The SW pin connected to the inductor must be as short as possible, and just wide enough to carry the load

current without excessive heating. Short, thick traces or copper pours (shapes) must be used for high current

conduction path to minimize parasitic resistance. The output capacitors must be placed close to the V_OUTend of

the inductor and closely grounded to the GND pin.

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9.4.1.2 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, make sure to place the resistor divider close to

the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance

node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace length of FB

signal and reduces noise coupling. The output node is a low impedance node, so the trace from V_OUTto the

resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provides the best output accuracy. The voltage sense trace from the load to

the feedback resistor divider must be routed away from the SW node path and the inductor to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This effect is most

important when high value resistors are used to set the output voltage. TI recommends to route the voltage

sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that

there is a ground plane in between the feedback trace and inductor and SW node polygon, which provides

further shielding for the voltage feedback path from EMI noises.

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9.4.2 Layout Example

Trace on the

bottom layer

GND

VOUT

Additional

Vias to the

GND plane

OUTPUT

CAPACITOR

BOOST

CAPACITOR

GND

FEEDBACK

TO ENABLE

RESISTORS

CONTROL

OUTPUT

INDUCTOR

VIN

GND trace under IC

On top layer

INPUT BYPASS

CAPACITOR

GND

图9-10. Layout

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10 Device and Documentation Support

10.1 Device Support

10.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

10.1.2 Development Support

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR51430 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, AN-1149 Layout Guidelines for Switching Power Supplies

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®and SIMPLE SWITCHER^®are registered trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

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10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

13-Jul-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMR51430XDDCR

LMR51430XFDDCR

LMR51430YDDCR

LMR51430YFDDCR

ACTIVE SOT-23-THIN

DDC

3000 RoHS & Green

Call TI | SN

Level-1-260C-UNLIM

-40 to 150

4BXP

4BXF

4BYP

4BYF

Samples

Call TI | SN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

13-Jul-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMR51430XDDCR

LMR51430XFDDCR

LMR51430YDDCR

LMR51430YFDDCR

SOT-23-

THIN

DDC

3000

180.0

8.4

3.2

1.4

4.0

8.0

SOT-23-

THIN

SOT-23-

THIN

SOT-23-

THIN

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMR51430XDDCR

LMR51430XFDDCR

LMR51430YDDCR

LMR51430YFDDCR

SOT-23-THIN

DDC

3000

210.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

3.05

2.55

1.1

0.7

1.75

1.45

0.1 C

PIN 1

INDEX AREA

4X 0.95

1.9

3.05

2.75

0.5

0.3

0.1

TYP

0.0

0.2

C A B

0 -8 TYP

0.25

GAGE PLANE

SEATING PLANE

0.20

0.12

TYP

0.6

0.3

TYP

4214841/C 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Reference JEDEC MO-193.

www.ti.com

EXAMPLE BOARD LAYOUT

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X (0.95)

(R0.05) TYP

(2.7)

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN

SCALE:15X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDERMASK DETAILS

4214841/C 04/2022

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDC0006A

SOT-23 - 1.1 max height

SMALL OUTLINE TRANSISTOR

SYMM

6X (1.1)

6X (0.6)

SYMM

4X(0.95)

(R0.05) TYP

(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL

SCALE:15X

4214841/C 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMR51430XDDCR [TI]

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