LMR51440 [TI]
36V、4A 同步降压转换器;
| 型号： | LMR51440 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36V、4A 同步降压转换器 转换器 |
| 文件： | 总37页 (文件大小：2627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMR51440, LMR51450
ZHCSR98 –DECEMBER 2022
LMR514x0 具有低IQ 的36V、4A/5A 同步直流/直流降压转换器
1 特性
3 说明
• 提供功能安全
LMR514x0 是一款简单易用的宽 VIN 同步降压转换
器，能够驱动高达 4A 或 5A 的负载电流。该器件具有
4V 至 36V 的宽输入范围，适用于从非稳压源进行电源
调节的各种工业应用。
– 有助于进行功能安全系统设计的文档
• 专用于条件严苛的工业应用
– 宽输入电压范围：4V 至36V
– 4A 或5A 持续输出电流
– 室温下±1.0% 容差电压基准
– 最短打开时间：75ns（典型值）
– 低静态电流：25µA
LMR514x0 具有可调开关频率，该频率可以通过外部
电阻在200kHz 至1.1MHz 范围内调节，这提供了优化
效率或外部元件尺寸的灵活性。该器件具有可在轻负载
时实现高效率的 PFM 版本和实现恒定频率的 FPWM
版本，并可在整个负载范围内实现低输出电压纹波。软
启动和补偿电路在内部实现，从而允许器件使用最少的
外部元件。
– 可调频率：200kHz 至1.1MHz
– 展频频谱（PFM 模式）
– 保护特性
• 精密使能输入
• 开漏PGOOD
• VIN 欠压锁定(UVLO)
• 逐周期电流限制
• 断续模式短路保护
该器件具有内置的保护功能，例如逐周期电流限制、断
续模式短路保护以及功耗过大时热关断功能。
LMR514x0 采用WSON-12 封装。
器件信息
• 热关断
– 低压降模式运行
封装尺寸（标称
值）
电流(1)
封装(2)
器件型号
– 结温范围：–40°C 至150°C
• 解决方案小巧且易于使用
– 集成同步整流
LMR51440
LMR51450
4A
5A
DRR
3.00mm ×
3.00mm
（WSON，12）
– 内置补偿功能，便于使用
– WSON-12 封装
• 采用引脚到引脚兼容封装的各种选项
– PFM 和强制PWM (FPWM) 选项
• 使用LMR5144x0 并借助WEBENCH® Power
Designer 创建定制设计方案
(1) 请参阅器件比较表。
(2) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 大型电器
• PLC、DCS 和PAC
• 测试和测量仪表
• 电力输送
100
90
80
70
60
50
40
30
PFM, VIN=12V
PFM, VIN=24V
20
FPWM, VIN=12V
FPWM, VIN=24V
10
0
0.001
0.01 0.02 0.05 0.1 0.2
IOUT(A)
0.5
1
2 3 45
简化原理图
效率与输出电流间的关系VOUT = 5V，500kHz
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSEP7
LMR51440, LMR51450
ZHCSR98 –DECEMBER 2022
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 20
9.3 Best Design Practices...............................................26
9.4 Power Supply Recommendations.............................26
9.5 Layout....................................................................... 26
10 Device and Documentation Support..........................29
10.1 Device Support....................................................... 29
10.2 Documentation Support.......................................... 29
10.3 接收文档更新通知................................................... 29
10.4 支持资源..................................................................29
10.5 Trademarks.............................................................29
10.6 Electrostatic Discharge Caution..............................29
10.7 术语表..................................................................... 29
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
ESD Ratings..................................................................... 4
7.2 Recommended Operating Conditions.........................4
7.3 Thermal Information....................................................5
7.4 Electrical Characteristics.............................................5
7.5 System Characteristics............................................... 7
7.6 Typical Characteristics................................................8
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................12
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial release
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5 Device Comparison Table
ORDERABLE PART NUMBER
LMR51440SDRRR
Current
4 A
PFM OR FPWM
PFM
Spread Specturm
Yes
Yes
No
LMR51450SDRRR
5 A
PFM
LMR51450FNDRRR
5 A
FPWM
6 Pin Configuration and Functions
SW
1
2
3
4
5
6
12
VIN
VIN
SW
11
10
9
SW
VIN
PGND/DAP
13
BOOT
PG
EN
8
AGND
FB
RT
7
图6-1. 12-Pin WSON DRR Package (Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO
Switching output of the converter. Internally connected to source of the high-side FET and
drain of the low-side FET. Connect to power inductor.
SW
1, 2, 3
P
P
Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100-nF
capacitor from this pin to the SW pin.
BOOT
PG
4
5
Open-drain power-good monitor output that asserts low if the FB voltage is not within the
specified window thresholds. A 10-kΩto 100-kΩpullup resistor to a suitable voltage is
required. If not used, PG can be left open or connected to GND.
A
Frequency setting pin used to set the switching frequency between 200 kHz and 1.1 MHz by
placing an external resistor from RT to AGND. RT open defaults to 500 kHz and RT short to
ground defaults to 1 MHz.
RT
FB
6
7
8
A
A
G
Feedback input to the converter. Connect a resistor divider to set the output voltage. Never
short this terminal to ground during operation.
Analog ground. Zero-voltage reference for internal references and logic. All electrical
parameters are measured with respect to this pin. These pins must be connected to PGND
using a small net-tie.
AGND
Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable
allows the pin to be used as an adjustable input voltage UVLO. Connect an external resistor
divider between this pin, VIN and AGND to create an external UVLO. Do not float.
EN
9
A
Input supply voltage. Connect the input supply to these pins. Connect input capacitors CIN
between these pins and PGND in close proximity to the device.
VIN
10, 11, 12
13
P
Power ground terminals, connected to the source of low-side FET internally. Connect to
system ground, ground side of CIN and COUT. Path to CIN must be as short as possible.
PGND
G
(1) A = Analog, P = Power, G = Ground.
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7 Specifications
7.1 Absolute Maximum Ratings
Over junction temperature range of -40°C to 150°C (unless otherwise noted)(1)
MIN
MAX
38
UNIT
V
VIN to PGND
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–4
EN to PGND
VIN+0.3
5.5
V
Input voltage
FB to PGND
V
RT to PGND
5.5
V
BOOT to SW
5.5
V
SW to PGND
38
V
Output voltage
SW to PGND less than 10-ns transients
PG to PGND
40
V
20
V
–0.3
–40
–65
Junction Temperature TJ
Storage temperature, Tstg
150
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
2000
–2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM),
500
–500
per ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40°C to 150°C (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
V
Input voltage
Input voltage
Input voltage
Input voltage
Output voltage
Output voltage
Frequency
Input voltage range
4.0
36
EN to PGND
VIN
5
V
RT to PGND
V
PGOOD to PGND
20
V
SW to PGND
36
V
Output voltage range (2)
0.8
200
0
28
V
Frequency range
1100
5
kHz
A
Load current
Load current
Temperature
Output DC current range, 5 A Version (3)
Output DC current rang, 4 A Version (3)
Operating junction temperature TJ range (4)
0
4
A
150
°C
–40
(1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics table.
(2) Under no conditions should the output voltage be allowed to fall below zero volts.
(3) Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature. See
Application section for details.
(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 150℃.
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7.3 Thermal Information
LMR514x0
THERMAL METRIC(1)
DRR (WSON)
12 PINS
47.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA(Effecitve)
RθJC(top)
RθJB
Junction-to-ambient thermal resistance with TI EVM board
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
23
44.6
20.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJT
20.7
ψJB
RθJC(bot)
6.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.4 Electrical Characteristics
Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND CURRENT
Operating quiescent current (non-
switching)
IQ-nonSW
ISD
VEN = 3.3 V (PFM variant only)
VEN = 0 V, VIN = 24 V
25
3
µA
µA
Shutdown quiescent current;
measured at VIN pin
6
VIN rising, Needed to start up
VIN falling, Once operating
3.9
V
V
VIN_OPERATE VIN UVLO threshold
3.4
ENABLE
VEN-H
VEN-L
Enable input high level
Enable input low level
EN rising, Enable switching
EN falling, Disable switching
VEN = 3.3V
1.1
0.8
1.25
1
1.4
V
V
1.12
ILKG-EN
Enable input leakage current
0.1
µA
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
TJ = 25°C
FB = 1 V
0.792
0.8
0.808
100
V
ILKG-FB
Feedback leakage current
nA
CURRENT LIMITS AND HICCUP
ISC
High-side current limit(3)
5 A Version
6.4
5.5
8
5
9.6
7.5
A
A
A
A
A
A
A
A
A
ILS-LIMIT
ISC
ILS-LIMIT
IL-ZC
Low-side current limit(3)
5 A Version
High-side current limit(3)
4 A Version
6.5
Low-side current limit(3)
4 A Version
4
Zero cross detector threshold
Minimum inductor peak current(3)
Minimum inductor peak current(3)
Negative current limit(3)
PFM variants only
–0.1
1
IPEAK-MIN
IPEAK-MIN
IL-NEG
IL-NEG
5 A Version, PFM variants only
4 A Version, PFM variants only
5 A Version, FPWM variant only
4 A Version, FPWM variant only
0.8
–2.5
–1.7
Negative current limit(3)
Ratio of FB voltage to in-regulation FB
voltage
VHICCUP
40
%
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Limits apply over operating junction temperature (TJ ) range of –40°C to +150°C, unless otherwise stated. Minimum and
Maximum limits(1) are specified through test, design or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
VPG-HIGH-UP
VPG-LOW-DN
Power-Good upper threshold - rising
Power-Good lower threshold - falling
% of FB voltage
110
88
112
90
115
92
%
%
% of FB voltage
% of FB voltage
Power-Good hysteresis (rising &
falling)
VPG-HYS
2.0
%
Minimum input voltage for proper
Power-Good function
VPG-VALID
1.5
V
RPG
Power-Good on-resistance
VEN = 3.3 V
84
Ω
MOSFETS
RDS-ON-HS
RDS-ON-LS
High-side MOSFET ON-resistance
Low-side MOSFET ON-resistance
78
45
mΩ
mΩ
VBOOT-SW-
BOOT-SW UVLO rising threshold
VBOOT-SW rising
2.2
V
UVLO(R)
SWITCHING CHARACTERISTICS
FSW (CCM)
FSW (CCM)
FSW (CCM)
FSW (CCM)
Switching frequency
Switching frequency
Switching frequency
Switching frequency
425
450
495
500
560
550
kHz
kHz
kHz
kHz
RT = 31.6 kΩ
RT = Open or pull-up to voltage >1.0V
RT = 14.3 kΩ
1000
1000
RT = Short to GND
Spread of internal oscillator with
Spread
FSPREAD
±10
%
Spectrum Enabled
TIMING REQUIREMENT
tON-MIN
tOFF-MIN
tON-MAX
tSS
Minimum switch on-time(2)
VIN =24 V, Iout = 1 A
75
135
5
ns
ns
Minimum switch off-time
Maximum switch on-time
Internal soft-start time
µs
3.2
5
7.2
ms
ms
tw
Short circuit wait time ("Hiccup" time)
96
THERMAL SHUTDOWN
(2)
TSD-Rising
Thermal shutdown
Thermal shutdown
Shutdown threshold
Recovery threshold
160
140
℃
℃
(2)
TSD-Falling
(1) MIN and MAX limits are 100% production tested at 25℃. Limits over the operating temperature range verified through correlation using
Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Not production tested. Specified by correlation by design.
(3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
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7.5 System Characteristics
The following specifications apply to a typical application circuit with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25℃only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40℃to 150℃. These specifications are not ensured by
production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Operating input voltage range
Adjustable output voltage regulation(1)
4
36
V
VOUT
PFM operation
1.5%
35
VIN = 24 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ, PFM variant
ISUPPLY
DMAX
VHC
Input supply current when in regulation
Maximum switch duty cycle(2)
µA
97%
0.32
FB pin voltage required to trip short-circuit
hiccup mode
V
TSD
TSD
Thermal shutdown temperature
Thermal shutdown temperature
Shutdown temperature
Recovery temperature
160
140
°C
°C
(1) Deviation in VOUT from nominal output voltage value at VIN = 24 V, IOUT = 0 A to full load
(2) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: FMIN
= 1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.6 Typical Characteristics
VIN = 12 V, fSW= 500 kHz ,TA = 25°C, unless otherwise specified.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PFM, VIN = 8V
PFM, VIN = 12V
PFM, VIN = 24V
PFM, VIN = 36V
FPWM, VIN = 8V
FPWM, VIN = 12V
FPWM, VIN = 24V
FPWM, VIN = 36V
VIN=8V
VIN=12V
VIN=24V
VIN=36V
0.001
0.01 0.02 0.05 0.1 0.2
IOUT(A)
0.5
1
2
3 45
0.001
0.01 0.02 0.05 0.1 0.2
IOUT(A)
0.5
1
2
3 45
fSW = 500 kHz
VOUT = 5 V
LMR51450
fSW = 500 kHz
VOUT = 5 V
LMR51440
图7-1. 5-V Efficiency versus Load Current
图7-2. 5-V Efficiency versus Load Current
100
90
80
70
60
100
90
80
70
60
50
40
30
50
PFM, VIN=8V
PFM, VIN=12V
PFM, VIN=24V
PFM, VIN=36V
FPWM, VIN=8V
FPWM, VIN=12V
FPWM, VIN=24V
FPWM, VIN=36V
40
30
20
10
0
VIN=8V
20
10
0
VIN=12V
VIN=24V
VIN=36V
0.001
0.01 0.02 0.05 0.1 0.2
IOUT(A)
0.5
1
2
3 45
0.001
0.01 0.02 0.05 0.1 0.2
IOUT(A)
0.5
1
2
3 45
fSW = 500 kHz
VOUT = 3.3 V
LMR51450
fSW = 500 kHz
VOUT = 3.3 V
LMR51440
图7-3. 3.3-V Efficiency versus Load Current
图7-4. 3.3-V Efficiency versus Load Current
3.42
5.14
PFM, VIN=8V
PFM, VIN=12V
PFM, VIN=24V
PFM, VIN=36V
PFM, VIN=8V
PFM, VIN=12V
PFM, VIN=24V
PFM, VIN=36V
3.4
3.38
3.36
3.34
3.32
3.3
5.12
5.1
5.08
5.06
5.04
5.02
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
IOUT(A)
IOUT(A)
fSW = 500 kHz
VOUT = 3.3 V
PFM version
fSW = 500 kHz
VOUT = 5 V
PFM version
图7-5. 3.3-V Load Regulation
图7-6. 5-V Load Regulation
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5.5
5
4.5
4
IOUT=2mA
IOUT=1A
IOUT=3A
IOUT=5A
3.5
3
4
4.5
5
5.5
6
6.5
7
VIN(V)
fSW = 500 kHz
VOUT = 5 V
PFM version
fSW = 500 kHz
VOUT = 3.3 V
PFM version
图7-7. 5-V Dropout
图7-8. 3.3-V Dropout
图7-10. VIN UVLO
VFB = 1 V
图7-9. Non-Switching Input Supply Current
图7-11. Reference Voltage
图7-12. High Side and Low Side Switches RDS_ON
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图7-13. LMR51450 High Side and Low Side Current
图7-14. LMR51440 High Side and Low Side Current
Limits
Limits
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8 Detailed Description
8.1 Overview
The LMR514x0 converter is an easy-to-use synchronous step-down DC-DC converter operating from a 4-V to
36-V supply voltage. The device is capable of delivering up to 4-A or 5-A DC load current in a very small solution
size. The family has multiple versions applicable to various applications. See Device Comparison Table for
detailed information.
The LMR514x0 employs fixed-frequency peak-current mode control. The PFM version enters PFM Mode at light
load to achieve high efficiency. A FPWM version is provided to achieve low output voltage ripple, tight output
voltage regulation, and constant switching frequency at light load. The device is internally compensated, which
reduces design time and requires few external components.
Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for
a wide range of applications. Protection features include thermal shutdown, VIN undervoltage lockout, cycle-by-
cycle current limit, and hiccup mode short-circuit protection.
This family of devices requires very few external components and has a pin-out designed for simple, optimum
PCB layout.
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LMR514x0 refers to Functional Block Diagram and to the waveforms in
图 8-1. The LMR514x0 is a step-down synchronous buck converter with integrated high-side (HS) and low-side
(LS) switches (synchronous rectifier). The LMR514x0 supplies a regulated output voltage by turning on the high-
side and low-side NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin
voltage swings up to approximately VIN, and the inductor current, iL, increases with linear slope (VIN –VOUT) / L.
When the high-side switch is turned off by the control logic, the low-side switch is turned on after an anti-shoot-
through dead time. Inductor current discharges through the low-side switch with a slope of –VOUT / L. The
control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch
ON time and TSW is the switching period. The converter control loop maintains a constant output voltage by
adjusting the duty cycle D. In an ideal buck converter, where losses are ignored, D is proportional to the output
voltage and inversely proportional to the input voltage: D = VOUT / VIN.
VSW
VIN
D = tON/ TSW
tON
tOFF
t
0
TSW
iL
ILPK
IOUT
∆iL
t
0
图8-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LMR514x0 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally-compensated, which allows for fewer
external components, making designing easy, and providing stable operation when using a variety of output
capacitors. The converter operates with fixed switching frequency at normal load conditions. During light-load
condition, the LMR514x0 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM mode for
low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM version).
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8.3.2 Adjustable Output Voltage
A precision 0.8-V reference voltage (VREF) is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from VOUT to the FB pin. TI
recommends to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
bottom-side resistor RFBB for the desired divider current and use 方程式 1 to calculate top-side resistor RFBT
.
The recommend range for RFBT is 10 kΩ to 100 kΩ. A lower RFBT value can be used if pre-loading is desired to
reduce VOUT offset in PFM operation. Lower RFBT reduces efficiency at very light load. Less static current goes
through a larger RFBT and can be more desirable when light-load efficiency is critical. However, TI does not
recommend RFBT larger than 1 MΩ because it makes the feedback path more susceptible to noise. Larger RFBT
values require more carefully designed feedback path trace from the feedback resistors to the feedback pin of
the device. The tolerance and temperature variation of the resistor divider network affect the output voltage
regulation.
VOUT
RFBT
FB
RFBB
图8-2. Output Voltage Setting
V
− V
OUT
V
REF
R
=
× R
(1)
FBT
FBB
REF
8.3.3 Enable
The voltage on the EN pin controls the ON and OFF operation of the LMR514x0. A voltage of less than 0.8 V
shuts down the device, while a voltage of greater than 1.4 V is required to start the converter. The EN pin is an
input and cannot be left open or floating. The simplest way to enable the operation of the LMR514x0 is to
connect the EN to VIN. This connection allows self-start-up of the LMR514x0 when VIN is within the operating
range.
Many applications benefit from the employment of an enable divider RENT and RENB (图 8-3) to establish a
precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. System UVLO can be used for sequencing, ensuring reliable operation, or
supplying protection, such as a battery discharge level. An external logic signal can also be used to drive EN
input for system sequencing and protection. Note, the EN pin voltage must not to be greater than VIN + 0.3 V. TI
does not recommend to apply EN voltage when VIN is 0 V.
VIN
RENT
EN
RENB
图8-3. System UVLO by Enable Divider
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8.3.4 Switching Frequency
The switching frequency of the LMR514x0 can be programmed by the resistor RT from the RT pin and GND pin.
To determine the timing resistance for a given switching frequency, use 方程式 2 or the curve in 图 8-4. 表 8-1
gives typical RT values for a given fSW
.
−1.108
R
kΩ = 30542 × f
kHz
SW
(2)
T
图8-4. RT Versus Frequency Curve
表8-1. Typical Frequency Setting RT Resistance
fSW (kHz)
RT (kΩ)
84.5
200
400
39.2
31.6
495
500
800
Open or pull-up to voltage >1.0 V
18.2
14.3
1000
1000
Short to GND
8.3.5 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR514x0 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. Output voltage excursions
lasting less than t
35 μs (typical) do not trip the power-good flag. After the FB voltage has returned to the
dg
regulation value and after a delay of t pg-delay 3.1 ms (typical) , the power-good flag goes high.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic
supply. It can be pulled up to power supply below 20 V through a 10-kΩ to 100-kΩ resistor, as desired. If this
function is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low.
With EN low, power good remains valid as long as the input voltage is greater than or equal to 1.5 V (typical).
Limit the current into the power-good flag pin to less than 5-mA D.C.
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图8-5. Static Power-Good Operation
图8-6. Power-Good Timing Behavior (OV Events Not Included)
8.3.6 Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback
Minimum ON-time (TON_MIN) is the shortest duration of time that the high-side switch can be turned on. TON_MIN
is typically 75 ns for the LMR514x0 . Minimum OFF-time (TOFF_MIN) is the shortest duration of time that the high-
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side switch can be off. TOFF_MIN is typically 135 ns. In CCM operation, TON_MIN and TOFF_MIN limit the voltage
conversion range without switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is:
D
= T
× f
SW
(3)
(4)
MIN
ON_MIN
The maximum duty cycle without frequency foldback allowed is:
D
= 1 − T
× f
OFF_MIN SW
MAX
Given a required output voltage, the maximum VIN without frequency foldback can be found by:
V
OUT
V
=
(5)
(6)
IN_MAX
f
× T
SW
ON_MIN
The minimum VIN without frequency foldback can be calculated by:
V
OUT
V
=
1 − f
IN_MIN
× T
SW
OFF_MIN
In the LMR514x0, a frequency foldback scheme is employed after the TON_MIN or TOFF_MIN is triggered, which
can extend the maximum duty cycle or lower the minimum duty cycle.
The on-time decreases while VIN voltage increases. After the on-time decreases to TON_MIN, the switching
frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in
regulation according to Equation 5.
The frequency foldback scheme also works after larger duty cycle is needed under low VIN condition. The
frequency decreases after the device hits its TOFF_MIN, which extends the maximum duty cycle according to
Equation 6. In such condition, the frequency can be as low as approximately 200 kHz. Wide range of frequency
foldback allows for the LMR514x0 output voltage to stay in regulation with a much lower supply voltage VIN,
which leads to a lower effective dropout.
With frequency foldback while maintaining a regulated output voltage, VIN_MAX is raised, and VIN_MIN is lowered
by decreased fSW
.
8.3.7 Bootstrap Voltage
The LMR514x0 provides an integrated bootstrap voltage converter. A small capacitor between the CB and SW
pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when the
high-side MOSFET is off and the low-side switch is on. The recommended value of the bootstrap capacitor is 0.1
µF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or
higher for stable performance over temperature and voltage.
8.3.8 Overcurrent and Short-Circuit Protection
The LMR514x0 incorporates both peak and valley inductor current limit to provide protection to the device from
overloads and short circuits and limit the maximum output current. Valley current limit prevents inductor current
runaway during short circuits on the output, while both peak and valley limits work together to limit the maximum
output current of the converter. Cycle-by-cycle current limit is used for overloads, while hiccup mode is used for
sustained short circuits.
High-side MOSFET overcurrent protection is implemented by the nature of the peak current mode control. The
high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch
current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle.
See Functional Block Diagram for more details. The peak current of high-side switch is limited by a clamped
maximum peak current threshold Isc which is constant.
The current going through low-side MOSFET is also sensed and monitored. When the low-side switch turns on,
the inductor current begins to ramp down. The low-side switch is not turned OFF at the end of a switching cycle
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if its current is above the low-side current limit ILS_LIMIT . The low-side switch is kept ON so that inductor current
keeps ramping down, until the inductor current ramps below the ILS_LIMIT. Then the low-side switch is turned OFF
and the high-side switch is turned on after a dead time. After ILS_LIMIT is achieved, peak and valley current limit
controls the maximum current deliver and can be calculated using Equation 7.
I
+ I
SC
LS_LIMIT
2
I
=
(7)
OUT_MAX
If the feedback voltage is lower than 40% of the VREF, the current of the low-side switch triggers ILS_LIMIT for 128
consecutive cycles and hiccup current protection mode is activated. In hiccup mode, the converter shuts down
and keeps off for a period of hiccup, THICCUP (96-ms typical) before the LMR514x0 tries to start again. If
overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup
mode reduces power dissipation under severe overcurrent conditions, prevents over-heating and potential
damage to the device.
For FPWM version, the inductor current is allowed to go negative. When this current exceed the low-side
negative current limit ILS_NEG, the low-side switch is turned off and high-side switch is turned on immediately.
This is used to protect the low-side switch from excessive negative current.
8.3.9 Soft Start
The integrated soft-start circuit prevents input inrush current impacting the LMR514x0 and the input power
supply. Soft start is achieved by slowly ramping up the internal reference voltage when the device is first enabled
or powered up. The typical soft-start time is 5 ms.
8.3.10 Thermal Shutdown
The LMR514x0 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 160°C. Both high-side and low-side FETs stop switching in thermal shutdown. After the die temperature
falls below 140°C, the device reinitiates the power-up sequence controlled by the internal soft-start circuitry.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMR514x0. When VEN is below 0.8 V, the device is in
shutdown mode. The LMR514x0 also employs VIN undervoltage lockout protection (UVLO). If VIN voltage is
below its UVLO threshold 3.4 V, the converter is turned off.
8.4.2 Active Mode
The LMR514x0 is in active mode when both VEN and VIN are above their respective operating threshold. The
simplest way to enable the LMR514x0 is to connect the EN pin to VIN pin. This allows self-start-up when the
input voltage is in the operating range of 4 V to 36 V. See Enable for details on setting these operating levels.
In active mode, depending on the load current, the LMR514x0 is in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is greater than half of
the peak-to-peak inductor current ripple (for both PFM and FPWM versions)
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is less than half of
the peak-to-peak inductor current ripple(only for PFM version)
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM version)
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM version).
8.4.3 CCM Mode
Continuous Conduction Mode (CCM) operation is employed in the LMR514x0 when the load current is greater
than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed, output
voltage ripple is at a minimum in this mode and the maximum output current of 4 A or 5 A can be supplied by the
LMR514x0.
8.4.4 Light-Load Operation (PFM Version)
For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
LMR514x0 operates in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In
DCM operation, the low-side switch is turned off when the inductor current drops to ILS_ZC (100-mA typical) to
improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to forced PWM
operation at light load.
During light load operation, Pulse Frequency Modulation (PFM) mode is activated to maintain high efficiency
operation. When either the minimum high-side switch ON time tON_MIN or the minimum peak inductor current
IPEAK_MIN (1-A typical for LMR51450 and 0.8-A typical for LMR51440) is reached, the switching frequency
decreases to maintain regulation. In PFM mode, switching frequency is decreased by the control loop to
maintain output voltage regulation when load current reduces. Switching loss is further reduced in PFM
operation due to a significant drop in effective switching frequency.
8.4.5 Light-Load Operation (FPWM Version)
For FPWM version, LMR514x0 is locked in PWM mode at full load range. This operation is maintained, even in
no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off reduced
light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching
frequency.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LMR514x0 is a step-down DC-to-DC converter. The device is typically used to convert a higher input voltage
to a lower output DC voltage with a maximum output current of 4 A or 5 A. The following design procedure can
be used to select components for the LMR514x0 . Alternately, the WEBENCH® software can be used to
generate complete designs. When generating a design, the WEBENCH® software uses iterative design
procedure and accesses comprehensive databases of components. Go to ti.com for more details.
备注
All of the capacitance values given in the following application information refer to effective values
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and
temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with
an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to
ensure that the minimum value of effective capacitance is provided.
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9.2 Typical Application
The LMR514x0 only requires a few external components to convert from a wide voltage range supply to a fixed
output voltage. 图9-1 shows a basic schematic.
CBOOT
VIN
VIN
EN
BOOT
SW
LOUT
VOUT
CIN
CHF
RFF
CFF
RFBT
LMR51450
COUT
RT
PG
FB
RFBB
RT
AGND
PGND
图9-1. Application Circuit
The external components have to fulfill the needs of the application and the stability criteria of the control loop of
the device. Use 表9-1 and 表9-2 to simplify the output filter component selection.
表9-1. L and COUT Typical Values for LMR51440
fSW (kHz)
VOUT (V)
L (µH)
COUT (µF) (1)
CFF (pF)
RFBT (kΩ)
RFBB (kΩ)
RFF (kΩ)
3.3
5
4.7
2 × 47
100
31.6
33
33
33
1
1
1
500
5.6
2 × 33
100
19.1
12
8.2
2 × 10
100
7.15
3.3
5
2.2
3.3
47
33
100
100
31.6
19.1
22
22
1
1
1000
(1) A ceramic capacitor is used in this table. All the COUT values are after derating.
表9-2. L and COUT Typical Values for LMR51450
fSW (kHz)
VOUT (V)
L (µH)
COUT (µF) (1)
CFF (pF)
RFBT (kΩ)
RFBB (kΩ)
RFF (kΩ)
3.3
5
3.3
2 × 47
100
31.6
33
33
33
1
1
1
500
4.7
2 × 33
100
19.1
12
6.8
2 × 10
100
7.15
(1) A ceramic capacitor is used in this table. All the COUT values are after derating.
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9.2.1 Design Requirements
The detailed design procedure is described based on a design example. For this design example, use the
parameters listed in 表9-3 as the input parameters.
表9-3. Design Example Parameters
PARAMETER
VALUE
Input voltage, VIN
12-V typical, range from 6 V to 36 V
Output voltage, VOUT
5 V ±3%
5 A
Maximum output current, IOUT_MAX
Output overshoot/ undershoot 1.5 A to 4 A
Output voltage ripple
5%
0.5%
Operating frequency
500 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Set-Point
The output voltage of the LMR514x0 device is externally adjustable using a resistor divider network. The divider
network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 8 is used to
determine the output voltage of the converter:
V
− V
OUT
V
REF
R
=
× R
(8)
FBT
FBB
REF
Choose the value of RFBB to be 19.1 kΩ. With the desired output voltage set to 5 V and the VREF = 0.8 V, the
RFBT value can then be calculated using Equation 8. The formula yields to a value 100.28 kΩ, a standard value
of 100 kΩ is selected.
9.2.2.2 Switching Frequency
The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in
smaller solution size and lower component cost. However, higher switching frequency brings more switching
loss, making the solution less efficient and produce more heat. The switching frequency is also limited by the
minimum on-time of the integrated power switch, the input voltage, the output voltage, and the frequency shift
limitation as mentioned in Minimum ON-Time, Minimum OFF-Time, and Frequency Foldback.
For this example, a switching frequency of 500 kHz is selected. RT open defaults to 500 kHz.
9.2.2.3 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 10 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND must be 20% to 60% of maximum IOUT supported by converter. During an instantaneous overcurrent
operation event, the RMS and peak inductor current can be high. The inductor saturation current must be higher
than peak current limit level.
V
× V
− V
OUT
V
IN_MAX
× L × f
OUT
SW
∆ i =
(9)
L
IN_MAX
V
− V
V
IN_MAX
OUT
OUT
× f
L
=
×
(10)
MIN
I
× K
V
OUT
IND
IN_MAX
SW
In general, choosing lower inductance in switching power supplies is preferable because it usually corresponds
to faster transient response, smaller DCR, and reduced size for more compact designs. Too low of an inductance
can generate too large of an inductor current ripple such that overcurrent protection at the full load can be falsely
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triggered. It also generates more inductor core loss because the current ripple is larger. Larger inductor current
ripple also implies larger output voltage ripple with the same output capacitors. With peak current mode control,
TI recommends to have adequate amount of inductor ripple current. A larger inductor ripple current improves the
comparator signal-to-noise ratio.
For this design example, choose KIND = 0.4. The minimum inductor value is calculated to be 4.31 µH. Choose
the nearest standard 4.7 µH power inductor with a capability of 6 -A RMS current and 10 -A saturation current.
9.2.2.4 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. Minimize the output capacitance to keep cost
and size down. The output capacitor or capacitors, COUT, must be chosen with care because it directly affects
the steady state output voltage ripple, loop stability, and output voltage overshoot and undershoot during load
current transient. The output voltage ripple is essentially composed of two parts. One part is caused by the
inductor ripple current flowing through the Equivalent Series Resistance (ESR) of the output capacitors:
∆ V
= ∆ i × ESR = K
× I × ESR
OUT
(11)
OUT_ESR
L
IND
The other part is caused by the inductor current ripple charging and discharging the output capacitors:
∆ i
K
× I
L
IND OUT
∆ V
=
=
(12)
OUT_C
8 × f
× C
8 × f × C
SW
OUT
SW
OUT
The two components of the voltage ripple are not in-phase, therefore, the actual peak-to-peak ripple is less than
the sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rates. When a large load step occurs, output
capacitors provide the required charge before the inductor current can slew to an appropriate level. The control
loop of the converter usually requires eight or more clock cycles to regulate the inductor current equal to the new
load level during this time. The output capacitance must be large enough to supply the current difference for 6
clock cycles to maintain the output voltage within the specified range. Equation 13 shows the minimum output
capacitance needed for a specified VOUT overshoot and undershoot.
6 × I
OH
− I
OL
1
2
C
>
×
(13)
OUT
f
× ∆ V
SW
OUT_SHOOT
where
• KIND = Ripple ratio of the inductor current (ΔiL / IOUT
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
)
• VOUT_SHOOT = Target output voltage overshoot or undershoot
For this design example, the target output ripple is 25 mV. Assuming ΔVOUT_ESR = ΔVOUT_C = 25mV, choose
IND = 0.4. Equation 11 yields ESR no larger than 12.5 mΩ and Equation 12 yields COUT no smaller than 20 µF.
K
For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 5% × VOUT = 250 mV. The
COUT can be calculated to be no less than 60 µF by Equation 13. In summary, the most stringent criteria for the
output capacitor is 60 µF. Considering derating, two 33-µF, 16-V, X7R ceramic capacitor with 5-mΩ ESR is used.
9.2.2.5 Input Capacitor Selection
The LMR514x0 device requires a high frequency input decoupling capacitor or capacitor. The typical
recommended value for the high frequency decoupling capacitor is 10 µF or higher. TI recommends a high-
quality ceramic type X5R or X7R with sufficiency voltage rating. The voltage rating must be greater than the
maximum input voltage. To compensate the derating of ceramic capacitors, TI recommends a voltage rating of
twice the maximum input voltage. For this design, two 4.7-µF, X7R dielectric capacitor rated for 50 V is used for
the input decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ. Include a
capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the device pins.
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9.2.2.6 Bootstrap Capacitor
Every LMR514x0 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is 0.1 µF
and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.7 Undervoltage Lockout Set-Point
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. Equation 14 can be used to determine the VIN UVLO level.
R
+ R
EBT
R
ENB
V
= V
×
ENH
(14)
IN_RISING
ENB
The EN rising threshold (VENH) for LMR514x0 is set to be 1.25 V (typical). Choose a value of 21.5 kΩ for RENB
to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT can be
calculated using Equation 15:
V
IN_RISING
R
=
− 1 × R
(15)
EBT
ENB
V
ENH
The above equation yields a value of 81.7 kΩ, a standard value of 82 kΩis selected. The resulting falling UVLO
threshold, equals 4.8 V, can be calculated by Equation 16 where EN hysteresis voltage, VEN_HYS, is 0.25 V
(typical).
R
+ R
EBT
R
ENB
V
= V
− V ×
ENH_HYS
(16)
IN_FALLING
ENH
ENB
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, VOUT = 5 V, fSW =500 kHz, L = 4.7 µH,
COUT = 66 µF, T = 25°C.
图9-2. Ripple at No Load
图9-4. Start-Up by VIN
图9-6. Load Transient
图9-3. Ripple at Full Load
图9-5. Start-Up by EN
图9-7. Line Transient
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图9-8. Short Protection
图9-9. Short Recovery
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9.3 Best Design Practices
• Do not exceed the Absolute Maximum Ratings .
• Do not exceed the Recommended Operating Conditions.
• Do not exceed the ESD Ratings.
• Do not allow the EN input to float.
• Do not allow the output voltage to exceed the input voltage, nor go below ground.
• Follow all the guidelines and suggestions found in this data sheet before committing the design to production.
TI application engineers are ready to help critique your design and PCB layout to help make your project a
success.
9.4 Power Supply Recommendations
The LMR514x0 is designed to operate from an input voltage supply range between 4 V and 36 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the LMR514x0 supply voltage that can cause a false UVLO fault triggering and system reset. If
the input supply is located more than a few inches from the LMR514x0 additional bulk capacitance can be
required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but a 47-µF
or 100-µF electrolytic capacitor is a typical choice.
9.5 Layout
9.5.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with
the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding
for both the input and output capacitors must consist of localized top side planes that connect to the PGND
pin.
2. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB, must be located close to
the FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT
sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.
4. Make VIN, VOUT, and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the top side ground
plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal
vias can also be connected to inner layer heat-spreading ground planes. Make sure enough copper area is
used for heat-sinking to keep the junction temperature below 150°C.
9.5.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing a
ceramic bypass capacitor or capacitors as close as possible to the VIN and PGND pins is the key to EMI
reduction.
The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) must be used for high current
conduction path to minimize parasitic resistance. The output capacitors must be placed close to the VOUT end of
the inductor and closely grounded to PGND pin.
9.5.1.2 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, make sure to place the resistor divider close to
the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high impedance
node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace length of FB
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signal and reduces noise coupling. The output node is a low impedance node, so the trace from VOUT to the
resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provides the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider must be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. TI recommends to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This action provides
further shielding for the voltage feedback path from EMI noises.
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9.5.2 Layout Example
Top Trace
Bo om Trace
VIA to Ground Plane
INDUCTOR
COUT
COUT
CIN-HF
CIN
CIN
SW
SW
VIN
VIN
VIN
EN
SW
si
BOOT
PG
RT
AGND
FB
GND
HEATSINK
图9-10. Layout
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
10.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR51450 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Layout Guidelines for Switching Power Supplies
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Texas Instruments, How to Properly Evaluate Junction Temperature with Thermal Metrics
10.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR51440SDRRR
LMR51450FNDRRR
LMR51450SDRRR
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
DRR
DRR
DRR
12
12
12
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
L5144S
Samples
Samples
Samples
NIPDAU
NIPDAU
L5145F
L5145S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DRR0012G
WSON - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
3.1
2.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
1.3 0.1
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
(0.43) TYP
7
6
SYMM
13
2X 2.5
2.5 0.1
10X 0.5
1
12
0.3
12X
0.2
PIN 1 ID
(45 X 0.3)
0.52
0.32
12X
0.1
C A B
C
0.05
4227052/A 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRR0012G
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.3)
SEE SOLDER MASK
DETAIL
12X (0.62)
SYMM
12
1
12X (0.25)
(2.5)
10X (0.5)
13
SYMM
(1)
(R0.05) TYP
6
7
(
0.2) TYP
VIA
(2.78)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4227052/A 08/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRR0012G
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
12X (0.62)
2X (1.21)
12
12X (0.25)
1
10X (0.5)
(0.65)
13
SYMM
(R0.05) TYP
2X (1.1)
7
6
SYMM
(2.78)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 13
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4227052/A 08/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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