LMS3655AMRNLT_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

LMS3655 5.5A、36V 同步、400kHz 直流/直流降压转换器

1 特性

3 说明

1

•

在将 12V 转换为 5V 时具有 96% 的峰值效率

低 EMI 和开关噪声

LMS3655 同步降压稳压器针对高性能应用进行了优

化，可提供 1V 至 20V 的可调节输出。PWM 和 PFM

模式之间的无缝转换以及低静态电流可确保在所有负载

下实现高效率和出色的瞬态响应。

–

最少的开关节点振铃

假随机扩频

•

400kHz (±10%) 固定开关频率

高级高速电路支持 LMS3655 将 24V 的输入调节至

3.3V 的输出（400kHz 固定频率），同时还支持 5.5A

的持续负载电流。创新的频率折返架构允许该器件通过

仅 3.5V 的输入电压调节生成 3.3V 的输出。输入电压

范围可高达 36V，瞬态容差高达 42V，有助于轻松实

现输入浪涌保护设计。

–40°C 至 +150°C 结温范围

外部频率同步

具有内部滤波器和 3ms 释放计时器的 RESET 输出

可提高效率的自动轻负载模式

引脚可选强制 PWM 模式

内置补偿、软启动、电流限制、热关断和 UVLO

25°C 时在 3.5A 负载下具有 0.35V 压降（典型值）

开漏复位输出具有内置的滤波和延迟功能，可提供正确

的系统状态指示。凭借这一特性，器件无需使用附加监

控组件，这节省了成本和电路板空间。

32µA I_{Q_VIN}：在 3.3V_OUT且无负载情况下的静态电

流（典型值）

•

5.5A 持续负载电流

器件信息⁽¹⁾

可调节输出电压（1V 至 20V）

±1.5% 基准电压容差

器件名称

LMS3655

封装

封装尺寸

VQFN-HR (22)

4.00mm × 5.00mm

4mm × 5mm、0.5mm 间距 SON 封装

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

•

噪声敏感型医疗应用

电信

高性能工业

典型应用电路

LMS3655 效率：输出电压 = 5V

VIN

3.5 V to 36 V

100%

98%

96%

94%

92%

90%

88%

86%

84%

10 µF

PVIN 1

PVIN 2

10 µF

PGND1

AVIN

PGND2

RESET

VCC

SYNC

4.7 µF

LMS3655

BIAS

AGND

0.1 µF

FB

NC

CFF

RFBB

RFBT

FPWM

CBOOT

470 nF

SW

V_IN= 12

V_IN= 24

EN

82%

80%

L1=10 µH

V_OUT

3 X 47 µF

0.001

0.01

0.1

1

10

Output Current (A)

LMS3

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNAS744

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 19

Application and Implementation ........................ 23

9.1 Application Information............................................ 23

9.2 Typical Applications ................................................ 23

9.3 Do's and Don't's ...................................................... 40

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Thermal Information (for Device Mounted on PCB).. 6

7.6 Electrical Characteristics........................................... 6

7.7 System Characteristics ............................................. 8

7.8 Timing Requirements................................................ 9

7.9 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 13

9

10 Power Supply Recommendations ..................... 40

11 Layout................................................................... 40

11.1 Layout Guidelines ................................................. 40

11.2 Layout Example .................................................... 42

12 器件和文档支持 ..................................................... 43

12.1 器件支持................................................................ 43

12.2 文档支持................................................................ 43

12.3 接收文档更新通知 ................................................. 43

12.4 社区资源................................................................ 43

12.5 商标....................................................................... 43

12.6 静电放电警告......................................................... 43

12.7 Glossary................................................................ 43

13 机械、封装和可订购信息....................................... 43

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (October 2017) to Revision B

Page

•

将最大可调节输出电压从 15V 更改成了 20V.......................................................................................................................... 1

Changed maximum extended output adjustment from: 15 V to: 20 V .................................................................................. 5

Added new extended output adjustment tablenote to the Recommended Operating Conditions.......................................... 5

Changes from Original (July 2017) to Revision A

Page

•

Changed symbol from: I_Bto: I_{B_NSW}....................................................................................................................................... 6

Added I_Bspec to System Characteristics............................................................................................................................... 8

Added System Characteristics crossreference links for the I_Bspec..................................................................................... 18

2

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

5 Device Comparison Table

Table 1. LMS3655 Devices (5.5-A Output)

SPREAD

SPECTRUM

PART NUMBER

OUTPUT VOLTAGE

PACKAGE QTY

LMS3655AMRNLR

LMS3655AMRNLT

LMS3655MMRNLR

LMS3655MMRNLT

Adjustable

No

3000

250

Yes

3000

250

3

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

6 Pin Configuration and Functions

RNL Package

22-Pin VQFN

Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Internal 3.1-V LDO output. Used as supply to internal control circuits. Connect a high-quality 4.7-µF

capacitor from this pin to AGND.

1

VCC

A

P

I

Bootstrap capacitor connection for gate drivers. Connect a high quality 470-nF capacitor from this pin to

the SW pin.

2

3

4

CBOOT

SYNC

Synchronization input to regulator. Used to synchronize the device switching frequency to a system clock.

Triggers on rising edge of external clock; frequency must be in the range of 250 kHz and 500 kHz.

Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect

PVIN1 and PVIN2 pins directly together at PCB.

PVIN1

P

5

6

Power ground to internal low-side MOSFET. These pins must be tied together on the PCB. Connect

PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground.

PGND1

SW

G

P

7

8

9

Regulator switch node. Connect to power inductor.

10

11

12

13

Power ground to internal low-side MOSFET. These pins must be tied together. Connect PGND1 and

PGND2 directly together at PCB. Connect to AGND and system ground.

PGND2

G

Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect

PVIN1 and PVIN2 pins directly together at PCB.

14

PVIN2

P

15

16

1 7

18

AVIN

FPWM

NC

A

I

Analog VIN. Connect to PVIN1 and PVIN2 on PCB.

Mode control input of regulator. High = FPWM, low = Automatic light load mode. Do not float.

No internal connection.

—

I

EN

Enable input to regulator. High = on, Low = off. Can be connected to VIN. Do not float.

Open-drain reset output flag. Connect to suitable voltage supply through a current limiting resistor. High =

regulator OK, Low = regulator fault. Goes low when EN = low.

19

20

RESET

AGND

O

G

Analog ground for regulator and system. All electrical parameters are measured with respect to this pin.

Connect to PGND on PCB.

21

22

FB

A

P

Feedback input to regulator. Connect to feedback voltage divider.

Input to auxiliary bias regulator. Connect to output voltage node.

BIAS

(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

4

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

7 Specifications

7.1 Absolute Maximum Ratings

(1)

Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted).

PARAMETER

VIN (AVIN, PVIN1, and PVIN2) to AGND, PGND⁽²⁾

SW to AGND, PGND⁽³⁾

MIN

–0.3

MAX

40

UNIT

V

V_IN+ 0.3

3.6

V

CBOOT to SW

EN to AGND, PGND⁽²⁾

V

40

V

BIAS to AGND, PGND

16

V

FB to AGND, PGND

16

V

RESET to AGND, PGND

RESET sink current⁽⁴⁾

SYNC to AGND, PGND⁽²⁾

FPWM to AGND, PGND⁽²⁾

VCC to AGND, PGND

8

V

10

mA

V

–0.3

–40

40

V

3.6

V

Junction temperature

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) A maximum of 42 V can be sustained at this pin for a duration of ≤ 500 ms at a duty cycle of ≤ 0.01%.

(3) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.

(4) Do not exceed the voltage rating on this pin.

7.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted).

MIN

3.9

3.3

1

NOM

MAX

36

UNIT

V

Input voltage after start-up⁽¹⁾

Output adjustment for LMS3655⁽²⁾

Extended output adjustment for LMS3655⁽³⁾⁽⁴⁾

Load current for LMS3655

6

V

20

V

5.5

125

A

Operating ambient temperature⁽⁵⁾

–40

°C

(1) An extended input voltage range to 3.5 V is possible; see System Characteristics table. See Input UVLO for start-up conditions.

(2) The output voltage must not be allowed to fall below zero volts during normal operation.

(3) Operation below 3.3 V and above 6 V may require changes to the typical application schematic, operation may not be possible over the

full input voltage range, and some system specifications will not be achieved for this extended output voltage range. Consult the factory

for further information.

(4) Operation above 15 V requires the BIAS pin grounded or powered by an external source. A maximum of 16 V can be sustained on the

BIAS pin.

(5) High junction temperatures degrade operating lifetime.

5

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

7.4 Thermal Information

LMS3655

RNL (VQFN)

22 PINS

38.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

16.3

16.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.0

ψ_JB

16.4

R_θJC(bot)

4.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Thermal Information (for Device Mounted on PCB)

LMS3655

THERMAL METRIC⁽¹⁾

RNL (VQFN)

22 PINS

29.4

UNIT

R_θJA

R_θJC

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

14.2

5.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.2

ψ_JB

5.4

R_θJC(bot)

2.4

(1) Mounted on a thermally optimized FR4 four layer EVM with a size of 4000 mill × 3000 mill.

7.6 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

V_IN= 3.8 V to 36 V, T_J= 25°C

V_IN= 3.8 V to 36 V

MIN

–1%

TYP

MAX

1%

UNIT

Initial reference voltage for 5-V

and 3.3-V options

V_FB

–1.5%

1.5%

Operating quiescent current;

measured at VIN pin when

enabled and not switching⁽¹⁾

I_Q

V_IN= 13.5 V, V_BIAS= 5 V

7.5

16

µA

V_IN= 13.5 V, V_BIAS= 5 V, FPWM =

0 V

53

2

62

3

Bias current into BIAS pin,

enabled, not switching

I_{B_NSW}

V_IN= 13.5 V, V_BIAS= 3.3 V, FPWM

= 0 V

Shutdown quiescent current;

measured at VIN pin

I_SD

EN ≤ 0.4 V

µA

V

Rising

3.2

2.95

3.55

3.25

0.3

3.90

3.55

V_IN-OPERATE

Minimum input voltage to operate Falling

Hysteresis

0.28

0.4

RESET upper threshold voltage

RESET lower threshold voltage

Rising, % of V_OUT

Falling, % V_OUT

105%

92%

107%

94%

110%

96.5%

V_RESET

Magnitude of RESET lower

threshold from steady state

output voltage

Steady-state output voltage and

RESET falling threshold read at the

same T_Jand V_IN

96%

(1) This is the current used by the device while not switching, open loop on the ATE. It does not represent the total input current from the

regulator system.

6

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESET hysteresis as a percent of

output voltage setpoint

V_{RESET_HYST}

V_{RESET_VALID}

±1%

50-µA pullup to RESET pin,

EN = 0 V, T_J= 25°C

Minimum input voltage for proper

RESET function

1.5

0.4

440

V

50-µA pullup to RESET pin,

V_IN= 1.5 V, EN = 0 V

0.5-mA pullup to RESET pin,

V_IN= 13.5 V, EN = 0 V

Low level RESET function output

voltage

V_OL

V

1-mA pullup to RESET pin,

V_IN= 13.5 V, EN = 3.3 V

V_IN= 13.5 V, center frequency with

spread spectrum, PWM operation

360

400

F_SW

Switching frequency

kHz

V_IN= 13.5 V, without spread

spectrum, PWM operation

400

F_SYNC

D_SYNC

Sync frequency range

250

25%

1.5

500

Sync input duty cycle range

High state input < 5.5 V and > 2.3 V

FPWM input high (MODE = FPWM)

75%

FPWM input low (MODE = AUTO

with diode emulation)

V_FPWM

FPWM input threshold voltage

0.4

1

V

FPWM input hysteresis

0.15

Frequency span of spread

spectrum operation

FS_SS

F_PSS

±3%

Spread-spectrum pattern

frequency⁽²⁾

1.2

Hz

µA

V_IN= 13.5 V, V_FPWM= 3.3 V

V_IN= V_FPWM= 13.5 V

V_IN= 13.5 V, V_SYNC= 3.3 V

V_IN= V_SYNC= 13.5 V

LMS3655

1

I_FPWM

FPWM leakage current

SYNC leakage current

1

I_SYNC

µA

1

I_L-HS

I_L-LS

High-side switch current limit

Low-side switch current limit

6.7

6

8.5

7

9.5

7.7

A

LMS3655

Zero-cross current limit FPWM =

low

I_L-ZC

–0.02

–1.5

60

A

Negative current limit FPWM =

high

I_L-NEG

High-side MOSFET R_DSON

V_IN= 13 V, IL = 1 A

,

130

80

R_DSON

Power switch on-resistance

mΩ

Low-side MOSFET R_DSON

,

40

V_IN= 13 V, IL = 1 A

Enable input threshold voltage -

rising

V_EN

Enable rising

1.7

2

V

V_{EN_HYST}

V_{EN_WAKE}

I_EN

Enable threshold hysteresis

Enable wake-up threshold

EN pin input current

0.45

0.4

0.55

V

V_IN= V_EN= 13.5 V

2

3.05

3.15

2.7

3

µA

V_IN= 13.5 V, V_BIAS= 0 V

V_CC

Internal V_CCvoltage

V

V_IN= 13.5 V, V_BIAS= 3.3 V

V_INrising

V

Internal V_CCinput undervoltage

lockout

V_{CC_UVLO}

Hysteresis below V_CC-UVLO

185

mV

(2) Ensured by Design, Not tested at production.

7

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

FB = 1 V

MIN

TYP

20

1

MAX

UNIT

I_FB

Input current from FB to AGND

nA

T_J= 25°C

0.993

0.99

1.007

1.01

V_REF

Reference voltage

V

T_J= –40°C to 125°C

1

Pull FB pin low. Sink 1-mA at

RESET pin

R_RESET

R_DSONof RESEToutput

50

120

Ω

V_IH

1.5

V_SYNC

V_IL

0.4

1

V

V_HYST

0.15

160

Rising

185

T_SD

Thermal shutdown thresholds⁽²⁾

°C

Hysteresis

15

F_sw= 400 kHz

While in dropout⁽²⁾

96%

D_MAX

Maximum switch duty cycle

98%

7.7 System Characteristics

The following specifications are ensured by design provided that the component values in the typical application circuit are

used. These parameters are not ensured by production testing. Limits apply over the recommended operating junction

temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only. Unless otherwise stated the following conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum input voltage for full functionality at

3.5-A load, after start-up.

V_OUT= 3.3 V +2% or –3% regulation

3.5

V_IN-MIN

V

Minimum input voltage for full functionality at

maximum rated load 5.5 A after start-up.

V_OUT= 3.3 V +2% or –3% regulation

V_IN= V_OUT+ 1 V to 36 V, I_OUT= 3.5 A

3.8

V_OUT

F_SW

Output voltage

–2.25%

2.25%

V_IN= 24 V, FPWM = 24V, V_OUT= 3.3 V,

I_OUT= 200 mA

Switching frequency

400

32

kHz

µA

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 0 A ,

FPWM = 0, RFBT = 49.9 kΩ, RFBB = 21.7

kΩ

I_{Q_VIN}

Input current to VIN pin

V_IN= 13.5 V, V_OUT= 5.0 V, I_OUT= 0 A,

FPWM = 0, RFBT = 49.9 kΩ, RFBB = 12.4

kΩ

57

I_B

Bias current in AUTO mode at no load

V_IN= 13.5 V, I_OUT= 0 A, FPWM = 0

32

42

µA

V

V_OUT= 3.3 V or 5 V, I_OUT= 3.5 A, +2% or

–3% output accuracy

0.35

0.6

Minimum input to output voltage differential to

maintain regulation accuracy without inductor

DCR drop

V_DROP1

V_OUT= 3.3 V or 5 V, I_OUT= 5.5 A, +2% or

–3% output accuracy

0.65

0.5

0.85

0.7

V

V_OUT= 3.3 V or 5 V, I_OUT= 3.5 A,

F_SW= 330 kHz, 2% regulation accuracy

Minimum input to output voltage differential to

maintain F_SW≥ 330 kHz without inductor DCR

drop

V_DROP2

V_OUT= 3.3 V or 5 V, I_OUT= 5.5 A,

F_SW= 330 kHz, 2% regulation accuracy

0.7

1.2

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 3.5 A

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 3.5 A

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 100 mA

94%

92%

Efficiency

Typical efficiency

8

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

7.8 Timing Requirements

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

MIN

NOM

60

65

3

MAX

UNIT

t_ON

Minimum switch on-time, V_IN= 18 V, I_L= 1 A

Minimum switch off-time, V_IN= 3.8 V, I_L= 1 A

Delay time to RESET high signal

84

ns

t_OFF

80

ns

t_RESET-act

t_RESET-filter

t_SS

2

4

ms

µs

Glitch filter time for RESET function⁽¹⁾

24

4

Soft-start time from first switching pulse to V_REFat 90%

Turnon delay, C_VCC= 4.7 µF⁽²⁾

2.5

5

ms

t_EN

0.8

6

t_W

Short-circuit wait time (hiccup time)⁽³⁾

Change transition time from AUTO to FPWM MODE, 10-mA load, V_IN= 13.5 V

Change transition time from FPWM to AUTO MODE, 10-mA load, V_IN= 13.5 V

250

450

t_FPWM

µs

(1) See Detailed Description.

(2) This is the time from the rising edge of EN to the time that the soft-start ramp begins.

(3) T_wis the wait time between current limit trip and restart. T_wis proportional to the soft-start time. However, provision must be made to

make T_wlonger to ensure survivability during an output short circuit.

9

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

7.9 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25ºC. Specified temperatures are ambient.

104%

103%

102%

101%

100%

99%

450000

440000

430000

420000

410000

400000

390000

380000

370000

360000

350000

-50

-25

0

25

50

75

100 125 150 175

-40

10

60

110

160

Temperature (èC)

LMS3

V_IN= 12 V

Figure 1. Reference Voltage Drift

V_IN= 12 V

Figure 2. Switching Frequency vs Temperature

10

8

7

6

5

4

3

2

1

0

6

4

2

LMS3655

150 200

LMS3655

0

-50

0

50

100

-50

0

50

100

150

200

Temperature (èC)

LMS3

V_IN= 12 V

V_IN= 12V

Figure 3. High-Side/Peak Current Limit for LMS3655

Figure 4. Low-Side/Valley Current Limit for LMS3655

25

0.25

0.2

0.15

0.1

0.05

0

3.8 V_IN

5.5 V_IN

13.5 V_IN

18 V_IN

20

15

10

5

0

-50

0

5

10

15

20

25

30

35

40

0

50

100

150

200

Temperature (èC)

LMS3

V_IN= 12 V

Figure 5. Short Circuit Average Input Current

for LMS3655

Figure 6. Shutdown Current

10

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25ºC. Specified temperatures are ambient.

5.4

5.3

5.2

5.1

5

108%

106%

104%

102%

100%

98%

V_{RESET_UPPER}

V_{RESET_UPPER_FALLING}

V_OUT

4.9

4.8

4.7

4.6

4.5

V_{RESET_LOWER_RISING}

V_{RESET_LOWER}

96%

V_{RESET_LOWER}

94%

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Termperature (èC)

Temperature (èC)

D026

D027

Figure 7. RESET Threshold 5-V Output

Figure 8. RESET Threshold as Percentage of Output Voltage

11

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

8 Detailed Description

8.1 Overview

The LMS3655 devices are wide-input voltage range, low quiescent current, high-performance regulators with

internal compensation. This device is designed to minimize end-product cost and size while operating in

demanding high-performance industrial environments. Normal operating frequency is 400 kHz allowing the use of

small passive components. This device has a low unloaded current consumption, eliminating the need for an

external backup LDO. The LMS3655 low shutdown current and high maximum operating voltage also allow for

the elimination of an external load switch. To further reduce system cost, an advanced reset output is provided,

which can often eliminate the use of an external reset or supervisor device.

The LMS3655 family is designed with a flip-chip or HotRod™ technology, greatly reducing the parasitic

inductance of the pins. In addition, the layout of the device allows for partial cancellation of the current generated

magnetic field which reduces the radiated noise generated by the switching action.

As a result the switch-node waveform exhibits less overshoot and ringing.

Figure 9. Switch Node Waveform (V_IN= 13.5 V, I_OUT= 5.5 A)

The LMS3655 is available in a VQFN package with wettable flanks which allows easy inspection of the soldering

without the requirement of x-ray checks.

12

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

8.2 Functional Block Diagram

SYNC

VCC

BIAS

VIN

* = not used in -ADJ

Oscillator

Int. Reg. Bias

CBOOT

Enable

Logic

HS Current

Sense

EN

FB

¯

1.0-V

Reference

PWM

Comp.

+

-

Error

Amplifier

Control Logic

Driver

SW

*

+

-

LS Current

Sense

RESET

Reset

Control

Mode Logic

FPWM

AGND

PGND

13

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Functional Block Diagram (continued)

8.2.1 Control Scheme

The LMS3655 control scheme allows this device to operate under a wide range of conditions with a low number

of external components. Peak current mode control allows a wide range of input voltages and output capacitance

values while maintaining a constant switching frequency. Stable operation is maintained while output capacitance

is changed during operation as well. This allows use in systems that require high performance during load

transients and which have load switches that remove loads as the operating state changes. Short minimum on

and off times ensure constant frequency regulation over a wide range of conversion ratios.

This architecture uses frequency spreading to achieve low dropout voltage maintaining output regulation as the

input voltage falls close to output voltage. The frequency spreading is smooth and continuous, and activated as

the off time approaches its minimum. Under these conditions, the LMS3655 operates like a constant off-time

converter, allowing the maximum duty cycle to reach 98% and output voltage regulation with 650-mV dropout. As

load current is reduced, the LMS3655 transitions to light load mode. In this mode, diode emulation is used to

reduce RMS inductor current and switching frequency. Average output voltage increases slightly while lightly

loaded as well.

8.3 Feature Description

8.3.1 RESET Flag Output

While the LMS3655 reset function resembles a standard Power-Good function, its functionality is designed to

replace a discrete reset device, reducing additional component cost. There are three major differences between

the reset function and the normal power good function seen in most regulators.

•

A delay has been added between the point at which the output voltage is within specified limits and the flag

asserts Power Good. A glitch filter prevents false flag operation for short excursions in the output voltage,

such as during line and load transients. See Figure 11 and Figure 12 for more detail.

•

RESET output signals a fault (pulls its output to ground) while the part is disabled.

RESET continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET output may

be high impedance.

Because the RESET comparator and the regulation loop share the same reference, the thresholds track with the

output voltage. When EN is pulled low, the RESET flag output is forced low. When the device is disabled,

RESET remains valid as long as the input voltage is ≥ 1.5 V. RESET operation can best be understood by

reference to Figure 10 and Figure 11. Output voltage excursions lasting less than T_RESET-filterdo not trip RESET.

Once the output voltage is within the prescribed limits, a delay of T_RESET-actis imposed before RESET goes high.

This enables tighter tolerance than is possible with an external supervisor device while also expanding the

system allowance for transient response without the need for extremely accurate internal circuitry.

This output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply. It

can also be pulled up to either V_CCor V_OUT, through an appropriate resistor, as desired. The pin can be left

floating or grounded if the RESET function is not used in the application. The maximum current into this pin must

be limited to 10 mA, and the maximum voltage must be less than 8 V.

14

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

Feature Description (continued)

Figure 10. Static RESET Operation

Figure 11. RESET Timing Behavior

15

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Feature Description (continued)

The threshold voltage for the RESET function takes advantage of the availability of the LMS3655 internal

feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected output voltage

to be specified at the same time as 96% of actual set point.

8.3.2 Enable and Start-Up

Start-up and shutdown of the LMS3655 are controlled by the EN input. Applying a voltage of ≥ 2 V activates the

device, while a voltage of ≤ 1.45 V is required for shutdown. The EN input may also be connected directly to the

input voltage supply. This input must not be left floating. The LMS3655 uses a reference-based soft start that

prevents output voltage overshoots and large inrush currents as the regulator is starting up.

A typical start-up waveform is shown in Figure 12 along with timing definitions. This waveform indicates the

sequence and timing between the enable input, output voltage, and RESET. From the figure, the user can define

several different start-up times depending on what is relevant to the application. Table 2 lists the timing

definitions and typical values.

t_RESET-UP

t_POWER-UP

t_RESET-ACT

t_EN

t_SS

2 ms/div

Figure 12. Typical Start-Up Waveform

Table 2. Typical Start-Up Times

PARAMETER

DEFINITION

VALUE

UNIT

ms

t_RESET-READY

t_POWER-UP

t_SS

Total start-up sequence time

Start-up time

Time from EN to RESET released

Time from EN to 90% of V_OUT

7.5

4

ms

Soft-start time

Rise time of V_OUTfrom 10% to 90%

Time from EN to start of V_OUTrising

3.2

1

ms

t_EN

Delay time

ms

Time from output voltage within 94% and

RESET released

t_RESET-ACT

RESET time

3

ms

8.3.3 Soft-Start Function

Soft-start time is fixed internally at about 4 ms. Soft start is achieved by ramping the internal reference. The

LMS3655 operates correctly even if there is a voltage present on the output before activation of the LMS3655

(prebiased start-up). The device operates in AUTO mode during soft start, and the state of the FPWM pin is

ignored during that period.

8.3.4 Current Limit

The LMS3655 incorporates a valley current limit for normal overloads and for short-circuit protection. A precision

low-side current limit prevents excessive average output current from the buck converter of the LMS3655. A

high-side peak-current limit is employed for protection of the top N MOSFET and inductors. The two current limits

enable use of smaller inductors than a system with a single current limit. This scheme allows use of inductors

with saturation current rated less than twice the operating current of the LMS3655.

16

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

During overloads the low-side current limit, I_L-LS(see Electrical Characteristics), determines the maximum load

current that the LMS3655 can supply. When the low-side switch turns on, the inductor current begins to ramp

down. If the current does not fall below I_L-LSbefore the next turnon cycle, then that cycle is skipped, and the low-

side FET is left on until the current falls below I_L-LS. This is different than the more typical peak current limit, and

results in Equation 1 for the maximum load current.

(

V

_IN- V_OUT

2∂F_S∂L

)

∂

V_OUT

I_OUT

= I_LS

+

max

V

IN

(1)

If the converter continues triggering valley current limit for more than about 64 clock cycles, the device turns off

both high and low side switches for approximately 6 ms (see T_Win Timing Requirements). If the overload is still

present after the hiccup time, another 64 cycles is counted, and the process is repeated. If the current limit is not

tripped for two consecutive clock cycles, the counter is reset. The hiccup time allows the inductor current to fall to

zero, resetting the inductor volt-second balance. Of course the output current is greatly reduced in this condition

(see Typical Characteristics). A typical short-circuit transient and recovery is shown in Figure 13.

SPACE

Figure 13. Short-Circuit Transient and Recovery

SPACE

The high-side current limit trips when the peak inductor current reaches I_L-HS(see Electrical Characteristics). This

is a cycle-by-cycle current limit and does not produce any frequency or current foldback. It is meant to protect the

high-side MOSFET from excessive current. Under some conditions, such as high input voltage, this current limit

may trip before the low-side protection. The peak value of this current limit varies with duty cycle.

In response to a short circuit, the peak current limit prevents excessive peak current while valley current limit

prevents excessive average inductor current and keeps the power dissipation low during a fault. After a small

number of cycles of valley current limit triggers, hiccup mode is activated.

In addition, the I_NEGcurrent limit also protects the low-side switch from excessive negative current when the

device is in FPWM mode. If this current exceeds I_NEG, the low-side switch is turned off until the next clock cycle.

When the device is in AUTO mode, the negative current limit is increased to about I_ZC(about 0 A). This allows

the device to operate in DCM.

8.3.5 Hiccup Mode

Hiccup mode prevents excessive heating and power consumption under sustained short-circuit conditions. If an

overcurrent condition is maintained, the LMS3655 shuts off its output and waits for T_W(approximately 6 ms),

after which the LMS3655 restarts operation by activating soft start.

17

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Vout

Figure 14. Hiccup Operation

During hiccup mode operation, the switch node of the LMS3655 is high impedance after a short circuit or

overcurrent persists for a short duration. Periodically, the LMS3655 attempts to restart. If the short has been

removed before one of these restart attempts, the LMS3655 operates normally.

8.3.6 Synchronizing Input

It is often desirable to synchronize the operation of multiple regulators in a single system. This technique results

in better-defined EMI and can reduce the need for capacitance on some power rails. The LMS3655 provides a

SYNC input which allows synchronization with an external clock. The LMS3655 implements an in-phase locking

scheme—the rising edge of the clock signal provided to the SYNC input corresponds to turning on the high-side

device within the LMS3655. The SYNC mode operation is implemented using phase locking over a limited

frequency range eliminating large glitches upon initial application of an external clock. The clock fed into the

LMS3655 replaces the internal free running clock but does not affect frequency foldback operation. Output

voltage continues to be well regulated with duty factors outside of the normal 4% through 96% range though at

reduced frequency.

The SYNC input recognizes a valid high level as that ≥ 1.5 V, and a valid low as that ≤ 0.4 V. The frequency

synchronization signal must be in the range of 250 kHz to 500 kHz with a duty cycle of 10% to 90%. The internal

clock is synced to the rising edge of the external clock. Ground this input if not used; this input must not be

allowed to float. See Device Functional Modes to determine which modes are valid for synchronizing the clock.

The device remains in FPWM mode and operates in CCM for light loads when a synchronization input is

provided. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load.

8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)

The LMS3655 incorporates an input UVLO function. The device accepts an EN command when the input voltage

rises above about 3.64 V and shuts down when the input falls below about 3.3 V. See Electrical Characteristics

under V_IN-OPERATEfor detailed specifications.

TSD is provided to protect the device from excessive temperature. When the junction temperature reaches about

165°C, the device shuts down; restart occurs at a temperature of about 150°C.

8.3.8 Input Supply Current

The LMS3655 is designed to have very low input supply current when regulating light loads. This is achieved by

powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that powers the

majority of the control circuits. By connecting the BIAS input to the output of the regulator, this current acts as a

small load on the output. This current is reduced by the ratio of V_OUT/ V_IN, just like any other load.

18

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

I_{Q_VIN}is defined as the current consumed by a converter using a LMS3655 device while regulating without a

load. To calculate the theoretical total quiescent current, the below equation can be used with parameters from

the Electrical Characteristics and System Characteristics tables. While operating without a load, the LMS3655

only powers itself. The device draws power from three sources: the V_INpin (I_Q), the EN pin (I_EN), and the BIAS

pin (I_B). Because the BIAS input is connected to the output of the circuit, the power consumed is converted from

input power with an effective efficiency, ηeff. Here, effective efficiency is the added input power needed when

lightly loading the converter of the LMS3655 device and is divided by the corresponding additional load. This

allows unloaded current to be calculated in Equation 2:

Output Voltage

I_{Q_ VIN}= I_Q+I_EN+ I +I

(

)

h_effìInput Voltage

B

div

where

•

I_{Q_VIN}is the current consumed by the operating (switching) buck converter while unloaded.

I_Qis the current drawn by the LMS3655 from its V_INterminal. See I_Qin Electrical Characteristics.

I_ENis current drawn by the LMS3655 from its EN terminal. Include this current if EN is connected to VIN. See

I_ENin Electrical Characteristics. Note that this current drops to a very low value if connected to a voltage less

than 5 V.

•

I_Bis bias current drawn by the unloaded LMS3655. See I_Bin System Characteristics.

I_divis the current drawn by the feedback voltage divider used to set output voltage.

η_effis the light load efficiency of the Buck converter with I_{Q_VIN}removed from the input current of the buck

converter.

(2)

NOTE

The EN pin consumes a few micro-amperes when tied to high; see I_EN. Add I_ENto I_Qas

shown in Equation 2 if EN is tied to V_IN. If EN is tied to a voltage less than 5 V, virtually no

current is consumed allowing EN to be used as an UVLO pin once a voltage divider is

added.

8.4 Device Functional Modes

Refer to Table 3 and the following paragraphs for a detailed description of the functional modes for the

LMS3655.

These modes are controlled by the FPWM input as listed in Table 3. This input can be controlled by any

compatible logic while the regulator is operating. If it is desired to fix the mode for a given application, the input

can be either connected to ground, a logic supply, the VIN pin, or the VCC pin, as desired. The FPWM pin must

not be allowed to float.

Table 3. Mode Selection

FPWM INPUT VOLTAGE

OPERATING MODE

Forced PWM: The regulator operates as a constant frequency, current mode, full-

synchronous converter for all loads; without diode emulation.

> 1.5 V

AUTO: The regulator moves between PFM and PWM as the load current changes, using

diode-emulation mode to allow DCM (see the Glossary).

< 0.4 V

8.4.1 AUTO Mode

In AUTO mode the device moves between PWM and PFM as the load changes. At light loads, the regulator

operates in PFM. At higher loads, the mode changes to PWM. The load currents at which the mode changes can

be found in the Application Curves.

In PWM, the converter operates as a constant frequency, current mode, full synchronous converter using PWM

to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a

constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line

and load regulation and low output voltage ripple. When in PWM, the converter synchronizes to any valid clock

signal on the SYNC input (see Synchronizing Input); during PFM operation, the SYNC input is ignored.

19

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

In PFM, the high-side FET is turned on in a burst of one or more cycles to provide energy to the load. The

frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency

(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current

required to regulate the output voltage at small loads. A small increase in the output voltage occurs in PFM. This

trades off very good light load efficiency for larger output voltage ripple and variable switching frequency. The

actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and load. See

the Application Curves for output voltage variation in AUTO mode. A typical switching waveform for PFM is

shown in Figure 15.

A unique feature of this device is that a minimum input voltage is required for the regulator to switch from PWM

to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high

efficiency at light loads. Figure 16 indicates typical values of input voltage required to switch modes at no load.

Also, once the regulator switches to PFM at light load, it remains in that mode if the input voltage is reduced.

SPACE

4.2

Inductor Current:

250 mA/div

Light Load Deactivation Threshold (Falling)

Light Load Activation Threshold (Rising)

4

3.8

SW:

5V/div

3.6

3.4

VOUT:

5V/div

3.2

10 µs/div

-50

0

50

100

150

Temperature (èC)

LMS3

Figure 15. Typical PFM Switching Waveforms

Figure 16. Input Voltage for Mode Change — 3.3-V

Output, 10-µH Inductor

6

Light Load Deactivation Threshold (Falling)

Light Load Activation Threshold (Rising)

5.9

5.8

5.7

5.6

5.5

5.4

5.3

5.2

5.1

5

-50

0

50

100

150

Temperature (èC)

LMS3

Figure 17. Input Voltage for Mode Change — 5-V Output, 10-µH Inductor

8.4.2 FPWM Mode

With a logic high on the FPWM input, the device is locked in PWM mode. CCM operation is maintained, even at

no load, by allowing the inductor current to reverse its normal direction. To prevent frequency foldback behavior

at low duty cycles, provide a 200-mA load. This mode trades off reduced light load efficiency for low output

voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current

limit of I_NEGis imposed to prevent damage to the low-side FET of the regulator. When in PWM, the converter

synchronizes to any valid clock signal on the SYNC input (see Synchronizing Input).

When constant frequency operation is more important than light load efficiency, pull the LMS3655 FPWM input

high or provide a valid synchronization input. Once activated, the diode emulation feature is turned off in this

mode. This means that the device remains in CCM under light loads. Under conditions where the device must

reduce the on time or off time below the ensured minimum, the frequency reduces to maintain the effective duty

cycle required for regulation. This can occur for high input or output voltage ratios.

With the FPWM pin pulled low (normal mode), the diode emulation feature is activated. Device operation is the

same as above; however, the regulator goes into DCM operation when the valley of the inductor current reaches

zero.

20

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

This feature may be activated and deactivated while the part is regulating without removing the load. This feature

activates and deactivates gradually preventing perturbation of output voltage. When in FPWM mode, a limited

reverse current is allowed through the inductor allowing power to pass from the regulator's output to its input. In

this case, ensure that a large enough input capacitor is used to absorb the reverse current.

NOTE

While FPWM is activated, larger currents pass through the inductor than in AUTO mode

when lightly loaded. This may result in more EMI, though at a predictable frequency. Once

loads are heavy enough to necessitate CCM operation, FPWM has no measurable effect

on the operation of the regulator.

8.4.3 Dropout

The minimum off time influences the dropout performance of the buck regulator. As the input voltage is reduced,

to near the output voltage, the off time of the high-side switch starts to approach the minimum value (see

Electrical Characteristics). Beyond this point the switching may become erratic or the output voltage falls out of

regulation. To avoid this problem, the LMS3655 automatically reduces the switching frequency to increase the

effective duty cycle. This results in two specifications regarding dropout voltage, as shown in System

Characteristics. One specification indicates when the switching frequency drops to 330 kHz. The other

specification indicates when the output voltage has fallen to 3% of nominal. See the Application Curves for

typical dropout values. Figure 18 and Figure 19 show the overall dropout characteristic for the 5-V option.

Additional dropout information is discussed in Application Curves for 5-V output and in Application Curves for

3.3-V output.

SPACE

450000

400000

350000

300000

250000

200000

150000

100000

50000

0

5.2

0 A

2 A

4 A

5.5 A

5

4.8

4.6

4.4

4.2

4

0 A

2 A

4 A

5.5 A

4

4.5

5

5.5

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6 5.8

6

Input Voltage (V)

LMS3

Figure 18. Overall Dropout Characteristics

(V_OUT= 5 V)

Figure 19. Frequency Dropout Characteristics

(V_OUT= 5 V)

21

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

8.4.4 Spread-Spectrum Operation

The spread spectrum is a factory option. In order to find which parts have spread spectrum enabled, see Device

Comparison Table.

The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading

emissions across a wider range of frequencies. In most systems containing the LMS3655 devices, low frequency

conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more

difficult design criterion is reduction of emissions at higher harmonics which fall in the FM band. These harmonics

often couple to the environment through electric fields around the switch node. The LMS3655 devices use a ±3%

spread of frequencies which spread energy smoothly across the FM band but is small enough to limit sub-

harmonic emissions below its switching frequency. Peak emissions at the switching frequency of the part are

only reduced by slightly less than 1 dB, while peaks in the FM band are typically reduced by more than 6 dB.

The LMS3655 devices use a cycle-to-cycle frequency hopping method based on a linear feedback shift register

(LFSR). Intelligent pseudo random generator limits cycle to cycle frequency changes to limit output ripple.

Pseudo random pattern repeats by approximately 1.2 Hz which is below the audio band.

The spread spectrum is only available while the clock of the LMS3655 devices is free running at its natural

frequency. Any of the following conditions overrides spread spectrum, turning it off:

•

An external clock is applied to the SYNC/MODE terminal.

The clock is slowed due to operation at low input voltage; this is operation in dropout.

The clock is slowed under light load in AUTO mode; this is normally not seen above 200 mA of load. In

FPWM mode, spread spectrum is active even if there is no load.

22

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMS3655 is a step-down DC-DC converter, typically used to convert a higher DC voltage to a lower DC

voltage with a maximum output current of 5.5 A. The following design procedures can be used to select

components for the LMS3655. Alternately, the WEBENCH^®Design Tool may be used to generate a complete

design. This tool uses an iterative design procedure and has access to a comprehensive database of

components. This allows the tool to create an optimized design and allows the user to experiment with various

design options.

9.2 Typical Applications

9.2.1 General Application

Figure 20 shows a general application schematic. FPWM, SYNC, and EN are digital inputs. RESET is an open-

drain output.

•

The FPWM pin can be connected to GND to enable light-load PFM operation. Select this option if current

consumption at light load is critical. The pin can be connected to VCC or VIN for forced 400-kHz operation.

Select this option if constant switching frequency is critical. The pin can also be driven by an external signal

and can be toggled while the part is in operation (by an MCU, for example). Refer to the Device Functional

Modes for more details on the operation and signal requirements of the FPWM pin.

•

The SYNC pin can be used to control the switching frequency and the phase of the converter. If the function

is not needed, tie the SYNC pin to GND, VCC, or VIN.

The RESET pin can be left floating or tied to ground if the function is not required. If the function is needed,

the pin must be connected to a DC rail through a pullup resistor (100 kΩ is the typical recommended value).

Check RESET Flag Output for the details of the RESET pin function.

•

Connect the output to the FB pin through a voltage divider. See Detailed Design Procedure for details on

component selection.

The BIAS pin can be connected directly to the output voltage. In applications that can experience inductive

shorts (such as cases with long leads on the output), a 3 Ω or so is necessary between the output and the

BIAS pin, and a small capacitor to GND is necessary close to the BIAS pin (C_BIAS). Alternatively, a Schottky

diode can be connected between OUT and GND to limit the negative voltage that can arise on the output

during inductive shorts. In addition, BIAS can also be connected to an external rail if necessary and if

available. The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 400

kHz.

•

Power components must be chosen carefully for proper operation of the converter. Detailed Design

Procedure discusses the details of the process of choosing the input capacitors, output capacitors, and

inductor for the application.

23

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Typical Applications (continued)

VIN

3.5 V to 36 V

10 µF

PVIN 1

PVIN 2

10 µF

PGND1

PGND2

RESET

AVIN

VCC

SYNC

BIAS

4.7 µF

LMS3655

AGND

0.1 µF

FB

NC

CFF

RFBB

RFBT

FPWM

CBOOT

470 nF

SW

EN

L1=10 µH

V_OUT

3 X 47 µF

Figure 20. General Application Circuit

9.2.1.1 Design Requirements

Three sets of application-specific design requirements are outlined in Table 8, Table 9, and Table 10. The

minimum input voltage shown in Figure 20 is not the minimum operating voltage of the LMS3655. Rather, it is a

typical operating range for the systems. For the complete information regarding minimum input voltage see

Electrical Characteristics.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 External Components Selection

The device requires input capacitors and an output inductor-capacitor filter. These components are critical to the

performance of the device.

9.2.1.2.1.1 Input Capacitors

The input capacitor supplies the AC switching current drawn from the switching action of the internal power

FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor

is large. The input capacitor must be rated to handle both the RMS current and the dissipated power.

The device is designed to be used with ceramic capacitors on the input of the buck regulator. The recommended

dielectric type of these capacitors is X5R, X7R, or of comparable material to maintain proper tolerances over

voltage and temperature.

The device requires a minimum of 20 µF of ceramic capacitance at the input. TI recommends 2 × 10 µF, 10 µF

for PVIN1 and 10 µF for PVIN2. Place these capacitors close to the PVIN1, PGND1, PVIN2, and the PGND2

pads. The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying

ripple current and isolating switching noise from other circuits. Table 4 shows the nominal and minimum values of

total input capacitance recommended for the LMS3655. Also shown are the measured values of effective

capacitance for the indicated capacitor.

24

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

Typical Applications (continued)

In addition, it is especially important to have small ceramic bypass capacitors of 10 nF to 100 nF very close to

the PVIN1 and PVIN2 inputs to minimize ringing and EMI generation due to the high-speed switching of the

device coupled with trace inductance. TI recommends that a small case size 10-nF ceramic capacitor be placed

across the input, as close to the device as possible. Additional high-frequency capacitors can be used to help

manage conducted EMI or voltage spike issues that may be encountered.

Many times it is desirable to use an additional electrolytic capacitor on the input, in parallel with the ceramics.

This is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate

ESR of this capacitor can help damp any ringing on the input supply caused by long power leads. The use of this

additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Table 4. Recommended Input Capacitors

NOMINAL INPUT CAPACITANCE

MINIMUM INPUT CAPACITANCE

PART NUMBER

RATED

CAPACITANCE

MEASURED

MEASURED CAPACITANCE⁽¹⁾

RATED CAPACITANCE

CAPACITANCE⁽¹⁾

3 × 10 μF

22.5 μF

2 × 10 μF

15 μF

CL32B106KBJNNNE

(1) Measured at 14 V and 25°C.

9.2.1.2.1.2 Output Inductors and Capacitors

There are several design considerations related to the selection of output inductors and capacitors:

•

Load transient response

Stability

Efficiency

Output ripple voltage

Overcurrent ruggedness

The device has been optimized for use with LC values as shown in the Figure 20.

9.2.1.2.1.2.1 Inductor Selection

The LMS3655 devices run in current mode and with internal compensation. The compensation of the adjustable

5-V and 3.3-V configurations is stable with inductance between 6.5 µH and 20 µH. For most applications, the

adjustable 5-V and 3.3-V configurations of the LMS3655 devices are optimized for a nominal inductance of 10

μH. This gives a ripple current that is approximately 20% to 30% of the full load current of 5.5 A. If applying a

synchronization clock signal, the designer should appropriately size the inductor for the converter's operating

switching frequency. For output voltages greater than 5 V, a proportionally larger inductor can be used, thus

keeping the ratio of inductor current slope to internal compensating slope constant. Inductance that is too high is

not recommended because it can result in poor load transient behavior and instability.

The inductor must be rated to handle the peak load current plus the ripple current—carefully review the different

saturation current ratings specified by different manufacturers. Saturation current ratings are typically specified at

25°C, so ratings at maximum ambient temperature of the application should be requested from the manufacturer.

For the LMS3655, TI recommends a saturation current of 10 A or higher. Carefully review the inductor parasitic

resistance; the inductor parasitic resistance must be as low as possible to minimize losses at heavy loads. The

best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.

Table 5 gives a list of several possible inductors that can be used with the LMS3655.

The designer should choose the inductors that best match the system requirements. A very wide range of

inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance

loss limited), series resistance, maximum operating frequency, losses, and so forth. In general, inductors of

smaller physical size have higher series resistance (DCR) and implicitly lower overall efficiency is achieved. Very

low-profile inductors may have even higher series resistance. TI recommends finding the best compromise

between system performance and cost.

25

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Table 5. Recommended Inductors

MANUFACTURER

Würth

PART NUMBER

SATURATION CURRENT

DC RESISTANCE

16 mΩ

7443251000

7447709100

8.5 A

10.5 A

12 A

Würth

21 mΩ

Vishay

IHLP4040DZER100M01

36.5 mΩ

9.2.1.2.1.2.2 Output Capacitor Selection

The output capacitor of a switching converter absorbs the AC ripple current from the inductor, reduces the output

voltage ripple, and provides the initial response to a load transient. The ripple voltage at the output of the

converter is the product of the ripple current flowing through the output capacitor and the impedance of the

capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within

the capacitor, depending on the frequency of the ripple current. Ceramic capacitors have very low ESR and

remain capacitive up to high frequencies. Their inductive component can be usually neglected at the operating

frequency range of the converter.

The LMS3655 is designed to work with low-ESR ceramic capacitors. TI recommends X5R and X7R type

capacitors. The effective value of these capacitors is defined as the actual capacitance under voltage bias and

temperature. All ceramic capacitors have a large voltage coefficient, in addition to normal tolerances and

temperature coefficients. Under DC bias, the capacitance value drops considerably. Larger case sizes or higher

voltage capacitors are better in this regard. To help mitigate these effects, multiple small capacitors can be used

in parallel to bring the minimum effective capacitance up to the desired value. This can also ease the RMS

current requirements on a single capacitor. Table 6 shows the nominal and minimum values of total output

ceramic capacitance recommended for the LMS3655.The values shown also provide a starting point for other

output voltages. More output capacitance can be used to improve transient performance and reduce output

voltage ripple.

In order to minimize ceramic capacitance, a low-ESR electrolytic capacitor can be used in parallel with minimal

ceramic capacitance. As a starting point for designing with an output electrolytic capacitor, Table 7 shows the

minimum ceramic capacitance recommended when paired with a 120-µF Aluminum-polymer (ESR = 25 mΩ) in

order to maintain stable operation. Depending on load transient design requirements, the designer may choose

to add additional capacitance.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and bode plots are the best way to validate any given design and should always be completed

before the application goes into production. Make a careful study of temperature and bias voltage variation of any

candidate ceramic capacitor in order to ensure that the minimum value of effective capacitance is provided. The

best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.

In adjustable applications the feed-forward capacitor, C_FF, provides another degree of freedom when stabilizing

and optimizing the design. Refer to Optimizing Transient Response of Internally Compensated DC-DC

Converters With Feedforward Capacitor (SLVA289) for helpful information when adjusting the feed-forward

capacitor.

In addition to the capacitance shown in Table 6, a small ceramic capacitor placed on the output can help to

reduce high frequency noise. Small case-size ceramic capacitors in the range of 1 nF to 100 nF can be very

helpful in reducing spikes on the output caused by inductor parasitics.

Limit the maximum value of total output capacitance to between 800 μF and 1200 μF. Large values of output

capacitance can prevent the regulator from starting up correctly and adversely effect the loop stability. If values

greater than the given range are to be used, then a careful study of start-up at full load and loop stability must be

performed.

(1)

Table 6. Recommended Output Ceramic Capacitors

NOMINAL OUTPUT CERAMIC

CAPACITANCE

MINIMUM OUTPUT CERAMIC

CAPACITANCE

OUTPUT VOLTAGE

PART NUMBER

RATED CAPACITANCE

4 × 47 µF

RATED CAPACITANCE

3 x 47µF

3.3 V

5 V

GRM32ER71A476KE15L

4 × 47 µF

3 × 47µF

(1) L = 10 μH

26

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

Table 6. Recommended Output Ceramic Capacitors ⁽⁾(continued)

NOMINAL OUTPUT CERAMIC

CAPACITANCE

MINIMUM OUTPUT CERAMIC

CAPACITANCE

RATED CAPACITANCE

3 × 47μF

OUTPUT VOLTAGE

PART NUMBER

RATED CAPACITANCE

4× 47 μF

6 V

10 V⁽²⁾

GRM32ER71A476KE15L

4 × 47 μF

3 × 47 μF

(2) L = 20 μH

(1)

Table 7. Recommended Output Al-Polymer and Ceramic Capacitors

MINIMUM OUTPUT CERAMIC

OUTPUT AL-POLYMER CAPACITANCE

CAPACITANCE

RATED CAPACITANCE

1 × 47µF + 1 x 20µF

1 × 47µF

OUTPUT VOLTAGE

PART NUMBER

RATED CAPACITANCE

120 µF

3.3 V

5 V

APXE160ARA121MH70G

120 µF

(1) L = 10 μH

Consult Output Ripple Voltage for Buck Switching Regulator (SLVA630) for more details on the estimation of the

output voltage ripple for this converter.

9.2.1.2.2 FB for Adjustable Output

The LMS3655 devices regulate output voltage to a level that results in the FB node being V_REF, which is

approximately 1 V (see Electrical Characteristics). Output voltage given a specific feedback divider can be

calculated using Equation 3:

R_FBB+ R_FBT

Output Voltage = V_ref

ì

R_FBB

(3)

To ensure proper behavior for all modes of operation, a 50-kΩ resistor is recommended for R_FBT. R_FBBcan then

be determined using Equation 4:

V

ìR_FBT

ref

R_FBB

=

Output Voltage - V

ref

(4)

In addition, a feed-forward capacitor C_FFmay be required to optimize the transient response. For output voltages

greater than 6 V, the WEBENCH Design Tool can be used to optimize the design.

9.2.1.2.3 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the LMS3655. This output

requires a 4.7-µF, 10-V ceramic capacitor connected from VCC to GND for proper operation. X7R type is

recommended. In general, this output must not be loaded with any external circuitry. However, the output can be

used to supply a logic level to the FPWM input or for the pullup resistor used with the RESET output. The

nominal output of the LDO is 3.15 V.

9.2.1.2.4 BIAS

The BIAS pin is the input to the internal LDO. As detailed in Input Supply Current, this input is connected directly

to V_OUTto provide the lowest possible supply current at light loads. Because this input is connected directly to the

output, it must be protected from negative voltage transients. Such transients may occur when the output is

shorted at the end of a long PCB trace or cable. If this is likely in a given application, then place a small resistor

in series between the BIAS input and V_OUTas shown in Figure 23.

Size the resistor to limit the current out of the BIAS pin to < 100 mA. Values in the range of 2 Ω to 5 Ω are

typically sufficient. Values greater than 5 Ω are not recommended. As a rough estimate, assume that the full

negative transient appears across R_BIASand design for a current of < 100 mA. In severe cases, a Schottky diode

can be placed in parallel with the output to limit the transient voltage and current.

When a resistor is used between the output and the BIAS pin, a 0.1-µF capacitor is required close to the BIAS

pin. In general, TI recommends having a 0.1-µF capacitor near the BIAS pin, regardless of the presence of the

resistor, unless the trace between the output capacitors and the BIAS pin is very short.

27

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 400 kHz.

9.2.1.2.5 CBOOT

The LMS3655 requires a boot-strap capacitor between the CBOOT pin and the SW pin. This capacitor stores

energy that is used to supply the gate drivers for the power MOSFETs. A ceramic capacitor of 0.47 µF, ≥ 6.3 V is

required.

9.2.1.2.6 Maximum Ambient Temperature

As with any power conversion device, the LMS3655 dissipates internal power while operating. The effect of this

power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal resistance,

R_θJAof the device and PCB combination. The maximum internal die temperature for the LMS3655 is 150°C, thus

establishing a limit on the maximum device power dissipation and therefore load current at high ambient

temperatures. Equation 5 shows the relationships between the important parameters.

(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

(

)

V_OUT

(5)

The device uses an advanced package technology that uses the pads and pins as heat spreading paths. As a

result, the pads must be connected to large copper areas to dissipate the heat from the IC. All pins provide some

heat relief capability but the PVINs, PGNDs, and SW pins are of particular importance for proper heat dissipation.

Utilization of all the board layers for heat dissipation and using vias as heat pipes is recommended. The Layout

Guidelines includes an example that shows layout for proper heat management.

28

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

9.2.1.3 Application Curves

These parameters are not tested and represent typical performance only. Unless otherwise stated, the following

conditions apply: V_IN= 12 V, T_A= 25°C. For the purpose of offering more information to the designer, information

for the application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although

the schematic shows the application running specifically in FPWM mode. The mode is specified under each

following graph.

3.5

3

3.5

3

8.0 V_IN

4.0 V_IN

6.0 V_IN

12.0 V_IN

13.5 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Output Current (A)

LMS3

Figure 21. Power Dissipation 5-V Output

Figure 22. Power Dissipation 3.3-V Output

29

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

9.2.2 Adjustable 5-V Output

VIN

5.5 V œ 36 V

PVIN 1

10 µF

PVIN 2

10 µF

PGND1

0.1 µF

PGND2

RESET

0.1 µF

RESET/PG OUT

AVIN

100 kΩ

VCC

NC

4.7 µF

LMS3655

BIAS

AGND

3 Ω

0.1 µF

FPWM

EN

FB

22 pF

21.7 kΩ

470 nF

49.9 kΩ

CBOOT

VOUT = 5 V

SYNC IN

SYNC

SW

L1 = 10 µF

1 X 47 µF

100 kΩ

1 X 120 µF

ESR = 25 mΩ

Figure 23. 5-V, 5.5-A Output Power Supply

9.2.2.1 Design Requirements

Example requirements for a typical 5-V application. The input voltages are here for illustration purposes only.

See Electrical Characteristics for minimum operating input voltage. The minimum input voltage necessary to

achieve proper output regulation depends on the components used. See Figure 29 for typical drop-out behavior.

Table 8. Example Requirements for 5-V Typical Application

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

8 V to 18 V steady-state, 5.5 V to 36 V transients

0 A to 5.5 A

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Critical: must have > 250 kHz

Not critical: < 100 mA acceptable

Yes: 300 kHz supplied by MCU

9.2.2.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that the load is connected to the output through long

wires so a 3-Ω resistor is inserted to minimize risks of damage to the part during load shorts. In addition 0.1-

µF capacitor is required close to the bias pin.

•

FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when

the output is at 5 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to

improve transient behavior. BIAS and FB are connected to the output through separate traces. This is

important to reduce noise and achieve good performance. See Layout Guidelines for more details on the

proper layout method.

•

SYNC is connected to ground through a pulldown resistor, and an external synchronization signal can be

30

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

applied. The pulldown resistor ensures that the pin is not floating when the SYNC pin is not driven by any

source.

•

EN is connected to VIN so the device operates as soon as the input voltage rises above the V_IN-OPERATE

threshold.

FPWM is connected to VIN. This causes the device to operate in FPWM mode. In this mode, the device

remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by

F_SW. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load. The drawback is that

the efficiency is not optimized for light loads. See Device Functional Modes for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation

of the internal LDO.

RESET is biased to the output in this example. A pullup resistor is necessary. A 100-kΩ is selected for this

application and is generally sufficient. The value can be selected to match the needs of the application but

must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Absolute

Maximum Ratings for the maximum current allowed. In addition, a low pullup resistor could lead to an

incorrect logic level due to the value of R_RESET. Consult Electrical Characteristics for details on the RESET

pin.

•

Input capacitor selection is detailed in Input Capacitors. It is important to connect small high-frequency

capacitors C_{IN_HF1}and C_{IN_HF2}as close to both inputs PVIN1 and PVIN2 as possible.

•

Output capacitor selection is detailed in Output Capacitor Selection.

Inductor selection is detailed in Inductor Selection. In general, a 10-µH inductor is recommended for the

nominal adjustable output range of 3.3 V to 5 V. The inductance can vary with the output voltage due to ripple

and current limit requirements.

9.2.2.3 Application Curves

The following characteristics apply only to the circuit of Adjustable 5-V Output. These parameters are not tested

and represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A=

25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin

high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application

running specifically in FPWM mode. The mode is specified under each following graph.

100%

95%

90%

85%

80%

75%

70%

65%

60%

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

0.001

0.01

0.1

1

10

0

1

2

3

4

5

6

Output Current (A)

LMS3

V_OUT= 5 V

AUTO

V_OUT= 5 V

FPWM

Figure 24. Efficiency

Figure 25. Efficiency

31

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

5.12

5.11

5.1

5.05

5.03

5.01

4.99

4.97

4.95

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

5.09

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0

1

2

3

4

5

6

Output Current (A)

LMS3

V_OUT= 5 V

AUTO

V_OUT= 5 V

FPWM

Figure 26. Load and Line Regulation

Figure 27. Load and Line Regulation

1.2

1

1000

-40èC

900

800

700

600

500

400

300

200

100

0

25èC

105èC

0.8

0.6

0.4

0.2

0

1

2

3

4

5

6

0

10

20

30

40

Output Current (A)

Input Voltage (V)

LMS3

V_OUT= 5 V

Figure 29. Dropout for –3% Regulation

Figure 28. Load Current for PFM-to-PWM Transition

450000

400000

350000

300000

250000

200000

150000

100000

50000

0

1.2

1

-40èC

25èC

105èC

0.8

0.6

0.4

0.2

0

8 V_IN

12 V_IN

18 V_IN

24 V_IN

0.001

0.01

0.1

1

10

0

1

2

3

4

5

6

Output Current (A)

LMS3

Output Current (A)

LMS3

V_OUT= 5 V

AUTO

V_OUT= 5 V

Figure 31. Switching Frequency vs Load Current

Figure 30. Dropout for ≥ 330 kHz

32

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

9

8

7

6

5

4

3

2

1

0

LMS3655

40

0

5

10

15

20

25

30

35

45

AUTO

V_OUT= 5 V

L = 10 µH

Input Voltage (V)

LMS3

C_OUT= 170 µF

I_OUT= 10 mA to 3.5 A

T_R= T_F= 1 µs

V_OUT= 5 V

L = 10 µH

Figure 33. Load Transients

Figure 32. Output Current Level Limit Before Overcurrent

Protection

FPWM

V_OUT= 5 V

I_OUT= 0 A to 3.5 A

L = 10 µH

C_OUT= 170 µF

T_R= T_F= 1 µs

Figure 34. Load Transient

33

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

9.2.3 Adjustable 3.3-V Output

VIN

3.8 V to 36 V

VDD

PVIN 1

10 µF

PVIN 2

PGND2

RESET

10 µF

100 kΩ

RESET/PG OUT

PGND1

0.1 µF

AVIN

VCC

NC

4.7 µF

LMS3655

BIAS

AGND

0.1 µF

FPWM

EN

FB

22 pF

21.7 kΩ

49.9 kΩ

CBOOT

470 nF

VOUT = 3.3 V

SW

SYNC

L1 = 10 µH

1 X 67 µF

1 X 120 µF

ESR = 25 mΩ

Figure 35. Adjustable 3.3-V, 5.5-A Output Power Supply

9.2.3.1 Design Requirements

Example requirements for a typical 3.3-V application. The input voltages are here for illustration purposes only.

See Electrical Characteristics for minimum operating input voltage. The minimum input voltage necessary to

achieve proper output regulation depends on the components used. See Figure 41 for typical drop-out behavior.

Table 9. Example Requirements for 3.3-V Application

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

8-V to 18-V steady-state, 4.0-V to 36-V transients

0 A to 5.5 A

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Not critical: Need >330 kHz at high load only

Critical: Need to ensure low current consumption to reduce battery drain

No

9.2.3.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that the load is close to the output so no bias

resistance is necessary. A 0.1-µF capacitor is still recommended close to the bias pin.

•

FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when

the output is at 3.3 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to

improve transient behavior. BIAS and FB are connected to the output through separate traces. This is

important to reduce noise and achieve good performance. See Layout Guidelines for more details on the

proper layout method.

•

SYNC is connected to ground directly as there is no need for this function in this application.

EN is connected to VIN so the device operates as soon as the input voltage rises above the V_IN-OPERATE

threshold.

34

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

•

FPWM is connected to GND. This causes the device to operate in AUTO mode. In this mode, the switching

frequency is adjusted at light loads to optimize efficiency. As a result the switching frequency changes with

the output current until medium load is reached. The part will then switch at the frequency defined by F_SW

.

See Device Functional Modes for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation

of the internal LDO.

RESET is biased to an external rail in this example. A pullup resistor is necessary. A 100-kΩ pullup resistor is

selected for this application and is generally sufficient. The value can be selected to match the needs of the

application but must not lead to excessive current into the RESET pin when RESET is in a low state. Consult

Absolute Maximum Ratings for the maximum current allowed. In addition, a low pullup resistor could lead to

an incorrect logic level due to the value of R_RESET. Consult Electrical Characteristics for details on the RESET

pin.

•

It is important to connect small high frequency capacitors C_{IN_HF1}and C_{IN_HF2}as close to both inputs PVIN1

and PVIN2 as possible. For the detailed process of choosing input capacitors, refer to Input Capacitors.

•

Output capacitor selection is detailed in Output Capacitor Selection.

Inductor selection is detailed in Inductor Selection. In general, a 10-µH inductor is recommended for the

nominal adjustable output range of 3.3 V to 5 V. The inductance can vary with the output voltage due to ripple

and current limit requirements.

9.2.3.3 Application Curves

The following characteristics apply only to the circuit of Figure 35. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A

=

25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin

high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application

running specifically in AUTO mode. The mode is specified under each of the following graphs.

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

45%

40%

35%

30%

25%

20%

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

6.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

0.1

0.0001

0.001

0.01

0.1

1

10

1.0001

2.0001

Output Current (A)

3.0001

4.0001

5.0001

Output Current (A)

LMS3

V_OUT= 3.3 V

AUTO

V_OUT= 3.3 V

FPWM

Figure 36. Efficiency

Figure 37. Efficiency

35

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

3.4

3.38

3.36

3.34

3.32

3.3

3.4

3.38

3.36

3.34

3.32

3.3

6.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

3.28

3.26

3.24

3.22

3.2

3.28

3.26

3.24

3.22

3.2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0

1

2

3

4

5

6

Output Current (A)

LMS3

V_OUT= 3.3 V

AUTO

V_OUT= 3.3 V

FPWM

Figure 38. Load and Line Regulation

Figure 39. Load and Line Regulation

1.2

1

1400

1200

1000

800

600

400

200

0

-40èC

25èC

105èC

0.8

0.6

0.4

0.2

0

1

2

3

4

5

6

0

5

10

15

20

25

30

35

40

Output Current (A)

Input Voltage (V)

LMS3

V_OUT= 3.3 V

Figure 41. Dropout for –3% Regulation

Figure 40. Load Current for PFM-to-PWM Transition

450000

400000

350000

300000

250000

200000

150000

100000

50000

0

1.2

1

-40èC

25èC

105èC

0.8

0.6

0.4

0.2

0

8 V_IN

12 V_IN

18 V_IN

24 V_IN

0.001

0.01

0.1

1

10

0

1

2

3

4

5

6

Output Current (A)

LMS3

V_OUT= 3.3 V

AUTO

V_OUT= 3.3 V

Figure 42. Dropout for ≥ 330 kHz

Figure 43. Switching Frequency vs Load Current

36

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

9

8

7

6

5

4

3

2

1

LMS3655

40

0

5

10

15

20

25

30

35

45

Input Voltage (V)

AUTO

V_OUT= 3.3 V

L = 10 µH,

LMS3

V_OUT= 3.3 V

L = 10 µH

C_OUT= 190 µF

I_OUT= 0 A to 3.5 A

T_R= T_F= 1 µs

Figure 44. Output Current Level for Overcurrent Protection

Trip

Figure 45. Load Transient

FPWM

V_OUT= 3.3 V

L = 10 µH,

V_OUT= 3.3 V

I_OUT= 10 mA

C_OUT= 190 µF

I_OUT= 0 A to 3.5 A

T_R= T_F= 1 µs

Figure 47. Mode Change Transient AUTO to FPWM mode

Figure 46. Load Transient

37

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

9.2.4 6-V Adjustable Output

VIN

8 V œ 36 V

PVIN 1

PVIN 2

10 µF

PGND1

AVIN

PGND2

RESET

0.1 µF

VCC

NC

4.7 µF

LMS3655

BIAS

AGND

3Ω

0.1 µF

FB

FPWM

EN

22 pF

10.2 kΩ

49.9 kΩ

CBOOT

470 nF

VOUT = 6 V

SW

SYNC

L1 = 10 µH

1 X 67 µF

1 X 120 µF

ESR = 25 mΩ

Figure 48. 6-V Output Power Supply

9.2.4.1 Design Requirements

The application highlighted in this section is for a typical 6-V system. The input voltages are here for illustration

purposes only. See Electrical Characteristics for minimum operating input voltage.

Table 10. Example Requirements for 6-V Application

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

8-V to 18-V steady-state

0 A to 5.5 A

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

> 250 kHz preferred

Not critical

No

9.2.4.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that inductive shorts are a risk for this application so

a 3-Ω resistor is added between BIAS and the output. A 0.1-µF capacitor is added close to the BIAS pin.

•

FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin when

the output is at 6 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order to

improve transient behavior. BIAS and FB are connected to the output through separate traces. This is

important to reduce noise and achieve good performances. See Layout Guidelines for more details on the

proper layout method.

•

SYNC is connected to ground directly as there is no need for this function in this application.

EN is toggled by an external device (like an MCU for example). A pulldown resistor is placed to ensure the

part does not turn on if the external source is not driving the pin (Hi-Z condition).

•

FPWM is connected to VIN. This causes the device to operate in FPWM mode. To prevent frequency

foldback behavior at low duty cycles, provide a 200mA load. In this mode, the device remains in CCM

operation regardless of the output current and is ensured to be within the boundaries set by F_SW. The

drawback is that the efficiency is not optimized for light loads. See Device Functional Modes for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensure stable operation

of the internal LDO.

•

RESET is not used in this example so the pin has been left floating. Other possible connections can be seen

38

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

in the previous typical applications and in RESET Flag Output.

•

Power components (input capacitor, output capacitor, and inductor) selection can be found here in External

Components Selection.

9.2.4.3 Application Curves

The following characteristics apply only to the circuit of Figure 48. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A

=

25°C.

V_OUT= 6 V

FPWM

I_OUT= 0 A

V_OUT= 6 V

FPWM

I_OUT= 0 A

Figure 50. Start-Up Waveform (EN Tied to VIN)

Figure 49. Start-Up Waveform

FPWM

V_OUT= 6 V

I_OUT= 0 A to 3.5 A

L = 10 µH,

C_OUT= 190 µF

T_R= T_F= 1 µs

Figure 51. Load Transient

39

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

9.3 Do's and Don't's

•

Don't: Exceed the Absolute Maximum Ratings.

Don't: Exceed the Recommended Operating Conditions.

Don't: Allow the EN, FPWM or SYNC input to float.

Don't: Allow the output voltage to exceed the input voltage, nor go below ground.

Don't: Use the thermal data given in the Thermal Information table to design your application.

Do: Follow all of the guidelines and/or suggestions found in this data sheet before committing a design to

production. TI Application Engineers are ready to help critique designs and PCB layouts to help ensure

successful projects.

•

Do: Refer to the helpful documents found in 相关文档.

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and

Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable of

delivering the required input current to the loaded regulator. The average input current can be estimated with

Equation 6:

V_OUT∂I_OUT

I_IN=

V ∂ h

IN

where

•

η is the efficiency

(6)

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input

capacitors, can form an under-damped resonant circuit. This circuit may cause overvoltage transients at the VIN

pin, each time the input supply is cycled on and off. The parasitic resistance causes the voltage at the VIN pin to

dip when the load on the regulator is switched on or exhibits a transient. If the regulator is operating close to the

minimum input voltage, this dip may cause the device to shut down or reset. The best way to solve these kinds

of issues is to reduce the distance from the input supply to the regulator or use an aluminum or tantalum input

capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors helps to damp the input

resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is usually sufficient

to provide input damping and help to hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability, as well as some of the effects mentioned above, unless it is designed carefully. LP3913 Power

Management IC for Flash Memory Based Portable Media Players (SNVA489) provides helpful suggestions when

designing an input filter for any switching regulator.

In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back V-I characteristic (thyristor type). The use of a device with this type of characteristic is not

recommend. When the TVS fires, the clamping voltage drops to a very low value. If this holding voltage is less

than the output voltage of the regulator, the output capacitors are discharged through the regulator back to the

input. This uncontrolled current flow could damage the regulator.

11 Layout

11.1 Layout Guidelines

The PCB layout of a DC-DC converter is critical for optimal performance of the application. For a buck converter

the input loop formed by the input capacitors and power grounds are very critical. The input loop carries fast

transient currents that cause larger transient voltages when reacting with a parasitic loop inductance. The IC

uses two input loops in parallel IN1 and IN2 as shown in Figure 52 that cuts the parasitic input inductance in half.

To get the minimum input loop area two small high frequency capacitors CIN1 and CIN2 are placed as close as

possible.

40

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

Layout Guidelines (continued)

To further reduce inductance, an input current return path should be placed underneath the loops IN1 and IN2.

The closest metal plane is MID1 Layer2, and there is a solid copper plane placed right under the IN1 and IN2

loop the parasitic loop inductance is minimized. Connecting this MID1 Layer2 plane to GND provides a nice

bridge connection between GND1 and GND2 as well. Minimizing the parasitic input loop inductance will minimize

switch node ringing and EMI.

The output current loop can be optimized as well by using two ceramic output caps COUT1 and COUT2, one on

each side. They form two parallel ground return paths OUT1 from COUT1 back to the low-side FET PGND1 pins

5, 6, 7, 8, and a second symmetric ground return path OUT2 from COUT2 back to low-side FET PGND2 pins 10,

11, 12, and 13. Having two parallel ground return paths yield reduced ground bouncing and reduced sensitivity of

surrounding circuits.

Figure 52. Layout of the Power Components and Current Flow

Providing adequate thermal paths to dissipate heat is critical for operation at full current. The recommended

method for heat dissipation is to use large solid 2-oz copper planes well connected to the power pins VIN1, VIN2,

GND1, and GND2 which transfer the heat out of the IC over the TOP Layer1 copper planes. It is important to

leave the TOP Layer1 copper planes as unbroken as possible so that heat is not trapped near the IC. The heat

flow can be further optimized by thermally connecting the TOP Layer1 plane to large BOTTOM Layer 4 2-oz

copper planes with vias. MID2 Layer3 is then open for all other signal routing. A fully filled or solid BOTTOM

Layer4 ground plane without any interruptions or ground splitting is beneficial for EMI as well. Most important for

low EMI is to use the smallest possible switch node copper area. The switch node including the C_BOOTcap has

the largest dV/dt signal causing common-mode noise coupling. Using any kind of grounded shield around the

switch node shortens and reduces this e-field.

All these DC-DC converter descriptions can be transformed into layout guidelines:

1. Place two 0.047-µF, 50-V high frequency input capacitors C_IN1and C_IN2as close as possible to the VIN1,

VIN2, PGND1, PGND2 pins to minimize switch node ringing.

41

LMS3655

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

www.ti.com.cn

Layout Guidelines (continued)

2. Place bypass capacitors for VCC and BIAS close to their respective pins. Make sure AGND pin sees the

C_VCCand C_BIAScapacitors first before a connection to PGND.

3. Place C_BOOTcapacitor with smallest parasitic loop. Shielding the C_BOOTcapacitor and switch node has the

biggest impact to reduce common-mode noise. Placing a small R_BOOTresistor (less than 3 Ω is

recommended) in series to C_BOOTslows down the dV/dt of the switch node and reduce EMI.

4. Place the feedback resistor divider as close as possible to the FB pin and to AGND pin of the device. Use a

dedicated feedback trace, and route away from switch node and C_BOOTcapacitor to avoid any cross coupling

into sensitive analog feedback.

5. Use a dedicated BIAS trace to avoid noise into feedback trace.

6. Use a 3-Ω to 5-Ω resistor between the output and BIAS if the load is far from the output of the converter or

inductive shorts on the output are possible.

7. Use well connected large 2-oz. TOP and BOTTOM copper planes for all power pins VIN1/2 and PGND1/2.

8. Minimize switch node and C_BOOTarea for lowest EMI common mode noise.

9. Place input and output wires on the same side of the PCB using an EMI filter and away from the switch node

for lowest EMI.

The resources in 器件和文档支持 provide additional important guidelines.

11.2 Layout Example

This example layout is the one used in the LMS3655 EVM. It shows the C_INand C_{IN_HF}capacitors placed

symmetrically on either side of the device.

Figure 53. Recommended Layout for LMS3655

42

LMS3655

www.ti.com.cn

ZHCSGY9B –JULY 2017–REVISED MARCH 2018

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 文档支持

12.2.1 相关文档

更多信息，请参见以下文档：

•

《采用前馈电容器优化内部补偿直流/直流转换器的瞬态响应》(SLVA289)

《降压开关稳压器的输出纹波电压》(SLVA630)

《AN-1149 开关电源布局指南》(SNVA021)

《AN-1229 Simple Switcher® PCB 布局指南》(SNVA054)

《构建电源 - 布局注意事项》(SLUP230)

《AN-2020 热设计：学会洞察先机，不做事后诸葛》(SNVA419)

《半导体和 IC 封装热指标》(SPRA953)

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

HotRod, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

43

GENERIC PACKAGE VIEW

RNL 22

5 X 4, 0.5 mm pitch

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226989/A

www.ti.com

PACKAGE OUTLINE

RNL0022A

VQFN-HR - 0.9 mm max height

SCALE 2.800

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

0.9

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2

1

0.45

0.35

2X 0.8 0.1

8X 0.5

5X

(0.2) TYP

9

8

10

7

4

11

2X

1.45 0.1

2X

2.175

2.95 0.1

0.25

PKG

14

0.3

0.2

15X

2X

2

2X 0.85

A

0.1

0.05

C A B

C

0.65

0.45

5X

22

17

1

2X 0.575

0.45

0.35

18

0.45

0.35

SYMM

2

0.5

0.3

11X

0.5

0.3

4221861/E 07/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RNL0022A

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

18

SYMM

15X (0.25)

22

12X (0.6)

2X (0.4)

(2.325)

1

17

2X (2)

5X (0.75)

2X (1.425)

SEE SOLDER MASK

DETAILS

3X (0.4)

2X (0.575)

2X (1)

2X (0.4)

0.000 PKG

2X (0.25)

14

(0.295)

4

(

0.2) VIA TYP

NOTE 4

(3.15)

(1.125)

2X (1.65)

2X (1.875)

(2.175)

(1.955)

11

7

4X (0.5)

8

9

(2)

10

(3.4)

6X (3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

(PREFERRED)

4221861/E 07/2019

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNL0022A

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

SYMM

15X (0.25)

5X (0.75)

18

22

12X (0.6)

2X (0.4)

(2.325)

1

2X (2)

17

(R0.05) TYP

2X (1.425)

2X (0.575)

6X

EXPOSED

METAL

7X

EXPOSED

METAL

(1.4)

(0.12)

0.000 PKG

(0.25)

4X ( 0.4)

4

14

(0.71)

(2)

2X (1.445)

(1.54)

4X (0.5)

11

2X (2.175)

2X (2.305)

4X

(0.66)

7

(2.37)

9

10

8

8X (0.4)

4X (0.63)

(2)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PADS 4,8,9,10 & 14

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221861/E 07/2019

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMS3655AMRNLT
厂家：	TEXAS INSTRUMENTS
描述：	5.5A、36V 同步 400kHz 降压转换器 \| RNL \| 22 \| -40 to 125 开关输出元件转换器
文件：	总50页 (文件大小：2300K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMS3655AMRNLT [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E