LMS3655MQRNLTQ1_技术文档

LMS3655-Q1, LMS3635-Q1

SNAS714C – NOVEMBER 2016 – REVISED AUGUST 2021

LMS3635-Q1 3.5-A, LMS3655-Q1 5.5-A, 36-V Synchronous, 400-kHz Step-Down

Converter

1 Features

3 Description

•

AEC-Q100-qualified for automotive applications

– Device temperature grade 1: –40°C to +125°C

ambient operating temperature

– Device HBM classification level 2

– Device CDM classification level C6

96% Peak efficiency while converting 12 V to 5 V

Low EMI and minimized switch node ringing

400-kHz (±10%) fixed switching frequency

–40°C to +150°C junction temperature range

External frequency synchronization

RESET output with internal filter and 3-ms release

timer

Automatic light load mode for improved efficiency

Pin-selectable forced PWM mode

Built-In compensation, soft start, current limit,

thermal shutdown, and UVLO

0.35-V dropout with 3.5-A Load at 25°C (Typical)

18-µA I_{Q_VIN}: quiescent current at 3.3 V_OUTand no

load (typical)

The LMS3635-Q1 and LMS3655-Q1 synchronous

buck regulators are optimized for high performance

applications, providing an output voltage of 3.3 V, 5

V, or an adjustable output of 1 V to 20 V. Seamless

transition between PWM and PFM modes, along with

a low quiescent current, ensures high efficiency and

superior transient responses at all loads.

•

Advanced high-speed circuitry allows the LMS3655-

Q1 to regulate an input of 24 V to an output of 3.3 V

at a fixed frequency of 400 kHz while also enabling

a continuous load current of 5.5 A. An innovative

frequency foldback architecture allows this device to

regulate a 3.3-V output from an input voltage of only

3.5 V. The input voltage can range up to 36 V, with

transient tolerance up to 42 V, easing input surge

protection design.

•

An open-drain reset output, with built-in filtering and

delay, provides a true indication of system status.

This feature negates the requirement for an additional

supervisory component, saving cost and board space.

•

Output voltage: 5 V, 3.3 V, and ADJ (1 V to 20 V)

±1.5% reference voltage tolerance

Create a custom design using the LMS3655-Q1

with the WEBENCH^®Power Designer

Device Information

DEVICE NAME

LMS3635-Q1

PACKAGE⁽¹⁾

BODY SIZE

2 Applications

SON (22)

4.00 mm × 5.00 mm

LMS3655-Q1

•

Automotive USB charge

Driver monitoring

Surround view system ECU

Mechanically scanning LIDAR

Vehicle to vehicle

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

100%

98%

96%

94%

92%

90%

88%

86%

84%

82%

80%

V_IN= 12

V_IN= 24

0.001

0.01

0.1

Output Current (A)

1

10

LMS3

LMS3655-Q1 Conducted EMI: V_{OUT = 5 V}, I_OUT= 5 A

LMS3655-Q1 Efficiency: V_OUT= 5 V

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMS3655-Q1, LMS3635-Q1

SNAS714C – NOVEMBER 2016 – REVISED AUGUST 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Tables.............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................5

7.4 Thermal Information....................................................6

7.5 Thermal Information (for Device Mounted on PCB)....6

7.6 Electrical Characteristics.............................................6

7.7 System Characteristics............................................... 8

7.8 Timing Requirements................................................10

7.9 Typical Characteristics.............................................. 11

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................15

8.4 Device Functional Modes..........................................20

9 Application and Implementation..................................24

9.1 Application Information............................................. 24

9.2 Typical Applications.................................................. 24

9.3 Do's and Don't's........................................................ 42

10 Power Supply Recommendations..............................42

11 Layout...........................................................................43

11.1 Layout Guidelines................................................... 43

11.2 Layout Example...................................................... 44

12 Device and Documentation Support..........................46

12.1 Device Support....................................................... 46

12.2 Documentation Support.......................................... 46

12.3 Receiving Notification of Documentation Updates..46

12.4 Support Resources................................................. 46

12.5 Trademarks.............................................................46

12.6 Electrostatic Discharge Caution..............................47

12.7 Glossary..................................................................47

13 Mechanical, Packaging, and Orderable

Information.................................................................... 48

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2018) to Revision C (August 2021)

Page

•

Added WEBENCH link and sections.................................................................................................................. 1

Updated applications.......................................................................................................................................... 1

Updated the numbering format for tables, figures, and cross-references throughout the document. ................1

Added non-wettable flank options.......................................................................................................................1

Changes from Revision A (September 2017) to Revision B (March 2018)

Page

•

Changed maximum adjustable output voltage from: 15 V to: 20 V ....................................................................1

Changed maximum extended output adjustment from: 15 V to: 20 V ............................................................... 5

Added new extended output adjustment tablenote to the Recommended Operating Conditions ..................... 5

2

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5 Device Comparison Tables

Table 5-1. LMS3635-Q1 Devices (3.5-A Output)

SPREAD

SPECTRUM

WETTABLE

FLANKS

PART NUMBER

OUTPUT VOLTAGE

PACKAGE QTY

LMS3635AQRNLRQ1

LMS3635AQRNLTQ1

LMS36353QRNLRQ1

LMS36353QRNLTQ1

LMS36355QRNLRQ1

LMS36355QRNLTQ1

LMS3635MQRNLRQ1

LMS3635MQRNLTQ1

LMS3635NQRNLRQ1

LMS3635NQRNLTQ1

LMS3635LQRNLRQ1

LMS3635LQRNLTQ1

LMS3635MQURNLRQ1

LMS3635LQURNLRQ1

Adjustable

3.3 V

No

3000

250

Y

N

No

3000

250

3.3 V

No

5 V

No

3000

250

5 V

No

Adjustable

3.3 V

Yes

3000

250

3000

250

3.3 V

5 V

3000

250

5 V

Adjustable

5V

3000

Table 5-2. LMS3655-Q1 Devices (5.5-A Output)

SPREAD

SPECTRUM

WETTABLE

FLANK

PART NUMBER

OUTPUT VOLTAGE

PACKAGE QTY

LMS3655AQRNLRQ1

LMS3655AQRNLTQ1

LMS36553QRNLRQ1

LMS36553QRNLTQ1

LMS36555QRNLRQ1

LMS36555QRNLTQ1

LMS3655MQRNLRQ1

LMS3655MQRNLTQ1

LMS3655NQRNLRQ1

LMS3655NQRNLTQ1

LMS3655LQRNLRQ1

LMS3655LQRNLTQ1

LMS3655MQURNLRQ1

LMS3655NQURNLRQ1

Adjustable

3.3 V

No

3000

250

Y

N

No

3000

250

3.3 V

No

5 V

No

3000

250

5 V

No

Adjustable

3.3 V

Yes

3000

250

3000

250

3.3 V

5 V

3000

250

5 V

Adjustable

3.3

3000

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6 Pin Configuration and Functions

Figure 6-1. RNL Package 22-Pin VQFN Top View

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NO.

NAME

Internal 3.1-V LDO output. Used as supply to internal control circuits. Connect a high-quality 4.7-µF

capacitor from this pin to AGND.

1

VCC

A

P

I

Bootstrap capacitor connection for gate drivers. Connect a high quality 470-nF capacitor from this pin to

the SW pin.

2

3

4

CBOOT

SYNC

Synchronization input to regulator. Used to synchronize the device switching frequency to a system clock.

Triggers on rising edge of external clock; frequency must be in the range of 250 kHz and 500 kHz.

Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect

PVIN1 and PVIN2 pins directly together at PCB.

PVIN1

P

5

6

Power ground to internal low-side MOSFET. These pins must be tied together on the PCB. Connect

PGND1 and PGND2 directly together at PCB. Connect to AGND and system ground.

PGND1

SW

G

P

7

8

9

Regulator switch node. Connect to power inductor.

10

11

12

13

Power ground to internal low-side MOSFET. These pins must be tied together. Connect PGND1 and

PGND2 directly together at PCB. Connect to AGND and system ground.

PGND2

G

Input supply to regulator. Connect input bypass capacitors directly to this pin and PGND pins. Connect

PVIN1 and PVIN2 pins directly together at PCB.

14

PVIN2

P

15

16

1 7

18

AVIN

FPWM

NC

A

I

Analog VIN. Connect to PVIN1 and PVIN2 on PCB.

Mode control input of regulator. High = FPWM, low = Automatic light load mode. Do not float.

No internal connection.

—

I

EN

Enable input to regulator. High = on, Low = off. Can be connected to VIN. Do not float.

Open-drain reset output flag. Connect to suitable voltage supply through a current limiting resistor. High =

regulator OK, Low = regulator fault. Goes low when EN = low.

19

20

RESET

AGND

O

G

Analog ground for regulator and system. All electrical parameters are measured with respect to this pin.

Connect to PGND on PCB.

Feedback input to regulator. Connect to output voltage node for fixed VOUT options. Connect to feedback

voltage divider for adjustable option.

21

22

FB

A

P

BIAS

Input to auxiliary bias regulator. Connect to output voltage node.

(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

4

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7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted). ⁽¹⁾

PARAMETER

VIN (AVIN, PVIN1, and PVIN2) to AGND, PGND⁽²⁾

SW to AGND, PGND⁽³⁾

MIN

–0.3

MAX

UNIT

V

40

V_IN+ 0.3

3.6

40

V

CBOOT to SW

V

EN to AGND, PGND⁽²⁾

V

BIAS to AGND, PGND

16

V

FB to AGND, PGND: Fixed 3.3-V Output, Fixed 5-V Output

FB to AGND, PGND: Adjustable Output

RESET to AGND, PGND

16

V

16

V

8

V

RESET sink current⁽⁴⁾

10

mA

V

SYNC to AGND, PGND⁽²⁾

–0.3

–40

40

FPWM to AGND, PGND⁽²⁾

40

V

VCC to AGND, PGND

3.6

150

V

Junction temperature

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Section 7.1 may cause permanent damage to the device. These are stress ratings only, functional

operation of the device at these or any other conditions beyond those indicated under Section 7.3 are not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) A maximum of 42 V can be sustained at this pin for a duration of ≤ 500 ms at a duty cycle of ≤ 0.01%.

(3) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.

(4) Do not exceed the voltage rating on this pin.

7.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted).

MIN

NOM

MAX

36

UNIT

V

Input voltage after start-up⁽¹⁾

3.9

Output voltage for 3.3-V LMS36x5-Q1⁽²⁾

3.3

5

V

Output voltage for 5-V LMS36x5-Q1⁽²⁾

V

Output adjustment for adjustable version of LMS36x5-Q1 ⁽²⁾

Extended output adjustment for adjustable version of LMS36x5-Q1 ^{(3) (4)}

Load current for LMS3635-Q1, fixed output option and adjustable

Load current for LMS3655-Q1 , fixed output option and adjustable

Operating ambient temperature⁽⁵⁾

3.3

1

6

V

20

V

3.5

5.5

125

A

–40

°C

(1) An extended input voltage range to 3.5 V is possible; see Section 7.7 table. See Input UVLO for start-up conditions.

(2) The output voltage must not be allowed to fall below zero volts during normal operation.

(3) Operation below 3.3 V and above 6 V may require changes to the typical application schematic, operation may not be possible over

the full input voltage range, and some system specifications will not be achieved for this extended output voltage range. Consult the

factory for further information.

(4) Operation above 15 V requires the BIAS pin grounded or powered by an external source. A maximum of 16 V can be sustained on the

BIAS pin.

(5) High junction temperatures degrade operating lifetime.

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7.4 Thermal Information

LMS36x5-Q1

RNL (VQFN)

22 PINS

38.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

16.3

16.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.0

ψ_JB

16.4

R_θJC(bot)

4.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Thermal Information (for Device Mounted on PCB)

LMS36x5-Q1

THERMAL METRIC⁽¹⁾

RNL (VQFN)

22 PINS

29.4

UNIT

R_θJA

R_θJC

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

14.2

5.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.2

ψ_JB

5.4

R_θJC(bot)

2.4

(1) Mounted on a thermally optimized FR4 four layer EVM with a size of 4000 mill × 3000 mill.

7.6 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

V_IN= 3.8 V to 36 V, T_J= 25°C

V_IN= 3.8 V to 36 V

MIN

TYP

MAX

UNIT

–1%

1%

Initial reference voltage for 5-V

and 3.3-V options

V_FB

–1.5%

1.5%

Operating quiescent current;

measured at VIN pin when

enabled and not switching⁽¹⁾

I_Q

V_IN= 13.5 V, V_BIAS= 5 V

7.5

16

µA

V_IN= 13.5 V, V_BIAS= 5 V, FPWM = 0

V

53

2

62

3

Bias current into BIAS pin,

enabled, not switching

I_{B_NSW}

V_IN= 13.5 V, V_BIAS= 3.3 V, FPWM =

0 V

Shutdown quiescent current;

measured at VIN pin

I_SD

EN ≤ 0.4 V

Rising

µA

V

3.2

2.95

3.55

3.25

0.3

3.90

3.55

V_IN-OPERATE

Minimum input voltage to operate Falling

Hysteresis

0.28

0.4

RESET upper threshold voltage

RESET lower threshold voltage

Magnitude of RESET lower

Rising, % of V_OUT

105%

92%

107%

94%

110%

96.5%

Falling, % V_OUT

V_RESET

Steady-state output voltage and

threshold from steady state output RESET falling threshold read at the

96%

voltage

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same T_Jand V_IN

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Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESET hysteresis as a percent of

output voltage setpoint

V_{RESET_HYST}

V_{RESET_VALID}

±1%

Minimum input voltage for proper 50-µA pullup to RESET pin,

RESET function

1.5

0.4

440

V

EN = 0 V, T_J= 25°C

50-µA pullup to RESET pin,

V_IN= 1.5 V, EN = 0 V

Low level RESET function output 0.5-mA pullup to RESET pin,

V_OL

V

voltage

V_IN= 13.5 V, EN = 0 V

1-mA pullup to RESET pin,

V_IN= 13.5 V, EN = 3.3 V

V_IN= 13.5 V, center frequency with

spread spectrum, PWM operation

360

400

F_SW

Switching frequency

kHz

V_IN= 13.5 V, without spread

spectrum, PWM operation

400

F_SYNC

D_SYNC

Sync frequency range

250

25%

1.5

500

Sync input duty cycle range

High state input < 5.5 V and > 2.3 V

FPWM input high (MODE = FPWM)

75%

FPWM input low (MODE = AUTO

with diode emulation)

V_FPWM

FPWM input threshold voltage

0.4

1

V

FPWM input hysteresis

0.15

Frequency span of spread

spectrum operation

FS_SS

F_PSS

±3%

Spread-spectrum pattern

frequency⁽²⁾

1.2

Hz

µA

V_IN= 13.5 V, V_FPWM= 3.3 V

V_IN= V_FPWM= 13.5 V

V_IN= 13.5 V, V_SYNC= 3.3 V

V_IN= V_SYNC= 13.5 V

LMS3635-Q1

1

I_FPWM

I_SYNC

I_L-HS

FPWM leakage current

1

SYNC leakage current

µA

A

1

4.5

6.7

4

6

7.5

9.5

6.5

7.5

High-side switch current limit

Low-side switch current limit

LMS3655-Q1

8.5

4.5

7

LMS3635-Q1

I_L-LS

A

LMS3655-Q1

6

Zero-cross current limit FPWM =

low

I_L-ZC

–0.02

–1.5

60

A

Negative current limit FPWM =

high

I_L-NEG

High-side MOSFET R_DSON

V_IN= 13 V, IL = 1 A

,

130

80

R_DSON

Power switch on-resistance

mΩ

V

Low-side MOSFET R_DSON

,

40

V_IN= 13 V, IL = 1 A

Enable input threshold voltage -

rising

V_EN

Enable rising

1.7

2

V_{EN_HYST}

V_{EN_WAKE}

I_EN

Enable threshold hysteresis

Enable wake-up threshold

EN pin input current

0.45

0.4

0.55

V

V_IN= V_EN= 13.5 V

2

3.05

3.15

3

µA

V_IN= 13.5 V, V_BIAS= 0 V

V_CC

Internal V_CCvoltage

V

V_IN= 13.5 V, V_BIAS= 3.3 V

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Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

2.7

185

20

1

MAX

UNIT

V_INrising

V

Internal V_CCinput undervoltage

lockout

V_{CC_UVLO}

I_FB

Hysteresis below V_CC-UVLO

Adjustable LMS36x5-Q1, FB = 1 V

T_J= 25°C

mV

nA

Input current from FB to AGND

0.993

0.99

1.007

1.01

Reference voltage for adjustable

option only

V_REF

V

T_J= –40°C to 125°C

1

Pull FB pin low. Sink 1-mA at

RESET pin

R_RESET

R_DSONof RESEToutput

50

120

Ω

V_IH

1.5

V_SYNC

V_IL

0.4

1

V

V_HYST

0.15

160

Rising

185

T_SD

Thermal shutdown thresholds⁽²⁾

°C

Hysteresis

15

F_sw= 400 kHz

While in dropout⁽²⁾

96%

D_MAX

Maximum switch duty cycle

98%

(1) This is the current used by the device while not switching, open loop on the ATE. It does not represent the total input current from the

regulator system.

(2) Ensured by Design, Not tested at production.

7.7 System Characteristics

The following specifications are ensured by design provided that the component values in the typical application circuit

are used. These parameters are not ensured by production testing. Limits apply over the recommended operating junction

temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only. Unless otherwise stated the following conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum input voltage for full functionality at

3.5-A load, after start-up.

V_OUT= 3.3 V +2% or –3% regulation

3.5

V_IN-MIN

V

Minimum input voltage for full functionality at

maximum rated load 5.5 A after start-up.

V_OUT= 3.3 V +2% or –3% regulation

3.8

Output voltage for 5-V option

Output voltage for 3.3-V option

V_IN= 5.6 V to 36 V, I_OUT= 3.5 A

V_IN= 3.9 V to 36 V, I_OUT= 3.5 A

4.925

3.24

5

5.08

3.35

3.3

V_IN= 5.5 V to 36 V, I_OUT= 100 µA to 100

mA

V

Output voltage for 5-V option

4.92

5.05

3.33

5.125

V_OUT

V_IN= 3.8 V to 36 V, I_OUT= 100 µA to 100

mA

Output voltage for 3.3-V option

Output voltage for adjustable option

Switching frequency

3.24

3.38

2.25

V_IN= V_OUT+ 1 V to 36 V, I_OUT= 3.5 A

–2.25

%

V_IN= 24 V, FPWM = 24V, V_OUT= 3.3 V, I_OUT

= 200 mA

F_SW

400

18

kHz

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 0 A,

FPWM = 0

I_{Q_VIN}

Input current to VIN pin

µA

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 0 A, FPWM

= 0

24

32

I_B

Bias current in AUTO mode at no load

V_IN= 13.5 V, I_OUT= 0 A, FPWM = 0

42

µA

V

V_OUT= 3.3 V or 5 V, I_OUT= 3.5 A, +2% or

–3% output accuracy

0.35

0.6

Minimum input to output voltage differential to

maintain regulation accuracy without inductor

DCR drop

V_DROP1

V_OUT= 3.3 V or 5 V, I_OUT= 5.5 A, +2% or

–3% output accuracy

0.65

0.5

0.85

0.7

V

V_OUT= 3.3 V or 5 V, I_OUT= 3.5 A,

F_SW= 330 kHz, 2% regulation accuracy

Minimum input to output voltage differential to

maintain F_SW≥ 330 kHz without inductor DCR

drop

V_DROP2

V_OUT= 3.3 V or 5 V, I_OUT= 5.5 A,

F_SW= 330 kHz, 2% regulation accuracy

0.7

1.2

8

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The following specifications are ensured by design provided that the component values in the typical application circuit

are used. These parameters are not ensured by production testing. Limits apply over the recommended operating junction

temperature range of –40°C to +150°C, unless otherwise noted. Minimum and maximum limits are specified through test,

design, or statistical correlation. Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for

reference purposes only. Unless otherwise stated the following conditions apply: V_IN= 13.5 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

94%

92%

MAX

UNIT

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 3.5 A

V_IN= 13.5 V, V_OUT= 3.3 V, I_OUT= 3.5 A

V_IN= 13.5 V, V_OUT= 5 V, I_OUT= 100 mA

Efficiency Typical efficiency

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7.8 Timing Requirements

Limits apply over the recommended operating junction temperature range of –40°C to +150°C, unless otherwise noted.

Minimum and maximum limits are ensured through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25°C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 13.5 V.

MIN

NOM

60

65

3

MAX

UNIT

t_ON

Minimum switch on-time, V_IN= 18 V, I_L= 1 A

Minimum switch off-time, V_IN= 3.8 V, I_L= 1 A

Delay time to RESET high signal

84

ns

t_OFF

80

ns

t_RESET-act

t_RESET-filter

t_SS

2

4

ms

µs

Glitch filter time for RESET function⁽¹⁾

24

4

Soft-start time from first switching pulse to V_REFat 90%

Turnon delay, C_VCC= 4.7 µF⁽²⁾

2.5

5

ms

t_EN

0.8

6

t_W

Short-circuit wait time (hiccup time)⁽³⁾

Change transition time from AUTO to FPWM MODE, 10-mA load, V_IN= 13.5 V

Change transition time from FPWM to AUTO MODE, 10-mA load, V_IN= 13.5 V

250

450

t_FPWM

µs

(1) See Section 8.

(2) This is the time from the rising edge of EN to the time that the soft-start ramp begins.

(3) T_wis the wait time between current limit trip and restart. T_wis proportional to the soft-start time. However, provision must be made to

make T_wlonger to ensure survivability during an output short circuit.

10

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7.9 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25°C. Specified temperatures are

ambient.

104%

103%

102%

101%

100%

99%

450000

440000

430000

420000

410000

400000

390000

380000

370000

360000

350000

-50

-25

0

25

50

75

100 125 150 175

-40

10

60

Temperature (èC)

110

160

Temperature (èC)

LMS3

V_IN= 12 V

Figure 7-1. Reference Voltage Drift

Figure 7-2. Switching Frequency vs Temperature

10

8

7

6

5

4

3

2

6

4

2

LMS3655

LMS3635

1

0

LMS3655

LMS3635

0

-50

0

50

100

150

200

-50

0

50

100

150

200

Temperature (èC)

LMS3

Temperature (èC)

LMS3

V_IN= 12 V

V_IN= 12V

Figure 7-3. High-Side/Peak Current Limit for

LMS36x5-Q1

Figure 7-4. Low-Side/Valley Current Limit for

LMS36x5-Q1

0.25

25

3.8 V_IN

5.5 V_IN

13.5 V_IN

0.2

20

18 V_IN

0.15

0.1

15

10

5

0.05

0

5

10

15

20

25

30

35

40

-50

0

50

100

150

200

Temperature (èC)

LMS3

Temperature (èC)

LMS3

V_IN= 12 V

Figure 7-5. Short Circuit Average Input Current for

LMS3635-Q1

Figure 7-6. Shutdown Current

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5.4

108

106

104

102

100

98

V_{RESET_UPPER}

5.3

V_{RESET_UPPER_FALLING}

5.2

5.1

5

4.9

V_{RESET_LOWER_RISING}

4.8

V_{RESET_LOWER}

4.7

4.6

4.5

96

V_{RESET_LOWER}

94

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

LMS3

Figure 7-7. RESET Threshold Fixed 5-V Output

Figure 7-8. RESET Threshold as Percentage of

Output Voltage

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8 Detailed Description

8.1 Overview

The LMS36x5-Q1 devices are wide-input voltage range, low quiescent current, high-performance regulators

with internal compensation. This device is designed to minimize end-product cost and size while operating in

demanding automotive and high-performance industrial environments. Normal operating frequency is 400 kHz,

allowing the use of small passive components. This device has a low unloaded current consumption, eliminating

the need for an external backup LDO. The LMS36x5-Q1 low shutdown current and high maximum operating

voltage also allow for the elimination of an external load switch. To further reduce system cost, an advanced

reset output is provided, which can often eliminate the use of an external reset or supervisor device.

The LMS36x5-Q1 is designed with a flip-chip or HotRod^™technology, greatly reducing the parasitic inductance

of the pins. In addition, the layout of the device allows for partial cancellation of the current generated magnetic

field which reduces the radiated noise generated by the switching action.

As a result the switch-node waveform exhibits less overshoot and ringing.

Figure 8-1. Switch Node Waveform (V_IN= 13.5 V, I_OUT= 5.5 A)

The LMS36x5-Q1 is AEC-Q1-qualified and has electrical characteristics ensured up to a maximum junction

temperature of 150°C.

The LMS36x5-Q1 is available in a VQFN package with wettable flanks which allows easy inspection of the

soldering without the requirement of x-ray checks.

Note

Throughout this data sheet, references to the LMS3635-Q1 apply equally to the LMS3655-Q1. The

difference between the two devices is the maximum output current and specified MOSFET current

limits.

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8.2 Functional Block Diagram

SYNC

VCC

BIAS

VIN

* = not used in -ADJ

Oscillator

Int. Reg. Bias

CBOOT

Enable

Logic

HS Current

Sense

EN

FB

¯

1.0-V

Reference

PWM

Comp.

Error

Amplifier

+

-

Control Logic

Driver

SW

*

+

-

LS Current

Sense

RESET

Reset

Control

Mode Logic

FPWM

AGND

PGND

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8.2.1 Control Scheme

The LMS36x5-Q1 control scheme allows this device to operate under a wide range of conditions with a

low number of external components. Peak current mode control allows a wide range of input voltages and

output capacitance values while maintaining a constant switching frequency. Stable operation is maintained

while output capacitance is changed during operation as well. This allows use in systems that require high

performance during load transients and which have load switches that remove loads as the operating state

changes. Short minimum on and off times ensure constant frequency regulation over a wide range of conversion

ratios.

This architecture uses frequency spreading to achieve low dropout voltage maintaining output regulation as the

input voltage falls close to output voltage. The frequency spreading is smooth and continuous, and activated as

the off time approaches its minimum. Under these conditions, the LMS36x5-Q1 operates like a constant off-time

converter, allowing the maximum duty cycle to reach 98% and output voltage regulation with 650-mV dropout. As

load current is reduced, the LMS36x5-Q1 transitions to light load mode. In this mode, diode emulation is used

to reduce RMS inductor current and switching frequency. Average output voltage increases slightly while lightly

loaded as well.

Fixed voltage versions do not need a voltage divider connected to FB saving additional power. As a result, only

18 µA (typical, while converting 13.5 V to 3.3 V) is consumed to regulate output voltage if output is unloaded.

8.3 Feature Description

8.3.1 RESET Flag Output

While the LMS36x5-Q1 reset function resembles a standard Power-Good function, its functionality is designed to

replace a discrete reset device, reducing additional component cost. There are three major differences between

the reset function and the normal power good function seen in most regulators.

•

A delay has been added between the point at which the output voltage is within specified limits and the flag

asserts Power Good. A glitch filter prevents false flag operation for short excursions in the output voltage,

such as during line and load transients. See Figure 8-3 and Figure 8-4 for more detail.

•

RESET output signals a fault (pulls its output to ground) while the part is disabled.

RESET continues to operate with input voltage as low as 1.5 V. Below this input voltage, RESET output may

be high impedance.

Because the RESET comparator and the regulation loop share the same reference, the thresholds track with

the output voltage. When EN is pulled low, the RESET flag output is forced low. When the device is disabled,

RESET remains valid as long as the input voltage is ≥ 1.5 V. RESET operation can best be understood

by reference to Figure 8-2 and Figure 8-3. Output voltage excursions lasting less than T_RESET-filterdo not

trip RESET. Once the output voltage is within the prescribed limits, a delay of T_RESET-actis imposed before

RESET goes high. This enables tighter tolerance than is possible with an external supervisor device while also

expanding the system allowance for transient response without the need for extremely accurate internal circuitry.

This output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply. It

can also be pulled up to either V_CCor V_OUT, through an appropriate resistor, as desired. The pin can be left

floating or grounded if the RESET function is not used in the application. The maximum current into this pin must

be limited to 10 mA, and the maximum voltage must be less than 8 V.

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Figure 8-2. Static RESET Operation

Figure 8-3. RESET Timing Behavior

The threshold voltage for the RESET function takes advantage of the availability of the LMS36x5-Q1 internal

feedback threshold to the RESET circuit. This allows a maximum threshold of 96.5% of selected output voltage

to be specified at the same time as 96% of actual set point.

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8.3.2 Enable and Start-Up

Start-up and shutdown of the LMS36x5-Q1 are controlled by the EN input. Applying a voltage of ≥ 2 V activates

the device, while a voltage of ≤ 1.45 V is required for shutdown. The EN input may also be connected directly to

the input voltage supply. This input must not be left floating. The LMS36x5-Q1 uses a reference-based soft start

that prevents output voltage overshoots and large inrush currents as the regulator is starting up.

A typical start-up waveform is shown in Figure 8-4 along with timing definitions. This waveform indicates the

sequence and timing between the enable input, output voltage, and RESET. From the figure, the user can

define several different start-up times depending on what is relevant to the application. Table 8-1 lists the timing

definitions and typical values.

t_RESET-UP

t_POWER-UP

t_RESET-ACT

t_EN

t_SS

2 ms/div

Figure 8-4. Typical Start-Up Waveform

Table 8-1. Typical Start-Up Times

PARAMETER

DEFINITION

VALUE

UNIT

ms

t_RESET-READY

t_POWER-UP

t_SS

Total start-up sequence time

Start-up time

Time from EN to RESET released

Time from EN to 90% of V_OUT

7.5

4

ms

Soft-start time

Rise time of V_OUTfrom 10% to 90%

Time from EN to start of V_OUTrising

3.2

1

ms

t_EN

Delay time

ms

Time from output voltage within 94% and

RESET released

t_RESET-ACT

RESET time

3

ms

8.3.3 Soft-Start Function

Soft-start time is fixed internally at about 4 ms. Soft start is achieved by ramping the internal reference.

The LMS36x5-Q1 operates correctly even if there is a voltage present on the output before activation of the

LMS36x5-Q1 (prebiased start-up). The device operates in AUTO mode during soft start, and the state of the

FPWM pin is ignored during that period.

8.3.4 Current Limit

The LMS36x5-Q1 incorporates a valley current limit for normal overloads and for short-circuit protection. A

precision low-side current limit prevents excessive average output current from the buck converter of the

LMS36x5-Q1. A high-side peak-current limit is employed for protection of the top N MOSFET and inductors.

The two current limits enable use of smaller inductors than a system with a single current limit. This scheme

allows use of inductors with saturation current rated less than twice the operating current of the LMS36x5-Q1.

During overloads the low-side current limit, I_L-LS(see Section 7.6), determines the maximum load current that the

LMS36x5-Q1 can supply. When the low-side switch turns on, the inductor current begins to ramp down. If the

current does not fall below I_L-LSbefore the next turnon cycle, then that cycle is skipped, and the low-side FET is

left on until the current falls below I_L-LS. This is different than the more typical peak current limit, and results in

Equation 1 for the maximum load current.

(

V

_IN- V_OUT

2∂F_S∂L

)

∂

V_OUT

I_OUT

= I_LS

+

max

V

IN

(1)

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If the converter continues triggering valley current limit for more than about 64 clock cycles, the device turns off

both high and low side switches for approximately 6 ms (see T_Win Section 7.8). If the overload is still present

after the hiccup time, another 64 cycles is counted, and the process is repeated. If the current limit is not tripped

for two consecutive clock cycles, the counter is reset. The hiccup time allows the inductor current to fall to zero,

resetting the inductor volt-second balance. Of course the output current is greatly reduced in this condition . A

typical short-circuit transient and recovery is shown in Figure 8-5.

SPACE

Figure 8-5. Short-Circuit Transient and Recovery

SPACE

The high-side current limit trips when the peak inductor current reaches I_L-HS(see Section 7.6). This is a

cycle-by-cycle current limit and does not produce any frequency or current foldback. It is meant to protect the

high-side MOSFET from excessive current. Under some conditions, such as high input voltage, this current limit

may trip before the low-side protection. The peak value of this current limit varies with duty cycle.

In response to a short circuit, the peak current limit prevents excessive peak current while valley current limit

prevents excessive average inductor current and keeps the power dissipation low during a fault. After a small

number of cycles of valley current limit triggers, hiccup mode is activated.

In addition, the I_NEGcurrent limit also protects the low-side switch from excessive negative current when the

device is in FPWM mode. If this current exceeds I_NEG, the low-side switch is turned off until the next clock cycle.

When the device is in AUTO mode, the negative current limit is increased to about I_ZC(about 0 A). This allows

the device to operate in DCM.

8.3.5 Hiccup Mode

Hiccup mode prevents excessive heating and power consumption under sustained short-circuit conditions. If an

overcurrent condition is maintained, the LMS36x5-Q1 shuts off its output and waits for T_W(approximately 6 ms),

after which the LMS36x5-Q1 restarts operation by activating soft start.

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Vout

Figure 8-6. Hiccup Operation

During hiccup mode operation, the switch node of the LMS36x5-Q1 is high impedance after a short circuit or

overcurrent persists for a short duration. Periodically, the LMS3655-Q1 attempts to restart. If the short has been

removed before one of these restart attempts, the LMS36x5-Q1 operates normally.

8.3.6 Synchronizing Input

It is often desirable to synchronize the operation of multiple regulators in a single system. This technique results

in better-defined EMI and can reduce the need for capacitance on some power rails. The LMS36x5-Q1 provides

a SYNC input which allows synchronization with an external clock. The LMS36x5-Q1 implements an in-phase

locking scheme—the rising edge of the clock signal provided to the SYNC input corresponds to turning on the

high-side device within the LMS36x5-Q1. The SYNC mode operation is implemented using phase locking over

a limited frequency range eliminating large glitches upon initial application of an external clock. The clock fed

into the LMS36x5-Q1 replaces the internal free running clock but does not affect frequency foldback operation.

Output voltage continues to be well regulated with duty factors outside of the normal 4% through 96% range

though at reduced frequency.

The SYNC input recognizes a valid high level as that ≥ 1.5 V, and a valid low as that ≤ 0.4 V. The frequency

synchronization signal must be in the range of 250 kHz to 500 kHz with a duty cycle of 10% to 90%. The internal

clock is synced to the rising edge of the external clock. Ground this input if not used; this input must not be

allowed to float. See Section 8.4 to determine which modes are valid for synchronizing the clock.

The device remains in FPWM mode and operates in CCM for light loads when a synchronization input is

provided. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load.

8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)

The LMS36x5-Q1 incorporates an input UVLO function. The device accepts an EN command when the input

voltage rises above about 3.64 V and shuts down when the input falls below about 3.3 V. See Section 7.6 under

V_IN-OPERATEfor detailed specifications.

TSD is provided to protect the device from excessive temperature. When the junction temperature reaches about

165°C, the device shuts down; restart occurs at a temperature of about 150°C.

8.3.8 Input Supply Current

The LMS36x5-Q1 is designed to have very low input supply current when regulating light loads. This is achieved

by powering much of the internal circuitry from the output. The BIAS pin is the input to the LDO that powers the

majority of the control circuits. By connecting the BIAS input to the output of the regulator, this current acts as

a small load on the output. This current is reduced by the ratio of V_OUT/ V_IN, just like any other load. Another

advantage of the LMS36x5-Q1 is that the feedback divider is integrated into the device. This allows the use of

much larger resistors than can be used externally (>> 100 kΩ); this results in much lower divider current than is

possible with external resistors.

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I_{Q_VIN}is defined as the current consumed by a converter using a LMS3635-Q1 or LMS3655-Q1 device while

regulating without a load. To calculate the theoretical total quiescent current, the below equation can be used

with parameters from the Section 7.6 and Section 7.7 tables. While operating without a load, the LMS3635-Q1

or LMS3655-Q1 only powers itself. The device draws power from three sources: the V_INpin (I_Q), the FB pin

(I_div), and the BIAS pin (I_B). Because the BIAS and FB pins are connected to the output of the circuit, the

power consumed is converted from input power with an effective efficiency, ηeff, of approximately 80%. Here,

effective efficiency is the added input power needed when lightly loading the converter of the LMS3635-Q1 and

LMS3655-Q1 devices and is divided by the corresponding additional load. This allows unloaded current to be

calculated in Equation 2:

Output Voltage

I_{Q_ VIN}= I_Q+I_EN+ I +I

(

)

B

div

h_effìInput Voltage

(2)

where

•

I_{Q_VIN}is the current consumed by the operating (switching) buck converter while unloaded.

I_Qis the current drawn by the LMS36x5-Q1 from its V_INterminal. See I_Qin Section 7.6.

I_ENis current drawn by the LMS36x5-Q1 from its EN terminal. Include this current if EN is connected to VIN.

See I_ENin Section 7.6. Note that this current drops to a very low value if connected to a voltage less than 5 V.

I_Bis bias current drawn by the unloaded LMS36x5-Q1. See I_Bin Section 7.7.

I_divis the current drawn by the feedback voltage divider used to set output voltage for adjustable devices.

This current is zero for fixed output voltage devices.

•

η_effis the light load efficiency of the Buck converter with I_{Q_VIN}removed from the input current of the buck

converter. 0.8 is a conservative value that can be used under normal operating conditions

Note

The EN pin consumes a few micro-amperes when tied to high; see I_EN. Add I_ENto I_Qas shown in

Equation 2 if EN is tied to V_IN. If EN is tied to a voltage less than 5 V, virtually no current is consumed

allowing EN to be used as an UVLO pin once a voltage divider is added.

The Section 9.2.2.3 show measured values for the input supply current for both the 3.3-V and the 5-V output

voltage versions.

8.4 Device Functional Modes

Refer to Table 8-2 and the following paragraphs for a detailed description of the functional modes for the

LMS36x5-Q1.

These modes are controlled by the FPWM input as listed in Table 8-2. This input can be controlled by any

compatible logic while the regulator is operating. If it is desired to fix the mode for a given application, the input

can be either connected to ground, a logic supply, the VIN pin, or the VCC pin, as desired. The FPWM pin must

not be allowed to float.

Table 8-2. Mode Selection

FPWM INPUT VOLTAGE

OPERATING MODE

Forced PWM: The regulator operates as a constant frequency, current mode, full-

synchronous converter for all loads; without diode emulation.

> 1.5 V

AUTO: The regulator moves between PFM and PWM as the load current changes, using

diode-emulation mode to allow DCM (see the Glossary).

< 0.4 V

8.4.1 AUTO Mode

In AUTO mode the device moves between PWM and PFM as the load changes. At light loads, the regulator

operates in PFM. At higher loads, the mode changes to PWM. The load currents at which the mode changes can

be found in the Section 9.2.2.3.

In PWM, the converter operates as a constant frequency, current mode, full synchronous converter using PWM

to regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a

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constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line

and load regulation and low output voltage ripple. When in PWM, the converter synchronizes to any valid clock

signal on the SYNC input (see Section 8.3.6); during PFM operation, the SYNC input is ignored.

In PFM, the high-side FET is turned on in a burst of one or more cycles to provide energy to the load. The

frequency of these bursts is adjusted to regulate the output, while diode emulation is used to maximize efficiency

(see the Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current

required to regulate the output voltage at small loads. A small increase in the output voltage occurs in PFM. This

trades off very good light load efficiency for larger output voltage ripple and variable switching frequency. The

actual switching frequency and output voltage ripple depend on the input voltage, output voltage, and load. See

the Section 9.2.2.3 for output voltage variation in AUTO mode. A typical switching waveform for PFM is shown in

Figure 8-7.

A unique feature of this device is that a minimum input voltage is required for the regulator to switch from PWM

to PFM at light load. This feature is a consequence of the advanced architecture employed to provide high

efficiency at light loads. Figure 8-8 indicates typical values of input voltage required to switch modes at no load.

Also, once the regulator switches to PFM at light load, it remains in that mode if the input voltage is reduced.

SPACE

4.2

Inductor Current:

250 mA/div

Light Load Deactivation Threshold (Falling)

Light Load Activation Threshold (Rising)

4

3.8

3.6

3.4

3.2

SW:

5V/div

VOUT:

5V/div

10 µs/div

-50

0

50

Temperature (èC)

100

150

LMS3

Figure 8-7. Typical PFM Switching Waveforms

Figure 8-8. Input Voltage for Mode Change — 3.3-V

Output, 10-µH Inductor

6

Light Load Deactivation Threshold (Falling)

Light Load Activation Threshold (Rising)

5.9

5.8

5.7

5.6

5.5

5.4

5.3

5.2

5.1

5

-50

0

50

Temperature (èC)

100

150

LMS3

Figure 8-9. Input Voltage for Mode Change — 5-V Output, 10-µH Inductor

8.4.2 FPWM Mode

With a logic high on the FPWM input, the device is locked in PWM mode. CCM operation is maintained, even at

no load, by allowing the inductor current to reverse its normal direction. To prevent frequency foldback behavior

at low duty cycles, provide a 200-mA load. This mode trades off reduced light load efficiency for low output

voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current

limit of I_NEGis imposed to prevent damage to the low-side FET of the regulator. When in PWM, the converter

synchronizes to any valid clock signal on the SYNC input (see Section 8.3.6).

When constant frequency operation is more important than light load efficiency, pull the LMS36x5-Q1 FPWM

input high or provide a valid synchronization input. Once activated, the diode emulation feature is turned off in

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this mode. This means that the device remains in CCM under light loads. Under conditions where the device

must reduce the on time or off time below the ensured minimum, the frequency reduces to maintain the effective

duty cycle required for regulation. This can occur for high input or output voltage ratios.

With the FPWM pin pulled low (normal mode), the diode emulation feature is activated. Device operation is the

same as above; however, the regulator goes into DCM operation when the valley of the inductor current reaches

zero.

This feature may be activated and deactivated while the part is regulating without removing the load. This feature

activates and deactivates gradually preventing perturbation of output voltage. When in FPWM mode, a limited

reverse current is allowed through the inductor allowing power to pass from the regulator's output to its input. In

this case, ensure that a large enough input capacitor is used to absorb the reverse current.

Note

While FPWM is activated, larger currents pass through the inductor than in AUTO mode when lightly

loaded. This may result in more EMI, though at a predictable frequency. Once loads are heavy enough

to necessitate CCM operation, FPWM has no measurable effect on the operation of the regulator.

8.4.3 Dropout

The minimum off time influences the dropout performance of the buck regulator. As the input voltage is reduced,

to near the output voltage, the off time of the high-side switch starts to approach the minimum value (see Section

7.6). Beyond this point the switching may become erratic or the output voltage falls out of regulation. To avoid

this problem, the LMS36x5-Q1 automatically reduces the switching frequency to increase the effective duty

cycle. This results in two specifications regarding dropout voltage, as shown in Section 7.7. One specification

indicates when the switching frequency drops to 330 kHz. The other specification indicates when the output

voltage has fallen to 3% of nominal. See the Section 9.2.2.3 for typical dropout values. Figure 8-10 and Figure

8-11 show the overall dropout characteristic for the 5-V option. Additional dropout information is discussed in

Section 9.2.2.3 for 5-V output and in Section 9.2.3.3 for 3.3-V output.

SPACE

450000

400000

350000

300000

250000

200000

150000

100000

50000

0

5.2

5

0 A

2 A

4 A

5.5 A

4.8

4.6

4.4

4.2

4

0 A

2 A

4 A

5.5 A

4

4.2 4.4 4.6 4.8

5 5.2 5.4 5.6 5.8

Input Voltage (V)

6

4

4.5

5

5.5

LMS3

Input Voltage (V)

LMS3

Figure 8-11. Frequency Dropout Characteristics

(V_OUT= 5 V)

Figure 8-10. Overall Dropout Characteristics (V_OUT

= 5 V)

22

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8.4.4 Spread-Spectrum Operation

The spread spectrum is a factory option. In order to find which parts have spread spectrum enabled, see Section

5.

The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading

emissions across a wider range of frequencies. In most systems containing the LMS36x5-Q1 devices, low

frequency conducted emissions from the first few harmonics of the switching frequency can be easily filtered.

A more difficult design criterion is reduction of emissions at higher harmonics which fall in the FM band.

These harmonics often couple to the environment through electric fields around the switch node. The LMS36x5-

Q1 devices use a ±3% spread of frequencies which spread energy smoothly across the FM band but is

small enough to limit sub-harmonic emissions below its switching frequency. Peak emissions at the switching

frequency of the part are only reduced by slightly less than 1 dB, while peaks in the FM band are typically

reduced by more than 6 dB.

The LMS36x5-Q1 devices use a cycle-to-cycle frequency hopping method based on a linear feedback shift

register (LFSR). Intelligent pseudo random generator limits cycle to cycle frequency changes to limit output

ripple. Pseudo random pattern repeats by approximately 1.2 Hz which is below the audio band.

The spread spectrum is only available while the clock of the LMS36x5-Q1 devices is free running at its natural

frequency. Any of the following conditions overrides spread spectrum, turning it off:

•

An external clock is applied to the SYNC/MODE terminal.

The clock is slowed due to operation at low input voltage; this is operation in dropout.

The clock is slowed under light load in AUTO mode; this is normally not seen above 200 mA of load. In

FPWM mode, spread spectrum is active even if there is no load.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LMS36x5-Q1 is a step-down DC-DC converter, typically used to convert a higher DC voltage to a lower

DC voltage with a maximum output current of 3.5 A or 5.5 A. The following design procedures can be used to

select components for the LMS36x5-Q1. Alternately, the WEBENCH^®Design Tool may be used to generate a

complete design. This tool uses an iterative design procedure and has access to a comprehensive database of

components. This allows the tool to create an optimized design and allows the user to experiment with various

design options.

9.2 Typical Applications

9.2.1 General Application

Figure 9-1 shows a general application schematic. FPWM, SYNC, and EN are digital inputs. RESET is an

open-drain output. FB connection is different for the fixed output options and the adjustable option.

•

The FPWM pin can be connected to GND to enable light-load PFM operation. Select this option if current

consumption at light load is critical. The pin can be connected to VCC or VIN for forced 400-kHz operation.

Select this option if constant switching frequency is critical. The pin can also be driven by an external signal

and can be toggled while the part is in operation (by an MCU, for example). Refer to the Section 8.4 for more

details on the operation and signal requirements of the FPWM pin.

•

The SYNC pin can be used to control the switching frequency and the phase of the converter. If the function

is not needed, tie the SYNC pin to GND, VCC, or VIN.

The RESET pin can be left floating or tied to ground if the function is not required. If the function is needed,

the pin must be connected to a DC rail through a pullup resistor (100 kΩ is the typical recommended value).

Check Section 8.3.1 for the details of the RESET pin function.

•

If the device is a fixed-output version (3.3-V or 5-V output option), connect the FB pin directly to the output. In

the case of an adjustable-output part, connect the output to the FB pin through a voltage divider. See Section

9.2.1.2 for details on component selection.

The BIAS pin can be connected directly to the output voltage. In applications that can experience inductive

shorts (such as cases with long leads on the output), a 3 Ω or so is necessary between the output and

the BIAS pin, and a small capacitor to GND is necessary close to the BIAS pin (C_BIAS). Alternatively, a

Schottky diode can be connected between OUT and GND to limit the negative voltage that can arise on the

output during inductive shorts. In addition, BIAS can also be connected to an external rail if necessary and if

available. The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 400

kHz.

•

Power components must be chosen carefully for proper operation of the converter. Section 9.2.1.2 discusses

the details of the process of choosing the input capacitors, output capacitors, and inductor for the application.

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VIN

3.5 V to 36 V

10 µF

PVIN 1

PVIN 2

PGND2

RESET

10 µF

PGND1

AVIN

VCC

SYNC

BIAS

4.7 µF

LMS3635/55-Q1

AGND

0.1 µF

NC

FB

FPWM

CBOOT

470 nF

SW

EN

V_OUT

L1 = 10 µH

3 X 47 µF

Figure 9-1. General Application Circuit

9.2.1.1 Design Requirements

Three sets of application-specific design requirements are outlined in Table 9-5, Table 9-6, and Table 9-7. The

minimum input voltage shown in Figure 9-1 is not the minimum operating voltage of the LMS36x5-Q1. Rather, it

is a typical operating range for the systems. For the complete information regarding minimum input voltage see

Section 7.6.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMS3655-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

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9.2.1.2.2 External Components Selection

The device requires input capacitors and an output inductor-capacitor filter. These components are critical to the

performance of the device.

9.2.1.2.2.1 Input Capacitors

The input capacitor supplies the AC switching current drawn from the switching action of the internal power

FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor

is large. The input capacitor must be rated to handle both the RMS current and the dissipated power.

The device is designed to be used with ceramic capacitors on the input of the buck regulator. The recommended

dielectric type of these capacitors is X7R rating to maintain proper tolerances over voltage and temperature.

The device requires a minimum of 20 µF of ceramic capacitance at the input. TI recommends 2 × 10 µF, 10 µF

for PVIN1 and 10 µF for PVIN2. Place these capacitors close to the PVIN1, PGND1, PVIN2, and the PGND2

pads. The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying

ripple current and isolating switching noise from other circuits. Table 9-1 shows the nominal and minimum values

of total input capacitance recommended for the LMS36x5-Q1. Also shown are the measured values of effective

capacitance for the indicated capacitor.

In addition, it is especially important to have small ceramic bypass capacitors of 10 nF to 100 nF very close

to the PVIN1 and PVIN2 inputs to minimize ringing and EMI generation due to the high-speed switching of the

device coupled with trace inductance. TI recommends that a small case size 10-nF ceramic capacitor be placed

across the input, as close to the device as possible. Additional high-frequency capacitors can be used to help

manage conducted EMI or voltage spike issues that may be encountered.

Many times it is desirable to use an additional electrolytic capacitor on the input, in parallel with the ceramics.

This is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate

ESR of this capacitor can help damp any ringing on the input supply caused by long power leads. The use of this

additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

Table 9-1. Recommended Input Capacitors

NOMINAL INPUT CAPACITANCE

MINIMUM INPUT CAPACITANCE

PART NUMBER

RATED

CAPACITANCE

MEASURED

MEASURED CAPACITANCE⁽¹⁾

RATED CAPACITANCE

CAPACITANCE⁽¹⁾

3 × 10 μF

22.5 μF

2 × 10 μF

15 μF

CL32B106KBJNNNE

(1) Measured at 14 V and 25°C.

9.2.1.2.2.2 Output Inductors and Capacitors

There are several design considerations related to the selection of output inductors and capacitors:

•

Load transient response

Stability

Efficiency

Output ripple voltage

Overcurrent ruggedness

The device has been optimized for use with LC values as shown in the Figure 9-1.

9.2.1.2.2.2.1 Inductor Selection

The LMS36x5-Q1 devices run in current mode and with internal compensation. The compensation of the fixed

5-V and 3.3-V configurations is stable with inductance between 6.5 µH and 20 µH. For most applications, the

fixed 5-V and 3.3-V configurations of the LMS36x5-Q1 devices are optimized for a nominal inductance of 10

μH. This gives a ripple current that is approximately 20% to 30% of the full load current of 5.5 A. If applying

a synchronization clock signal, the designer should appropriately size the inductor for the converter's operating

switching frequency. For output voltages greater than 5 V, a proportionally larger inductor can be used, thus

keeping the ratio of inductor current slope to internal compensating slope constant. Inductance that is too high is

not recommended because it can result in poor load transient behavior and instability.

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The inductor must be rated to handle the peak load current plus the ripple current—carefully review the

different saturation current ratings specified by different manufacturers. Saturation current ratings are typically

specified at 25°C, so ratings at maximum ambient temperature of the application should be requested from

the manufacturer. For the LMS3635-Q1, TI recommends a saturation current of 7.5 A or higher, and for the

LMS3655-Q1, a saturation current of 10 A or higher is recommended. Carefully review the inductor parasitic

resistance; the inductor parasitic resistance must be as low as possible to minimize losses at heavy loads. The

best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.

Table 9-2 gives a list of several possible inductors that can be used with the LMS36x5-Q1.

The designer should choose the inductors that best match the system requirements. A very wide range of

inductors are available as regarding physical size, height, maximum current (thermally limited, and inductance

loss limited), series resistance, maximum operating frequency, losses, and so forth. In general, inductors of

smaller physical size have higher series resistance (DCR) and implicitly lower overall efficiency is achieved.

Very low-profile inductors may have even higher series resistance. TI recommends finding the best compromise

between system performance and cost.

Table 9-2. Recommended Inductors

MANUFACTURER

Würth

PART NUMBER

SATURATION CURRENT

DC RESISTANCE

16 mΩ

7443251000

8.5 A

10.5 A

7.8 A

7.9 A

8 A

Würth

7447709100

21 mΩ

Coilcraft

Coiltronics

Vishay

DO3316T-222MLB

MPI4040R3-2R2-R

IHLP2525CZER2R2M01

IHLP4040DZER100M01

XAL6060-103MEC

XAL8080-103MED

11 mΩ

48 mΩ

18 mΩ

Vishay

12 A

36.5 mΩ

27 mΩ

Coilcraft

7.6 A

10.9 A

21 mΩ

9.2.1.2.2.2.2 Output Capacitor Selection

The output capacitor of a switching converter absorbs the AC ripple current from the inductor, reduces the

output voltage ripple, and provides the initial response to a load transient. The ripple voltage at the output of

the converter is the product of the ripple current flowing through the output capacitor and the impedance of

the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements

within the capacitor, depending on the frequency of the ripple current. Ceramic capacitors have very low ESR

and remain capacitive up to high frequencies. Their inductive component can be usually neglected at the

operating frequency range of the converter.

The LMS36x5-Q1 is designed to work with low-ESR ceramic capacitors. For automotive applications, TI

recommends X7R type capacitors. The effective value of these capacitors is defined as the actual capacitance

under voltage bias and temperature. All ceramic capacitors have a large voltage coefficient, in addition to normal

tolerances and temperature coefficients. Under DC bias, the capacitance value drops considerably. Larger

case sizes or higher voltage capacitors are better in this regard. To help mitigate these effects, multiple small

capacitors can be used in parallel to bring the minimum effective capacitance up to the desired value. This

can also ease the RMS current requirements on a single capacitor. Table 9-3 shows the nominal and minimum

values of total output ceramic capacitance recommended for the LMS36x5-Q1.The values shown also provide a

starting point for other output voltages, when using the adjustable option. More output capacitance can be used

to improve transient performance and reduce output voltage ripple.

In order to minimize ceramic capacitance, a low-ESR electrolytic capacitor can be used in parallel with minimal

ceramic capacitance. As a starting point for designing with an output electrolytic capacitor, Table 9-4 shows the

minimum ceramic capacitance recommended when paired with a 120-µF Aluminum-polymer (ESR = 25 mΩ) in

order to maintain stable operation. Depending on load transient design requirements, the designer may choose

to add additional capacitance.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load

transient testing and bode plots are the best way to validate any given design and should always be completed

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before the application goes into production. Make a careful study of temperature and bias voltage variation of

any candidate ceramic capacitor in order to ensure that the minimum value of effective capacitance is provided.

The best way to obtain an optimum design is to use the Texas Instruments WEBENCH Design Tool.

In adjustable applications the feed-forward capacitor, C_FF, provides another degree of freedom when stabilizing

and optimizing the design. Refer to Optimizing Transient Response of Internally Compensated DC-DC

Converters With Feedforward Capacitor (SLVA289) for helpful information when adjusting the feed-forward

capacitor.

In addition to the capacitance shown in Table 9-3, a small ceramic capacitor placed on the output can help to

reduce high frequency noise. Small case-size ceramic capacitors in the range of 1 nF to 100 nF can be very

helpful in reducing spikes on the output caused by inductor parasitics.

Limit the maximum value of total output capacitance to between 800 μF and 1200 μF. Large values of output

capacitance can prevent the regulator from starting up correctly and adversely effect the loop stability. If values

greater than the given range are to be used, then a careful study of start-up at full load and loop stability must be

performed.

Table 9-3. Recommended Output Ceramic Capacitors

NOMINAL OUTPUT CERAMIC

CAPACITANCE

MINIMUM OUTPUT CERAMIC

CAPACITANCE

OUTPUT VOLTAGE

PART NUMBER

RATED CAPACITANCE

5 × 47 µF

RATED CAPACITANCE

4 x 47µF

3.3 V (fixed option) ⁽¹⁾

5 V (fixed option) ⁽¹⁾

6 V⁽¹⁾

GRM32ER71A476KE15L

4 × 47 µF

3 × 47µF

4× 47 μF

3 × 47μF

10 V⁽²⁾

4 × 47 μF

3 × 47 μF

(1) L = 10 μH

(2) L = 20 μH

Table 9-4. Recommended Output Al-Polymer and Ceramic Capacitors

MINIMUM OUTPUT CERAMIC

OUTPUT AL-POLYMER CAPACITANCE

CAPACITANCE

RATED CAPACITANCE

1 × 47µF + 1 x 20µF

1 × 47µF

OUTPUT VOLTAGE

PART NUMBER

RATED CAPACITANCE

120 µF

3.3 V (fixed option) ⁽¹⁾

5 V (fixed option) ⁽¹⁾

APXE160ARA121MH70G

120 µF

(1) L = 10 μH

Consult Output Ripple Voltage for Buck Switching Regulator (SLVA630) for more details on the estimation of the

output voltage ripple for this converter.

9.2.1.2.3 Setting the Output Voltage

For the fixed output voltage versions, the FB input is connected directly to the output voltage node. Preferably,

near the top of the output capacitor. If the feedback point is located further away from the output capacitors (that

is, remote sensing), then a small 100-nF capacitor may be needed at the sensing point.

9.2.1.2.4 FB for Adjustable Output

The adjustable version of the LMS3635-Q1 and LMS3655-Q1 devices regulate output voltage to a level that

results in the FB node being V_REF, which is approximately 1 V (see Section 7.6). Output voltage given a specific

feedback divider can be calculated using Equation 3:

R_FBB+ R_FBT

R_FBB

Output Voltage = V_ref

ì

(3)

To ensure proper behavior for all modes of operation, a 50-kΩ resistor is recommended for R_FBT. R_FBBcan then

be determined using Equation 4:

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V

ìR_FBT

ref

R_FBB

=

Output Voltage - V

ref

(4)

In addition, a feed-forward capacitor C_FFmay be required to optimize the transient response. For output voltages

greater than 6 V, the WEBENCH Design Tool can be used to optimize the design.

9.2.1.2.5 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the LMS36x5-Q1. This

output requires a 4.7-µF, 10-V ceramic capacitor connected from VCC to GND for proper operation. X7R type is

recommended for automotive applications. In general, this output must not be loaded with any external circuitry.

However, the output can be used to supply a logic level to the FPWM input or for the pullup resistor used with

the RESET output. The nominal output of the LDO is 3.15 V.

9.2.1.2.6 BIAS

The BIAS pin is the input to the internal LDO. As detailed in Section 8.3.8, this input is connected directly to

V_OUTto provide the lowest possible supply current at light loads. Because this input is connected directly to

the output, it must be protected from negative voltage transients. Such transients may occur when the output is

shorted at the end of a long PCB trace or cable. If this is likely in a given application, then place a small resistor

in series between the BIAS input and V_OUT

.

Size the resistor to limit the current out of the BIAS pin to < 100 mA. Values in the range of 2 Ω to 5 Ω are

typically sufficient. Values greater than 5 Ω are not recommended. As a rough estimate, assume that the full

negative transient appears across R_BIASand design for a current of < 100 mA. In severe cases, a Schottky diode

can be placed in parallel with the output to limit the transient voltage and current.

When a resistor is used between the output and the BIAS pin, a 0.1-µF capacitor is required close to the BIAS

pin. In general, TI recommends having a 0.1-µF capacitor near the BIAS pin, regardless of the presence of the

resistor, unless the trace between the output capacitors and the BIAS pin is very short.

The typical current into the bias pin is 15 mA when the device is operating in PWM mode at 400 kHz.

9.2.1.2.7 CBOOT

The LMS36x5-Q1 requires a boot-strap capacitor between the CBOOT pin and the SW pin. This capacitor stores

energy that is used to supply the gate drivers for the power MOSFETs. A ceramic capacitor of 0.47 µF, ≥ 6.3 V is

required.

9.2.1.2.8 Maximum Ambient Temperature

As with any power conversion device, the LMS36x5-Q1 dissipates internal power while operating. The effect

of this power dissipation is to raise the internal temperature of the converter above ambient. The internal die

temperature (T_J) is a function of the ambient temperature, the power loss, and the effective thermal resistance,

R_θJAof the device and PCB combination. The maximum internal die temperature for the LMS3655-Q1 is 150°C,

thus establishing a limit on the maximum device power dissipation and therefore load current at high ambient

temperatures. Equation 5 shows the relationships between the important parameters.

(

T_J- T_A

R_qJA

)

∂

h

1- h

1

I_OUT

=

∂

(

)

V_OUT

(5)

The device uses an advanced package technology that uses the pads and pins as heat spreading paths. As

a result, the pads must be connected to large copper areas to dissipate the heat from the IC. All pins provide

some heat relief capability but the PVINs, PGNDs, and SW pins are of particular importance for proper heat

dissipation. Utilization of all the board layers for heat dissipation and using vias as heat pipes is recommended.

The Section 11.1 includes an example that shows layout for proper heat management.

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9.2.1.3 Application Curves

These parameters are not tested and represent typical performance only. Unless otherwise stated, the following

conditions apply: V_IN= 12 V, T_A= 25°C. For the purpose of offering more information to the designer, information

for the application with FPWM pin high (FPWM mode) and FPWM pin low (AUTO mode) is included, although

the schematic shows the application running specifically in FPWM mode. The mode is specified under each

following graph.

3.5

3

3.5

3

8.0 V_IN

4.0 V_IN

6.0 V_IN

12.0 V_IN

13.5 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

1

2

3

Output Current (A)

4

5

6

0

1

2

3

Output Current (A)

4

5

6

LMS3

Figure 9-2. Power Dissipation 5-V Output

Figure 9-3. Power Dissipation 3.3-V Output

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9.2.2 Fixed 5-V Output for USB-Type Applications

VIN

5.5 V œ 36 V

PVIN 1

10 µF

PVIN 2

10 µF

PGND1

0.1 µF

PGND2

RESET

0.1 µF

RESET/PG OUT

AVIN

100 kΩ

VCC

NC

4.7 µF

LMS3655

BIAS

AGND

0.1 µF

3 Ω

FPWM

EN

FB

CBOOT

470 nF

VOUT: 5 V

SYNC IN

SW

SYNC

L1 = 10 µF

1 X 47 µF

100 kΩ

1 X 120 µF

ESR = 25 mΩ

Figure 9-4. Fixed 5-V, 5.5-A Output Power Supply

9.2.2.1 Design Requirements

Example requirements for a typical 5-V application. The input voltages are here for illustration purposes only.

See Section 7.6 for minimum operating input voltage. The minimum input voltage necessary to achieve proper

output regulation depends on the components used. See Dropout for –3% Regulation for typical drop-out

behavior.

Table 9-5. Example Requirements for 5-V Typical Application

DESIGN PARAMETER

EXAMPLE VALUE

8 V to 18 V steady-state, 5.5 V to 36 V transients

0 A to 5.5 A

Input voltage range

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Critical: must have > 250 kHz

Not critical: < 100 mA acceptable

Yes: 300 kHz supplied by MCU

9.2.2.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that the load is connected to the output through

long wires so a 3-Ω resistor is inserted to minimize risks of damage to the part during load shorts. In addition

0.1-µF capacitor is required close to the bias pin.

FB is connected directly to the output. BIAS and FB are connected to the output through separate traces.

This is important to reduce noise and achieve good performances. See Section 11.1 for more details on the

proper layout method.

SYNC is connected to ground through a pulldown resistor, and an external synchronization signal can be

applied. The pulldown resistor ensures that the pin is not floating when the SYNC pin is not driven by any

source.

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•

EN is connected to VIN so the device operates as soon as the input voltage rises above the V_IN-OPERATE

threshold.

FPWM is connected to VIN. This causes the device to operate in FPWM mode. In this mode, the device

remains in CCM operation regardless of the output current and is ensured to be within the boundaries set by

F_SW. To prevent frequency foldback behavior at low duty cycles, provide a 200-mA load. The drawback is that

the efficiency is not optimized for light loads. See Section 8.4 for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation

of the internal LDO.

RESET is biased to the output in this example. A pullup resistor is necessary. A 100-kΩ is selected for this

application and is generally sufficient. The value can be selected to match the needs of the application but

must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Section 7.1 for

the maximum current allowed. In addition, a low pullup resistor could lead to an incorrect logic level due to

the value of R_RESET. Consult Section 7.6 for details on the RESET pin.

•

Input capacitor selection is detailed in Section 9.2.1.2.2.1. It is important to connect small high-frequency

capacitors C_{IN_HF1}and C_{IN_HF2}as close to both inputs PVIN1 and PVIN2 as possible.

Output capacitor selection is detailed in Section 9.2.1.2.2.2.2.

Inductor selection is detailed in Section 9.2.1.2.2.2.1. In general, a 10-µH inductor is recommended for the

fixed output options. For the adjustable output configurations, the inductance can vary with the output voltage

due to ripple and current limit requirements.

•

9.2.2.3 Application Curves

The following characteristics apply only to the circuit of Section 9.2.2. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A=

25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin

high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application

running specifically in FPWM mode. The mode is specified under each following graph.

32

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100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

100%

95%

90%

85%

80%

75%

70%

65%

60%

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

0

1

2

3

Output Current (A)

4

5

6

LMS3

V_OUT= 5 V

FPWM

0.001

0.01

0.1

Output Current (A)

1

10

LMS3

Figure 9-6. Efficiency

V_OUT= 5 V

AUTO

Figure 9-5. Efficiency

5.12

5.11

5.1

5.05

5.03

5.01

4.99

4.97

4.95

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

5.09

5.08

5.07

5.06

5.05

5.04

5.03

5.02

5.01

8.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

0

0.5

1

1.5

2

Output Current (A)

2.5

3

3.5

4

4.5

5

5.5

0

1

2

3

Output Current (A)

4

5

6

LMS3

V_OUT= 5 V

AUTO

V_OUT= 5 V

FPWM

Figure 9-7. Load and Line Regulation

Figure 9-8. Load and Line Regulation

1000

900

800

700

600

500

400

300

200

100

0

1.2

-40èC

25èC

1

0.8

0.6

0.4

0.2

0

105èC

0

10

20

Input Voltage (V)

30

40

0

1

2

3

Output Current (A)

4

5

6

LMS3

V_OUT= 5 V

Figure 9-9. Load Current for PFM-to-PWM

Transition

Figure 9-10. Dropout for –3% Regulation

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450000

400000

350000

300000

250000

200000

150000

100000

50000

0

1.2

-40èC

25èC

1

105èC

0.8

0.6

0.4

0.2

0

8 V_IN

12 V_IN

18 V_IN

24 V_IN

0.001

0.01

0.1

Output Current (A)

1

10

LMS3

0

1

2

3

Output Current (A)

4

5

6

V_OUT= 5 V

AUTO

LMS3

V_OUT= 5 V

Figure 9-12. Switching Frequency vs Load Current

Figure 9-11. Dropout for ≥ 330 kHz

9

8

7

6

5

4

3

2

1

0

LMS3655

LMS3635

0

5

10

15

20 25

Input Voltage (V)

30

35

40

45

AUTO

V_OUT= 5 V

L = 10 µH

LMS3

C_OUT= 170 µF I_OUT= 10 mA to 3.5 A

T_R= T_F= 1 µs

V_OUT= 5 V

L = 10 µH

Figure 9-14. Load Transients

Figure 9-13. Output Current Level Limit Before

Overcurrent Protection

FPWM

V_OUT= 5 V

I_OUT= 0 A to 3.5 A

L = 10 µH

C_OUT= 170 µF

T_R= T_F= 1 µs

Figure 9-15. Load Transient

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9.2.3 Fixed 3.3-V Output

VIN

3.8 V to 36 V

VDD

PVIN 1

PVIN 2

10 µF

100 kΩ

PGND1

AVIN

PGND2

RESET

0.1 µF

RESET/PG OUT

VCC

NC

4.7 µF

LMS3655

BIAS

AGND

0.1 µF

FB

FPWM

EN

CBOOT

470 nF

VOUT = 3.3 V

SW

SYNC

L1 = 10 µH

1 X 67 µF

1 X 120 µF

ESR = 25 mΩ

Figure 9-16. Fixed 3.3-V, 5.5-A Output Power Supply

9.2.3.1 Design Requirements

Example requirements for a typical 3.3-V application. The input voltages are here for illustration purposes

only. See Section 7.6 for minimum operating input voltage. The minimum input voltage necessary to achieve

proper output regulation depends on the components used. See Dropout for –3% Regulation for typical drop-out

behavior.

Table 9-6. Example Requirements for 3.3-V Application

DESIGN PARAMETER

EXAMPLE VALUE

8-V to 18-V steady-state, 4.0-V to 36-V transients

0 A to 5.5 A

Input voltage range

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

Not critical: Need >330 kHz at high load only

Critical: Need to ensure low current consumption to reduce battery drain

No

9.2.3.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that the load is close to the output so no bias

resistance is necessary. A 0.1-µF capacitor is still recommended close to the bias pin.

FB is connected directly to the output. BIAS and FB are connected to the output through separate traces.

This is important to reduce noise and achieve good performances. See Section 11.1 for more details on the

proper layout method.

•

SYNC is connected to ground directly as there is no need for this function in this application.

EN is connected to VIN so the device operates as soon as the input voltage rises above the V_IN-OPERATE

threshold.

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•

FPWM is connected to GND. This causes the device to operate in AUTO mode. In this mode, the switching

frequency is adjusted at light loads to optimize efficiency. As a result the switching frequency changes with

the output current until medium load is reached. The part will then switch at the frequency defined by F_SW

.

See Section 8.4 for more details.

•

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensures stable operation

of the internal LDO.

RESET is biased to an external rail in this example. A pullup resistor is necessary. A 100-kΩ pullup resistor is

selected for this application and is generally sufficient. The value can be selected to match the needs of the

application but must not lead to excessive current into the RESET pin when RESET is in a low state. Consult

Section 7.1 for the maximum current allowed. In addition, a low pullup resistor could lead to an incorrect logic

level due to the value of R_RESET. Consult Section 7.6 for details on the RESET pin.

It is important to connect small high frequency capacitors C_{IN_HF1}and C_{IN_HF2}as close to both inputs PVIN1

and PVIN2 as possible. For the detailed process of choosing input capacitors, refer to Section 9.2.1.2.2.1.

Output capacitor selection is detailed in Section 9.2.1.2.2.2.2.

•

Inductor selection is detailed in Section 9.2.1.2.2.2.1. In general, a 10-µH inductor is recommended for the

fixed output options. For the adjustable output configurations, the inductance can vary with the output voltage

due to ripple and current limit requirements.

9.2.3.3 Application Curves

The following characteristics apply only to the circuit of Figure 9-16. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A=

25°C. For the purpose of offering more information to the designer, information for the application with FPWM pin

high (FPWM mode) and FPWM pin low (AUTO mode) is included, although the schematic shows the application

running specifically in AUTO mode. The mode is specified under each of the following graphs.

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100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

45%

40%

35%

30%

25%

20%

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

6.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

0.0001

0.001

0.01 0.1

Output Current (A)

1

10

0.1

0.0001

LMS3

1.0001

2.0001 3.0001

Output Current (A)

4.0001

5.0001

V_OUT= 3.3 V

AUTO

LMS3

V_OUT= 3.3 V

FPWM

Figure 9-17. Efficiency

Figure 9-18. Efficiency

3.4

3.38

3.36

3.34

3.32

3.3

3.4

3.38

3.36

3.34

3.32

3.3

6.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

12.0 V_IN

13.5 V_IN

18.0 V_IN

24.0 V_IN

36.0 V_IN

3.28

3.26

3.24

3.22

3.2

3.28

3.26

3.24

3.22

3.2

0

0.5

1

1.5

2

Output Current (A)

2.5

3

3.5

4

4.5

5

5.5

1

2

3

Output Current (A)

4

5

6

LMS3

V_OUT= 3.3 V

AUTO

V_OUT= 3.3 V

FPWM

Figure 9-19. Load and Line Regulation

Figure 9-20. Load and Line Regulation

35

1400

1200

1000

800

600

400

200

0

30

25

20

15

10

5

10

15

20 25

Input Voltage (V)

30

35

40

0

5

10

15

Input Voltage (V)

20

25

30

35

40

LMS3

V_OUT= 3.3 V

AUTO

I_OUT= 0 A

V_OUT= 3.3 V

Figure 9-21. Input Supply Current (Includes

Leakage Current of Capacitor)

Figure 9-22. Load Current for PFM-to-PWM

Transition

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1.2

1

-40èC

25èC

105èC

-40èC

25èC

105èC

1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1

2

3

Output Current (A)

4

5

6

0

1

2

3

Output Current (A)

4

5

6

LMS3

V_OUT= 3.3 V

Figure 9-24. Dropout for ≥ 330 kHz

Figure 9-23. Dropout for –3% Regulation

450000

400000

350000

300000

250000

200000

150000

9

8

7

6

5

4

3

2

1

0

8 V_IN

12 V_IN

18 V_IN

24 V_IN

100000

50000

0

0.001

0.01

0.1

Output Current (A)

1

10

LMS3655

LMS3635

LMS3

V_OUT= 3.3 V

AUTO

0

5

10

15

20 25

Input Voltage (V)

30

35

40

45

Figure 9-25. Switching Frequency vs Load Current

LMS3

V_OUT= 3.3 V

L = 10 µH

Figure 9-26. Output Current Level for Overcurrent

Protection Trip

AUTO

V_OUT= 3.3 V

L = 10 µH,

FPWM

V_OUT= 3.3 V

L = 10 µH,

C_OUT= 190 µF

I_OUT= 0 A to 3.5 A

T_R= T_F= 1 µs

C_OUT= 190 µF

I_OUT= 0 A to 3.5 A

T_R= T_F= 1 µs

Figure 9-27. Load Transient

Figure 9-28. Load Transient

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V_OUT= 3.3 V

I_OUT= 10 mA

Figure 9-29. Mode Change Transient AUTO to FPWM mode

9.2.4 6-V Adjustable Output

VIN

8 V œ 36 V

PVIN 1

PVIN 2

10 µF

PGND1

AVIN

PGND2

RESET

0.1 µF

VCC

NC

4.7 µF

LMS3655

BIAS

AGND

3Ω

0.1 µF

FB

FPWM

EN

22 pF

10.2 kΩ

49.9 kΩ

CBOOT

470 nF

VOUT = 6 V

SW

SYNC

L1 = 10 µH

1 X 67 µF

1 X 120 µF

ESR = 25 mΩ

Figure 9-30. 6-V Output Power Supply

9.2.4.1 Design Requirements

The application highlighted in this section is for a typical 6-V system but can be used as a basis for the

implementation of the adjustable version of the LMS36x5-Q1 for other output voltages as well. The input

voltages are here for illustration purposes only. See Section 7.6 for minimum operating input voltage.

Table 9-7. Example Requirements for 6-V Application

DESIGN PARAMETER

EXAMPLE VALUE

8-V to 18-V steady-state

0 A to 5.5 A

Input voltage range

Output current

Switching Frequency at 0-A load

Current Consumption at 0-A load

Synchronization

> 250 kHz preferred

Not critical

No

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9.2.4.2 Detailed Design Procedure

•

BIAS is connected to the output. This example assumes that inductive shorts are a risk for this application so

a 3-Ω resistor is added between BIAS and the output. A 0.1-µF capacitor is added close to the BIAS pin.

FB is connected to the output through a voltage divider in order to create a voltage of 1 V at the FB pin

when the output is at 6 V. A 22-pF capacitance is added in parallel with the top feedback resistor in order

to improve transient behavior. BIAS and FB are connected to the output through separate traces. This is

important to reduce noise and achieve good performances. See Section 11.1 for more details on the proper

layout method.

•

SYNC is connected to ground directly as there is no need for this function in this application.

EN is toggled by an external device (like an MCU for example). A pulldown resistor is placed to ensure the

part does not turn on if the external source is not driving the pin (Hi-Z condition).

FPWM is connected to VIN. This causes the device to operate in FPWM mode. To prevent frequency

foldback behavior at low duty cycles, provide a 200mA load. In this mode, the device remains in CCM

operation regardless of the output current and is ensured to be within the boundaries set by F_SW. The

drawback is that the efficiency is not optimized for light loads. See Section 8.4 for more details.

A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin. This ensure stable operation

of the internal LDO.

RESET is not used in this example so the pin has been left floating. Other possible connections can be seen

in the previous typical applications and in Section 8.3.1.

Power components (input capacitor, output capacitor, and inductor) selection can be found here in Section

9.2.1.2.2.

•

9.2.4.3 Application Curves

The following characteristics apply only to the circuit of Figure 9-30. These parameters are not tested and

represent typical performance only. Unless otherwise stated, the following conditions apply: V_IN= 12 V, T_A=

25°C.

V_OUT= 6 V (ADJ part)

FPWM

I_OUT= 0 A

V_OUT= 6 V (ADJ part)

FPWM

I_OUT= 0 A

Figure 9-31. Start-Up Waveform

Figure 9-32. Start-Up Waveform (EN Tied to VIN)

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FPWM

V_OUT= 6 V (ADJ)

I_OUT= 0 A to 3.5 A

L = 10 µH,

C_OUT= 190 µF

T_R= T_F= 1 µs

Figure 9-33. Load Transient

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9.3 Do's and Don't's

•

Don't: Exceed the Section 7.1.

Don't: Exceed the Section 7.3.

Don't: Allow the EN, FPWM or SYNC input to float.

Don't: Allow the output voltage to exceed the input voltage, nor go below ground.

Don't: Use the thermal data given in the Section 7.4 table to design your application.

Do: Follow all of the guidelines and/or suggestions found in this data sheet before committing a design

to production. TI Application Engineers are ready to help critique designs and PCB layouts to help ensure

successful projects.

•

Do: Refer to the helpful documents found in Section 12.2.1.

10 Power Supply Recommendations

The characteristics of the input supply must be compatible with the Section 7.1 and Section 7.3 found in this

data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded

regulator. The average input current can be estimated with Equation 6:

V_OUT∂I_OUT

I_IN=

V ∂ h

IN

(6)

where

•

η is the efficiency

If the regulator is connected to the input supply through long wires or PCB traces, special care is required to

achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse

effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR ceramic input

capacitors, can form an under-damped resonant circuit. This circuit may cause overvoltage transients at the VIN

pin, each time the input supply is cycled on and off. The parasitic resistance causes the voltage at the VIN pin to

dip when the load on the regulator is switched on or exhibits a transient. If the regulator is operating close to the

minimum input voltage, this dip may cause the device to shut down or reset. The best way to solve these kinds

of issues is to reduce the distance from the input supply to the regulator or use an aluminum or tantalum input

capacitor in parallel with the ceramics. The moderate ESR of these types of capacitors helps to damp the input

resonant circuit and reduce any voltage overshoots. A value in the range of 20 µF to 100 µF is usually sufficient

to provide input damping and help to hold the input voltage steady during large load transients.

Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to

instability, as well as some of the effects mentioned above, unless it is designed carefully. LP3913 Power

Management IC for Flash Memory Based Portable Media Players (SNVA489) provides helpful suggestions when

designing an input filter for any switching regulator.

In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device

has a snap-back V-I characteristic (thyristor type). The use of a device with this type of characteristic is not

recommend. When the TVS fires, the clamping voltage drops to a very low value. If this holding voltage is less

than the output voltage of the regulator, the output capacitors are discharged through the regulator back to the

input. This uncontrolled current flow could damage the regulator.

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11 Layout

11.1 Layout Guidelines

The PCB layout of a DC-DC converter is critical for optimal performance of the application. For a buck converter

the input loop formed by the input capacitors and power grounds are very critical. The input loop carries fast

transient currents that cause larger transient voltages when reacting with a parasitic loop inductance. The IC

uses two input loops in parallel IN1 and IN2 as shown in Figure 11-1 that cuts the parasitic input inductance in

half. To get the minimum input loop area two small high frequency capacitors CIN1 and CIN2 are placed as close

as possible.

To further reduce inductance, an input current return path should be placed underneath the loops IN1 and IN2.

The closest metal plane is MID1 Layer2, and there is a solid copper plane placed right under the IN1 and

IN2 loop the parasitic loop inductance is minimized. Connecting this MID1 Layer2 plane to GND provides a

nice bridge connection between GND1 and GND2 as well. Minimizing the parasitic input loop inductance will

minimize switch node ringing and EMI.

The output current loop can be optimized as well by using two ceramic output caps COUT1 and COUT2, one on

each side. They form two parallel ground return paths OUT1 from COUT1 back to the low-side FET PGND1 pins

5, 6, 7, 8, and a second symmetric ground return path OUT2 from COUT2 back to low-side FET PGND2 pins 10,

11, 12, and 13. Having two parallel ground return paths yield reduced ground bouncing and reduced sensitivity of

surrounding circuits.

Figure 11-1. Layout of the Power Components and Current Flow

Providing adequate thermal paths to dissipate heat is critical for operation at full current. The recommended

method for heat dissipation is to use large solid 2-oz copper planes well connected to the power pins VIN1,

VIN2, GND1, and GND2 which transfer the heat out of the IC over the TOP Layer1 copper planes. It is important

to leave the TOP Layer1 copper planes as unbroken as possible so that heat is not trapped near the IC. The

heat flow can be further optimized by thermally connecting the TOP Layer1 plane to large BOTTOM Layer 4 2-oz

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copper planes with vias. MID2 Layer3 is then open for all other signal routing. A fully filled or solid BOTTOM

Layer4 ground plane without any interruptions or ground splitting is beneficial for EMI as well. Most important for

low EMI is to use the smallest possible switch node copper area. The switch node including the C_BOOTcap has

the largest dV/dt signal causing common-mode noise coupling. Using any kind of grounded shield around the

switch node shortens and reduces this e-field.

All these DC-DC converter descriptions can be transformed into layout guidelines:

1. Place two 0.047-µF, 50-V high frequency input capacitors C_IN1and C_IN2as close as possible to the VIN1,

VIN2, PGND1, PGND2 pins to minimize switch node ringing.

2. Place bypass capacitors for VCC and BIAS close to their respective pins. Make sure AGND pin sees the

C_VCCand C_BIAScapacitors first before a connection to PGND.

3. Place C_BOOTcapacitor with smallest parasitic loop. Shielding the C_BOOTcapacitor and switch node has

the biggest impact to reduce common-mode noise. Placing a small R_BOOTresistor (less than 3 Ω is

recommended) in series to C_BOOTslows down the dV/dt of the switch node and reduce EMI.

4. Place the feedback resistor divider for adjustable parts as close as possible to the FB pin and to AGND pin

of the device. Use a dedicated feedback trace, and route away from switch node and C_BOOTcapacitor to

avoid any cross coupling into sensitive analog feedback.

5. Use a dedicated BIAS trace to avoid noise into feedback trace.

6. Use a 3-Ω to 5-Ω resistor between the output and BIAS if the load is far from the output of the converter or

inductive shorts on the output are possible.

7. Use well connected large 2-oz. TOP and BOTTOM copper planes for all power pins VIN1/2 and PGND1/2.

8. Minimize switch node and C_BOOTarea for lowest EMI common mode noise.

9. Place input and output wires on the same side of the PCB using an EMI filter and away from the switch node

for lowest EMI.

The resources in Section 12 provide additional important guidelines.

11.2 Layout Example

This example layout is the one used in the LMS36x5-Q1 EVM. It shows the C_INand C_{IN_HF}capacitors placed

symmetrically on either side of the device.

Figure 11-2. Recommended Layout for LMS36x5-Q1

The evaluation module solution size is 17.8 mm by 43.2 mm. This is a typical of an automotive layout, as

pictured in Figure 11-3.

44

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LMS3655-Q1, LMS3635-Q1

SNAS714C – NOVEMBER 2016 – REVISED AUGUST 2021

www.ti.com

Figure 11-3. LMS3655MQEVM Layout

Submit Document Feedback

45

Product Folder Links: LMS3655-Q1 LMS3635-Q1

LMS3655-Q1, LMS3635-Q1

SNAS714C – NOVEMBER 2016 – REVISED AUGUST 2021

www.ti.com

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

12.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMS3635-Q1 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For additional information, see the following:

•

Optimizing Transient Response of Internally Compensated DC-DC Converters With Feedforward Capacitor

(SLVA289)

•

Output Ripple Voltage for Buck Switching Regulator (SLVA630)

AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021)

AN-1229 Simple Switcher® PCB Layout Guidelines (SNVA054)

Constructing Your Power Supply- Layout Considerations (SLUP230)

AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)

Semiconductor and IC Package Thermal Metrics (SPRA953)

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

HotRod^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

is a registered trademark of Texas Instruments.

46

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Product Folder Links: LMS3655-Q1 LMS3635-Q1

LMS3655-Q1, LMS3635-Q1

SNAS714C – NOVEMBER 2016 – REVISED AUGUST 2021

www.ti.com

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

Submit Document Feedback

47

Product Folder Links: LMS3655-Q1 LMS3635-Q1

LMS3655-Q1, LMS3635-Q1

SNAS714C – NOVEMBER 2016 – REVISED AUGUST 2021

www.ti.com

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

48

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Product Folder Links: LMS3655-Q1 LMS3635-Q1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMS3635LQURNLRQ1

VQFN-

HR

RNL

22

3000

330.0

12.4

4.3

5.3

1.3

8.0

12.0

Q1

LMS3635MQURNLRQ1 VQFN-

HR

LMS3655MQURNLRQ1 VQFN-

HR

LMS3655NQURNLRQ1 VQFN-

HR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMS3635LQURNLRQ1

LMS3635MQURNLRQ1

LMS3655MQURNLRQ1

LMS3655NQURNLRQ1

VQFN-HR

RNL

22

3000

367.0

38.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RNL 22

5 X 4, 0.5 mm pitch

VQFN-HR - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226989/A

www.ti.com

PACKAGE OUTLINE

RNL0022A

VQFN-HR - 0.9 mm max height

SCALE 2.800

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

5.1

4.9

0.1 MIN

(0.05)

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

0.9

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2

1

0.45

0.35

2X 0.8 0.1

8X 0.5

5X

(0.2) TYP

9

8

10

7

4

11

2X

1.45 0.1

2X

2.175

2.95 0.1

0.25

PKG

14

0.3

0.2

15X

2X

2

2X 0.85

A

0.1

0.05

C A B

C

0.65

0.45

5X

22

17

1

2X 0.575

0.45

0.35

18

0.45

0.35

SYMM

2

0.5

0.3

11X

0.5

0.3

4221861/E 07/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RNL0022A

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

18

SYMM

15X (0.25)

22

12X (0.6)

2X (0.4)

(2.325)

1

17

2X (2)

5X (0.75)

2X (1.425)

SEE SOLDER MASK

DETAILS

3X (0.4)

2X (0.575)

2X (1)

2X (0.4)

0.000 PKG

2X (0.25)

14

(0.295)

4

(

0.2) VIA TYP

NOTE 4

(3.15)

(1.125)

2X (1.65)

2X (1.875)

(2.175)

(1.955)

11

7

4X (0.5)

8

9

(2)

10

(3.4)

6X (3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

(PREFERRED)

4221861/E 07/2019

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNL0022A

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

SYMM

15X (0.25)

5X (0.75)

18

22

12X (0.6)

2X (0.4)

(2.325)

1

2X (2)

17

(R0.05) TYP

2X (1.425)

2X (0.575)

6X

EXPOSED

METAL

7X

EXPOSED

METAL

(1.4)

(0.12)

0.000 PKG

(0.25)

4X ( 0.4)

4

14

(0.71)

(2)

2X (1.445)

(1.54)

4X (0.5)

11

2X (2.175)

2X (2.305)

4X

(0.66)

7

(2.37)

9

10

8

8X (0.4)

4X (0.63)

(2)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PADS 4,8,9,10 & 14

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221861/E 07/2019

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

RNL0022B

VQFN-HR - 0.9 mm max height

SCALE 2.800

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

5.1

4.9

PIN 1 INDEX AREA

0.9

0.8

SEATING PLANE

0.08 C

0.05

0.00

2

0.9

0.7

0.45

0.35

2X

1

5X

(0.2) TYP

9

8

10

8X 0.5

7

4

11

1.55

1.35

2X

3.05

2.85

2X

2.175

0.25

PKG

14

0.3

0.2

0.1

15X

2X

2

2X 0.85

C A B

C

0.65

0.45

5X

22

0.05

17

1

2X 0.575

0.45

0.35

18

0.45

0.35

SYMM

2

0.5

0.3

11X

0.5

0.3

4226904/A 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

RNL0022B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

18

SYMM

15X (0.25)

22

12X (0.6)

2X (0.4)

(2.325)

1

17

2X (2)

5X (0.75)

2X (1.425)

SEE SOLDER MASK

DETAILS

3X (0.4)

2X (0.575)

2X (1)

2X (0.4)

0.000 PKG

2X (0.25)

14

(0.295)

4

(

0.2) VIA TYP

NOTE 4

(3.15)

(1.125)

2X (1.65)

2X (1.875)

(2.175)

(1.955)

11

7

4X (0.5)

8

9

(2)

10

(3.4)

6X (3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

SOLDER MASK DETAILS

(PREFERRED)

4226904/A 07/2021

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RNL0022B

VQFN-HR - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X (0.5)

SYMM

15X (0.25)

5X (0.75)

18

22

12X (0.6)

2X (0.4)

(2.325)

1

2X (2)

17

(R0.05) TYP

2X (1.425)

2X (0.575)

6X

EXPOSED

METAL

7X

EXPOSED

METAL

(1.4)

(0.12)

0.000 PKG

(0.25)

4X ( 0.4)

4

14

(0.71)

(2)

2X (1.445)

(1.54)

4X (0.5)

11

2X (2.175)

2X (2.305)

4X

(0.66)

7

(2.37)

9

10

8

8X (0.4)

4X (0.63)

(2)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

FOR PADS 4,8,9,10 & 14

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4226904/A 07/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMS3655MQRNLTQ1
厂家：	TEXAS INSTRUMENTS
描述：	5.5A、36V 同步、400kHz 降压转换器 \| RNL \| 22 \| -40 to 150 开关转换器
文件：	总61页 (文件大小：3404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMS3655MQRNLTQ1 [TI]

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