LMV324A-Q1 [TI]
LMV321A-Q1, LMV358A-Q1, LMV324A-Q1 Automotive Low-Voltage Rail-to-Rail Output Operational Amplifiers;
| 型号： | LMV324A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMV321A-Q1, LMV358A-Q1, LMV324A-Q1 Automotive Low-Voltage Rail-to-Rail Output Operational Amplifiers |
| 文件： | 总40页 (文件大小：2588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMV321A-Q1, LMV324A-Q1, LMV358A-Q1
SLOSE67B – JUNE 2020 – REVISED OCTOBER 2021
LMV321A-Q1, LMV358A-Q1, LMV324A-Q1 Automotive Low-Voltage Rail-to-Rail Output
Operational Amplifiers
gain stability, an integrated RFI and EMI rejection
filter, and no-phase reversal in overdrive conditions.
1 Features
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C, TA
– Device HBM ESD classification level 2
– Device CDM ESD classification level C6
Low input offset voltage: ±1 mV
Rail-to-rail output
Unity-gain bandwidth: 1 MHz
Low broadband noise: 30 nV/√ Hz
Low input bias current: 10 pA
Low quiescent current: 70 µA/Ch
Unity-gain stable
The LMV3xxA-Q1 family is available in industry-
standard packages such as SOIC, MSOP, SOT-23,
and TSSOP packages.
Device Information(1)
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•
•
•
•
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•
•
•
PART NUMBER
PACKAGE
SOT-23 (5)(2)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
3.91 mm × 4.90 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
4.20mm × 1.90 mm
LMV321A-Q1
SC70 (5)(2)
SOIC (8)
LMV358A-Q1
LMV324A-Q1
VSSOP (8)
SOIC (14)
TSSOP (14)
SOT-23 (14)
Internal RFI and EMI filter
Operational at supply voltages as low as 2.5 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Extended temperature range: –40°C to 125°C
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
(2) Package is for preview only.
2 Applications
•
•
•
•
•
•
•
•
•
Optimized for AEC-Q100 grade 1 applications
Infotainment & Cluster
Passive safety
Body electronics and lighting
HEV/EV inverter and motor control
On-board (OBC) & wireless charger
Powertrain current sensor
Advanced driver assistance systems (ADAS)
Single-supply, low-side, unidirectional current-
sensing circuit
3 Description
Single-Pole, Low-Pass Filter
The LMV3xxA-Q1 family includes single - (LMV321A-
Q1), dual
(LMV324A-Q1) low-voltage (2.5
-
(LMV358A-Q1), and quad-channel
to 5.5 V)
V
automotive operational amplifiers (op amps) with
rail-to-rail output swing capabilities. These op amps
provide a cost-effective solution for space-constrained
applications such as infotainment and lighting where
low-voltage operation and high capacitive-load drive
are required. The capacitive-load drive of the
LMV3xxA-Q1 family is 500 pF, and the resistive open-
loop output impedance makes stabilization easier with
much higher capacitive loads. These op amps are
designed specifically for low-voltage operation (2.5 V
to 5.5 V) with performance specifications similar to the
LMV3xx-Q1 devices.
The robust design of the LMV3xxA-Q1 family
simplifies circuit design. The op amps feature unity-
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV321A-Q1, LMV324A-Q1, LMV358A-Q1
SLOSE67B – JUNE 2020 – REVISED OCTOBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information: LMV321A-Q1............................6
6.5 Thermal Information: LMV358A-Q1............................6
6.6 Thermal Information: LMV324A-Q1............................6
6.7 Electrical Characteristics.............................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 16
9 Power Supply Recommendations................................21
9.1 Input and ESD Protection......................................... 21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Documentation Support.......................................... 23
11.2 Related Links.......................................................... 23
11.3 Receiving Notification of Documentation Updates..23
11.4 Support Resources................................................. 23
11.5 Trademarks............................................................. 23
11.6 Electrostatic Discharge Caution..............................23
11.7 Glossary..................................................................23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2021) to Revision B (October 2021)
Page
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•
•
•
Added LMV321A-Q1 GPN to the data sheet......................................................................................................1
Added SOT-23 (5) and SC70 (5) packages in Device Information table............................................................ 1
Deleted preview note from SOT-23 (14) and TSSOP (14) packages in Device Information table..................... 1
Added LMV321A-Q1 SOT-23 (5), SC70 (5), and LMV321AU-Q1 SOT-23 (5) packages to Pin Configuration
and Functions section.........................................................................................................................................3
Added Thermal Information: LMV321A-Q1 table................................................................................................6
•
Changes from Revision * (June 2020) to Revision A (April 2021)
Page
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•
•
•
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Updated the numbering format for tables, figures and cross-references throughout the document...................1
Deleted preview note from VSSOP (8) package in Device Information table.....................................................1
Removed SOT-23 (8), TSSOP (8), SOT-23 (5), and SC70 (5) packages from Device Information table.......... 1
Removed TSSOP (8) package from Pin Configuration and Functions section.................................................. 3
Added note (4) to differential input voltage in Absolute Maximum Ratings table................................................5
Added thermal information for DGK package.....................................................................................................6
Added thermal information for DYY package..................................................................................................... 6
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5 Pin Configuration and Functions
OUT
1
2
3
5
4
V+
V-
+IN
-IN
Figure 5-1. LMV321A-Q1 DBV Package 5-Pin SOT-23 Top View
+IN
V-
1
2
3
5
4
V+
-IN
OUT
Figure 5-2. LMV321A-Q1 DCK, LMV321AU-Q1 DBV Package 5-Pin SC70, SOT-23 Top View
Table 5-1. Pin Functions: LMV321A-Q1
PIN
I/O
DESCRIPTION
NAME
–IN
DBV
DCK, DBV (U)
4
3
1
2
5
3
1
4
2
5
I
Inverting input
Noninverting input
Output
+IN
I
OUT
V–
O
—
—
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
OUT A
1
2
3
4
8
7
6
5
V+
-IN A
+IN A
V-
OUT B
-IN B
+IN B
Figure 5-3. LMV358A-Q1 D and DGK Packages 8-Pin SOIC and VSSOP Top View
Table 5-2. Pin Functions: LMV358A-Q1
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
8
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OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
A
D
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
Figure 5-4. LMV324A-Q1 D, PW, and DYY Packages 14-Pin SOIC, TSSOP, and SOT-23 Top View
Table 5-3. Pin Functions: LMV324A-Q1
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
3
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
Supply voltage, ([V+] – [V–])
6
(V+) + 0.5
(V+) – (V–) + 0.2
10
Common-mode
Differential(4)
(V–) – 0.5
V
Voltage(2)
Current(2)
Signal input pins
V
–10
–55
–65
mA
Output short-circuit(3)
Operating, TA
Continuous
150
°C
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
(4) Differential input voltages greater than 0.5 V applied continuously can result in a shift to the input offset voltage and quiescent current
above the maximum specifications of these parameters. The magnitude of this effect increases as the ambient operating temperature
rises.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002 HBM ESD Classification
Level 2(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011 CDM ESD
Classification Level C5
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 Specification
6.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
VS
TA
Supply voltage
2.5
Specified temperature
–40
125
°C
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6.4 Thermal Information: LMV321A-Q1
LMV321A-Q1
DBV (SOT-23)
THERMAL METRIC(1)
DCK (SC70)
5 PINS
TBD
UNIT
5 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
TBD
TBD
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
TBD
ψJB
TBD
RθJC(bot)
TBD
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.5 Thermal Information: LMV358A-Q1
LMV358A-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
151.9
92.0
DGK (VSSOP)
8 PINS
196.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
86.2
95.4
118.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
40.2
23.2
ψJB
94.7
116.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
6.6 Thermal Information: LMV324A-Q1
LMV324A-Q1
THERMAL METRIC(1)
D (SOIC)
14 PINS
115.1
71.2
PW (TSSOP)
14 PINS
135.3
DYY (SOT-23)
14 PINS
154.3
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
63.5
86.8
RθJB
ψJT
Junction-to-board thermal resistance
71.1
78.4
67.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.6
13.6
10.1
ψJB
70.7
77.9
67.5
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6.7 Electrical Characteristics
For VS = (V+) – (V–) = 2.5 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Vs = 5 V
±1
±4
±5
VOS
Input offset voltage
mV
Vs = 5 V, TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT
PSRR
VOS vs temperature
±1
µV/°C
dB
Power-supply rejection ratio
VS = 2.5 to 5.5 V, VCM = (V–)
78
100
INPUT VOLTAGE RANGE
Common-mode
voltage range
VCM
No phase reversal, rail-to-rail input
(V–) – 0.1
(V+) – 1
V
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
86
95
77
68
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C
Common-mode
CMRR
dB
rejection ratio
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = –40°C to 125°C
63
VS = 2.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = –40°C to 125°C
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
Vs = 5 V
±10
±3
pA
pA
IOS
NOISE
Input voltage noise
(peak-to-peak)
En
ƒ = 0.1 Hz to 10 Hz, Vs = 5 V
5.1
µVPP
ƒ = 1 kHz, Vs = 5 V
ƒ = 10 kHz, Vs = 5 V
ƒ = 1 kHz, Vs = 5 V
33
30
25
en
in
Input voltage noise density
nV/√ Hz
fA/√ Hz
Input current noise density
INPUT CAPACITANCE
CID
CIC
Differential
1.5
5
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ
VS = 2.5 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ
VS = 2.5 V, (V–) + 0.1 V < VO < (V+) – 0.1 V, RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ
100
115
98
AOL
Open-loop voltage gain
dB
112
128
FREQUENCY RESPONSE
GBW
φm
Gain-bandwidth product
Vs = 5 V
1
76
1.7
3
MHz
°
Phase margin
Slew rate
VS = 5.5 V, G = 1
SR
Vs = 5 V
V/µs
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
To 0.01%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
VS = 5 V, VIN × gain > VS
tS
Settling time
µs
µs
4
tOR
Overload recovery time
0.9
Total harmonic distortion
+ noise
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz,
80-kHz measurement BW
THD+N
OUTPUT
0.005%
VS = 5.5 V, RL = 10 kΩ
VS = 5.5 V, RL = 2 kΩ
Vs = 5.5 V
20
40
50
75
Voltage output swing
from supply rails
VO
mV
ISC
ZO
Short-circuit current
±40
1200
mA
Ω
Open-loop output impedance
Vs = 5 V, f = 1 MHz
POWER SUPPLY
VS
Specified voltage range
2.5 (±1.25)
5.5 (±2.75)
125
V
IO = 0 mA, VS = 5.5 V
70
50
IQ
Quiescent current per amplifier
Power-on time
µA
µs
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
VS = 0 V to 5 V, to 90% IQ level
150
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6.8 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
6
4
3.5
3
IB-
IB+
IOS
IB-
IB+
IOS
2.5
2
2
1.5
1
0
0.5
0
-2
-4
-6
-8
-10
-0.5
-1
-1.5
-2
-2.5
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D007
D006
Figure 6-2. IB and IOS vs Common-Mode Voltage
Figure 6-1. IB and IOS vs Temperature
100
80
60
40
20
0
120
160
140
120
100
80
100
80
60
40
20
0
60
40
Gain
Phase
20
VS = 5.5 V
VS = 2.5 V
-20
0
-40
1k
10k
100k
Frequency (Hz)
1M
-20
0
20
40
60
80
100 120 140
D009
Temperature (èC)
D008
CL = 10 pF
Figure 6-3. Open-Loop Gain vs Temperature
Figure 6-4. Open-Loop Gain and Phase vs Frequency
80
160
140
120
100
80
Gain = -1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
70
60
50
40
30
20
10
0
60
40
20
-10
-20
0
100
1k
10k 100k
Frequency (Hz)
1M
-3
-2
-1 0
Output Voltage (V)
1
2
3
D011
D010
Figure 6-5. Open-Loop Gain vs Output Voltage
CL = 10 pF
Figure 6-6. Closed-Loop Gain vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
3
2.5
2
120
100
80
60
40
20
0
PSRR+
PSRR-
1.5
1
125°C
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
25°C
-40°C
-1.5
-2
125°C
-2.5
-3
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
100
1k
10k
Frequency (Hz)
100k
1M
D012
D013
Figure 6-7. Output Voltage vs Output Current (Claw)
Figure 6-8. PSRR vs Frequency
120
120
100
80
60
40
20
0
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D014
D015
Figure 6-10. CMRR vs Frequency
VS = 1.8 V to 5.5 V
Figure 6-9. DC PSRR vs Temperature
2.5 V
Time (1 s/div)
D017
Figure 6-12. 0.1 Hz to 10 Hz Integrated Voltage Noise
VCM = (V–) – 0.1 V to (V+) – 1.4 V
Figure 6-11. DC CMRR vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-50
120
100
80
60
40
20
0
-60
-70
-80
-90
RL = 2K
RL = 10K
-100
10
100
1k
Frequency (Hz)
10k
100k
100
1k
Frequency (Hz)
10k
D018
D019
Figure 6-13. Input Voltage Noise Spectral Density
VS = 5.5 V, VCM = 2.5 V, G = 1, BW = 80 kHz, VOUT = 0.5
VRMS
Figure 6-14. THD + N vs Frequency
0
70
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
60
50
40
30
20
10
0
-20
-40
-60
-80
-100
0.001
0.01
0.1
Amplitude (VRMS
1
2
1.5
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
)
D020
D021
Figure 6-16. Quiescent Current vs Supply Voltage
VS = 5.5 V, VCM = 2.5 V, f = 1 kHz, G = 1, BW = 80 kHz
Figure 6-15. THD + N vs Amplitude
70
60
50
40
30
20
10
0
2000
1800
1600
1400
1200
1000
800
600
400
200
0
1k
10k
100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40
60
80
100 120 140
D023
Temperature (èC)
D022
Figure 6-18. Open-Loop Output Impedance vs Frequency
Figure 6-17. Quiescent Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
Overshoot (+)
Overshoot (–)
0
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D024
D025
G = 1, VIN = 100 mVpp
G = –1, VIN = 100 mVpp
Figure 6-19. Small Signal Overshoot vs Capacitive Load
Figure 6-20. Small Signal Overshoot vs Capacitive Load
90
80
70
60
50
40
30
20
10
0
VOUT
VIN
Time (100 ms/div)
0
200
400 600
Capacitance Load (pF)
800
1000
D027
D026
G = 1, VIN = 6.5 VPP
Figure 6-21. Phase Margin vs Capacitive Load
Figure 6-22. No Phase Reversal
VOUT
VIN
VOUT
VIN
Time (20 ms/div)
Time (10 ms/div)
D028
D029
G = –10, VIN = 600 mVPP
G = 1, VIN = 100 mVPP, CL = 10 pF
Figure 6-23. Overload Recovery
Figure 6-24. Small-Signal Step Response
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
VOUT
VIN
Time (10 ms/div)
Time (1 μs/div)
D030
D031
G = 1, VIN = 4 VPP, CL = 10 pF
G = 1, CL = 100 pF, 2-V step
Figure 6-25. Large-Signal Step Response
Figure 6-26. Large-Signal Settling Time (Negative)
80
60
40
20
0
-20
-40
-60
-80
Sinking
Sourcing
Time (1 ms/div)
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D032
D033
G = 1, CL = 100 pF, 2-V step
Figure 6-28. Short-Circuit Current vs Temperature
Figure 6-27. Large-Signal Settling Time (Positive)
6
140
VS = 5.5 V
120
100
80
60
40
20
0
5
4
3
2
1
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
10M
100M
Frequency (Hz)
1G
10G
D034
D035
Figure 6-29. Maximum Output Voltage vs Frequency
Figure 6-30. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
0
-20
-40
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
D036
Figure 6-31. Channel Separation
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7 Detailed Description
7.1 Overview
The LMV3xxA-Q1 is a family of low-power, rail-to-rail output op amps. These devices operate from 2.5 V to
5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input
common-mode voltage range includes the negative rail and allows the LMV3xxA-Q1 family to be used in
many single-supply applications. Rail-to-rail output swing significantly increases dynamic range, especially in
low-supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Operating Voltage
The LMV3xxA-Q1 family of op amps are for operation from 2.5 V to 5.5 V. In addition, many specifications
such as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to
125°C. Parameters that vary significantly with operating voltages or temperature are shown in the Typical
Characteristics section.
7.3.2 Input Common Mode Range
The input common-mode voltage range of the LMV3xxA-Q1 family extends 100 mV beyond the negative supply
rail and within 1 V below the positive rail for the full supply voltage range of 2.5 V to 5.5 V. This performance
is achieved with a P-channel differential pair, as shown in the Functional Block Diagram. Additionally, a
complementary N-channel differential pair has been included in parallel to eliminate issues with phase reversal
that are common with previous generations of op amps. However, the N-channel pair is not optimized for
operation. TI recommends limiting any voltages applied at the inputs to less than VCC – 1 V to ensure that the op
amp conforms to the specifications detailed in the Electrical Characteristics table.
7.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the LMV3xxA-Q1 family delivers a robust output
drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
7.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the LMV3xxA-Q1 family is approximately 850 ns.
7.4 Device Functional Modes
The LMV3xxA-Q1 family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 2.5 V (±1.25 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LMV3xxA-Q1 family of low-power, rail-to-rail output operational amplifiers is specifically designed for
portable applications. The devices operate from 2.5 V to 5.5 V, are unity-gain stable, and are suitable for a
wide range of general-purpose applications. The class AB output stage is capable of driving less than or equal
to 10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes the
negative rail, and allows the LMV3xxA-Q1 devices to be used in many single-supply applications.
8.2 Typical Application
8.2.1 LMV3xxA-Q1 Low-Side, Current Sensing Application
Figure 8-1 shows the LMV3xxA-Q1 configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5V
+
LMV358A
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
57.6 kΩ
Þ
RG
1.2 kΩ
Figure 8-1. LMV3xxA-Q1 in a Low-Side, Current-Sensing Application
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8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 8-1 is given in Equation 1.
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the LMV3xxA-Q1 to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by
the LMV3xxA-Q1 to produce the necessary output voltage is calculated using Equation 3.
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the LMV3xxA-Q1 to 49 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 8-2 shows the
measured transfer function of the circuit shown in Figure 8-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
8.2.1.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
Figure 8-2. Low-Side, Current-Sense Transfer Function
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8.2.2 Single-Supply Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through
the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 8-3 is
an example of a single-supply photodiode amplifier circuit using the LMV358A-Q1.
+3.3 V
R1
11.5 kΩ
10 pF
CF
VREF
R2
357 Ω
RF
309 kΩ
+3.3 V
œ
LMV358A
VOUT
+
VREF
CPD
IIN
0-10 µA
RL
10 kꢀ
47 pF
Figure 8-3. Single-Supply Photodiode Amplifier Circuit
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8.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Supply voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
8.2.2.2 Detailed Design Procedure
The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF
)
is defined in Equation 5.
VOUT = IIN ìRF + VREF
(5)
(6)
Where:
≈
∆
«
’
÷
R1 ìR2
R1 + R2 ◊
VREF = V ì
+
Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.
VREF
0.1 V
3.3 V
=
= 0.0303
V+
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.
VOUT - VREF
3.2 V - 0.1 V
10 mA
kV
A
RF =
=
= 310
ö 309 kW
I
IN
(8)
Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using
Equation 9.
1
1
CF =
=
= 10.3 pF ö 10 pF
2ì pìRF ì f-3dB 2ì pì309 kWì50 kHz
(9)
The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the
capacitance on the INx– pin of the LMV358A-Q1 which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10
shows.
C
= CPD + CCM + CD = 47 pF+ 5 pF +1pF = 53 pF
IN
(10)
The minimum op amp bandwidth is calculated in Equation 11.
CIN + CF
f=BGW
í
í 324 kHz
2
2ì pìRF ì CF
(11)
The 1-MHz bandwidth of the LMV3xxA-Q1 meets the minimum bandwidth requirement and remains stable in this
application configuration.
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8.2.2.3 Application Curves
The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 8-4. The
measured performance of the photodiode amplifier circuit is shown in Figure 8-5.
120
100
80
3
2.5
2
1.5
1
60
0.5
0
40
10
100
1k 10k
Frequency (Hz)
100k
1M
0
2E-6
4E-6 6E-6
Input Current (A)
8E-6
1E-5
D001
D002
Figure 8-4. Photodiode Amplifier Circuit AC Gain
Results
Figure 8-5. Photodiode Amplifier Circuit DC
Results
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9 Power Supply Recommendations
The LMV3xxA-Q1 family is specified for operation from 2.5 V to 5.5 V (±1.25 V to ±2.75 V); many specifications
apply from –40°C to 125°C. The Typical Characteristics section presents parameters that may exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
9.1 Input and ESD Protection
The LMV3xxA-Q1 family incorporates internal ESD protection circuits on all pins. For input and output pins,
this protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 9-1 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 9-1. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible, as shown in Figure 10-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
Figure 10-1. Schematic Representation for Figure 10-2
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
VIN 1
GND
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
Figure 10-2. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 11-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
LMV321A-Q1
LMV358A-Q1
LMV324A-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV324AQDRQ1
LMV324AQDYYRQ1
LMV324AQPWRQ1
LMV358AQDGKRQ1
LMV358AQDRQ1
ACTIVE
SOIC
D
14
14
14
8
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LM324Q
ACTIVE SOT-23-THIN
DYY
PW
DGK
D
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI
LM324Q
LM324A
27FT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
VSSOP
SOIC
8
L358AQ
PLMV324AQPWRQ1
TSSOP
PW
14
2000
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV324A-Q1, LMV358A-Q1 :
Catalog : LMV324A, LMV358A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV324AQDRQ1
SOIC
D
14
14
2500
3000
330.0
330.0
16.4
12.4
6.5
4.8
9.0
3.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q3
LMV324AQDYYRQ1
SOT-
DYY
23-THIN
LMV358AQDGKRQ1
LMV358AQDRQ1
VSSOP
SOIC
DGK
D
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
6.4
3.4
5.2
1.4
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV324AQDRQ1
LMV324AQDYYRQ1
LMV358AQDGKRQ1
LMV358AQDRQ1
SOIC
SOT-23-THIN
VSSOP
D
14
14
8
2500
3000
2500
2500
853.0
336.6
366.0
853.0
449.0
336.6
364.0
449.0
35.0
31.8
50.0
35.0
DYY
DGK
D
SOIC
8
Pack Materials-Page 2
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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