LMV358AIDDFR [TI]
双路、5.5V、1MHz、4mV 失调电压、RRO 运算放大器 | DDF | 8 | -40 to 125;型号: | LMV358AIDDFR |
厂家: | TEXAS INSTRUMENTS |
描述: | 双路、5.5V、1MHz、4mV 失调电压、RRO 运算放大器 | DDF | 8 | -40 to 125 放大器 运算放大器 |
文件: | 总52页 (文件大小:3100K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LMV321A, LMV358A, LMV324A
ZHCSH88H –DECEMBER 2017 –REVISED APRIL 2023
LMV3xxA 低电压轨到轨输出运算放大器
1 特性
3 说明
• 低输入失调电压:±1mV
• 轨至轨输出
• 单位增益带宽:1MHz
LMV3xxA 系列包括单通道 - (LMV321A)、 双通道 -
(LMV358A) 以及四通道 (LMV324A) 低电压(2.5V 至
5.5V)运算放大器,具有轨至轨输出摆幅能力。这些
运算放大器为空间受限、需要低压运行和高容性负载驱
动的应用(例如大型电器、烟雾探测器和个人电子产
品)提供了具有经济效益的解决方案。LMV3xxA 系列
的电容负载驱动为500pF ,而电阻式开环输出阻抗使
得在电容负载更高的情况下更易实现稳定。这些运算放
大器专为低工作电压(2.5V 至 5.5V)而设计,性能规格
类似于LMV3xx 器件。
• 低宽带噪声:30nV/√Hz
• 低输入偏置电流:10pA
• 低静态电流:70µA/通道
• 单位增益稳定
• 内置RFI 和EMI 滤波器
• 可在电源电压低至2.5V 的情况下运行
• 由于具有电阻式开环输出阻抗,因此在较高的电容
性负载下更易稳定
LMV3xxA 系列的稳健设计简化了电路设计。这些运算
放大器具有单位增益稳定性,集成了 RFI 和 EMI 抑制
滤波器,并且在过驱情况下不会出现相位反转。
• 工作温度范围:–40°C 至125°C
2 应用
• 烟雾探测器
• 运动检测器
• 可穿戴设备
• 大型和小型家用电器
• EPOS
• 条形码扫描仪
• 传感器信号调节
• 电源模块
• 个人电子产品
• 有源滤波器
LMV3xxA 系列采用行业标准封装( 如 SOIC 、
MSOP、SOT-23 和TSSOP 封装)。
封装信息
封装(1)
封装尺寸(标称值)
器件型号
LMV321A
DBV(SOT-23,5) 1.60mm × 2.90mm
DCK(SC70,5)
D(SOIC,8)
1.25mm × 2.00mm
3.91mm × 4.90mm
DGK(VSSOP,8) 3.00mm x 3.00mm
PW(TSSOP,8) 3.00mm × 4.40mm
DDF(SOT-23,8) 3.00mm × 3.00mm
LMV358A
LMV324A
• HVAC:暖通空调
• 电机控制:交流感应
• 低侧电流检测
D(SOIC,14)
8.65mm × 3.91mm
DYY(SOT-23,
14)
4.20mm × 1.90mm
PW(TSSOP,14) 4.40mm × 5.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
单极低通滤波器
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBOS923
LMV321A, LMV358A, LMV324A
ZHCSH88H –DECEMBER 2017 –REVISED APRIL 2023
www.ti.com.cn
内容
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 修订历史记录.....................................................................2
5 引脚功能和配置................................................................. 3
6 规格................................................................................... 5
6.1 绝对最大额定值...........................................................5
6.2 ESD 额定值.................................................................5
6.3 建议运行条件.............................................................. 5
6.4 热性能信息:LMV321A...............................................6
6.5 热性能信息:LMV358A...............................................6
6.6 热性能信息:LMV324A...............................................6
6.7 电气特性......................................................................7
6.8 典型特性......................................................................8
7 详细说明.......................................................................... 14
7.1 概述...........................................................................14
7.2 功能方框图................................................................14
7.3 特性说明....................................................................15
7.4 器件功能模式............................................................ 15
8 应用和实现.......................................................................16
8.1 应用信息....................................................................16
8.2 典型应用....................................................................16
9 电源相关建议...................................................................21
9.1 输入和ESD 保护.......................................................21
10 布局............................................................................... 22
10.1 布局指南..................................................................22
10.2 布局示例..................................................................22
11 器件和文档支持..............................................................23
11.1 文档支持..................................................................23
11.2 接收文档更新通知................................................... 23
11.3 支持资源..................................................................23
11.4 商标.........................................................................23
11.5 静电放电警告...........................................................23
11.6 术语表..................................................................... 23
12 机械、封装和可订购信息...............................................23
4 修订历史记录
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision G (February 2022) to Revision H (April 2023)
Page
• 将电气特性表的测试条件从“VS = (V+) –(V–) = 2.5V 至5.5V(±0.9V 至±2.75V)”更新为“VS = (V+) –
(V–) = 2.5V 至5.5V(±1.25V 至±2.75V)”....................................................................................................7
• 更新了典型特性部分.......................................................................................................................................... 8
Changes from Revision F (January 2020) to Revision G (February 2022)
Page
• 更新了整个文档中的表、图和交叉参考的编号格式............................................................................................ 1
• 向说明 部分新增了 SOT-23 (DYY) 封装............................................................................................................. 1
• 向引脚配置和功能部分中添加了SOT-23 (DYY) 封装信息..................................................................................3
• 向热性能信息:LMV324A 中添加了SOT-23 (DYY) 封装.................................................................................. 6
Changes from Revision E (September 2019) to Revision F (January 2020)
Page
• 向引脚配置和功能部分中添加了SOT-23 (U) 封装信息......................................................................................3
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOS923
2
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LMV321A, LMV358A, LMV324A
ZHCSH88H –DECEMBER 2017 –REVISED APRIL 2023
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5 引脚功能和配置
OUT
+IN
V-
V-
+IN
-IN
图5-2. LMV321A DCK 封装,5 引脚SOT-23、SC70
(顶视图)
图5-1. LMV321A DBV 封装,5 引脚SOT-23(顶视
图)
表5-1. 引脚功能:LMV321A
引脚
类型(1)
说明
DCK,DBV
DBV
名称
(U)
4
3
1
2
5
3
1
4
2
5
I
I
–IN
+IN
OUT
V–
V+
反相输入
同相输入
输出
O
负(最低)电源或接地(对于单电源供电)
正(最高)电源
—
—
(1) I = 输入,O = 输出
OUT A
1
2
3
4
8
7
6
5
V+
-IN A
+IN A
V-
OUT B
-IN B
+IN B
图5-3. LMV358A D、DDF、DGK 或PW 封装, 8 引脚SOIC、VSSOP 或TSSOP(顶视图)
表5-2. 引脚功能:LMV358A
引脚
类型(1)
说明
名称
编号
2
3
6
5
1
7
4
8
I
I
–IN A
+IN A
反相输入,通道A
同相输入,通道A
反相输入,通道B
同相输入,通道B
输出,通道A
I
–IN B
+IN B
OUT A
OUT B
V–
I
O
O
—
—
输出,通道B
负(最低)电源或接地(对于单电源供电)
正(最高)电源
V+
(1) I = 输入,O = 输出
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English Data Sheet: SBOS923
LMV321A, LMV358A, LMV324A
ZHCSH88H –DECEMBER 2017 –REVISED APRIL 2023
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OUT A
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
A
D
-IN A
+IN A
V+
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
图5-4. LMV324A D、DYY、PW 封装, 14 引脚SOIC、SOT-23、TSSOP (顶视图)
表5-3. 引脚功能:LMV324A
引脚
类型(1)
说明
名称
编号
2
I
I
–IN A
+IN A
反相输入,通道A
同相输入,通道A
反相输入,通道B
同相输入,通道B
反相输入,通道C
同相输入,通道C
反相输入,通道D
同相输入,通道D
输出,通道A
3
6
I
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
输出,通道B
8
输出,通道C
14
11
4
输出,通道D
负(最低)电源或接地(对于单电源供电)
正(最高)电源
V+
(1) I = 输入,O = 输出
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English Data Sheet: SBOS923
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6 规格
6.1 绝对最大额定值
在工作温度范围内(除非另有说明)(1)
最小值
最大值
单位
0
6
V
电源电压,([V+] –[V–])
(V+) + 0.5
(V+) –(V–) + 0.2
10
V
V
(V–) –0.5
共模
差分
电压(2)
信号输入引脚
电流(2)
-10
-55
-65
mA
输出短路(3)
持续
150
150
150
°C
°C
°C
温度,TA
运行结温,TJ
贮存温度,Tstg
(1) 超出绝对最大额定值下所列的值的应力可能会对器件造成损坏。这些仅仅是压力额定值,并不表示器件在这些条件下以及在建议运行条
件以外的任何其他条件下能够正常运行。长时间处于绝对最大额定条件下可能会影响器件的可靠性。
(2) 输入引脚被二极管钳制至电源轨。摆幅超过电源轨0.5V 的输入信号的电流必须限制在10mA 或者更少。
(3) 对地短路,每个封装对应一个放大器。
6.2 ESD 额定值
值
单位
人体放电模型(HBM),符合ANSI/ESDA/JEDEC JS-001 标准(1)
充电器件模型(CDM),符合JEDEC 规范JESD22-C101(2)
±2000
V(ESD)
V
静电放电
±1000
(1) JEDEC 文档JEP155 指出:500V HBM 时能够在标准ESD 控制流程下安全生产。
(2) JEDEC 文件JEP157 指出:250V CDM 可实现在标准ESD 控制流程下安全生产。
6.3 建议运行条件
在工作温度范围内(除非另有说明)
最小值
2.5
最大值
单位
V
VS
TA
5.5
电源电压
额定温度
-40
125
°C
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English Data Sheet: SBOS923
LMV321A, LMV358A, LMV324A
ZHCSH88H –DECEMBER 2017 –REVISED APRIL 2023
www.ti.com.cn
6.4 热性能信息:LMV321A
LMV321A
DBV (SOT-23)
热指标(1)
DCK (SC70)
5 引脚
239.6
单位
5 引脚
232.8
153.8
100.9
77.2
RθJA
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
RθJC(top)
RθJB
148.5
结至外壳(顶部)热阻
结至电路板热阻
82.3
54.5
ψJT
结至顶部特征参数
结至电路板特征参数
结至外壳(底部)热阻
100.4
81.8
ψJB
RθJC(bot)
不适用
不适用
(1) 有关新旧热性能指标的更多信息,请参阅半导体和IC 封装热指标。
6.5 热性能信息:LMV358A
LMV358A
热指标(1)
D (SOIC)
8 引脚
DGK (VSSOP) PW (TSSOP)
DDF (SOT-23)
8 引脚
单位
8 引脚
8 引脚
RθJA
147.4
201.2
205.8
183.7
°C/W
°C/W
结至环境热阻
Rθ
94.3
85.7
106.7
112.5
结至外壳(顶部)热阻
JC(top)
RθJB
ψJT
89.5
47.3
89
122.9
21.2
133.9
34.4
98.2
18.8
97.6
°C/W
°C/W
°C/W
结至电路板热阻
结至顶部特征参数
结至电路板特征参数
121.4
132.6
ψJB
(1) 有关新旧热性能指标的更多信息,请参阅半导体和IC 封装热指标。
6.6 热性能信息:LMV324A
LMV324A
热指标(1)
D (SOIC)
DYY (SOT-23)
14 引脚
154.3
PW (TSSOP)
8 引脚
148.3
68.1
单位
14 引脚
102.1
56.8
RθJA
RθJC(top)
RθJB
ψJT
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻
86.8
结至外壳(顶部)热阻
结至电路板热阻
58.5
67.9
92.7
20.5
10.1
16.9
结至顶部特征参数
结至电路板特征参数
58.1
67.5
91.8
ψJB
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English Data Sheet: SBOS923
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6.7 电气特性
TA = 25°C 时,VS = (V+) –(V–) = 2.5V 至5.5V(±0.9V 至±2.75V),RL = 10kΩ(连接至VS /2),并且VCM = VOUT
=
VS /2(除非另有说明)
参数
测试条件
最小值
典型值
最大值
单位
失调电压
Vs = 5V
±1
±4
±5
VOS
mV
输入失调电压
OS 温漂
Vs = 5V,TA = –40°C 至125°C
TA = –40°C 至125°C
VS = 2.5 至5.5V,VCM = (V–)
dVOS/dT
±1
µV/°C
dB
V
PSRR
78
100
电源抑制比
输入电压范围
共模
电压范围
VCM
V
无相位反向,轨到轨输入
(V–) –0.1
(V+) –1
VS = 2.5V,(V–) –0.1V < VCM < (V+) –1.4V
TA = –40°C 至125°C
86
95
77
68
VS = 5.5V,(V–) –0.1V < VCM < (V+) –1.4V
TA = –40°C 至125°C
共模
抑制比
CMRR
dB
VS = 5.5V,(V–) –0.1V < VCM < (V+) + 0.1V
TA = –40°C 至125°C
63
VS = 2.5V,(V–) –0.1V < VCM < (V+) + 0.1V
TA = –40°C 至125°C
输入偏置电流
IB
Vs = 5V
±10
±3
pA
pA
输入偏置电流
输入失调电流
IOS
噪声
输入电压噪声
(峰-峰值)
En
5.1
µVPP
ƒ= 0.1Hz 至10Hz,Vs = 5V
33
30
25
ƒ= 1kHz,Vs = 5V
ƒ= 10kHz,Vs = 5V
ƒ= 1kHz,Vs = 5V
en
in
nV/√Hz
fA/√Hz
输入电压噪声密度
输入电流噪声密度
输入电容
CID
1.5
5
pF
pF
差分
共模
CIC
开环增益
100
115
98
VS = 5.5V,(V–) + 0.05V < VO < (V+) –0.05V,RL = 10kΩ
VS = 2.5V,(V–) + 0.04V < VO < (V+) –0.04V,RL = 10kΩ
VS = 2.5V,(V–) + 0.1V < VO < (V+) –0.1V,RL = 2kΩ
VS = 5.5V,(V–) + 0.15V < VO < (V+) –0.15V,RL = 2kΩ
AOL
dB
开环电压增益
112
128
频率响应
GBW
Vs = 5V
1
76
1.7
3
MHz
°
增益带宽积
相位裕度
压摆率
VS = 5.5V,G = 1
φm
SR
Vs = 5V
V/µs
精度达到0.1%,VS = 5V,2V 阶跃,G = +1,CL = 100pF
精度达到0.01%,VS = 5V,2V 阶跃,G = +1,CL = 100pF
VS = 5V,VIN × 增益> VS
tS
µs
µs
趋稳时间
4
tOR
0.9
过载恢复时间
VS = 5.5V,VCM = 2.5V,VO = 1VRMS,G = +1,f = 1kHz,
80kHz 测量BW
总谐波失真
+ 噪声
THD+N
输出
0.005%
20
40
50
75
VS = 5.5V,RL = 10kΩ
VS=5.5V,RL=2kΩ
Vs = 5.5V
相对于电源轨的
电压输出摆幅
VO
mV
ISC
ZO
±40
1200
mA
短路电流
Vs = 5V,f = 1MHz
开环输出阻抗
Ω
电源
VS
2.5 (±1.25)
5.5 (±2.75)
125
V
额定电压范围
IO = 0mA,VS = 5.5V
70
50
IQ
µA
µs
每个放大器的静态电流
加电时间
150
IO = 0mA,VS = 5.5V,TA = –40°C 至125°C
VS = 0V 至5V,精度达到90% IQ 电平
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www.ti.com.cn
6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ(连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得(除非另
有说明)
6
4
3.5
3
IB-
IB+
IOS
IB-
IB+
IOS
2.5
2
2
1.5
1
0
0.5
0
-2
-4
-6
-8
-10
-0.5
-1
-1.5
-2
-2.5
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D007
D006
图6-2. IB 和IOS 与共模电压间的关系
图6-1. IB 和IOS 与温度间的关系
100
80
60
40
20
0
120
100
80
60
40
20
0
160
140
120
100
80
60
40
Gain
Phase
20
VS = 5.5 V
VS = 2.5 V
-20
0
-40
1k
10k
100k
Frequency (Hz)
1M
-20
0
20
40
60
80
100 120 140
D009
Temperature (èC)
D008
CL = 10pF
图6-3. 开环增益与温度间的关系
图6-4. 开环增益和相位与频率间的关系
80
70
60
50
40
30
20
10
0
160
140
120
100
80
Gain = -1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
60
40
20
-10
-20
0
100
1k
10k 100k
Frequency (Hz)
1M
-3
-2
-1 0
Output Voltage (V)
1
2
3
D011
D010
CL = 10pF
图6-5. 开环增益与输出电压间的关系
图6-6. 闭环增益与频率间的关系
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6.8 典型特性(continued)
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ(连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得(除非另
有说明)
3
2.5
2
120
100
80
60
40
20
0
PSRR+
PSRR-
1.5
1
125°C
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
25°C
-40°C
-1.5
-2
125°C
-2.5
-3
100
1k
10k
Frequency (Hz)
100k
1M
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
D013
D012
图6-8. PSRR 与频率间的关系
图6-7. 输出电压与输出电流间的关系(爪形)
120
100
80
60
40
20
0
120
100
80
60
40
20
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D014
D015
图6-10. CMRR 与频率之间的关系
VS = 1.25V 至5.5V
图6-9. 直流PSRR 与温度间的关系
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ(连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得(除非另
有说明)
2.5 V
Time (1 s/div)
D017
图6-12. 0.1Hz 至10Hz 集成电压噪声
VCM = (V–) –0.1V 至(V+) –1.4V
图6-11. 直流CMRR 与温度间的关系
-50
-60
120
100
80
60
40
20
0
-70
-80
-90
RL = 2K
RL = 10K
-100
10
100
1k
Frequency (Hz)
10k
100k
100
1k
Frequency (Hz)
10k
D018
D019
图6-13. 输入电压噪声频谱密度
VS = 5.5V,VCM = 2.5V,G = 1,BW = 80kHz,VOUT
=
0.5VRMS
图6-14. THD+N 与频率间的关系
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ(连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得(除非另
有说明)
0
70
60
50
40
30
20
10
0
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
-20
-40
-60
-80
-100
0.001
0.01
0.1
Amplitude (VRMS
1
2
1.5
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
)
D020
D021
VS = 5.5V,VCM = 2.5V,f = 1kHz,G = 1,BW = 80kHz
图6-15. THD + N 与幅度间的关系
图6-16. 静态电流与电源电压间的关系
70
60
50
40
30
20
10
0
2000
1800
1600
1400
1200
1000
800
600
400
200
0
1k
10k
100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40
60
80
100 120 140
D023
Temperature (èC)
D022
图6-18. 开环输出阻抗与频率间的关系
图6-17. 静态电流与温度间的关系
50
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
Overshoot (+)
Overshoot (–)
0
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D024
D025
G = 1,VIN = 100mVpp
G = –1,VIN = 100mVpp
图6-19. 小信号过冲与容性负载间的关系
图6-20. 小信号过冲与容性负载间的关系
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6.8 典型特性
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ(连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得(除非另
有说明)
90
VOUT
VIN
80
70
60
50
40
30
20
10
0
Time (100 ms/div)
0
200
400 600
Capacitance Load (pF)
800
1000
D027
D026
G = 1,VIN = 6.5VPP
图6-22. 无相位反转
图6-21. 相位裕度与容性负载间的关系
VOUT
VIN
VOUT
VIN
Time (20 ms/div)
Time (10 ms/div)
D028
D029
G = 1,VIN = 100mVPP,CL = 10pF
图6-24. 小信号阶跃响应
G = –10,VIN = 600mVPP
图6-23. 过载恢复
VOUT
VIN
Time (1 μs/div)
Time (10 ms/div)
D031
D030
G = 1,CL = 100pF,2V 阶跃
图6-26. 大信号建立时间(负)
G = 1,VIN = 4VPP,CL = 10pF
图6-25. 大信号阶跃响应
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6.8 典型特性(continued)
在TA = 25°C、V+ = 2.75V、V–= –2.75V、RL = 10kΩ(连接到VS/2、VCM = VS/2 并且VOUT = VS/2 条件下测得(除非另
有说明)
80
60
40
20
0
-20
-40
-60
-80
Sinking
Sourcing
Time (1 ms/div)
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D032
D033
G = 1,CL = 100pF,2V 阶跃
图6-27. 大信号建立时间(正)
图6-28. 短路电流与温度间的关系
6
5
4
3
2
1
0
140
VS = 5.5 V
120
100
80
60
40
20
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
10M
100M
Frequency (Hz)
1G
10G
D034
D035
图6-29. 最大输出电压与频率间的关系
图6-30. 以同相输入为基准的电磁干扰抑制比(EMIRR+) 与频率间的
关系
0
-20
-40
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
D036
图6-31. 通道分离
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7 详细说明
7.1 概述
LMV3xxA 是一系列低功率、轨对轨输出运算放大器。这些器件的工作电压介于 2.5V 至 5.5V 之间,单位增益稳
定,专为广泛的通用应用而设计。输入共模电压范围包括负电源轨,并支持将 LMV3xxA 系列用于许多单电源应
用。轨对轨输出摆动显著增加了动态范围,特别是在低电源应用中,使其适合驱动采样模数转换器(ADC)。
7.2 功能方框图
V+
Reference
Current
VIN+
VIN-
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V-
(Ground)
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7.3 特性说明
7.3.1 工作电压
LMV3xxA 系列运算放大器的工作电压为 2.5V 至 5.5V。此外,输入失调电压、静态电流、失调电流和短路电流等
多种规格适用于-40°C 至125°C 的温度范围。参数随工作电压或温度而显著变化,如节6.8 中所示。
7.3.2 输入共模范围
LMV3xxA 系列的输入共模电压范围超出负极供电轨 100mV,低于正极供电轨 1V,整个供电电压范围为 2.5V 至
5.5V。此性能通过P 沟道差分对实现,如功能方框图中所示。此外,还并联了一个互补的N 沟道差分对,以消除
前几代运算放大器常见的相位反转问题。然而,N 沟道对未针对操作进行优化。TI 建议将施加在输入端的任何电
压限制在小于VCC –1V,以确保运算放大器符合电气特性表中详述的规范。
7.3.3 轨到轨输出
LMV3xxA 系列设计为一种低功耗、低电压运算放大器,可提供强大的输出驱动能力。一个具有共源晶体管的 AB
类输出级可实现完全的轨到轨输出摆幅功能。对于 10kΩ 的阻性负载,无论施加的电源电压是多少,输出摆幅都
在两个电源轨的20 mV 范围内。不同的负载情况会改变放大器在靠近电源轨范围内摆动的能力。
7.3.4 过载恢复
过载恢复定义为运算放大器输出从饱和状态恢复到线性状态所需的时间。当输出电压由于高输入电压或高增益而
超过额定工作电压时,运算放大器的输出器件进入饱和区。器件进入饱和区后,输出器件中的电荷载体需要时间
回到线性状态。当电荷载体回到线性状态时,器件开始以指定的压摆率进行转换。因此,传播延迟(过载情况
下)等于过载恢复时间与转换时间之和。LMV3xxA 系列的过载恢复时间约为850ns。
7.4 器件功能模式
LMV3xxA 系列拥有单功能模式。只要电源电压在 2.5V (±1.25V) 和 5.5V (±2.75V) 之间,这些器件就处于通电状
态。
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8 应用和实现
备注
以下应用部分中的信息不属于 TI 组件规范,TI 不担保其准确性和完整性。TI 的客户应负责确定各元件
是否适用于其应用。客户应验证并测试其设计实现,以确认系统功能。
8.1 应用信息
LMV3xxA 系列低功耗轨对轨输出运算放大器是专为便携式应用而设计的。这些器件的工作电压介于 2.5V 至 5.5V
之间,单位增益稳定,并且适合广泛的通用应用。AB 类输出级能够驱动连接至V+ 和V–之间任一点且小于或等
于10kΩ的负载。输入共模电压范围包括负电源轨,并支持将LMV3xxA 器件用于许多单电源应用。
8.2 典型应用
8.2.1 LMV3xxA 低侧电流感测应用
图8-1 展示了低侧电流感测应用中配置的LMV3xxA。
VBUS
ILOAD
ZLOAD
5V
+
LMV358A
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
57.6 kΩ
Þ
RG
1.2 kΩ
图8-1. 低侧电流感测应用中的LMV3xxA
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8.2.1.1 设计要求
此设计的设计要求如下:
• 负载电流:0A 至1A
• 输出电压:4.9V
• 最大分流电压:100mV
8.2.1.2 详细设计过程
图8-1 中的电路传递函数如方程式1 所示。
V
= I
× R × Gain
SHUNT
(1)
OUT
LOAD
负载电流 (ILOAD) 在分流电阻器 (RSHUNT) 上产生压降。负载电流设置为 0A 至 1A。为了在最大负载电流下保持分
流电压低于100mV,使用方程式2 展示了最大分流电阻。
V
SHUNT_MAX
100 mV
1 A
R
=
=
= 100 mΩ
(2)
SHUNT
I
LOAD_MAX
使用方程式 2 计算出的 RSHUNT 为100mΩ。由ILOAD 和RSHUNT 产生的电压降被 LMV3xxA 放大,以产生大约 0V
到4.9V 的输出电压。使用方程式3 计算LMV3xxA 产生必要输出电压所需的增益。
V
− V
− V
OUT_MAX
OUT_MIN
Gain =
(3)
V
IN_MAX
IN_MIN
使用方程式 3 计算出的所需增益为49V/V,该值由电阻器 RF 和RG 设置。方程式 4 用于调整 RF 和RG 电阻器的
大小,将LMV3xxA 的增益设置为49V/V。
R
F
Gain = 1 +
(4)
R
G
选择RF 为57.6kΩ,RG 为1.2kΩ可提供等于49V/V 的组合。图8-2 展示了图8-1 中所示电路测得的传递函数。
请注意,增益只是反馈和增益电阻器的函数。通过改变电阻器的比率来调整该增益,并且实际电阻器值由设计人
员想要建立的阻抗水平确定。阻抗水平决定了电流损耗、杂散电容的影响以及其他一些行为。并不存在适用于每
个系统的最佳阻抗选择,您必须选择适合您的系统参数的阻抗。
8.2.1.3 应用曲线
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
图8-2. 低侧电流感测传递函数
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8.2.2 单电源光电二极管放大器
光电二极管在许多应用中用于将光信号转换为电信号。通过光电二极管的电流与吸收的光子能量成正比,通常在
几百皮安到几十微安的范围内。跨阻抗配置中的放大器通常用于将低电平光电二极管电流转换为电压信号以在
MCU 中处理。图8-3 中显示的电路是一个使用LMV358A 的单电源光电二极管放大器电路的示例。
+3.3 V
R1
11.5 kΩ
10 pF
CF
VREF
R2
357 Ω
RF
309 kΩ
+3.3 V
œ
LMV358A
VOUT
+
VREF
CPD
IIN
0-10 µA
RL
10 kꢀ
47 pF
图8-3. 单电源光电二极管放大器电路
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8.2.2.1 设计要求
此设计的设计要求如下:
• 电源电压:3.3V
• 输入:0µA 至10µA
• 输出:0.1 V 至3.2 V
• 带宽:50kHz
8.2.2.2 详细设计过程
方程式5 中定义了输出电压(VOUT) 、输入电流(IIN) 和参考电压(VREF) 之间的传递函数。
V
= I × R + V
REF
(5)
(6)
OUT
REF
IN
F
其中:
R
× R
1
1
2
2
V
= V
×
+
R
+ R
通过设置R1 和R2 以满足方程式7 中计算所需的比率,将VREF 设置为100mV 以满足最小输出电压电平。
V
REF
0.1 V
3.3 V
=
= 0.0303
(7)
V
+
满足该比率的最接近电阻比率将R1 设置为11.5kΩ,将R2 设置为357Ω。
可以基于输入电流和期望的输出电压来计算所需的反馈电阻。
V
− V
IN
OUT
REF
3.2 V − 0.1 V
10 µA
kV
A
R
=
=
= 310
≈ 309 kΩ
(8)
(9)
F
I
使用方程式9,基于RF 和所需的–3-dB 带宽(f–3dB) 计算反馈电容器的值。
1
1
C
=
=
= 10.3 pF ≈ 10 pF
F
2 × π × R × f
2 × π × 309 kΩ × 50 kHz
F
−3 dB
此应用所需的最小运算放大器带宽基于RF、CF 的值,以及LMV358A INx–引脚上的电容,该电容等于光电二极
管并联电容(CPD)、共模输入电容(CCM) 和差分输入电容(CD) 之和,如方程式10 所示。
C
= C
+ C
+ C = 47 pF + 5 pF + 1 pF = 53 pF
(10)
IN
PD
CM
D
最小运算放大器带宽在方程式11 中计算。
C
+ C
F
IN
2 × π × R × C
f = BGW ≥
≥ 324 kHz
(11)
2
F
F
LMV3xxA 的1MHz 带宽满足最低带宽要求,并在此应用配置中保持稳定。
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English Data Sheet: SBOS923
LMV321A, LMV358A, LMV324A
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8.2.2.3 应用曲线
光电二极管放大器电路的测量电流到电压传递函数如图 8-4 所示。光电二极管放大器电路的测量性能如图 8-5 所
示。
120
100
80
3
2.5
2
1.5
1
60
0.5
0
40
10
100
1k 10k
Frequency (Hz)
100k
1M
0
2E-6
4E-6 6E-6
Input Current (A)
8E-6
1E-5
D001
D002
图8-4. 光电二极管放大器电路交流增益结果
图8-5. 光电二极管放大器电路直流结果
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9 电源相关建议
LMV3xxA 系列的额定工作电压范围为2.5V 至5.5V(±1.25V 至±2.75V);多种规格适用于 –40°C 至125°C 的
温度范围。节6.8 中介绍了可能会随工作电压或温度而显著变化的参数。
CAUTION
电源电压超过6V 可能会对器件造成永久性损坏;请参阅节6.1。
将 0.1µF 旁路电容器置于电源引脚附近,以减少来自高噪声电源或高阻抗电源的耦合误差。有关旁路电容器放置
的更多详细信息,请参阅节10.1。
9.1 输入和ESD 保护
LMV3xxA 系列在所有引脚上均整合了内部 ESD 保护电路。对于输入和输出引脚,这种保护主要包括输入和电源
引脚之间连接的导流二极管。只要电流不超过 10mA,这些 ESD 保护二极管就能提供电路内输入过驱保护。图
9-1 显示了如何通过将串联输入电阻器添加到被驱动的输入端来限制输入电流。添加的电阻器会增加放大器输入端
的热噪声,在对噪声敏感的应用中,该值必须保持在最低。
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
图9-1. 输入电流保护
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10 布局
10.1 布局指南
为了使器件具有最佳运行性能,请使用良好的印刷电路板(PCB) 布局实践,包括:
• 噪声可以通过电路板的电源连接传播到模拟电路中,并传播到运算放大器本身的电源引脚。旁路电容器用于通
过提供低阻抗接地路径来降低耦合噪声。
– 在每个电源引脚和接地端之间连接低ESR 0.1µF 陶瓷旁路电容器,放置位置尽量靠近器件。从V+ 到接地
端的单个旁路电容器足以满足单电源应用的需求。
• 将电路中模拟和数字部分单独接地是最简单和最有效的噪声抑制方法之一。多层PCB 上的一层或多层通常专
门用于作为接地平面。接地层有助于散热和降低电磁干扰(EMI) 噪声拾取。请小心地对数字接地和模拟接地进
行物理隔离,同时应注意接地电流。
• 为了减少寄生耦合,请让输入走线尽可能远离电源或输出走线。如果这些走线不能保持分开,则以90 度角穿
过敏感走线比平行于噪声走线运行走线要好得多。
• 外部元件的位置应尽量靠近器件,如图10-2 中所示。使RF 和RG 接近反相输入可最大限度地减小寄生电容。
• 尽可能缩短输入走线。切记,输入走线是电路中最敏感的部分。
• 考虑在关键走线周围设定驱动型低阻抗保护环。这样可显著减少附近不同电势下的走线所产生的泄漏电流。
• 为获得最佳性能,建议在组装PCB 板后进行清洗。
• 任何精密集成电路都可能因湿气渗入塑料封装中而出现性能变化。请遵循所有的PCB 水清洁流程,建议将
PCB 组装烘干,以去除清洗时渗入器件封装中的湿气。大多数情形下,清洗后在85°C 下低温烘干30 分钟即
可。
10.2 布局示例
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
图10-1. 原理图表示
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
RG
VIN 1
GND
RG
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
图10-2. 布局示例
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档:
• 德州仪器(TI),运算放大器的EMI 抑制比
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 商标
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 机械、封装和可订购信息
下述页面包含机械、封装和订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查看左侧的导航面板。
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Product Folder Links: LMV321A LMV358A LMV324A
English Data Sheet: SBOS923
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV321AIDBVR
LMV321AIDCKR
LMV321AUIDBVR
LMV324AIDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DBV
D
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1OIF
1C2
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
SN
SOT-23
SOIC
5
NIPDAU | SN
NIPDAU
1WOF
14
14
14
8
LMV324
LM324I
LMV324A
358A
LMV324AIDYYR
LMV324AIPWR
LMV358AIDDFR
LMV358AIDGKR
LMV358AIDGKT
LMV358AIDR
ACTIVE SOT-23-THIN
ACTIVE TSSOP
ACTIVE SOT-23-THIN
DYY
PW
DDF
DGK
DGK
D
NIPDAU
SN
NIPDAU
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAU | SN
NIPDAU | SN
1MAX
8
250
RoHS & Green
1MAX
8
2500 RoHS & Green
2000 RoHS & Green
MV358A
LMV358
LMV358AIPWR
TSSOP
PW
8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2023
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV321A, LMV324A, LMV358A :
Automotive : LMV321A-Q1, LMV324A-Q1, LMV358A-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV321AIDBVR
LMV321AIDBVR
LMV321AIDCKR
LMV321AUIDBVR
LMV321AUIDBVR
LMV324AIDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DBV
DBV
D
5
5
3000
3000
3000
3000
3000
2500
3000
180.0
180.0
178.0
180.0
180.0
330.0
330.0
8.4
8.4
3.2
3.2
2.4
3.2
3.2
6.5
4.8
3.2
3.2
2.5
3.2
3.2
9.0
3.6
1.4
1.4
1.2
1.4
1.4
2.1
1.6
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q1
Q3
5
9.0
8.0
SOT-23
SOT-23
SOIC
5
8.4
8.0
5
8.4
8.0
14
14
16.4
12.4
16.0
12.0
LMV324AIDYYR
SOT-23-
THIN
DYY
LMV324AIPWR
LMV358AIDDFR
TSSOP
PW
14
8
2000
3000
330.0
180.0
12.4
8.4
6.9
3.2
5.6
3.2
1.6
1.4
8.0
4.0
12.0
8.0
Q1
Q3
SOT-23-
THIN
DDF
LMV358AIDGKR
LMV358AIDGKR
LMV358AIDGKT
LMV358AIDGKT
LMV358AIDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
6.4
7.0
3.4
3.4
3.4
3.4
5.2
3.6
1.4
1.4
1.4
1.4
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
250
2500
2000
LMV358AIPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV358AIPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV321AIDBVR
LMV321AIDBVR
LMV321AIDCKR
LMV321AUIDBVR
LMV321AUIDBVR
LMV324AIDR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DBV
DBV
D
5
5
3000
3000
3000
3000
3000
2500
3000
2000
3000
2500
2500
250
210.0
210.0
190.0
210.0
210.0
356.0
336.6
366.0
210.0
366.0
366.0
366.0
366.0
356.0
366.0
356.0
185.0
185.0
190.0
185.0
185.0
356.0
336.6
364.0
185.0
364.0
364.0
364.0
364.0
356.0
364.0
356.0
35.0
35.0
30.0
35.0
35.0
35.0
31.8
50.0
35.0
50.0
50.0
50.0
50.0
35.0
50.0
35.0
5
SOT-23
SOT-23
SOIC
5
5
14
14
14
8
LMV324AIDYYR
LMV324AIPWR
LMV358AIDDFR
LMV358AIDGKR
LMV358AIDGKR
LMV358AIDGKT
LMV358AIDGKT
LMV358AIDR
SOT-23-THIN
TSSOP
SOT-23-THIN
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DYY
PW
DDF
DGK
DGK
DGK
DGK
D
8
8
8
8
250
8
2500
2000
2000
LMV358AIPWR
LMV358AIPWR
TSSOP
TSSOP
PW
8
PW
8
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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