LMV711M6X [TI]

Low Power, RRIO Operational Amplifiers with High Output Current Drive and Shutdown Option; 低功耗, RRIO高输出电流驱动和关机选项运算放大器
LMV711M6X
型号: LMV711M6X
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Low Power, RRIO Operational Amplifiers with High Output Current Drive and Shutdown Option
低功耗, RRIO高输出电流驱动和关机选项运算放大器

运算放大器 驱动
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中文:  中文翻译
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LMV710,LMV711,LMV715  
LMV710/LMV711/LMV715 Low Power, RRIO Operational Amplifiers with High  
Output Current Drive and Shutdown Option  
Literature Number: SNOS519I  
January 9, 2009  
LMV710/LMV711/LMV715  
Low Power, RRIO Operational Amplifiers with High Output  
Current Drive and Shutdown Option  
General Description  
Features  
The LMV710/LMV711/LMV715 are BiCMOS operational am-  
plifiers with a CMOS input stage. These devices have greater  
than RR input common mode voltage range, rail-to-rail output  
and high output current drive. They offer a bandwidth of 5 MHz  
and a slew rate of 5 V/µs.  
(For 5V supply, typical unless otherwise noted).  
Low offset voltage  
Gain-bandwidth product  
Slew rate  
Space saving packages  
Turn on time from shutdown  
Industrial temperature range  
Supply current in shutdown mode  
3 mV, max  
5 MHz, typ  
5 V/µs, typ  
5-Pin and 6-Pin SOT23  
<10 µs  
On the LMV711/LMV715, a separate shutdown pin can be  
used to disable the device and reduces the supply current to  
0.2 µA (typical). They also feature a turn on time of less than  
10 µs. It is an ideal solution for power sensitive applications,  
such as cellular phone, pager, palm computer, etc. In addi-  
tion, once the LMV715 is in shutdown the output will be “Tri-  
stated”.  
−40°C to +85°C  
0.2 µA, typ  
Guaranteed 2.7V and 5V performance  
Unity gain stable  
Rail-to-rail input and output  
Capable of driving 600load  
The LMV710 is offered in the space saving 5-Pin SOT23 Tiny  
package. The LMV711/LMV715 are offered in the space sav-  
ing 6-Pin SOT23 Tiny package.  
Applications  
The LMV710/LMV711/LMV715 are designed to meet the de-  
mands of low power, low cost, and small size required by  
cellular phones and similar battery powered portable elec-  
tronics.  
Wireless phones  
GSM/TDMA/CDMA power amp control  
AGC, RF power detector  
Temperature compensation  
Wireless LAN  
Bluetooth  
HomeRF  
Typical Application  
High Side Current Sensing  
10132513  
© 2009 National Semiconductor Corporation  
101325  
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Current at Input Pin  
Mounting Temp.  
Infrared or Convection (20 sec)  
Storage Temperature Range  
Junction Temperature (TJMAX  
± 10 mA  
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
235°C  
−65°C to 150°C  
150°C  
)
ESD Tolerance (Note 2)  
(Note 5)  
Machine Model  
Human Body Model  
100V  
2000V  
Operating Ratings (Note 1)  
Supply Voltage  
Differential Input Voltage  
Voltage at Input/Output Pin  
± Supply Voltage  
(V+) + 0.4V  
2.7V to 5.0V  
−40°C to 85°C  
Temperature Range  
(V) − 0.4V  
Thermal Resistance (θJA  
MF05A Package, 5-Pin SOT23  
MF06A package, 6-Pin SOT23  
)
Supply Voltage (V+ - V )  
Output Short Circuit to V+  
Output Short Circuit to V−  
5.5V  
(Note 3)  
(Note 4)  
265 °C/W  
265 °C/W  
2.7V Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V = 0V, VCM = 1.35V and RL > 1 MΩ. Boldface limits  
apply at the temperature extremes.  
Symbol  
VOS  
Parameter  
Input Offset Voltage  
Condition  
Typ  
(Note 6)  
Limits  
(Note 7)  
Units  
VCM = 0.85V and VCM = 1.85V  
0.4  
3
mV  
3.2  
max  
IB  
Input Bias Current  
4
pA  
CMRR  
Common Mode Rejection Ratio  
75  
50  
45  
dB  
min  
0 VCM 2.7V  
2.7V V+ 5V,  
dB  
min  
PSRR  
Power Supply Rejection Ratio  
110  
95  
70  
68  
VCM = 0.85V  
2.7V V+ 5V,  
VCM = 1.85V  
dB  
min  
70  
68  
VCM  
ISC  
Input Common-Mode Voltage Range  
Output Short Circuit Current  
-0.3  
3
-0.2  
2.9  
For CMRR 50 dB  
V
Sourcing  
VO = 0V  
28  
15  
12  
mA  
min  
Sinking  
VO = 2.7V  
40  
2.68  
0.01  
2.55  
0.05  
50  
25  
22  
mA  
min  
VO  
Output Swing  
2.62  
2.60  
V
min  
RL = 10 kto 1.35V  
0.12  
0.15  
V
max  
2.52  
2.50  
V
min  
RL = 600Ω to 1.35V  
0.23  
0.30  
V
max  
VO (SD)  
IO (SD)  
CO (SD)  
IS  
Output Voltage Level in  
Shutdown Mode (LMV711 only)  
200  
mV  
pA  
pF  
Output Leakage Current in  
Shutdown Mode (LMV715 Only)  
1
Output Capacitance in  
Shutdown Mode (LMV715 Only)  
32  
Supply Current  
On Mode  
1.22  
0.002  
1.7  
1.9  
mA  
max  
Shutdown Mode, VSD = 0V  
10  
µA  
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2
Symbol  
AV  
Parameter  
Large Signal Voltage  
Condition  
Typ  
(Note 6)  
Limits  
(Note 7)  
Units  
Sourcing  
115  
113  
110  
100  
80  
76  
dB  
min  
RL = 10 kΩ  
VO = 1.35V to 2.3V  
Sinking  
80  
76  
dB  
min  
RL = 10 kΩ  
VO = 0.4V to 1.35V  
Sourcing  
80  
76  
dB  
min  
RL = 600Ω  
VO = 1.35V to 2.2V  
Sinking  
80  
dB  
76  
min  
RL = 600Ω  
VO = 0.5V to 1.35V  
SR  
Slew Rate  
(Note 8)  
5
5
V/µs  
MHz  
Deg  
GBWP  
φm  
Gain-Bandwidth Product  
Phase Margin  
60  
TON  
VSD  
Turn-on Time from Shutdown  
Shutdown Pin Voltage Range  
<10  
1.5 to 2.7  
0 to 1  
20  
µs  
V
On Mode  
2.4 to 2.7  
0 to 0.8  
Shutdown Mode  
f = 1 kHz  
V
en  
Input-Referred Voltage Noise  
3.2V Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 3.2V, V= 0V, VCM = 1.6V. Boldface limits apply at the  
temperature extremes.  
Symbol  
VO  
Parameter  
Conditions  
Typ  
(Note 6)  
Limit  
(Note 7)  
Units  
Output Swing  
IO = 6.5 mA  
3.0  
2.95  
V
2.92  
min  
0.01  
0.18  
V
0.25  
max  
5V Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 5V, V = 0V, VCM = 2.5V, and RL > 1 MΩ. Boldface limits  
apply at the temperature extremes.  
Symbol  
VOS  
Parameter  
Input Offset Voltage  
Condition  
Typ  
(Note 6)  
Limits  
(Note 7)  
Units  
VCM = 0.85V and VCM = 1.85V  
0.4  
3
mV  
3.2  
max  
IB  
Input Bias Current  
4
pA  
CMRR  
Common Mode Rejection Ratio  
70  
50  
48  
dB  
min  
0V VCM 5V  
2.7V V+ 5V,  
dB  
min  
PSRR  
Power Supply Rejection Ratio  
110  
95  
70  
68  
VCM = 0.85V  
2.7V V+ 5V,  
VCM = 1.85V  
dB  
min  
70  
68  
VCM  
Input Common-Mode Voltage Range  
-0.3  
5.3  
−0.2  
5.2  
For CMRR 50 dB  
V
3
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Symbol  
ISC  
Parameter  
Condition  
Typ  
(Note 6)  
Limits  
(Note 7)  
Units  
Output Short Circuit Current  
Sourcing  
VO = 0V  
35  
40  
25  
21  
mA  
min  
Sinking  
VO = 5V  
25  
21  
mA  
min  
VO  
Output Swing  
4.98  
0.01  
4.85  
0.05  
50  
4.92  
4.90  
V
min  
RL = 10 kto 2.5V  
0.12  
0.15  
V
max  
4.82  
4.80  
V
min  
RL = 600Ω to 2.5V  
0.23  
0.3  
V
max  
VO (SD)  
IO (SD)  
CO (SD)  
IS  
Output Voltage Level in  
Shutdown Mode (LMV711 only)  
200  
mV  
pA  
pF  
Output Leakage Current in  
Shutdown Mode (LMV715 Only)  
1
Output Capacitance in  
shutdown Mode (LMV715 Only)  
32  
Supply Current  
On Mode  
1.17  
1.7  
mA  
1.9  
max  
Shutdown Mode  
Sourcing  
0.2  
10  
µA  
AV  
Large Signal Voltage Gain  
123  
80  
dB  
76  
min  
RL = 10 kΩ  
VO = 2.5V to 4.6V  
Sinking  
120  
110  
118  
80  
76  
dB  
min  
RL = 10 kΩ  
VO = 0.4V to 2.5V  
Sourcing  
80  
76  
dB  
min  
RL = 600Ω  
VO = 2.5V to 4.5V  
Sinking  
80  
dB  
76  
min  
RL = 600Ω  
VO = 0.5V to 2.5V  
SR  
Slew Rate  
(Note 8)  
5
5
V/µs  
MHz  
Deg  
GBWP  
φm  
Gain-Bandwidth Product  
Phase Margin  
60  
TON  
VSD  
Turn-on Time from Shutdown  
Shutdown Pin Voltage Range  
<10  
2 to 5  
0 to 1.5  
20  
µs  
On Mode  
2.4 to 5  
0 to 0.8  
V
Shutdown Mode  
f = 1 kHz  
en  
Input-Referred Voltage Noise  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is  
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.  
Note 2: Human body model, 1.5 kin series with 100 pF. Machine model, 0in series with 100 pF.  
Note 3: Shorting circuit output to V+ will adversely affect reliability.  
Note 4: Shorting circuit output to Vwill adversely affect reliability.  
Note 5: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is  
PD = (TJ(MAX) - T A)/θJA. All numbers apply for packages soldered directly into a PC board.  
Note 6: Typical values represent the most likely parametric norm.  
Note 7: All limits are guaranteed by testing or statistical analysis.  
Note 8: Number specified is the slower of the positive and negative slew rates.  
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Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
Supply Current vs. Supply Voltage (On Mode)  
LMV711/LMV715 Supply Current vs.  
Supply Voltage (Shutdown Mode)  
10132527  
10132528  
Output Positive Swing vs. Supply Voltage  
Output Negative Swing vs. Supply Voltage  
10132529  
10132530  
Output Positive Swing vs. Supply Voltage  
Output Negative Swing vs. Supply Voltage  
10132531  
10132532  
5
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Output Positive Swing vs. Supply Voltage  
Output Negative Swing vs. Supply Voltage  
10132533  
10132534  
Input Voltage Noise vs. Frequency  
PSRR vs. Frequency  
10132535  
10132536  
CMRR vs. Frequency  
LMV711/LMV715 Turn On Characteristics  
10132538  
10132537  
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6
Sourcing Current vs. Output Voltage  
THD+N vs. Frequency (VS = 5V)  
THD+N vs. VOUT  
Sinking Current vs. Output Voltage  
THD+N vs. Frequency (VS = 2.7V)  
THD+N vs. VOUT  
10132539  
10132540  
10132541  
10132542  
10132543  
10132544  
7
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CCM vs. VCM  
CCM vs. VCM  
10132545  
10132546  
CDIFF vs. VCM (VS = 2.7V)  
CDIFF vs. VCM (VS = 5V)  
10132547  
10132548  
Open Loop Frequency Response  
Open Loop Frequency Response  
10132512  
10132510  
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8
Open Loop Frequency Response  
Open Loop Frequency Response  
10132511  
10132507  
Open Loop Frequency Response  
Open Loop Frequency Response  
10132509  
10132508  
Non-Inverting Large Signal Pulse Response  
Non-Inverting Small Signal Pulse Response  
10132503  
10132502  
9
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Inverting Large Signal Pulse Response  
Inverting Small Signal Pulse Response  
10132504  
10132505  
VOS vs. VCM  
VOS vs. VCM  
10132549  
10132550  
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10  
Application Information  
1.0 SUPPLY BYPASSING  
The application circuits in this datasheet do not show the  
power supply connections and the associated bypass capac-  
itors for simplification. When the circuits are built, it is always  
required to have bypass capacitors. Ceramic disc capacitors  
(0.1 µF) or solid tantalum (1 µF) with short leads, and located  
close to the IC are usually necessary to prevent interstage  
coupling through the power supply internal impedance. Inad-  
equate bypassing will manifest itself by a low frequency os-  
cillation or by high frequency instabilities. Sometimes, a 10 µF  
(or larger) capacitor is used to absorb low frequency varia-  
tions and a smaller 0.1 µF disc is paralleled across it to  
prevent any high frequency feedback through the power sup-  
ply lines.  
10132552  
FIGURE 1.  
When the input is a small signal and this small signal falls  
inside the VOS transition range, the gain, CMRR and some  
other parameters will be degraded. To resolve this problem,  
the small signal should be placed such that it avoids the  
VOS crossover point.  
To achieve maximum output swing, the output should be bi-  
ased at mid-supply. This is normally done by biasing the input  
at mid-supply. But with supply voltage range from 2V to 3.4V,  
the input of the op amp should not be biased at mid-supply  
because of the transition of the VOS. Figure 2 shows an ex-  
ample of how to get away from the VOS crossover point and  
maintain a maximum swing with a 2.7V supply. Figure 3  
2.0 SHUTDOWN MODE  
The LMV711/LMV715 have a shutdown pin. To conserve bat-  
tery life in portable applications, they can be disabled when  
the shutdown pin voltage is pulled low. For LMV711 during  
shutdown mode, the output stays at about 50 mV from the  
lower rail, and the current drawn from the power supply is 0.2  
µA (typical). This makes the LMV711 an ideal solution for  
power sensitive applications. For the LMV715 during shut-  
down mode, the output will be “Tri-stated”.  
shows the waveforms of VIN and VOUT  
.
The shutdown pin should never be left unconnected. In ap-  
plications where shutdown operation is not needed and the  
LMV711 or LMV715 is used, the shutdown pin should be con-  
nected to V+. Leaving the shutdown pin floating will result in  
an undefined operation mode and the device may oscillate  
between shutdown and active modes.  
3.0 RAIL-TO-RAIL INPUT  
10132517  
The rail-to-rail input is achieved by using paralleled PMOS  
and NMOS differential input stages. (See Simplified  
Schematics in this datasheet). When the common mode input  
voltage changes from ground to the positive rail, the input  
stage goes through three modes. First, the NMOS pair is cut-  
off and the PMOS pair is active. At around 1.4V, both PMOS  
and NMOS pairs operate, and finally the PMOS pair is cutoff  
and NMOS pair is active. Since both input stages have their  
own offset voltage (VOS), the offset of the amplifier becomes  
a function of the common-mode input voltage. See curves for  
VOS vs. VCM in curve section.  
FIGURE 2.  
As shown in the curve, the VOS has a crossover point at 1.4V  
above V. Proper design must be done in both DC and AC  
coupled applications to avoid problems. For large input sig-  
nals that include the VOS crossover point in their dynamic  
range, it will cause distortion in the output signal. One way to  
avoid such distortion is to keep the signal away from the  
crossover point. For example, in a unity gain buffer configu-  
ration and with VS = 5V, a 3V peak-to-peak signal center at  
2.5V will contain input-crossover distortion. To avoid this, the  
input signal should be centered at 3.5V instead. Another way  
to avoid large signal distortion is to use a gain of −1 circuit  
which avoids any voltage excursions at the input terminals of  
the amplifier. See Figure 1. In this circuit, the common mode  
DC voltage (VCM) can be set at a level away from the VOS  
crossover point.  
10132551  
FIGURE 3.  
The inputs can be driven 300 mV beyond the supply rails  
without causing phase reversal at the output. However, the  
inputs should not be allowed to exceed the maximum ratings.  
11  
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4.0 COMPENSATION OF INPUT CAPACITANCE  
In Figure 5, the isolation resistor RISO and the load capacitor  
CL form a pole to increase stability by adding more phase  
margin to the overall system. The desired performance de-  
pends on the value of RISO. The bigger the RISO resistor value,  
the more stable VOUT will be. But the DC accuracy is not great  
when the RISO gets bigger. If there were a load resistor in  
Figure 5, the output would be voltage divided by RISO and the  
load resistor.  
In the application (Figure 4) where a large feedback resistor  
is used, the feedback resistor can react with the input capac-  
itance of the op amp and introduce an additional pole to the  
close loop frequency response.  
The circuit in Figure 6 is an improvement to the one in Figure  
5 because it provides DC accuracy as well as AC stability. In  
this circuit, RF provides the DC accuracy by using feed-for-  
ward techniques to connect VIN to RL. CF and RISO serve to  
counteract the loss of phase margin by feeding the high fre-  
quency component of the output signal back to the amplifier's  
inverting input, thereby preserving phase margin in the overall  
feedback loop. Increased capacitive drive is possible by in-  
creasing the value of CF . This in turn will slow down the pulse  
response.  
10132518  
FIGURE 4. Cancelling the Effect of Input Capacitance  
This pole occurs at frequency fp , where  
Any stray capacitance due to external circuit board layout, any  
source capacitance from transducer or photodiode connected  
to the summing node will also be added to the input capaci-  
tance. If fp is less than or close to the unity-gain bandwidth (5  
MHz) of the op amp, the phase margin of the loop is reduced  
and can cause the system to be unstable.  
10132522  
FIGURE 6. Indirectly Driving A Capacitive A Load with DC  
Accuracy  
To avoid this problem, make sure that fp occurs at least 2 oc-  
taves beyond the expected −3 dB frequency corner of the  
close loop frequency response. If not, a feedback capacitor  
CF can be placed in parallel with RF such that  
6.0 APPLICATION CIRCUITS  
PEAK DETECTOR  
Peak detectors are used in many applications, such as test  
equipment, measurement instrumentation, ultrasonic alarm  
systems, etc. Figure 7 shows the schematic diagram of a peak  
detector using LMV710 or LMV711 or LMV715. This peak  
detector basically consists of a clipper, a parallel RC network,  
and a voltage follower.  
The paralleled RF and CF introduce a zero, which cancels the  
effect from the pole.  
5.0 CAPACITIVE LOAD TOLERANCE  
The LMV710/LMV711/ LMV715 can directly drive 200 pF in  
unity-gain without oscillation. The unity-gain follower is the  
most sensitive configuration to capacitive loading. Direct ca-  
pacitive loading reduces the phase margin of amplifiers. The  
combination of the amplifier's output impedance and the ca-  
pacitive load induces phase lag. This results in either an  
underdamped pulse response or oscillation. To drive a heav-  
ier capacitive load, circuit in Figure 5 can be used.  
10132523  
FIGURE 7. Peak Detector  
The capacitor C1 is first discharged by applying a positive  
pulse to the reset transistor. When a positive voltage VIN is  
applied to the input, the input voltage is higher than the volt-  
age across C1. The output of the op amp goes high and  
forward biases the diode D1. The capacitor C1 is charged to  
VIN. When the input becomes less than the current capacitor  
voltage, the output of the op amp A1 goes low and the diode  
10132521  
FIGURE 5. Indirectly Driving A Capacitive Load using  
Resistive Isolation  
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12  
 
 
 
 
D1 is reverse biased. This isolates the C1 and leaves it with  
the charge equivalent to the peak of the input voltage. The  
follower prevents unintentional discharging of C1 by loading  
from the following circuit.  
vent over-charging. A sense resistor RSENSE is connected to  
the battery directly. This system requires an op amp with rail-  
to-rail input. The LMV710/LMV711/LMV715 are ideal for this  
application because its common mode input range can go  
beyond the positive rail.  
R5 and C1 are properly selected so that the capacitor is  
charged rapidly to VIN. During the holding period, the capac-  
itor slowly discharge through C1, via leakage of the capacitor  
and the reverse-biased diode, or op amp bias currents. In any  
cases the discharging time constant is much larger than the  
charge time constant. And the capacitor can hold its voltage  
long enough to minimize the output ripple.  
Resistors R2 and R3 limit the current into the inverting input  
of A1 and the non-inverting input of A2 when power is dis-  
connected from the circuit. The discharging current from C1  
during power off may damage the input circuitry of the op  
amps.  
The peak detector can be reset by applying a positive pulse  
to the reset transistor. The charge on the capacitor is dumped  
into ground, and the detector is ready for another cycle.  
The maximum input voltage to this detector should be less  
than (V+ - VD), where VD is the forward voltage drop of the  
diode. Otherwise, the input voltage should be scaled down  
before applying to the circuit.  
10132513  
FIGURE 8. High Side Current Sensing  
HIGH SIDE CURRENT SENSING  
The high side current sensing circuit (Figure 8) is commonly  
used in a battery charger to monitor charging current to pre-  
10132506  
FIGURE 9. Typical of GSM P.A. Control Loop  
GSM POWER AMPLIFIER CONTROL LOOP  
equal. Power control is accomplished by changing the ramp-  
ing voltage.  
There are four critical sections in the GSM Power Amplifier  
Control Loop. The class-C RF power amplifier provides am-  
plification of the RF signal. A directional coupler couples small  
amount of RF energy from the output of the RF P. A. to an  
envelope detector diode. The detector diode senses the sig-  
nal level and rectifies it to a DC level to indicate the signal  
strength at the antenna. An op amp is used as an error am-  
plifier to process the diode voltage and ramping voltage. This  
loop control the power amplifier gain via the op amp and  
forces the detector diode voltage and ramping voltage to be  
The LMV710/LMV711/LMV715 are well suited as an error  
amplifier in this application. The LMV711/LMV715 have an  
extra shutdown pin to switch the op amp to shutdown mode.  
In shutdown mode, the LMV711/LMV715 consume very low  
current. The LMV711 provides a ground voltage to the power  
amplifier control pin VPC. Therefore, the power amplifier can  
be turned off to save battery life. The LMV715 output will be  
“tri-stated” when in shutdown.  
13  
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Simplified Schematic  
LMV711  
10132516  
Connection Diagrams  
5-Pin SOT23  
LMV710  
6-Pin SOT23  
LMV711 and LMV715  
10132514  
10132515  
Top View  
Top View  
Ordering Information  
Package  
Temperature Range  
Industrial  
Packaging Marking  
Transport Media  
NSC Drawing  
−40°C to +85°C  
LMV710M5  
1k Units Tape and Reel  
3k Units Tape and Reel  
1k Units Tape and Reel  
3k Units Tape and Reel  
1k Units Tape and Reel  
3k Units Tape and Reel  
5-Pin SOT23  
6-Pin SOT23  
A48A  
A47A  
A75A  
MF05A  
MF06A  
LMV710M5X  
LMV711M6  
LMV711M6X  
*LMV715MF  
*LMV715MFX  
*LMV715MF/LMV715MFX are not recommended for new designs with a last time buy date of 12/1/2009.  
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14  
SOT-23 Tape and Reel Specification  
Tape Format  
Tape Section  
# Cavities  
0 (min)  
75 (min)  
3000  
Cavity Status  
Empty  
Cover Tape Status  
Sealed  
Leader  
(Start End)  
Empty  
Sealed  
Carrier  
Filled  
Sealed  
1000  
Filled  
Sealed  
Trailer  
(Hub End)  
125 (min)  
0 (min)  
Empty  
Sealed  
Empty  
Sealed  
Tape Dimensions  
10132555  
TAPE SIZE DIM  
A
DIM Ao  
DIM  
B
DIM Bo  
DIM  
F
DIM  
Ko  
DIM P1  
DIM  
T
DIM  
W
8 mm  
.130  
(3.3)  
.124  
(3.15)  
.130  
(3.3)  
.126  
(3.2)  
.138 ± .002  
(3.5 ± 0.05)  
.055 ± .004  
(1.4 ± 0.1)  
.157  
(4)  
.008 ± .004  
(0.2 ± 0.1)  
.315 ± .012  
(8 ± 0.3)  
Note:  
UNLESS OTHERWISE SPECIFIED  
3. SMALLEST ALLOWABLE TAPE BENDING RADIUS: 1.181 IN/  
30mm.  
1. CUMULATIVE PITCH TOLERANCE FOR FEEDING HOLES AND  
CAVITIES (CHIP POCKETS) NOT TO EXCEED .008 IN / 0.2mm  
OVER 10 PITCH SPAN.  
4. DIMENSIONS WITH Δ ARE CRITICAL. DIMENSIONS TO BE AB-  
SOLUTELY INSPECTED.  
2. THRU HOLE INSIDE CAVITY IS CENTERED WITHIN CAVITY.  
15  
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Reel Dimensions  
10132554  
TAPE  
SIZE  
DIM A DIM B  
DIM C  
DIM D DIM N  
DIM W1  
DIM W2  
DIM W3  
(LSL-USL)  
8 mm  
7.00  
(177.8)  
.059  
(1.5)  
.512 + .020/−.008  
(13 +0.5/−0.2)  
.795  
(20.2)  
2.165  
(55)  
.331 + .059/−.000  
(8.4 + 1.5/0)  
.567  
(14.4)  
.311 - .429  
(7.9 - 10.9)  
Note:  
UNLESS OTHERWISE SPECIFIED  
1. MATERIAL:  
10. ALL GATING FROM THE MOLD MUST BE PROPERLY RE-  
MOVED.  
11. NO FLASHES ARE TO BE PRESENT ALONG THE PARTING  
LINES.  
POLYSTYRENE/PVC (WITH ANTISTATIC COATING).  
OR POLYSTYRENE/PVC, ANTISTATIC  
12. ALLOWABLE RADIUS FOR CORNERS AND EDGES IS .012  
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OR POLYSTYRENE/PVC, CONDUCTIVE.  
2. CONTROLLING DIMENSION IS MILLIMETER, DIMENSIONS IN  
INCHES ROUNDED.  
3. SURFACE RESISTIVITY: 1010 OHM/SQ MAXIMUM.  
13. SINK MARKS THAT WILL CAUSE A CHANGE TO THE SPEC-  
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LOWED.  
4. ALL OUTPUT REELS SHALL BE UNIFORM IN SHADE.  
14. MOLDED REELS SHALL BE FREE OF COSMETIC DEFECTS  
SUCH AS VOIDS. FLASHING, EXCESSIVE FLOW MARKS, ETC.  
5. PACKING OF REELS IN CONTAINERS MUST ENSURE NO  
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15. THERE MUST BE NO MISMATCH BETWEEN MATING PARTS.  
6. SURFACE FINISH OF THE FLANGES SHALL BE SMOOTH,  
MATTE FINISH PREFERRED.  
16. MOLDED REELS SHALL BE ANTISTATIC COATED OR  
BLENDED.  
7. ALL EDGES, ESPECIALLY THE TAPE ENTRY EDGES, MUST  
BE FREE OF BURRS.  
17. THE SOT23-5L AND SOT23-6L PACKAGE USE THE 7-INCH  
REEL.  
8. THE REEL SHOULD NOT WARP IN THE STORAGE TEMPER-  
ATURE OF 67°C MAXIMUM.  
9. GLASS TRANSITION TEMPERATURE (Tg) OF THE PLASTIC  
REEL SHALL BE LOWER THAN −20°C.  
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16  
Physical Dimensions inches (millimeters) unless otherwise noted  
SOT23-5  
NS Package Number MF05A  
SOT23-6  
NS Package Number MF06A  
17  
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