LMV794MM/NOPB [TI]
双通道 88MHz 低噪声 1.8V CMOS 输入、解补偿运算放大器 | DGK | 8 | -40 to 125;
| 型号： | LMV794MM/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道 88MHz 低噪声 1.8V CMOS 输入、解补偿运算放大器 | DGK | 8 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总38页 (文件大小：1595K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMV793, LMV794
www.ti.com
SNOSAX6D –MARCH 2007–REVISED MARCH 2013
LMV793/LMV794 88 MHz, Low Noise, 1.8V CMOS Input, Decompensated Operational
Amplifiers
Check for Samples: LMV793, LMV794
1
FEATURES
DESCRIPTION
The LMV793 (single) and the LMV794 (dual) CMOS
input operational amplifiers offer a low input voltage
noise density of 5.8 nV/√Hz while consuming only
1.15 mA (LMV793) of quiescent current. The
LMV793/LMV794 are stable at a gain of 10 and have
a gain bandwidth product (GBW) of 88 MHz. The
LMV793/LMV794 have a supply voltage range of
1.8V to 5.5V and can operate from a single supply.
2
(Typical 5V Supply, Unless Otherwise Noted)
•
•
•
•
Input Referred Voltage Noise 5.8 nV/√Hz
Input Bias Current 100 fA
Gain Bandwidth Product 88 MHz
Supply Current per Channel
–
–
LMV793 1.15 mA
LMV794 1.30 mA
The LMV793/LMV794 each feature
a rail-to-rail
output stage capable of driving a 600Ω load and
sourcing as much as 60 mA of current.
•
Rail-to-Rail Output Swing
–
–
@ 10 kΩ Load 25 mV from Rail
@ 2 kΩ Load 45 mV from Rail
The LMV793/LMV794 provide optimal performance in
low voltage and low noise systems. A CMOS input
stage, with typical input bias currents in the range of
a few femto-Amperes, and an input common mode
voltage range, which includes ground, make the
LMV793/LMV794 ideal for low power sensor
applications where high speeds are needed.
•
•
•
Ensured 2.5V and 5.0V Performance
Total Harmonic Distortion 0.04% @1 kHz, 600Ω
Temperature Range −40°C to 125°C
APPLICATIONS
The LMV793/LMV794 are manufactured using TI’s
advanced VIP50 process. The LMV793 is offered in
either a 5-Pin SOT23 or an 8-Pin SOIC package. The
LMV794 is offered in either the 8-Pin SOIC or the 8-
Pin VSSOP.
•
•
•
•
•
•
ADC Interface
Photodiode Amplifiers
Active Filters and Buffers
Low Noise Signal Processing
Medical Instrumentation
Sensor Interface Applications
Typical Application
C
F
1000
R
F
I
IN
C
5V
100
-
CM
+
-
2.5V
+
V
OUT
C
D
10
V
B
CIN = CD + CCM
VOUT
1
0.1
- R
=
F
1
10
100
1k
10k
IIN
FREQUENCY (Hz)
Figure 1. Photodiode Transimpedance Amplifier
Figure 2. Input Referred Voltage Noise vs.
Frequency
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMV793, LMV794
SNOSAX6D –MARCH 2007–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Human Body Model
Machine Model
2000V
200V
ESD Tolerance(3)
Charge-Device Model
1000V
VIN Differential
±0.3V
Supply Voltage (V+ – V−)
Input/Output Pin Voltage
Storage Temperature Range
Junction Temperature(4)
6.0V
V+ +0.3V, V− −0.3V
−65°C to 150°C
+150°C
Infrared or Convection (20 sec)
235°C
Soldering Information
Wave Soldering Lead Temp (10 sec)
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings(1)
Temperature Range(2)
−40°C to 125°C
2.0V to 5.5V
1.8V to 5.5V
180°C/W
−40°C ≤ TA ≤ 125°C
0°C ≤ TA ≤ 125°C
5-Pin SOT-23
Supply Voltage (V+ – V−)
(2)
Package Thermal Resistance (θJA
)
8-Pin SOIC
190°C/W
8-Pin VSSOP
236°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
2.5V Electrical Characteristics(1)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply
at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(3)
(2)
VOS
Input Offset Voltage
0.1
±1.35
±1.65
mV
TC VOS Input Offset Voltage Temperature Drift(4) LMV793
LMV794
−1.0
−1.8
μV/°C
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage average drift is determined by dividing the change in VOS by temperature change.
2
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Product Folder Links: LMV793 LMV794
LMV793, LMV794
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SNOSAX6D –MARCH 2007–REVISED MARCH 2013
2.5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply
at the temperature extremes.
Symbol
Parameter
Conditions
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
Min
Typ
Max
Units
(2)
(3)
(2)
IB
Input Bias Current
VCM = 1.0V(5) (6)
0.05
0.05
1
25
pA
1
100
IOS
Input Offset Current
VCM = 1.0V(6)
10
94
fA
CMRR Common Mode Rejection Ratio
0V ≤ VCM ≤ 1.4V
80
75
dB
PSRR
Power Supply Rejection Ratio
2.0V ≤ V+ ≤ 5.5V, VCM = 0V
1.8V ≤ V+ ≤ 5.5V, VCM = 0V
80
75
100
98
dB
V
80
CMVR
AVOL
Common Mode Voltage Range
Open Loop Voltage Gain
CMRR ≥ 60 dB
CMRR ≥ 55 dB
−0.3
-0.3
1.5
1.5
VOUT = 0.15V to 2.2V, LMV793
85
80
98
92
RL = 2 kΩ to V+/2
LMV794
82
78
dB
VOUT = 0.15V to 2.2V,
88
84
110
25
RL = 10 kΩ to V+/2
VOUT
Output Voltage Swing High
Output Voltage Swing Low
Output Current
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
75
82
20
65
71
mV from
either rail
30
75
78
15
65
67
IOUT
Sourcing to V−
VIN = 200 mV(7)
35
28
47
mA
Sinking to V+
7
5
15
VIN = –200 mV(7)
IS
Supply Current Per Amplifier
Slew Rate
LMV793
0.95
1.1
1.30
1.65
mA
LMV794
1.50
1.85
SR
AV = +10, Rising (10% to 90%)
AV = +10, Falling (90% to 10%)
AV = +10, RL = 10 kΩ
f = 1 kHz
32
24
V/μs
GBW
en
Gain Bandwidth
88
MHz
nV/√Hz
pA/√Hz
%
Input Referred Voltage Noise Density
Input Referred Current Noise Density
6.2
0.01
0.01
in
f = 1 kHz
THD+N Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, RL = 600Ω
(5) Positive current corresponds to current flowing into the device.
(6) This parameter is specified by design and/or characterization and is not tested in production.
(7) The short circuit test is a momentary test, the short circuit duration is 1.5 ms.
Copyright © 2007–2013, Texas Instruments Incorporated
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5V Electrical Characteristics(1)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at
the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(3)
(2)
VOS
Input Offset Voltage
0.1
±1.35
±1.65
mV
TC VOS Input Offset Voltage Temperature Drift(4) LMV793
LMV794
−1.0
−1.8
0.1
μV/°C
IB
Input Bias Current
VCM = 2.0V(5) (6)
−40°C ≤ TA ≤ 85°C
−40°C ≤ TA ≤ 125°C
1
25
pA
0.1
1
100
IOS
Input Offset Current
VCM = 2.0V(6)
10
fA
CMRR Common Mode Rejection Ratio
0V ≤ VCM ≤ 3.7V
80
75
100
dB
PSRR
Power Supply Rejection Ratio
2.0V ≤ V+ ≤ 5.5V, VCM = 0V
1.8V ≤ V+ ≤ 5.5V, VCM = 0V
80
75
100
98
dB
V
80
CMVR
AVOL
Common Mode Voltage Range
Open Loop Voltage Gain
CMRR ≥ 60 dB
CMRR ≥ 55 dB
−0.3
-0.3
4
4
VOUT = 0.3V to 4.7V, LMV793
85
80
97
89
RL = 2 kΩ to V+/2
LMV794
82
78
dB
VOUT = 0.3V to 4.7V,
88
84
110
35
RL = 10 kΩ to V+/2
VOUT
Output Voltage Swing High
Output Voltage Swing Low
RL = 2 kΩ to V+/2
LMV793
LMV794
75
82
35
75
82
RL = 10 kΩ to V+/2
RL = 2 kΩ to V+/2
25
65
71
mV from
either rail
LMV793
LMV794
42
75
78
45
80
83
RL = 10 kΩ to V+/2
20
65
67
IOUT
Output Current
Sourcing to V−
VIN = 200 mV(7)
45
37
60
mA
mA
Sinking to V+
10
6
21
VIN = –200 mV(7)
IS
Supply Current per Amplifier
LMV793
1.15
1.30
1.40
1.75
LMV794 per Channel
1.70
2.05
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) Offset voltage average drift is determined by dividing the change in VOS by temperature change.
(5) Positive current corresponds to current flowing into the device.
(6) This parameter is specified by design and/or characterization and is not tested in production.
(7) The short circuit test is a momentary test, the short circuit duration is 1.5 ms.
4
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMV793 LMV794
LMV793, LMV794
www.ti.com
SNOSAX6D –MARCH 2007–REVISED MARCH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2 = VO. Boldface limits apply at
the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(2)
(3)
(2)
SR
Slew Rate
AV = +10, Rising (10% to 90%)
AV = +10, Falling (90% to 10%)
AV = +10, RL = 10 kΩ
f = 1 kHz
35
28
V/μs
GBW
en
Gain Bandwidth
88
MHz
nV/√Hz
pA/√Hz
%
Input Referred Voltage Noise Density
Input Referred Current Noise Density
5.8
0.01
0.01
in
f = 1 kHz
THD+N Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, RL = 600Ω
Connection Diagram
1
8
1
5
+
N/C
N/C
1
8
7
6
5
+
V
OUTPUT
OUT A
V
2
3
4
-
2
3
4
7
6
5
-IN A
OUT B
-IN B
+
+
-IN
V
2
3
-
-
V
+IN A
-
+
-
+
+
+IN
OUTPUT
N/C
-
4
+IN B
V
-IN
+IN
-
V
Figure 3. 5-Pin SOT-23 (LMV793)
Top View
Figure 4. 8-Pin SOIC (LMV793)
Top View
Figure 5. 8-Pin SOIC/VSSOP
(LMV794)
Top View
Copyright © 2007–2013, Texas Instruments Incorporated
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Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2.
Supply Current vs. Supply Voltage (LMV793)
Supply Current vs. Supply Voltage (LMV794)
2
2
1.6
1.2
125°C
1.6
125°C
25°C
25°C
1.2
-40°C
0.8
0.8
0.4
0
-40°C
0.4
0
2.5
3.5
4.5
5.5 6.0
1.5
2.5
3.5
4.5
5.5
6
1.5
+
+
V
(V)
V
(V)
Figure 6.
Figure 7.
VOS vs. VCM
VOS vs. VCM
0.5
0.6
0.55
0.5
+
+
V
= 2.5V
V
= 1.8V
0.45
0.4
125°C
0.45
0.4
-40°C
0.35
0.3
0.35
0.3
25°C
25°C
0.25
0.25
0.2
0.2
-40°C
125°C
0.15
0.1
0.15
0.1
-0.3
0
0.3
0.6
(V)
0.9
1.2
-0.3
0.4
1.1
1.8
V
CM
(V)
V
CM
Figure 8.
Figure 9.
VOS vs. VCM
VOS vs. Supply Voltage
0.5
0.45
0.4
0.5
0.45
0.4
+
V
= 5V
-40°C
-40°C
0.35
0.3
0.35
0.3
25°C
0.25
0.2
0.25
0.2
25°C
0.15
0.1
0.15
0.1
125°C
125°C
2.4
0.05
0
0.05
0
1.5
2.5
3.5
4.5
5.5 6.0
-0.3
0.6
1.5
3.3
4.2
+
V
CM
(V)
V
(V)
Figure 10.
Figure 11.
6
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SNOSAX6D –MARCH 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2.
Slew Rate vs. Supply Voltage
Input Bias Current vs. VCM
36
34
32
1.5
+
V
= 5V
1
-40°C
25°C
RISING EDGE
0.5
0
30
28
26
-0.5
-1
-1.5
-2
FALLING EDGE
24
22
-2.5
-3
1.5
2.5
3.5
4.5
5.5
0
1
2
3
4
+
V
CM
(V)
V
(V)
Figure 12.
Figure 13.
Input Bias Current vs. VCM
Sourcing Current vs. Supply Voltage
80
70
60
50
40
30
+
V
= 5V
125°C
20
10
-40°C
125°C
50
40
30
25°C
0
85°C
-10
-20
20
-30
10
0
-40
-50
1
2
3
4
5
6
0
1
2
3
4
+
V
(V)
CM
V
(V)
Figure 14.
Figure 15.
Sinking Current vs. Supply Voltage
Sourcing Current vs. Output Voltage
35
30
70
60
125°C
125°C
25°C
25
20
15
10
50
40
30
20
-40°C
25°C
-40°C
5
0
10
0
1
2
3
4
5
6
0
1
2
3
4
5
+
V
(V)
OUT
V
(V)
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2.
Sinking Current vs. Output Voltage
Positive Output Swing vs. Supply Voltage
40
35
30
25
20
15
10
30
25
R
= 10 kW
LOAD
125°C
125°C
20
15
10
25°C
25°C
-40°C
-40°C
5
0
5
0
1.8
2.5
3.2
4.6
5.3
6
3.9
+
0
1
2
3
4
5
V
(V)
V
(V)
OUT
Figure 18.
Figure 19.
Negative Output Swing vs. Supply Voltage
Positive Output Swing vs. Supply Voltage
25
50
-40°C
45
25°C
20
125°C
40
25°C
35
15
30
25
125°C
10
5
20
-40°C
15
10
5
R
= 10 kW
LOAD
R
= 2 kW
LOAD
0
1.8
0
1.8
2.5
3.2
3.9
+
4.6
5.3
6
2.5
3.2
3.9
+
4.6
5.3
6
V
(V)
V
(V)
Figure 20.
Figure 21.
Positive Output Swing vs. Supply Voltage
Negative Output Swing vs. Supply Voltage
100
90
80
70
60
50
40
30
20
10
0
50
R
= 600W
-40°C
LOAD
45
25°C
40
125°C
-40°C
35
125°C
25°C
30
25
20
15
10
5
R
= 2 kW
LOAD
0
1.8
1.8
2.5
3.2
3.9
4.6
5.3
6
2.5
3.2
3.9
+
4.6
5.3
6
+
V
(V)
V
(V)
Figure 22.
Figure 23.
8
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SNOSAX6D –MARCH 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2.
Negative Output Swing vs. Supply Voltage
Time Domain Voltage Noise
120
V
V
= ±2.5V
S
125°C
R
LOAD
= 600W
25°C
= 0.0V
CM
100
80
60
40
20
0
-40°C
1S/DIV
1.8
2.5
3.2
3.9
+
4.6
5.3
6
V
(V)
Figure 24.
Figure 25.
Input Referred Voltage Noise vs. Frequency
Overshoot and Undershoot vs. CLOAD
1000
70
60
50
US%
5V
100
OS%
40
30
20
2.5V
10
10
0
1
0.1
1
10
100
1k
10k
0
20
40
80
100 120
60
FREQUENCY (Hz)
C
LOAD
(pF)
Figure 26.
Figure 27.
THD+N vs. Frequency
THD+N vs. Frequency
0.04
0.05
R
L
= 600W
R
L
= 600W
0.04
0.03
0.02
0.01
0
0.03
0.02
0.01
+
V
V
A
= 2.5V
= 1 V
O
V
PP
+
V
V
A
= 5V
= +10
= 4 V
O
V
PP
= +10
R
L
= 100 kW
R
L
= 100 kW
0
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 28.
Figure 29.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2.
THD+N vs. Peak-to-Peak Output Voltage (VOUT
-40
)
THD+N vs. Peak-to-Peak Output Voltage (VOUT)
-40
-50
-60
-70
-50
-60
R
L
= 600W
R
= 600W
L
-70
-80
V+ = 2.5V
f = 1 kHz
-80 V+ = 5V
f = 1 kHz
R = 100 kW
L
A
= +10
R
L
= 100 kW
A
= +10
V
V
-90
0.01
0.01
0.1
1
10
0.1
1
10
OUTPUT AMPLITUDE (V
)
PP
OUTPUT AMPLITUDE (V
)
PP
Figure 30.
Figure 31.
Open Loop Gain and Phase
Closed Loop Output Impedance vs. Frequency
1000
100
80
60
40
20
100
80
PHASE
100
10
1
60
GAIN
40
20
+
V
= 5V
0
0
C
R
= 20 pF
= 2 kW, 10 kW
L
L
-20
100M
0.1
10k
-20
100k
1M
10M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32.
Figure 33.
Small Signal Transient Response, AV = +10
Large Signal Transient Response, AV = +10
V = 100 mV
IN PP
V
= 2 mV
PP
IN
f = 1 MHz, A = +10
V
f = 1 MHz, A = +10
V
+
+
V
= 2.5V, C = 10 pF
L
V
= 5V, C = 10 pF
L
100 ns/DIV
100 ns/DIV
Figure 34.
Figure 35.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, V– = 0, V+ = Supply Voltage = 5V, VCM = V+/2.
Small Signal Transient Response, AV = +10
Large Signal Transient Response, AV = +10
V
= 2 mV
PP
V
= 100 mV
IN PP
IN
f = 1 MHz, A = +10
V
f = 1 MHz, A = +10
V
+
+
V
= 2.5V, C = 10 pF
V
= 5V, C = 10 pF
L
L
100 ns/DIV
100 ns/DIV
Figure 36.
Figure 37.
PSRR vs. Frequency
CMRR vs. Frequency
120
100
100
-PSRR, 5V
90
80
70
60
50
40
-PSRR, 2.5V
+
V
= 2.5V
+PSRR, 5V
+PSRR, 2.5V
80
60
40
20
+
V
= 5V
100k
0
10
10k
1M
100
1k
10k
FREQUENCY (Hz)
Figure 38.
100k
1M
100
1k
10M
FREQUENCY (Hz)
Figure 39.
Input Common Mode Capacitance vs. VCM
25
+
V
= 5V
20
15
10
5
0
0
1
2
3
4
V
CM
(V)
Figure 40.
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APPLICATION INFORMATION
ADVANTAGES OF THE LMV793/LMV794
Wide Bandwidth at Low Supply Current
The LMV793/LMV794 are high performance op amps that provide a GBW of 88 MHz with a gain of 10 while
drawing a low supply current of 1.15 mA. This makes them ideal for providing wideband amplification in data
acquisition applications.
With the proper external compensation the LMV793/LMV794 can be operated at gains of ±1 and still maintain
much faster slew rates than comparable unity gain stable amplifiers. The increase in bandwidth and slew rate is
obtained without any additional power consumption over the LMV796.
Low Input Referred Noise and Low Input Bias Current
The LMV793/LMV794 have a very low input referred voltage noise density (5.8 nV/√Hz at 1 kHz). A CMOS input
stage ensures a small input bias current (100 fA) and low input referred current noise (0.01 pA/√Hz). This is very
helpful in maintaining signal integrity, and makes the LMV793/LMV794 ideal for audio and sensor based
applications.
Low Supply Voltage
The LMV793 and LMV794 have performance specified at 2.5V and 5V supply. These parts are specified to be
operational at all supply voltages between 2.0V and 5.5V, for ambient temperatures ranging from −40°C to
125°C, thus utilizing the entire battery lifetime. The LMV793/LMV794 are also specified to be operational at 1.8V
supply voltage, for temperatures between 0°C and 125°C optimizing their usage in low-voltage applications.
RRO and Ground Sensing
Rail-to-rail output swing provides the maximum possible dynamic range. This is particularly important when
operating at low supply voltages. An innovative positive feedback scheme is used to boost the current drive
capability of the output stage. This allows the LMV793/LMV794 to source more than 40 mA of current at 1.8V
supply. This also limits the performance of these parts as comparators, and hence the usage of the LMV793 and
the LMV794 in an open-loop configuration is not recommended. The input common-mode range includes the
negative supply rail which allows direct sensing at ground in single supply operation.
Small Size
The small footprint of the LMV793 and the LMV794 package saves space on printed circuit boards, and enables
the design of smaller electronic products, such as cellular phones, pagers, or other portable systems. Long
traces between the signal source and the op amp make the signal path more susceptible to noise pick up.
The physically smaller LMV793/LMV794 packages, allow the op amp to be placed closer to the signal source,
thus reducing noise pickup and maintaining signal integrity.
USING THE DECOMPENSATED LMV793
Advantages of Decompensated Op Amps
A unity gain stable op amp, which is fully compensated, is designed to operate with good stability down to gains
of ±1. The large amount of compensation does provide an op amp that is relatively easy to use; however, a
decompensated op amp is designed to maximize the bandwidth and slew rate without any additional power
consumption. This can be very advantageous.
The LMV793/LMV794 require a gain of ±10 to be stable. However, with an external compensation network (a
simple RC network) these parts can be stable with gains of ±1 and still maintain the higher slew rate. Looking at
the Bode plots for the LMV793 and its closest equivalent unity gain stable op amp, the LMV796, one can clearly
see the increased bandwidth of the LMV793. Both plots are taken with a parallel combination of 20 pF and 10 kΩ
for the output load.
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100
80
100
80
PHASE
60
40
60
40
20
0
GAIN
20
0
-20
100M
-20
1M
FREQUENCY (Hz)
1k
10k
100k
10M
Figure 41. LMV793 AVOL vs. Frequency
100
80
100
80
60
40
60
40
20
0
20
0
-20
100M
-20
1M
100k
FREQUENCY (Hz)
10M
1k
10k
Figure 42. LMV796 AVOL vs. Frequency
Figure 41 shows the much larger 88 MHz bandwidth of the LMV793 as compared to the 17 MHz bandwidth of
the LMV796 shown in Figure 42. The decompensated LMV793 has five times the bandwidth of the LMV796.
What is a Decompensated Op Amp?
The differences between the unity gain stable op amp and the decompensated op amp are shown in Figure 43.
This Bode plot assumes an ideal two pole system. The dominant pole of the decompensated op amp is at a
higher frequency, f1, as compared to the unity-gain stable op amp which is at fd as shown in Figure 43. This is
done in order to increase the speed capability of the op amp while maintaining the same power dissipation of the
unity gain stable op amp. The LMV793/LMV794 have a dominant pole at 1.6 kHz. The unity gain stable
LMV796/LMV797 have their dominant pole at 300 Hz.
DECOMPENSATED OP AMP
A
OL
UNITY-GAIN STABLE OP AMP
G
min
f
GBWP
fu
f
1
f
f
d
2
'
f
u
Figure 43. Open Loop Gain for Unity-Gain Stable Op Amp and Decompensated Op Amp
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Having a higher frequency for the dominate pole will result in:
1. The DC open-loop gain (AVOL) extending to a higher frequency.
2. A wider closed loop bandwidth.
3. Better slew rate due to reduced compensation capacitance within the op amp.
The second open loop pole (f2) for the LMV793/LMV794 occurs at 45 MHz. The unity gain (fu’) occurs after the
second pole at 51 MHz. An ideal two pole system would give a phase margin of 45° at the location of the second
pole. The LMV793/LMV794 have parasitic poles close to the second pole, giving a phase margin closer to 0°.
Therefore it is necessary to operate the LMV793/LMV794 at a closed loop gain of 10 or higher, or to add external
compensation in order to assure stability.
For the LMV796, the gain bandwidth product occurs at 17 MHz. The curve is constant from fd to fu which occurs
before the second pole.
For the LMV793/LMV794, the GBW = 88 MHz and is constant between f1 and f2. The second pole at f2 occurs
before AVOL = 1. Therefore fu’ occurs at 51 MHz, well before the GBW frequency of 88 MHz. For decompensated
op amps the unity gain frequency and the GBW are no longer equal. Gmin is the minimum gain for stability and
for the LMV793/LMV794 this is a gain of 18 to 20 dB.
Input Lead-Lag Compensation
The recommended technique which allows the user to compensate the LMV793/LMV794 for stable operation at
any gain is lead-lag compensation. The compensation components added to the circuit allow the user to shape
the feedback function to make sure there is sufficient phase margin when the loop gain is as low as 0 dB and still
maintain the advantages over the unity gain op amp. Figure 44 shows the lead-lag configuration. Only RC and C
are added for the necessary compensation.
R
F
R
IN
R
C
LMV793
C
Figure 44. LMV793 with Lead-Lag Compensation for Inverting Configuration
To cover how to calculate the compensation network values it is necessary to introduce the term called the
feedback factor or F. The feedback factor F is the feedback voltage VA-VB across the op amp input terminals
relative to the op amp output voltage VOUT
.
- V
F = V
A
B
V
OUT
(1)
From feedback theory the classic form of the feedback equation for op amps is:
VOUT
VIN
A
=
1 + AF
(2)
A is the open loop gain of the amplifier and AF is the loop gain. Both are highly important in analyzing op amps.
Normally AF >>1 and so the above equation reduces to:
VOUT
VIN
1
F
=
(3)
Deriving the equations for the lead-lag compensation is beyond the scope of this datasheet. The derivation is
based on the feedback equations that have just been covered. The inverse of feedback factor for the circuit in
Figure 44 is:
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«
«
∆
∆
≈
≈
≈
∆
∆ ∆1 + s(Rc + RIN || RF) C
RF
1
∆∆1 +
=
∆
≈
1 + sRcC
RIN
F
«
«
(4)
(5)
where 1/F's pole is located at
1
fp =
2pRcC
1/F's zero is located at
1
fz =
2p(Rc + RIN || RF)C
(6)
(7)
RF
1
F
1 +
=
RIN
f = 0
The circuit gain for Figure 44 at low frequencies is −RF/RIN, but F, the feedback factor is not equal to the circuit
gain. The feedback factor is derived from feedback theory and is the same for both inverting and non-inverting
configurations. Yes, the feedback factor at low frequencies is equal to the gain for the non-inverting configuration.
«
«
∆
∆
≈
∆
≈
∆
≈
RIN || RF
RC
RF
1
F
∆ ∆
1 +
1 +
=
∆
«
≈ ∆
«
RIN
f =
Ñ
(8)
From this formula, we can see that
•
•
•
•
1/F's zero is located at a lower frequency compared with 1/F's pole.
1/F's value at low frequency is 1 + RF/RIN.
This method creates one additional pole and one additional zero.
This pole-zero pair will serve two purposes:
–
To raise the 1/F value at higher frequencies prior to its intercept with A, the open loop gain curve, in order
to meet the Gmin = 10 requirement. For the LMV793/LMV794 some overcompensation will be necessary
for good stability.
–
To achieve the previous purpose above with no additional loop phase delay.
Please note the constraint 1/F ≥ Gmin needs to be satisfied only in the vicinity where the open loop gain A and
1/F intersect; 1/F can be shaped elsewhere as needed. The 1/F pole must occur before the intersection with the
open loop gain A.
In order to have adequate phase margin, it is desirable to follow these two rules:
1. 1/F and the open loop gain A should intersect at the frequency where there is a minimum of 45° of phase
margin. When over-compensation is required the intersection point of A and 1/F is set at a frequency where
the phase margin is above 45°, therefore increasing the stability of the circuit.
2. 1/F’s pole should be set at least one decade below the intersection with the open loop gain A in order to take
advantage of the full 90° of phase lead brought by 1/F’s pole which is F’s zero. This ensures that the effect of
the zero is fully neutralized when the 1/F and A plots intersect each other.
Calculating Lead-Lag Compensation for LMV793/LMV794
Figure 45 is the same plot as Figure 41, but the AVOL and phase curves have been redrawn as smooth lines to
more readily show the concepts covered, and to clearly show the key parameters used in the calculations for
lead-lag compensation.
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100
80
PHASE
ADDITIONAL
COMPENSATION
A
VOL
60
40
20
45°PHASE
MARGIN
1
F
with ADDITIONAL
COMPENSATION
2nd POLE
f
2
1
F
0
GBP
-20
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 45. LMV793/LMV794 Simplified Bode Plot
To obtain stable operation with gains under 10 V/V the open loop gain margin must be reduced at high
frequencies to where there is a 45° phase margin when the gain margin of the circuit with the external
compensation is 0 dB. The pole and zero in F, the feedback factor, control the gain margin at the higher
frequencies. The distance between F and AVOL is the gain margin; therefore, the unity gain point (0 dB) is where
F crosses the AVOL curve.
For the example being used RIN = RF for a gain of −1. Therefore F = 6 dB at low frequencies. At the higher
frequencies the minimum value for F is 18 dB for 45° phase margin. From Equation 8 we have the following
relationship:
«
«
∆
∆
≈
∆
≈
RIN || RF
RC
RF
≈ ∆ = 18 dB = 7.9
∆
∆
≈ 1 +
1 +
∆
«
∆
RIN
«
(9)
Now set RF = RIN = R. With these values and solving for RC we have RC = R/5.9. Note that the value of C does
not affect the ratio between the resistors. Once the value of the resistors are set, then the position of the pole in
F must be set. A 2 kΩ resistor is used for RF and RIN in this design. Therefore the value for RC is set at 330Ω,
the closest standard value for 2 kΩ/5.9.
Rewriting Equation 5 to solve for the minimum capacitor value gives the following equation:
C = 1/(2πfpRC)
(10)
The feedback factor curve, F, intersects the AVOL curve at about 12 MHz. Therefore the pole of F should not be
any larger than 1.2 MHz. Using this value and Rc = 330Ω the minimum value for C is 390 pF. Figure 46 shows
that there is too much overshoot, but the part is stable. Increasing C to 2.2 nF did not improve the ringing, as
shown in Figure 47.
Figure 46. First Try at Compensation, Gain = −1
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Figure 47. C Increased to 2.2 nF, Gain = −1
Some over-compensation appears to be needed for the desired overshoot characteristics. Instead of intersecting
the AVOL curve at 18 dB, 2 dB of over-compensation will be used, and the AVOL curve will be intersected at 20
dB. Using Equation 8 for 20 dB, or 10 V/V, the closest standard value of RC is 240Ω. The following two
waveforms show the new resistor value with C = 390 pF and 2.2 nF. Figure 49 shows the final compensation and
a very good response for the 1 MHz square wave.
Figure 48. RC = 240Ω and C = 390 pF, Gain = −1
Figure 49. RC = 240Ω and C = 2.2 nF, Gain = −1
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To summarize, the following steps were taken to compensate the LMV793 for a gain of −1:
1. Values for Rc and C were calculated from the Bode plot to give an expected phase margin of 45°. The values
were based on RIN = RF = 2 kΩ. These calculations gave Rc = 330Ω and C = 390 pF.
2. To reduce the ringing C was increased to 2.2 nF which moved the pole of F, the feedback factor, farther
away from the AVOL curve.
3. There was still too much ringing so 2 dB of over-compensation was added to F. This was done by
decreasing RC to 240Ω.
The LMV796 is the fully compensated part which is comparable to the LMV793. Using the LMV796 in the same
setup, but removing the compensation network, provide the response shown in Figure 50 .
Figure 50. LMV796 Response
For large signal response the rise and fall times are dominated by the slew rate of the op amps. Even though
both parts are quite similar the LMV793 will give rise and fall times about 2.5 times faster than the LMV796. This
is possible because the LMV793 is a decompensated op amp and even though it is being used at a gain of −1,
the speed is preserved by using a good technique for external compensation.
Non-Inverting Compensation
For the non-inverting amp the same theory applies for establishing the needed compensation. When setting the
inverting configuration for a gain of −1, F has a value of 2. For the non-inverting configuration both F and the
actual gain are the same, making the non-inverting configuration more difficult to compensate. Using the same
circuit as shown in Figure 44, but setting up the circuit for non-inverting operation (gain of +2) results in similar
performance as the inverting configuration with the inputs set to half the amplitude to compensate for the
additional gain. Figure 51 below shows the results.
Figure 51. RC = 240Ω and C = 2.2 nF, Gain = +2
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Figure 52. LMV796 Response Gain = +2
The response shown in Figure 51 is close to the response shown in Figure 49. The part is actually slightly faster
in the non-inverting configuration. Decreasing the value of RC to around 200Ω can decrease the negative
overshoot but will have slightly longer rise and fall times. The other option is to add a small resistor in series with
the input signal. Figure 52 shows the performance of the LMV796 with no compensation. Again the
decompensated parts are almost 2.5 times faster than the fully compensated op amp.
The most difficult op amp configuration to stabilize is the gain of +1. With proper compensation the
LMV793/LMV794 can be used in this configuration and still maintain higher speeds than the fully compensated
parts. Figure 53 shows the gain = 1, or the buffer configuration, for these parts.
R
F
-
R
C
LMV793
R
P
C
+
Figure 53. LMV793 with Lead-Lag Compensation for Non-Inverting Configuration
Figure 53 is the result of using Equation 8 and additional experimentation in the lab. RP is not part of Equation 8,
but it is necessary to introduce another pole at the input stage for good performance at gain = +1. Equation 8 is
shown below with RIN = ∞.
«
∆
≈
∆
RF
Rc
≈ ∆ = 18 dB = 7.9
1 +
∆
«
(11)
Using 2 kΩ for RF and solving for RC gives RC = 2000/6.9 = 290Ω. The closest standard value for RC is 300Ω.
After some fine tuning in the lab RC = 330Ω and RP = 1.5 kΩ were choosen as the optimum values. RP together
with the input capacitance at the non-inverting pin inserts another pole into the compensation for the
LMV793/LMV794. Adding this pole and slightly reducing the compensation for 1/F (using a slightly higher resistor
value for RC) gives the optimum response for a gain of +1. Figure 54 is the response of the circuit shown in
Figure 53. Figure 55 shows the response of the LMV796 in the buffer configuration with no compensation and RP
= RF = 0.
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Figure 54. RC = 330Ω and C = 10 nF, Gain = +1
Figure 55. LMV796 Response Gain = +1
With no increase in power consumption the decompensated op amp offers faster speed over the compensated
equivalent part. These examples used RF = 2 kΩ. This value is high enough to be easily driven by the
LMV793/LMV794, yet small enough to minimize the effects from the parasitic capacitance of both the PCB and
the op amp.
Note: When using the LMV793/LMV794, proper high frequency PCB layout must be followed. The GBW of these
parts is 88 MHz, making the PCB layout significantly more critical than when using the compensated
counterparts which have a GBW of 17 MHz.
TRANSIMPEDANCE AMPLIFIER
An excellent application for either the LMV793 or the LMV794 is as a transimpedance amplifier. With a GBW
product of 88 MHz these parts are ideal for high speed data transmission by light. The circuit shown on the front
page of the datasheet is the circuit used to test the LMV793/LMV794 as transimpedance amplifiers. The only
change is that VB is tied to the VCC of the part, thus the direction of the diode is reversed from the circuit shown
on the front page.
Very high speed components were used in testing to check the limits of the LMV793/LMV794 in a
transimpedance configuration. The photo diode part number is PIN-HR040 from OSI Optoelectronics. The diode
capacitance for this part is only about 7 pF for the 2.5V bias used (VCC to virtual ground). The rise time for this
diode is 1 nsec. A laser diode was used for the light source. Laser diodes have on and off times under 5 nsec.
The speed of the selected optical components allowed an accurate evaluation of the LMV793 as a
transimpedance amplifier. TIs Evaluation Board for decompensated op amps, PN 551013271-001 A, was used
and only minor modifications were necessary and no traces had to be cut.
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C
F
2.5V
2.5V
R
F
D
PHOTO
-
V
LMV793
C
CM
C
D
OUT
+
-2.5V
Figure 56. Transimpedance Amplifier
Figure 56 is the complete schematic for a transimpedance amplifier. Only the supply bypass capacitors are not
shown. CD represents the photo diode capacitance which is given on its datasheet. CCM is the input common
mode capacitance of the op amp and, for the LMV793 it is shown in the last drawing of the Typical Performance
Characteristics section of this datasheet. In Figure 56 the inverting input pin of the LMV793 is kept at virtual
ground. Even though the diode is connected to the 2.5V line, a power supply line is AC ground, thus CD is
connected to ground.
Figure 57 shows the schematic needed to derive F, the feedback factor, for a transimpedance amplifier. In this
figure CD + CCM = CIN. Therefore it is critical that the designer knows the diode capacitance and the op amp input
capacitance. The photo diode is close to an ideal current source once its capacitance is included in the model.
What kind of circuit is this? Without CF there is only an input capacitor and a feedback resistor. This circuit is a
differentiator! Remember, differentiator circuits are inherently unstable and must be compensated. In this case CF
compensates the circuit.
C
F
R
F
V
A
-
I
V
OUT
DIODE
C
IN
LMV793
+
Figure 57. Transimpedance Feedback Model
Using feedback theory, F = VA/VOUT, this becomes a voltage divider giving the following equation:
1 + sCFRF
F =
1 + sRF (CF + CIN)
(12)
The noise gain is 1/F. Because this is a differentiator circuit, a zero must be inserted. The location of the zero is
given by:
1
“
=
‘z
1 + sRF (CF + CIN)
(13)
CF has been added for stability. The addition of this part adds a pole to the circuit. The pole is located at:
1
“
=
p
‘
1 + sCFRF
(14)
To attain maximum bandwidth and still have good stability the pole is to be located on the open loop gain curve
which is A. If additional compensation is required one can always increase the value of CF, but this will also
reduce the bandwidth of the circuit. Therefore A = 1/F, or AF = 1. For A the equation is:
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“
wGBW
w
‘
GBW
A =
=
“
‘
(15)
The expression fGBW is the gain bandwidth product of the part. For a unity gain stable part this is the frequency
where A = 1. For the LMV793 fGBW = 88 MHz. Multiplying A and F results in the following equation:
‘“GBW
1 + sCFRF
AF “
x
=
=
‘P
“
‘
1 + sRF (CF + CIN)
«
2
≈
∆
∆
≈
∆ CFRF
1 +
‘“GBW
«∆ CFRF
x
= 1
“
‘
«
2
≈
∆
∆
≈
RF (CF + CIN)
CFRF
∆
∆
«
1 +
(16)
For the above equation s = jω. To find the actual amplitude of the equation the square root of the square of the
real and imaginary parts are calculated. At the intersection of F and A, we have:
1
w
=
CFRF
(17)
After a bit of algebraic manipulation the above equation reduces to:
«
2
∆≈CF + CIN
∆
∆
≈
2 CF2
GBW RF
2
= 8p2
“
1 +
‘
∆
CF
«
(18)
In the above equation the only unknown is CF. In trying to solve this equation the fourth power of CF must be
dealt with. An excel spread sheet with this equation can be used and all the known values entered. Then through
iteration, the value of CF when both sides are equal will be found. That is the correct value for CF, and of course
the closest standard value is used for CF.
Before moving the lab, the transfer function of the transimpedance amplifier must be found and the units must be
in Ohms.
-RF
x
IDIODE
VOUT
=
1 + sCFRF
(19)
The LMV793 was evaluated for RF = 10 kΩ and 100 kΩ, representing a somewhat lower gain configuration and
with the 100 kΩ feedback resistor a fairly high gain configuration. The RF = 10 kΩ is covered first. Looking at the
Figure 39 chart for CCM for the operating point selected CCM = 15 pF. Note that for split supplies VCM = 2.5V, CIN
= 22 pF and fGBW = 88 MHz. Solving for CF the calculated value is 1.75 pF, so 1.8 pF is selected for use.
Checking the frequency of the pole finds that it is at 8.8 MHz, which is right at the minimum gain recommended
for this part. Some over compensation was necessary for stability and the final selected value for CF is 2.7 pF.
This moves the pole to 5.9 MHz. Figure 58 and Figure 59 show the rise and fall times obtained in the lab with a
1V output swing. The laser diode was difficult to drive due to thermal effects making the starting and ending point
of the pulse quite different, therefore the two separate scope pictures.
Figure 58. Fall Time
22
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMV793 LMV794
LMV793, LMV794
www.ti.com
SNOSAX6D –MARCH 2007–REVISED MARCH 2013
Figure 59. Rise Time
In Figure 58 the ringing and the hump during the on time is from the laser. The higher drive levels for the laser
gave ringing in the light source as well as light changing from the thermal characteristics. The hump is due to the
thermal characteristics.
Solving for CF using a 100 kΩ feedback resistor, the calculated value is 0.54 pF. One of the problems with more
gain is the very small value for CF. A 0.5 pF capacitor was used, its measured value being 0.64 pF. For the 0.64
pF location the pole is at 2.5 MHz. Figure 60 shows the response for a 1V output.
Figure 60. High Gain Response
A transimpedance amplifier is an excellent application for the LMV793. Even with the high gain using a 100 kΩ
feedback resistor, the bandwidth is still well over 1 MHz. Other than a little over compensation for the 10 kΩ
feedback resistor configuration using the LMV793 was quite easy. Of course a very good board layout was also
used for this test. For information on photo diodes please contact OSI Optoelectronics, (310) 978-0516. For
further information on transimpedance amplifiers please contact your Texas Instruments representative.
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: LMV793 LMV794
LMV793, LMV794
SNOSAX6D –MARCH 2007–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMV793 LMV794
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV793MA/NOPB
LMV793MAX/NOPB
ACTIVE
SOIC
SOIC
D
D
8
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LMV7
93MA
ACTIVE
2500 RoHS & Green
SN
LMV7
93MA
LMV793MF/NOPB
LMV793MFX/NOPB
LMV794MA/NOPB
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
1000 RoHS & Green
3000 RoHS & Green
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
AS4A
AS4A
95
RoHS & Green
LMV7
94MA
LMV794MAX/NOPB
ACTIVE
SOIC
D
8
2500 RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMV7
94MA
LMV794MM/NOPB
LMV794MMX/NOPB
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
1000 RoHS & Green
3500 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
AN4A
AN4A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV793MAX/NOPB
LMV793MF/NOPB
LMV793MFX/NOPB
LMV794MAX/NOPB
LMV794MM/NOPB
LMV794MMX/NOPB
SOIC
SOT-23
SOT-23
SOIC
D
8
5
5
8
8
8
2500
1000
3000
2500
1000
3500
330.0
178.0
178.0
330.0
178.0
330.0
12.4
8.4
6.5
3.2
3.2
6.5
5.3
5.3
5.4
3.2
3.2
5.4
3.4
3.4
2.0
1.4
1.4
2.0
1.4
1.4
8.0
4.0
4.0
8.0
8.0
8.0
12.0
8.0
Q1
Q3
Q3
Q1
Q1
Q1
DBV
DBV
D
8.4
8.0
12.4
12.4
12.4
12.0
12.0
12.0
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV793MAX/NOPB
LMV793MF/NOPB
LMV793MFX/NOPB
LMV794MAX/NOPB
LMV794MM/NOPB
LMV794MMX/NOPB
SOIC
SOT-23
SOT-23
SOIC
D
8
5
5
8
8
8
2500
1000
3000
2500
1000
3500
367.0
208.0
208.0
367.0
208.0
367.0
367.0
191.0
191.0
367.0
191.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
DBV
DBV
D
VSSOP
VSSOP
DGK
DGK
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMV793MA/NOPB
LMV794MA/NOPB
D
D
SOIC
SOIC
8
8
95
95
495
495
8
8
4064
4064
3.05
3.05
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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Copyright © 2023, Texas Instruments Incorporated
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