LMV821-N [TI]

LMV821-N/LMV822-N/LMV822-N-Q1/LMV824/LMV824-N-Q1 Single/Dual/Quad Low Voltage; LMV821 -N / LMV822 -N / LMV822 -N -Q1 / LMV824 / LMV824 -N -Q1单/双/四通道,低电压
LMV821-N
型号: LMV821-N
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

LMV821-N/LMV822-N/LMV822-N-Q1/LMV824/LMV824-N-Q1 Single/Dual/Quad Low Voltage
LMV821 -N / LMV822 -N / LMV822 -N -Q1 / LMV824 / LMV824 -N -Q1单/双/四通道,低电压

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LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
www.ti.com  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
LMV821-N/LMV822-N/LMV822-N-Q1/LMV824/LMV824-N-Q1 Single/Dual/Quad Low Voltage,  
Low Power, R-to-R Output, 5 MHz Op Amps  
Check for Samples: LMV821-N, LMV822-N, LMV822-N-Q1, LMV824-N, LMV824-N-Q1  
1
FEATURES  
APPLICATIONS  
2
(For Typical, 5 V Supply Values; Unless  
Otherwise Noted)  
Cordless Phones  
Cellular Phones  
Laptops  
LMV822-Q1 and LMV824-Q1 are available in  
Automotive AEC-Q100 Grade 1 version  
PDAs  
Ultra Tiny, SC70-5 Package 2.0 x 2.0 x 1.0 mm  
Guaranteed 2.5 V, 2.7 V and 5 V Performance  
Maximum VOS 3.5 mV (Guaranteed)  
VOS Temp. Drift 1 uV/° C  
PCMCIA  
DESCRIPTION  
The LMV821/LMV822/LMV824 bring performance  
and economy to low voltage / low power systems.  
With a 5 MHz unity-gain frequency and a guaranteed  
1.4 V/µs slew rate, the quiescent current is only 220  
µA/amplifier (2.7 V). They provide rail-to-rail (R-to-R)  
output swing into heavy loads (600 Guarantees).  
The input common-mode voltage range includes  
ground, and the maximum input offset voltage is  
3.5mV (Guaranteed). They are also capable of  
comfortably driving large capacitive loads (refer to the  
application notes section).  
GBW product @ 2.7 V 5 MHz  
ISupply @ 2.7 V 220 μA/Amplifier  
Minimum SR 1.4 V/us (Guaranteed)  
CMRR 90 dB  
PSRR 85 dB  
VCM @ 5V -0.3V to 4.3V  
Rail-to-Rail (R-to-R) Output Swing  
@600 Load 160 mV from rail  
@10 kLoad 55 mV from rail  
The LMV821 (single) is available in the ultra tiny  
SC70-5 package, which is about half the size of the  
previous title holder, the SOT23-5.  
Stable with High Capacitive Loads (Refer to  
Application Section)  
Overall,  
the  
LMV821/LMV822/LMV824  
(Single/Dual/Quad) are low voltage, low power,  
performance op amps, that can be designed into a  
wide range of applications, at an economical price.  
Telephone-line Transceiver for a PCMCIA Modem Card  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1999–2013, Texas Instruments Incorporated  
 
 
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)  
(3)  
ESD Tolerance  
Machine Model  
Human Body Model  
LMV822/824  
100V  
2000V  
1500V  
LMV821  
Differential Input Voltage  
± Supply Voltage  
5.5V  
Supply Voltage (V+–V −  
)
Output Short Circuit to V+(4)  
Output Short Circuit to V(4)  
Soldering Information  
Infrared or Convection (20 sec)  
Storage Temperature Range  
235°C  
65°C to 150°C  
150°C  
(5)  
Junction Temperature  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test  
conditions, see the Electrical Characteristics.  
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.  
(3) Human body model, 1.5 kin series wth 100 pF. Machine model, 200in series with 100 pF.  
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in  
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely  
affect reliability.  
(5) The maximum power dissipation is a function of TJ(max) , θJA, and TA. The maximum allowable power dissipation at any ambient  
temperature is PD = (TJ(max)–T A)/θJA. All numbers apply for packages soldered directly into a PC board.  
Operating Ratings(1)  
Supply Voltage  
2.5V to 5.5V  
Temperature Range  
LMV821, LMV822, LMV824  
LMV822-Q1, LMV824-Q1  
40°C T J 85°C  
40°C T J 125°C  
Thermal Resistance (θ JA  
)
Ultra Tiny SC70-5 Package, 5-Pin Surface Mount  
Tiny SOT23-5 Package, 5-Pin Surface Mount  
SOIC Package, 8-Pin Surface Mount  
VSSOP Package, 8-Pin Mini Surface Mount  
SOIC Package, 14-Pin Surface Mount  
TSSOP Package, 14-Pin  
440 °C/W  
265 °C/W  
190 °C/W  
235 °C/W  
145 °C/W  
155 °C/W  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test  
conditions, see the Electrical Characteristics.  
2
Submit Documentation Feedback  
Copyright © 1999–2013, Texas Instruments Incorporated  
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
 
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
www.ti.com  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
2.7V DC Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V = 0V, VCM = 1.0V, VO = 1.35V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
Typ  
LMV821/822/824  
Symbol  
VOS  
Parameter  
Input Offset Voltage  
Condition  
Units  
(1)  
(2)  
Limit  
3.5  
4
LMV821/822/822-Q1/824  
LMV824-Q1  
1
mV  
max  
1
1
5.5  
TCVOS  
IB  
Input Offset Voltage Average Drift  
Input Bias Current  
μV/°C  
90  
140  
nA  
max  
30  
0.5  
85  
IOS  
Input Offset Current  
30  
50  
nA  
max  
CMRR  
+PSRR  
Common Mode Rejection Ratio  
0V VCM 1.7V  
70  
68  
dB  
min  
Positive Power Supply Rejection  
Ratio  
1.7V V+ 4V, V- = 1V, VO = 0V,  
VCM = 0V  
LMV821/822/824/824-Q1  
75  
70  
dB  
min  
85  
85  
85  
LMV822-Q1  
-1.0V V- -3.3V, V+ = 1.7V, VO  
= 0V, VCM = 0V  
75  
dB  
PSRR  
Negative Power Supply Rejection  
Ratio  
73  
70  
dB  
min  
LMV821/822/824/824-Q1  
LMV822-Q1  
85  
-0.3  
2.0  
73  
-0.2  
1.9  
dB  
V
VCM  
Input Common-Mode Voltage  
Range  
For CMRR 50dB  
V
AV  
Large Signal Voltage Gain  
Sourcing, RL = 600to 1.35V,  
VO = 1.35V to 2.2V;  
LMV821/822/824  
90  
85  
dB  
min  
100  
100  
90  
LMV822-Q1/LMV824-Q1  
90  
dB  
Sinking, RL = 600to 1.35V,  
VO = 1.35V to 0.5V  
LMV821/822/824  
85  
80  
dB  
min  
LMV822-Q1/LMV824-Q1  
90  
85  
dB  
Sourcing, RL =2kto 1.35V,  
VO = 1.35V to 2.2V;  
LMV821/822/824  
95  
90  
dB  
min  
100  
100  
95  
LMV822-Q1/LMV824-Q1  
95  
dB  
Sinking, RL = 2kto 1.35V,  
VO = 1.35V to 0.5V  
LMV821/822/824  
90  
85  
dB  
min  
LMV822-Q1/LMV824-Q1  
95  
90  
dB  
V O  
Output Swing  
V+ = 2.7V, RL= 600to 1.35V  
2.50  
2.40  
V
min  
2.58  
0.20  
0.30  
V
max  
0.13  
2.66  
0.08  
V+ = 2.7V, RL= 2kto 1.35V  
2.60  
2.50  
V
min  
0.120  
0.200  
V
max  
IO  
Output Current  
Sourcing, VO = 0V  
Sinking, VO = 2.7V  
16  
26  
12  
12  
mA  
mA  
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are guaranteed by testing or statistical analysis.  
Copyright © 1999–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
 
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
www.ti.com  
2.7V DC Electrical Characteristics (continued)  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V = 0V, VCM = 1.0V, VO = 1.35V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
Typ  
LMV821/822/824  
Symbol  
IS  
Parameter  
Supply Current  
Condition  
LMV821 (Single)  
Units  
(1)  
(2)  
Limit  
0.3  
0.5  
mA  
max  
0.22  
0.45  
0.72  
LMV822 (Dual)  
LMV824 (Quad)  
0.6  
0.8  
mA  
max  
1.0  
1.2  
mA  
max  
2.5V DC Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.5V, V = 0V, VCM = 1.0V, VO = 1.25V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
Typ  
LMV821/822/824  
Symbol  
VOS  
Parameter  
Input Offset Voltage  
Condition  
Units  
(1)  
(2)  
Limit  
LMV821/822/822-Q1/824  
3.5  
4
mV  
max  
1
1
LMV824-Q1  
5.5  
V O  
Output Swing  
2.30  
2.20  
V
min  
2.37  
V+ = 2.5V, RL = 600to 1.25V  
0.20  
0.30  
V
max  
0.13  
2.46  
0.08  
2.40  
2.30  
V
min  
V+ = 2.5V, RL = 2kto 1.25V  
0.12  
0.20  
V
max  
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are guaranteed by testing or statistical analysis.  
2.7V AC Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 2.7V, V = 0V, VCM = 1.0V, VO = 1.35V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
(2)  
Typ  
LMV821/822/824 Limit  
Symbol  
Parameter  
Conditions  
Units  
(1)  
(3)  
(4)  
SR  
Slew Rate  
1.5  
5
V/μs  
MHz  
Deg.  
dB  
GBW  
Φm  
Gain-Bandwdth Product  
Phase Margin  
61  
10  
135  
28  
0.1  
Gm  
Gain Margin  
Amp-to-Amp Isolation  
Input-Related Voltage Noise  
Input-Referred Current Noise  
Total Harmonic Distortion  
dB  
en  
f = 1 kHz, VCM = 1V  
f = 1 kHz  
nV/Hz  
pA/Hz  
in  
THD  
f = 1 kHz, AV = 2,  
RL = 10 k, VO = 4.1 V PP  
0.01  
%
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are guaranteed by testing or statistical analysis.  
(3) V+ = 5V. Connected as voltage follower with 3V step input. Number specified is the slower of the positive and negative slew rates.  
(4) Input referred, V+ = 5V and RL = 100kconnected to 2.5V. Each amp excited in turn with 1 kHz to produce V O = 3 VPP  
.
4
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Copyright © 1999–2013, Texas Instruments Incorporated  
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
 
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
www.ti.com  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
5V DC Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 5V, V = 0V, VCM = 2.0V, VO = 2.5V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
Typ  
LMV821/822/824  
Symbol  
VOS  
Parameter  
Input Offset Voltage  
Condition  
Units  
(1)  
(2)  
Limit  
LMV821/822/822-Q1/824  
3.5  
4.0  
mV  
max  
1
LMV824-Q1  
1
1
5.5  
TCVOS  
IB  
Input Offset Voltage Average Drift  
Input Bias Current  
μV/°C  
100  
150  
nA  
max  
40  
0.5  
90  
IOS  
Input Offset Current  
30  
50  
nA  
max  
CMRR  
+PSRR  
Common Mode Rejection Ratio  
0V VCM 4.0V  
72  
70  
dB  
min  
Positive Power Supply Rejection  
Ratio  
1.7V V+ 4V, V- = 1V, VO = 0V,  
VCM = 0V  
LMV821/822/824/824-Q1  
75  
70  
dB  
min  
85  
85  
85  
LMV822-Q1  
-1.0V V- -3.3V, V+ = 1.7V, VO  
= 0V, VCM = 0V  
75  
dB  
PSRR  
Negative Power Supply Rejection  
Ratio  
73  
70  
dB  
min  
LMV821/822/824/824-Q1  
LMV822-Q1  
85  
-0.3  
4.3  
73  
-0.2  
4.2  
dB  
V
VCM  
Input Common-Mode Voltage  
Range  
For CMRR 50dB  
V
AV  
Large Signal Voltage Gain  
Sourcing, RL = 600to 1.35V,  
VO = 1.35V to 2.2V;  
LMV821/822/824  
95  
90  
dB  
min  
105  
105  
105  
105  
105  
105  
105  
LMV822-Q1/LMV824-Q1  
95  
dB  
Sinking, RL = 600to 1.35V,  
VO = 1.35V to 0.5V  
LMV821/822/824  
95  
90  
dB  
min  
LMV822-Q1/LMV824-Q1  
95  
dB  
Sourcing, RL =2kto 1.35V,  
VO = 1.35V to 2.2V;  
LMV821/822/824  
95  
90  
dB  
min  
LMV822-Q1/LMV824-Q1  
95  
dB  
Sinking, RL = 2kto 1.35V,  
VO = 1.35V to 0.5V  
LMV821/822/824  
95  
90  
dB  
min  
LMV822-Q1/LMV824-Q1  
105  
95  
dB  
V O  
Output Swing  
V+ = 5V,RL = 600to 2.5V  
4.75  
4.70  
4.84  
V
min  
V+ = 5V,RL = 600to 2.5V  
(LMV824-Q1)  
V+ = 5V,RL = 600to 2.5V  
4.84  
0.17  
0.17  
4.90  
0.10  
4.60  
0.250  
0.30  
V
max  
V+ = 5V,RL = 600to 2.5V  
(LMV824-Q1)  
V+ = 5V, RL = 2kto 2.5V  
0.40  
4.85  
4.80  
V
min  
0.15  
0.20  
V
max  
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are guaranteed by testing or statistical analysis.  
Copyright © 1999–2013, Texas Instruments Incorporated  
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5
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
 
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
www.ti.com  
5V DC Electrical Characteristics (continued)  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 5V, V = 0V, VCM = 2.0V, VO = 2.5V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
Typ  
LMV821/822/824  
Symbol  
IO  
Parameter  
Output Current  
Condition  
Sourcing, VO = 0V  
Units  
(1)  
(2)  
Limit  
20  
15  
mA  
min  
45  
40  
Sinking, VO = 5V  
LMV821 (Single)  
LMV822 (Dual)  
LMV824 (Quad)  
20  
15  
mA  
min  
IS  
Supply Current  
0.4  
0.6  
mA  
max  
0.30  
0.5  
1.0  
0.7  
0.9  
mA  
max  
1.3  
1.5  
mA  
max  
6
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Copyright © 1999–2013, Texas Instruments Incorporated  
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
www.ti.com  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
5V AC Electrical Characteristics  
Unless otherwise specified, all limits guaranteed for TJ = 25°C. V+ = 5V, V = 0V, VCM = 2V, VO = 2.5V and R L > 1 M.  
Boldface limits apply at the temperature extremes (40°C T J 85°C for LMV821/822/824 and 40°C T J 125°C for  
LMV822-Q1/LMV824-Q1).  
(2)  
Typ  
LMV821/822/824 Limit  
Symbol  
Parameter  
Conditions  
Units  
(1)  
(3)  
(4)  
SR  
Slew Rate  
2.0  
5.6  
67  
1.4  
V/μs min  
MHz  
GBW  
Φm  
Gain-Bandwdth Product  
Phase Margin  
Deg.  
Gm  
Gain Margin  
15  
dB  
Amp-to-Amp Isolation  
Input-Related Voltage Noise  
Input-Referred Current Noise  
Total Harmonic Distortion  
135  
24  
dB  
en  
f = 1 kHz, VCM = 1V  
f = 1 kHz  
nV/Hz  
pA/Hz  
in  
0.25  
THD  
f = 1 kHz, AV = 2,  
RL = 10 k, VO = 4.1 V PP  
0.01  
%
(1) Typical Values represent the most likely parametric norm.  
(2) All limits are guaranteed by testing or statistical analysis.  
(3) V+ = 5V. Connected as voltage follower with 3V step input. Number specified is the slower of the positive and negative slew rates.  
(4) Input referred, V+ = 5V and RL = 100kconnected to 2.5V. Each amp excited in turn with 1 kHz to produce V O = 3 VPP  
.
Copyright © 1999–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
www.ti.com  
Typical Performance Characteristics  
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
Supply Current  
Input Current  
vs.  
vs.  
Supply Voltage (LMV821)  
Temperature  
Figure 1.  
Figure 2.  
Sourcing Current  
vs.  
Output Voltage (VS = 2.7V)  
Sourcing Current  
vs  
Output Voltage (VS = 5V)  
Figure 3.  
Figure 4.  
Sinking Current  
vs.  
Output Voltage (VS = 2.7V)  
Sinking Current  
vs.  
Output Voltage (VS = 5V)  
Figure 5.  
Figure 6.  
8
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Copyright © 1999–2013, Texas Instruments Incorporated  
Product Folder Links: LMV821-N LMV822-N LMV822-N-Q1 LMV824-N LMV824-N-Q1  
LMV821-N, LMV822-N, LMV822-N-Q1  
LMV824-N, LMV824-N-Q1  
www.ti.com  
SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
Typical Performance Characteristics (continued)  
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
Output Voltage Swing  
Output Voltage Swing  
vs.  
Supply Voltage (RL = 2k)  
vs.  
Supply Voltage (RL = 10k)  
Figure 7.  
Figure 8.  
Output Voltage Swing  
vs.  
Supply Voltage (RL = 600)  
Output Voltage Swing  
vs.  
Load Resistance  
Figure 9.  
Figure 10.  
Input Voltage Noise  
vs.  
Input Current Noise  
vs.  
Frequency  
Frequency  
Figure 11.  
Figure 12.  
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LMV824-N, LMV824-N-Q1  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
Crosstalk Rejection  
+PSRR  
vs.  
Frequency  
vs.  
Frequency  
Figure 13.  
Figure 14.  
-PSRR  
vs.  
Frequency  
CMRR  
vs.  
Frequency  
Figure 15.  
Figure 16.  
Gain and Phase Margin  
vs.  
Input Voltage  
vs.  
Output Voltage  
Frequency  
(RL = 100k, 2k, 600) 2.7V  
Figure 17.  
Figure 18.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
Gain and Phase Margin  
Gain and Phase Margin  
vs.  
vs.  
Frequency  
(RL = 100k, 2k, 600) 5V  
Frequency  
(Temp.= 25, -40, 85°C, RL = 10k) 2.7V  
Figure 19.  
Figure 20.  
Gain and Phase Margin  
Gain and Phase Margin  
vs.  
vs.  
Frequency  
(Temp.= 25, -40, 85 °C, RL = 10k) 5V  
Frequency  
(CL = 100pF, 200pF, 0pF, RL = 10k)2.7V  
Figure 21.  
Figure 22.  
Gain and Phase Margin  
Gain and Phase Margin  
vs.  
vs.  
Frequency  
(CL = 100pF, 200pF, 0pF RL = 10k) 5V  
Frequency  
(CL = 100pF, 200pF, 0pF RL = 600) 2.7V  
Figure 23.  
Figure 24.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
Gain and Phase Margin  
vs.  
Slew Rate  
vs.  
Supply Voltage  
Frequency  
(CL = 100pF, 200pF, 0pF RL = 600) 5V  
Figure 25.  
Figure 26.  
Non-Inverting Large Signal Pulse Response  
Non-Inverting Small Signal Pulse Response  
Figure 27.  
Figure 28.  
Inverting Large Signal Pulse Response  
Inverting Small Signal Pulse Response  
Figure 29.  
Figure 30.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, VS = +5V, single supply, TA = 25°C.  
THD  
vs.  
Frequency  
Figure 31.  
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APPLICATION NOTE  
This application note is divided into two sections: design considerations and Application Circuits.  
DESIGN CONSIDERATIONS  
This section covers the following design considerations:  
1. Frequency and Phase Response Considerations  
2. Unity-Gain Pulse Response Considerations  
3. Input Bias Current Considerations  
FREQUENCY AND PHASE RESPONSE CONSIDERATIONS  
The relationship between open-loop frequency response and open-loop phase response determines the closed-  
loop stability performance (negative feedback). The open-loop phase response causes the feedback signal to  
shift towards becoming positive feedback, thus becoming unstable. The further the output phase angle is from  
the input phase angle, the more stable the negative feedback will operate. Phase Margin (φm) specifies this  
output-to-input phase relationship at the unity-gain crossover point. Zero degrees of phase-margin means that  
the input and output are completely in phase with each other and will sustain oscillation at the unity-gain  
frequency.  
The AC tables show φm for a no load condition. But φm changes with load. The Gain and Phase margin vs  
Frequency plots in the curve section can be used to graphically determine the φm for various loaded conditions.  
To do this, examine the phase angle portion of the plot, find the phase margin point at the unity-gain frequency,  
and determine how far this point is from zero degree of phase-margin. The larger the phase-margin, the more  
stable the circuit operation.  
The bandwidth is also affected by load. The graphs of Figure 32 and Figure 33 provide a quick look at how  
various loads affect the φm and the bandwidth of the LMV821/822/824 family. These graphs show capacitive  
loads reducing both φm and bandwidth, while resistive loads reduce the bandwidth but increase the φm. Notice  
how a 600resistor can be added in parallel with 220 picofarads capacitance, to increase the φm 20°(approx.),  
but at the price of about a 100 kHz of bandwidth.  
Overall, the LMV821/822/824 family provides good stability for loaded condition.  
Figure 32. Phase Margin vs Common Mode Voltage for Various Loads  
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Figure 33. Unity-Gain Frequency vs Common Mode Voltage for Various Loads  
UNITY GAIN PULSE RESPONSE CONSIDERATION  
A pull-up resistor is well suited for increasing unity-gain, pulse response stability. For example, a 600 pull-up  
resistor reduces the overshoot voltage by about 50%, when driving a 220 pF load. Figure 34 shows how to  
implement the pull-up resistor for more pulse response stability.  
Figure 34. Using a Pull-up Resistor at the Output for Stabilizing Capacitive Loads  
Higher capacitances can be driven by decreasing the value of the pull-up resistor, but its value shouldn't be  
reduced beyond the sinking capability of the part. An alternate approach is to use an isolation resistor as  
illustrated in Figure 35 .  
Figure 36 shows the resulting pulse response from a LMV824, while driving a 10,000 pF load through a 20Ω  
isolation resistor.  
Figure 35. Using an Isolation Resistor to Drive Heavy Capacitive Loads  
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Figure 36. Pulse Response per Figure 35  
INPUT BIAS CURRENT CONSIDERATION  
Input bias current (IB) can develop a somewhat significant offset voltage. This offset is primarily due to IB flowing  
through the negative feedback resistor, RF. For example, if IB is 90 nA (max @ room) and RF is 100 k, then an  
offset of 9 mV will be developed (VOS=IBx RF).Using a compensation resistor (RC), as shown in Figure 37,  
cancels out this affect. But the input offset current (IOS) will still contribute to an offset voltage in the same  
manner - typically 0.05 mV at room temp.  
Figure 37. Canceling the Voltage Offset Effect of Input Bias Current  
APPLICATION CIRCUITS  
This section covers the following application circuits:  
1. Telephone-Line Transceiver  
2. “Simple” Mixer (Amplitude Modulator)  
3. Dual Amplifier Active Filters (DAAFs)  
a. Low-Pass Filter (LPF)  
b. High-Pass Filter (HPF)  
4. Tri-level Voltage Detector  
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TELEPHONE-LINE TRANSCEIVER  
The telephone-line transceiver of Figure 38 provides a full-duplexed connection through a PCMCIA, miniature  
transformer. The differential configuration of receiver portion (UR), cancels reception from the transmitter portion  
(UT). Note that the input signals for the differential configuration of UR, are the transmit voltage (VT) and VT/2.  
This is because Rmatch is chosen to match the coupled telephone-line impedance; therefore dividing VT by two  
(assuming R1 >> Rmatch). The differential configuration of UR has its resistors chosen to cancel the VT and VT/2  
inputs according to the following equation:  
(1)  
Figure 38. Telephone-line Transceiver for a PCMCIA Modem Card  
Note that Cr is included for canceling out the inadequacies of the lossy, miniature transformer. Refer to  
application note AN-397 for detailed explanation.  
“SIMPLE” MIXER (AMPLITUDE MODULATOR)  
The mixer of Figure 39 is simple and provides a unique form of amplitude modulation. Vi is the modulation  
frequency (FM), while a +3V square-wave at the gate of Q1, induces a carrier frequency (FC). Q1 switches  
(toggles) U1 between inverting and non-inverting unity gain configurations. Offsetting a sine wave above ground  
at Vi results in the oscilloscope photo of Figure 40.  
The simple mixer can be applied to applications that utilize the Doppler Effect to measure the velocity of an  
object. The difference frequency is one of its output frequency components. This difference frequency magnitude  
(/FM-FC/) is the key factor for determining an object's velocity per the Doppler Effect. If a signal is transmitted to a  
moving object, the reflected frequency will be a different frequency. This difference in transmit and receive  
frequency is directly proportional to an object's velocity.  
Figure 39. Amplitude Modulator Circuit  
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Figure 40. Output signal per the Circuit of Figure 39  
DUAL AMPLIFIER ACTIVE FILTERS (DAAFs)  
The LMV822/24 bring economy and performance to DAAFs. The low-pass and the high-pass filters of Figure 41  
and Figure 42 (respectively), offer one key feature: excellent sensitivity performance. Good sensitivity is when  
deviations in component values cause relatively small deviations in a filter's parameter such as cutoff frequency  
(Fc). Single amplifier active filters like the Sallen-Key provide relatively poor sensitivity performance that  
sometimes cause problems for high production runs; their parameters are much more likely to deviate out of  
specification than a DAAF would. The DAAFs of Figure 41 and Figure 42 are well suited for high volume  
production.  
3 kHz Low-Pass Active Filter with a Butterworth Response and a Pass Band Gain of Times Two  
Figure 41. Dual Amplifier  
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300 Hz High-Pass Active Filter with a Butterworth Response and a Pass Band Gain of Times Two  
Figure 42. Dual Amplifier  
Table 1 provides sensitivity measurements for a 10 Mload condition. The left column shows the passive  
components for the 3 kHz low-pass DAAF. The third column shows the components for the 300 Hz high-pass  
DAAF. Their respective sensitivity measurements are shown to the right of each component column. Their values  
consists of the percent change in cutoff frequency (Fc) divided by the percent change in component value. The  
lower the sensitivity value, the better the performance.  
Each resistor value was changed by about 10 percent, and this measured change was divided into the measured  
change in Fc. A positive or negative sign in front of the measured value, represents the direction Fc changes  
relative to components' direction of change. For example, a sensitivity value of negative 1.2, means that for a 1  
percent increase in component value, Fc decreases by 1.2 percent.  
Note that this information provides insight on how to fine tune the cutoff frequency, if necessary. It should be also  
noted that R4 and R5 of each circuit also caused variations in the pass band gain. Increasing R4 by ten percent,  
increased the gain by 0.4 dB, while increasing R5 by ten percent, decreased the gain by 0.4 dB.  
Table 1.  
Component  
(LPF)  
Sensitivity  
(LPF)  
Component  
(HPF)  
Sensitivity  
(HPF)  
Ra  
C1  
R2  
R3  
C3  
R4  
R5  
-1.2  
-0.1  
-1.1  
+0.7  
-1.5  
-0.6  
+0.6  
Ca  
Rb  
R1  
C2  
R3  
R4  
R5  
-0.7  
-1.0  
+0.1  
-0.1  
+0.1  
-0.1  
+0.1  
Active filters are also sensitive to an op amp's parameters -Gain and Bandwidth, in particular. The LMV822/24  
provide a large gain and wide bandwidth. And DAAFs make excellent use of these feature specifications.  
Single Amplifier versions require a large open-loop to closed-loop gain ratio - approximately 50 to 1, at the Fc of  
the filter response. Figure 43 shows an impressive photograph of a network analyzer measurement (hp3577A).  
The measurement was taken from a 300 kHz version of Figure 41. At 300 kHz, the open-loop to closed-loop gain  
ratio @ Fc is about 5 to 1. This is 10 times lower than the 50 to 1 “rule of thumb” for Single Amplifier Active  
Filters.  
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Butterworth Response as Measured by the HP3577A Network Analyzer  
Figure 43. 300 kHz, Low-Pass Filter  
In addition to performance, DAAFs are relatively easy to design and implement. The design equations for the  
low-pass and high-pass DAAFs are shown below. The first two equation calculate the Fc and the circuit Quality  
Factor (Q) for the LPF (Figure 41). The second two equations calculate the Fc and Q for the HPF (Figure 42).  
(2)  
To simplify the design process, certain components are set equal to each other. Refer to Figure 41 and  
Figure 42. These equal component values help to simplify the design equations as follows:  
(3)  
To illustrate the design process/implementation, a 3 kHz, Butterworth response, low-pass filter DAAF (Figure 41)  
is designed as follows:  
1. Choose C1 = C3 = C = 1 nF  
2. Choose R4 = R5 = 1 kΩ  
3. Calculate Ra and R2 for the desired Fc as follows:  
(4)  
4. Calculate R3 for the desired Q. The desired Q for a Butterworth (Maximally Flat) response is 0.707 (45  
degrees into the s-plane). R3 calculates as follows:  
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(5)  
Notice that R3 could also be calculated as 0.707 of Ra or R2.  
The circuit was implemented and its cutoff frequency measured. The cutoff frequency measured at 2.92 kHz.  
The circuit also showed good repeatability. Ten different LMV822 samples were placed in the circuit. The  
corresponding change in the cutoff frequency was less than a percent.  
TRI-LEVEL VOLTAGE DETECTOR  
The tri-level voltage detector of Figure 44 provides a type of window comparator function. It detects three  
different input voltage ranges: Min-range, Mid-range, and Max-range. The output voltage (VO) is at VCC for the  
Min-range. VO is clamped at GND for the Mid-range. For the Max-range, VO is at Vee. Figure 45 shows a VO vs.  
VI oscilloscope photo per the circuit of Figure 44.  
Its operation is as follows: VI deviating from GND, causes the diode bridge to absorb IIN to maintain a clamped  
condition (VO= 0V). Eventually, IIN reaches the bias limit of the diode bridge. When this limit is reached, the  
clamping effect stops and the op amp responds open loop. The design equation directly preceding Figure 45,  
shows how to determine the clamping range. The equation solves for the input voltage band on each side GND.  
The mid-range is twice this voltage band.  
Figure 44. Tri-level Voltage Detector  
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'V  
'V  
OV  
-VIN  
+VIN  
OV  
Figure 45. X, Y Oscilloscope Trace showing VOUT vs VIN per the Circuit of Figure 44  
Connection Diagram  
Figure 46. 5-Pin SC70-5/SOT23-5  
Figure 47. 8-Pin SOIC/VSSOP  
Top View  
Top View  
Package Number DCK0005A/DBV0005A  
Package Number D0008A/DGK0008A  
Figure 48. 14-Pin SOIC/TSSOP  
Top View  
Package Number D0014A/PW0014A  
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SNOS032G AUGUST 1999REVISED NOVEMBER 2013  
REVISION HISTORY  
Changes from Revision D (February 2013) to Revision G  
Page  
Added new part ..................................................................................................................................................................... 1  
Added new device ................................................................................................................................................................ 1  
Added new device ................................................................................................................................................................ 2  
Added new device ................................................................................................................................................................ 3  
Added new device ................................................................................................................................................................ 4  
Added new device ................................................................................................................................................................ 5  
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PACKAGE OPTION ADDENDUM  
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8-Dec-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
1000  
1000  
(1)  
(2)  
(6)  
(3)  
(4/5)  
LMV821M5  
NRND  
ACTIVE  
SOT-23  
SOT-23  
DBV  
5
5
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
A14  
A14  
LMV821M5/NOPB  
DBV  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV821M5X  
NRND  
SOT-23  
SOT-23  
DBV  
DBV  
5
5
3000  
3000  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
A14  
A14  
LMV821M5X/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV821M7  
NRND  
SC70  
SC70  
DCK  
DCK  
5
5
1000  
1000  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
A15  
A15  
LMV821M7/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV821M7X  
NRND  
SC70  
SC70  
DCK  
DCK  
5
5
3000  
3000  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
A15  
A15  
LMV821M7X/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV822M  
NRND  
SOIC  
SOIC  
D
D
8
8
95  
95  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
LMV  
822M  
LMV822M/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV  
822M  
LMV822MM  
NRND  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
1000  
1000  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
V822  
V822  
LMV822MM/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV822MMX  
NRND  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
3500  
3500  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
V822  
V822  
LMV822MMX/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV822MX  
NRND  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
8
8
8
8
2500  
2500  
1000  
3500  
TBD  
Call TI  
CU SN  
CU SN  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
-40 to 125  
-40 to 125  
LMV  
822M  
LMV822MX/NOPB  
LMV822Q1MM/NOPB  
LMV822Q1MMX/NOPB  
D
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
LMV  
822M  
VSSOP  
VSSOP  
DGK  
DGK  
Green (RoHS  
& no Sb/Br)  
AKAA  
Green (RoHS  
& no Sb/Br)  
AKAA  
LMV824M  
NRND  
SOIC  
SOIC  
D
D
14  
14  
55  
55  
TBD  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
LMV824M  
LMV824M  
LMV824M/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
SN | CU SN  
Level-1-260C-UNLIM  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
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8-Dec-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
LMV824MT/NOPB  
LMV824MTX  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
PW  
14  
14  
14  
94  
Green (RoHS  
& no Sb/Br)  
CU SN  
Call TI  
CU SN  
Level-1-260C-UNLIM  
LMV824  
MT  
NRND  
PW  
PW  
2500  
2500  
TBD  
Call TI  
-40 to 85  
LMV824  
MT  
LMV824MTX/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
-40 to 85  
LMV824  
MT  
LMV824MX  
NRND  
SOIC  
SOIC  
D
D
14  
14  
2500  
2500  
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
LMV824M  
LMV824M  
LMV824MX/NOPB  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
LMV824Q1MA/NOPB  
LMV824Q1MAX/NOPB  
LMV824Q1MT/NOPB  
LMV824Q1MTX/NOPB  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
14  
14  
14  
14  
55  
2500  
94  
Green (RoHS  
& no Sb/Br)  
CU SN  
CU SN  
CU SN  
CU SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
LMV824Q1  
MA  
Green (RoHS  
& no Sb/Br)  
LMV824Q1  
MA  
TSSOP  
TSSOP  
PW  
PW  
Green (RoHS  
& no Sb/Br)  
LMV824  
Q1MT  
2500  
Green (RoHS  
& no Sb/Br)  
LMV824  
Q1MT  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
8-Dec-2013  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF LMV822-N, LMV822-N-Q1, LMV824-N, LMV824-N-Q1 :  
Catalog: LMV822-N, LMV824-N  
Automotive: LMV822-N-Q1, LMV824-N-Q1  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Dec-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LMV821M5  
LMV821M5/NOPB  
LMV821M5X  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SC70  
DBV  
DBV  
DBV  
DBV  
DCK  
DCK  
DCK  
DCK  
DGK  
DGK  
DGK  
DGK  
D
5
5
1000  
1000  
3000  
3000  
1000  
1000  
3000  
3000  
1000  
1000  
3500  
3500  
2500  
2500  
2500  
2500  
2500  
2500  
178.0  
178.0  
178.0  
178.0  
178.0  
178.0  
178.0  
178.0  
178.0  
178.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
8.4  
8.4  
3.2  
3.2  
3.2  
3.2  
1.4  
1.4  
1.4  
1.4  
1.2  
1.2  
1.2  
1.2  
1.4  
1.4  
1.4  
1.4  
2.0  
2.0  
1.6  
2.3  
2.3  
2.3  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
5
8.4  
3.2  
3.2  
8.0  
LMV821M5X/NOPB  
LMV821M7  
5
8.4  
3.2  
3.2  
8.0  
5
8.4  
2.25  
2.25  
2.25  
2.25  
5.3  
2.45  
2.45  
2.45  
2.45  
3.4  
8.0  
LMV821M7/NOPB  
LMV821M7X  
SC70  
5
8.4  
8.0  
SC70  
5
8.4  
8.0  
LMV821M7X/NOPB  
LMV822MM  
SC70  
5
8.4  
8.0  
VSSOP  
VSSOP  
VSSOP  
VSSOP  
SOIC  
8
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
16.4  
16.4  
16.4  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
16.0  
16.0  
16.0  
LMV822MM/NOPB  
LMV822MMX  
8
5.3  
3.4  
8
5.3  
3.4  
LMV822MMX/NOPB  
LMV822MX  
8
5.3  
3.4  
8
6.5  
5.4  
LMV822MX/NOPB  
LMV824MTX  
SOIC  
D
8
6.5  
5.4  
TSSOP  
SOIC  
PW  
D
14  
14  
14  
14  
6.95  
6.5  
8.3  
LMV824MX  
9.35  
9.35  
9.35  
LMV824MX/NOPB  
LMV824Q1MAX/NOPB  
SOIC  
D
6.5  
SOIC  
D
6.5  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Dec-2013  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LMV824Q1MTX/NOPB TSSOP  
PW  
14  
2500  
330.0  
12.4  
6.95  
8.3  
1.6  
8.0  
12.0  
Q1  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LMV821M5  
LMV821M5/NOPB  
LMV821M5X  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SC70  
DBV  
DBV  
DBV  
DBV  
DCK  
DCK  
DCK  
DCK  
DGK  
DGK  
DGK  
DGK  
D
5
5
1000  
1000  
3000  
3000  
1000  
1000  
3000  
3000  
1000  
1000  
3500  
3500  
2500  
2500  
2500  
2500  
210.0  
210.0  
210.0  
210.0  
210.0  
210.0  
210.0  
210.0  
210.0  
210.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
185.0  
185.0  
185.0  
185.0  
185.0  
185.0  
185.0  
185.0  
185.0  
185.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
5
LMV821M5X/NOPB  
LMV821M7  
5
5
LMV821M7/NOPB  
LMV821M7X  
SC70  
5
SC70  
5
LMV821M7X/NOPB  
LMV822MM  
SC70  
5
VSSOP  
VSSOP  
VSSOP  
VSSOP  
SOIC  
8
LMV822MM/NOPB  
LMV822MMX  
8
8
LMV822MMX/NOPB  
LMV822MX  
8
8
LMV822MX/NOPB  
LMV824MTX  
SOIC  
D
8
TSSOP  
SOIC  
PW  
14  
14  
LMV824MX  
D
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Dec-2013  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LMV824MX/NOPB  
LMV824Q1MAX/NOPB  
LMV824Q1MTX/NOPB  
SOIC  
SOIC  
D
D
14  
14  
14  
2500  
2500  
2500  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
35.0  
35.0  
35.0  
TSSOP  
PW  
Pack Materials-Page 3  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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Applications  
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