LMV851MGE/NOPB [TI]
Single, 5.5-V, 8-MHz, 62-mA output current, low noise (11-nV/√Hz) operational amplifier | DCK | 5 | -40 to 125;
| 型号： | LMV851MGE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single, 5.5-V, 8-MHz, 62-mA output current, low noise (11-nV/√Hz) operational amplifier | DCK | 5 | -40 to 125 放大器 光电二极管 |
| 文件： | 总35页 (文件大小：1223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMV851, LMV852, LMV854
www.ti.com
SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
LMV851/LMV852/LMV854 8 MHz Low Power CMOS, EMI Hardened Operational Amplifiers
Check for Samples: LMV851, LMV852, LMV854
1
FEATURES
DESCRIPTION
Texas Instrument’s LMV851/LMV852/LMV854 are
CMOS input, low power op amp ICs, providing a low
input bias current, a wide temperature range of
−40°C to +125°C and exceptional performance,
making them robust general purpose parts.
Additionally, the LMV851/LMV852/LMV854 are EMI
hardened to minimize any interference so they are
ideal for EMI sensitive applications. The unity gain
stable LMV851/LMV852/LMV854 feature 8 MHz of
bandwidth while consuming only 0.4 mA of current
per channel. These parts also maintain stability for
capacitive loads as large as 200 pF. The
2
•
Unless Otherwise Noted, Typical Values
at TA = 25°C, VSUPPLY = 3.3V
•
•
•
•
•
•
•
•
•
•
•
Supply Voltage 2.7V to 5.5V
Supply Current (Per Channel) 0.4 mA
Input Offset Voltage 1 mV max
Input Bias Current 0.1 pA
GBW 8 MHz
EMIRR at 1.8 GHz 87 dB
Input Noise Voltage at 1 kHz 11 nV/√Hz
Slew Rate 4.5 V/µs
LMV851/LMV852/LMV854
provide
superior
performance and economy in terms of power and
space usage. This family of parts has a maximum
input offset voltage of 1 mV, a rail-to-rail output stage
and an input common-mode voltage range that
includes ground. Over an operating supply range
from 2.7V to 5.5V the LMV851/LMV852/LMV854
provide a CMRR of 92 dB, and a PSRR of 93 dB.
The LMV851/LMV852/LMV854 are offered in the
space saving 5-Pin SC70 package, the 8-Pin VSSOP
and the 14-Pin TSSOP package.
Output Voltage Swing Rail-to-Rail
Output Current Drive 30 mA
Operating Ambient Temperature Range −40°C
to 125°C
APPLICATIONS
•
•
•
Photodiode Preamp
Piezoelectric Sensors
Portable/Battery-Powered Electronic
Equipment
•
•
•
Filters/Buffers
PDAs/Phone Accessories
Medical Diagnosis Equipment
Typical Application
R1
+
V
NO RF RELATED
DISTURBANCES
PRESSURE
SENSOR
-
R2
-
+
-
+
+
ADC
EMI HARDENED
EMI HARDENED
INTERFERING
RF SOURCES
Figure 1. Sensor Amplifiers Close to RF Sources
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LMV851, LMV852, LMV854
SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
Absolute Maximum Ratings
ESD Tolerance
(2)
Human Body Model
Charge-Device Model
Machine Model
2 kV
1 kV
200V
VINDifferential
Supply Voltage (V+ – V−)
± Supply Voltage
6V
Voltage at Input/Output Pins
V+ +0.4V
V− −0.4V
Storage Temperature Range
−65°C to +150°C
(3)
Junction Temperature
+150°C
Soldering Information
Infrared or Convection (20 sec)
+260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
(1)
Operating Ratings
(2)
Temperature Range
Supply Voltage (V+ – V−)
Package Thermal Resistance (θJA
5-Pin SC70
−40°C to +125°C
2.7V to 5.5V
(2)
)
313 °C/W
217 °C/W
135 °C/W
8-Pin VSSOP
14-Pin TSSOP
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
(1)
3.3V Electrical Characteristics
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Parameter
Test Conditions
Min
Typ
Max
Units
VOS
TCVOS
IB
Input Offset Voltage
±0.26
See
±1
±1.2
mV
(4)
(5)
Input Offset Voltage Drift
±0.4
±2
μV/°C
(4)
See
0.1
(5)
Input Bias Current
10
500
pA
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution
(5) This parameter is specified by design and/or characterization and is not tested in production.
2
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Product Folder Links: LMV851 LMV852 LMV854
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SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
3.3V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Parameter
Test Conditions
Min
Typ
Max
Units
IOS
Input Offset Current
1
pA
CMRR
Common Mode Rejection Ratio
−0.2V < VCM < V+ - 1.2V
76
75
92
See
dB
dB
(4)
PSRR
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 5.5V,
VOUT = 1V
75
74
93
(4)
(6)
EMIRR
EMI Rejection Ratio, IN+ and IN−
VRFpeak = 100 mVP (−20 dBVP),
64
f = 400 MHz
VRFpeak = 100 mVP (−20 dBVP),
f = 900 MHz
78
87
90
dB
VRFpeak = 100 mVP (−20 dBVP),
f = 1800 MHz
VRFpeak = 100 mVP (−20 dBVP),
f = 2400 MHz
CMVR
AVOL
Input Common-Mode Voltage Range
CMRR ≥ 76 dB
−0.2
2.1
V
(7)
Large Signal Voltage Gain
RL = 2 kΩ,
VOUT = 0.15V to 1.65V,
VOUT = 3.15V to 1.65V
100
97
114
115
dB
RL = 10 kΩ,
100
VOUT = 0.1V to 1.65V,
VOUT = 3.2V to 1.65V
97
VO
Output Swing High,
(measured from V+)
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
31
7
35
43
mV
mV
mA
10
12
Output Swing Low,
(measured from V−)
26
32
43
6
11
14
IO
Output Short Circuit Current
Supply Current
Sourcing, VOUT = VCM
VIN = 100 mV
,
25
20
28
Sinking, VOUT = VCM
,
28
20
31
VIN = −100 mV
IS
LMV851
LMV852
LMV854
0.42
0.79
1.54
0.50
0.58
0.90
1.06
mA
1.67
1.99
(8)
SR
Slew Rate
AV = +1, VOUT = 1 VPP, 10% to 90%
4.5
8
V/μs
MHz
deg
GBW
Φm
en
Gain Bandwidth Product
Phase Margin
62
Input-Referred Voltage Noise
f = 1 kHz
f = 10 kHz
f = 1 kHz
f = 6 MHz
11
nV/√Hz
10
in
Input-Referred Current Noise
0.005
400
11
pA/√Hz
ROUT
CIN
Closed Loop Output Impedance
Common-Mode Input Capacitance
Differential-Mode Input Capacitance
Total Harmonic Distortion + Noise
Ω
pF
%
6
THD+N
f = 1 kHz, AV = 1, BW = >500 kHz
0.006
(6) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRFpeak/ΔVOS).
(7) The specified limits represent the lower of the measured values for each output range condition.
(8) Number specified is the slower of positive and negative slew rates.
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(1)
5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Parameter
Test Conditions
Min
Typ
Max
Units
VOS
TCVOS
IB
Input Offset Voltage
±0.26
See
±1
±1.2
mV
(4)
(5)
Input Offset Voltage Drift
±0.4
±2
μV/°C
(4)
See
(5)
Input Bias Current
0.1
10
500
pA
pA
dB
IOS
Input Offset Current
1
CMRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
EMI Rejection Ratio, IN+ and IN−
−0.2V ≤ VCM ≤ V+ −1.2V
77
76
94
(4)
(4)
See
93
See
PSRR
2.7V ≤ V+ ≤ 5.5V,
VOUT = 1V
75
74
dB
(6)
EMIRR
VRFpeak = 100 mVP (−20 dBVP),
f = 400 MHz
64
76
84
89
VRFpeak = 100 mVP (−20 dBVP),
f = 900 MHz
dB
VRFpeak = 100 mVP (−20 dBVP),
f = 1800 MHz
VRFpeak = 100 mVP (−20 dBVP),
f = 2400 MHz
CMVR
AVOL
Input Common-Mode Voltage Range
CMRR ≥ 77 dB
−0.2
3.8
V
(7)
Large Signal Voltage Gain
RL = 2 kΩ,
VOUT = 0.15V to 2.5V,
VOUT = 4.85V to 2.5V
105
102
118
120
dB
RL = 10 kΩ,
105
VOUT = 0.1V to 2.5V,
VOUT = 4.9V to 2.5V
102
VO
Output Swing High,
(measured from V+)
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
RL = 2 kΩ to V+/2
RL = 10 kΩ to V+/2
34
7
39
47
mV
mV
mA
11
13
Output Swing Low,
(measured from V−)
31
38
50
7
12
15
IO
Output Short Circuit Current
Supply Current
Sourcing, VOUT = VCM
VIN = 100 mV
,
60
48
65
Sinking, VOUT = VCM
,
58
44
62
VIN = −100 mV
IS
LMV851
LMV852
LMV854
0.43
0.82
1.59
0.52
0.60
0.93
1.09
mA
1.73
2.05
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRFpeak/ΔVOS).
(7) The specified limits represent the lower of the measured values for each output range condition.
4
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMV851 LMV852 LMV854
LMV851, LMV852, LMV854
www.ti.com
SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL = 10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
(2)
(3)
(2)
Parameter
Test Conditions
Min
Typ
4.5
Max
Units
V/μs
MHz
deg
(8)
SR
Slew Rate
AV = +1, VOUT = 2 VPP, 10% to 90%
GBW
Φm
en
Gain Bandwidth Product
Phase Margin
8
64
11
10
Input-Referred Voltage Noise
f = 1 kHz
f = 10 kHz
f = 1 kHz
f = 6 MHz
nV/√Hz
in
Input-Referred Current Noise
0.005
400
11
pA/√Hz
ROUT
CIN
Closed Loop Output Impedance
Common-Mode Input Capacitance
Differential-Mode Input Capacitance
Total Harmonic Distortion + Noise
Ω
pF
%
6
THD+N
f = 1 kHz, AV = 1, BW = >500 kHz
0.003
(8) Number specified is the slower of positive and negative slew rates.
Connection Diagrams
Top View
Top View
Figure 2. 5-Pin SC70 Package
See Package Number DCK0005A
Figure 3. 8-Pin VSSOP Package
See Package Number DGK0008A
Top View
Figure 4. 14-Pin TSSOP Package
See Package Number PW0014A
Copyright © 2007–2013, Texas Instruments Incorporated
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Typical Performance Characteristics
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
VOS
vs.
VCM at 3.3V
VOS
vs.
VCM at 5.0V
0.3
0.3
0.2
0.2
125°C
85°C
125°C
85°C
0.1
0.1
0
0
25°C
25°C
-40°C
-40°C
-0.1
-0.1
-0.2
-0.2
V
= 5.0V
0.5
S
V
= 3.3V
S
-0.3
-0.3
-0.5
1.5
2.5
(V)
3.5
4.5
5.5
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
(V)
V
V
CM
CM
Figure 5.
Figure 6.
VOS
vs.
VOS
vs.
Temperature
Supply Voltage
0.3
200
150
0.2
100
3.3V
125°C
85°C
0.1
50
0
0
-50
5.0V
-40°C
25°C
-0.1
-100
-0.2
-150
-200
-0.3
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
-50 -25
0
25
50
75 100 125
V
TEMPERATURE (°C)
SUPPLY
Figure 7.
Figure 8.
VOS
vs.
Input Bias Current
vs.
VOUT
VCM at 25°C
5
4
12
V
= 5.0V, R = 2k
L
S
T
= 25°C
A
9
6
3
2
1
0
5V
3
0
-1
3.3V
-3
-6
-9
-12
-2
-3
-4
-5
-1
0
1
2
3
4
5
6
0
1
2
3
4
5
V
CM
(V)
V
(V)
OUT
Figure 9.
Figure 10.
6
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Product Folder Links: LMV851 LMV852 LMV854
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SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
Input Bias Current
Input Bias Current
vs.
vs.
VCM at 85°C
VCM at 125°C
500
400
50
T = 125°C
A
T
= 85°C
A
40
30
300
200
20
100
10
5.0V
0
0
-10
5.0V
-100
-200
-20
3.3V
-300
-400
-30
3.3V
-40
-500
-50
-1
0
1
2
3
4
5
6
-1
0
1
2
3
4
5
6
V
(V)
CM
V
CM
(V)
Figure 11.
Figure 12.
Supply Current
vs.
Supply Voltage Single LMV851
Supply Current
vs.
Supply Voltage Dual LMV852
1.2
0.7
0.6
1.1
1.0
125°C
85°C
85°C
125°C
0.9
0.5
0.8
0.4
25°C
0.7
25°C
0.6
0.5
-40°C
0.3
-40°C
0.2
0.4
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Figure 13.
Figure 14.
Supply Current
vs.
Supply Current
vs.
Temperature Single LMV851
Supply Voltage Quad LMV854
2.2
0.7
125°C 85°C
2.0
0.6
1.8
5.0V
0.5
1.6
1.4
0.4
25°C
3.3V
1.2
-40°C
0.3
1.0
0.8
0.2
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-50 -25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
Supply Current
vs.
Temperature Dual LMV852
1.2
Supply Current
vs.
Temperature Quad LMV854
2.2
2.0
1.8
1.0
5.0V
5.0V
1.6
0.8
1.4
3.3V
3.3V
0.6
1.2
1.0
0.4
0.8
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17.
Figure 18.
Sinking Current
vs.
Supply Voltage
Sourcing Current
vs.
Supply Voltage
100
100
90
90
80
80
25°C
70
70
25°C
-40°C
-40°C
60
60
50
50
125°C
40
85°C
40
125°C
85°C
30
30
20
10
20
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Figure 19.
Figure 20.
Output Swing High
vs.
Supply Voltage RL = 2 kΩ
Output Swing High
vs.
Supply Voltage RL = 10 kΩ
50
14
125°C
85°C
R
L
= 2 kW
R
L
= 10 kW
45
40
35
30
25
20
12
10
8
125°C
85°C
6
25°C
25°C
-40°C
4
-40°C
2
6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
Figure 21.
6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
Figure 22.
8
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SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
Output Swing Low
Output Swing Low
vs.
Supply Voltage RL = 10 kΩ
vs.
Supply Voltage RL = 2 kΩ
12
10
8
45
R
L
= 2 kW
R
= 10 kW
L
125°C
40
35
30
25
20
15
10
125°C
85°C
85°C
6
4
2
0
25°C
25°C
-40°C
-40°C
6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
5.0
2.5 3.0 3.5 4.0 4.5
5.5 6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 23.
Figure 24.
Output Voltage Swing
vs.
Load Current at 3.3V
Output Voltage Swing
vs.
Load Current at 5.0V
2.0
2.0
1.6
1.2
SINK
SINK
1.6
1.2
125°C
125°C
0.8
0.8
0.4
0.4
0
0
V
= 5.0V
-40°C
-40°C
V
S
= 3.3V
S
-0.4
-0.4
-0.8
-0.8
-1.2
-1.6
-2.0
-1.2
-1.6
-2.0
125°C
125°C
SOURCE
SOURCE
10
0
5
10 15 20 25 30 35 40
(mA)
0
20
30
40
50
60
70
I
I
(mA)
LOAD
LOAD
Figure 25.
Figure 26.
Open Loop Frequency Response
Open Loop Frequency Response
vs.
vs.
Temperature
Load Conditions
60
100
60
100
25°C, 85°C, 125°C
PHASE
20 pF 5 pF
50
80
50
40
30
20
10
0
80
40
GAIN
100 pF
50 pF
60
60
40
20
0
30
40
20
25°C
85°C
20
C
= 5 pF
125°C
L
5 pF
10
0
= 20 pF
= 50 pF
= 100 pF
-40°C
1M
100 pF
1M
-20
10M
0
-20
10M
10k
100k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27.
Figure 28.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
Phase Margin
PSRR
vs.
vs.
Capacitive Load
70
Frequency
120
100
80
60
40
20
0
60
50
40
3.3V
5.0V
-PSRR
3.3V
5.0V
30
5.0V
20
+PSRR
100k
10
3.3V
0
1
10
100
(pF)
1000
100
1k
10k
1M
10M
C
FREQUENCY (Hz)
LOAD
Figure 29.
Figure 30.
CMRR
vs.
Frequency
Channel Separation
vs.
Frequency
140
100
AC CMRR
120
80
DC CMRR
100
60
80
40
60
20
V
S
= 3.3V, 5.0V
10k
V
= 3.3V, 5.0V
S
1k
100k
1M
10M
100
1k
10k
100k
FREQUENCY (Hz)
Figure 31.
1M
10M
FREQUENCY (Hz)
Figure 32.
Large Signal Step Response with Gain = 1
Large Signal Step Response with Gain = 10
f = 250 kHz
f = 250 kHz
A
V
= +1
A
V
= +10
V
V
= 1 V
= 100 mV
PP
IN
PP
IN
400 ns/DIV
400 ns/DIV
Figure 33.
Figure 34.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
Small Signal Step Response with Gain = 1
Small Signal Step Response with Gain = 10
f = 250 kHz
f = 250 kHz
A
V
= +1
V
A
= +10
V
= 100 mV
IN
PP
V
IN
= 10 mV
PP
400 ns/DIV
400 ns/DIV
Figure 35.
Figure 36.
Slew Rate
vs.
Supply Voltage
Overshoot
vs.
Capacitive Load
5.0
4.8
40
35
30
25
20
15
10
5
f = 250 kHz
A
= +1
FALLING EDGE
V
V
=200 mVPP
IN
4.6
4.4
5.0V
RISING EDGE
4.2
A
= +1
V
3.3V
C
= 5 pF
L
4.0
0
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (Hz)
100
1000
C
(pF)
LOAD
Figure 37.
Figure 38.
Input Voltage Noise
vs.
THD+N
vs.
Frequency
Frequency
1
0.1
BW = >500 kHz
100
A
V
= 10x
V
= 3.3V, VIN = 220 mV
PP
S
10
V
= 5.0V, V = 400 mVPP
IN
S
A
= 1x
V
0.01
V
= 3.3V, VIN = 2.2V
PP
S
V
= 5.0V, V = 4.0V
IN PP
S
V
= 3.3V, 5.0V
100
1
S
0.001
10
1k
10k
100k
1M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39.
Figure 40.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
THD+N
ROUT
vs.
Frequency
vs.
Amplitude
1k
100
10
10
A
= 10x
V
V
= 3.3V
S
1
0.1
A
= 100x
V
A
= 1x
V
1
A
= 10x
100k
V
0.01
0.001
0.1
f = 1 kHz
BW = >500 kHz
A
= 1x
V
0.01
100
1m
10m
100m
1
10
10
10
1k
10k
1M
10M
FREQUENCY (Hz)
V
(V )
OUT PP
Figure 41.
Figure 42.
EMIRR IN+
vs.
Power at 400 MHz
EMIRR IN+
vs.
Power at 900 MHz
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
f
= 400 MHz
-30
f
= 900 MHz
-30
RF
RF
-40
-20
-10
0
-40
-20
-10
0
10
RF INPUT PEAK VOLTAGE (dBVp)
RF INPUT PEAK VOLTAGE (dBVp)
Figure 43.
Figure 44.
EMIRR IN+
vs.
Power at 1800 MHz
EMIRR IN+
vs.
Power at 2400 MHz
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
f
= 2400 MHz
f
= 1800 MHz
RF
RF
-40
-30
-20
-10
0
-40
-30
-20
-10
0
10
RF INPUT PEAK VOLTAGE (dBVp)
RF INPUT PEAK VOLTAGE (dBVp)
Figure 45.
Figure 46.
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Typical Performance Characteristics (continued)
At TA = 25°C, RL = 10 kΩ, VS = 3.3V, unless otherwise specified.
EMIRR IN+
EMIRR IN+
vs.
Frequency at 5.0V
vs.
Frequency at 3.3V
100
90
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
V
= 3.3V
V = 5.0V
S
S
V
= -20 dBVp
V
= -20 dBVp
PEAK
PEAK
20
10
100
1000
10000
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 47.
Figure 48.
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APPLICATION INFORMATION
INTRODUCTION
The LMV851/LMV852/LMV854 are operational amplifiers with very good specifications, such as low offset, low
noise and a rail-to-rail output. These specifications make the LMV851/LMV852/LMV854 great choices to use in
areas such as medical and instrumentation. The low supply current is perfect for battery powered equipment.
The small packages, SC-70 package for the LMV851, the VSSOP package for the dual LMV852 and the TSSOP
package for the quad LMV854, make any of these parts a perfect choice for portable electronics. Additionally, the
EMI hardening makes the LMV851/LMV852 or LMV854 a must for almost all op amp applications. Most
applications are exposed to Radio Frequency (RF) signals such as the signals transmitted by mobile phones or
wireless computer peripherals. The LMV851/LMV852/LMV854 will effectively reduce disturbances caused by RF
signals to a level that will be hardly noticeable. This again reduces the need for additional filtering and shielding.
Using this EMI resistant series of op amps will thus reduce the number of components and space needed for
applications that are affected by EMI, and will help applications, not yet identified as possible EMI sensitive, to be
more robust for EMI.
INPUT CHARACTERISTICS
The input common mode voltage range of the LMV851/LMV852/LMV854 includes ground, and can even sense
well below ground. The CMRR level does not degrade for input levels up to 1.2V below the supply voltage. For a
supply voltage of 5V, the maximum voltage that should be applied to the input for best CMRR performance is
thus 3.8V.
When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The
output is rail-to-rail and therefore will introduce no limitations to the signal range.
The typical offset is only 0.26 mV, and the TCVOS is 0.4 μV/°C, specifications close to precision op amps.
CMRR MEASUREMENT
The CMRR measurement results may need some clarification. This is because different setups are used to
measure the AC CMRR and the DC CMRR.
The DC CMRR is derived from ΔVOS versus ΔVCM. This value is stated in the tables, and is tested during
production testing.
The AC CMRR is measured with the test circuit shown in Figure 49.
R2
1 kW
V+
BUFFER
V+
R1
1 kW
-
V
-
IN
Buffer
V
OUT
LMV85x
+
+
R11
1 kW
V-
BUFFER
V-
R2
995W
P1
10W
Figure 49. AC CMRR Measurement Setup
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The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can
be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This
buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network.
Now the closed-loop output impedance of the buffer is a part of the balance. But as the closed-loop output
impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is
that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger
measured bandwidth of the AC CMRR.
One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is
because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So,
mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends
to be higher than the actual DC CMRR based on DC measurements.
The CMRR curve in Figure 50 shows a combination of the AC CMRR and the DC CMRR.
100
AC CMRR
80
DC CMRR
60
40
20
V
= 3.3V, 5.0V
S
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 50. CMRR Curve
OUTPUT CHARACTERISTICS
As already mentioned the output is rail to rail. When loading the output with a 10 kΩ resistor the maximum swing
of the output is typically 7 mV from the positive and negative rail
The LMV851/LMV852/LMV854 can be connected as non-inverting unity gain amplifiers. This configuration is the
most sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier
along with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the
amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking
in the transfer and, when there is too much peaking, the op amp might start oscillating. The
LMV851/LMV852/LMV854 can directly drive capacitive loads up to 200 pF without any stability issues. In order to
drive heavier capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 51. By using this
isolation resistor, the capacitive load is isolated from the amplifier’s output, and hence, the pole caused by CL is
no longer in the feedback loop. The larger the value of RISO, the more stable the amplifier will be. If the value of
RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values
of RISO result in reduced output swing and reduced output current drive.
R
ISO
-
V
OUT
+
V
IN
C
L
Figure 51. Isolating Capacitive Load
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EMIRR
With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those
devices and other equipment becomes a bigger challenge. The LMV851/LMV852/LMV854 are EMI hardened op
amps which are specifically designed to overcome electromagnetic interference. Along with EMI hardened op
amps, the EMIRR parameter is introduced to unambiguously specify the EMI performance of an op amp. This
section presents an overview of EMIRR. A detailed description on this specification for EMI hardened op amps
can be found in Application Note AN-1698(SNOA497).
The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As
a result the op amp itself will hardly receive any disturbances. The RF signals interfering with the op amp are
dominantly received by the PCB and wiring connected to the op amp. As a result the RF signals on the pins of
the op amp can be represented by voltages and currents. This representation significantly simplifies the
unambiguous measurement and specification of the EMI performance of an op amp.
RF signals interfere with op amps via the non-linearity of the op amp circuitry. This non-linearity results in the
detection of the so called out-of-band signals. The obtained effect is that the amplitude modulation of the out-of-
band signal is down-converted into the base band. This base band can easily overlap with the band of the op
amp circuit. As an example Figure 52 depicts a typical output signal of a unity-gain connected op amp in the
presence of an interfering RF signal. Clearly the output voltage varies in the rhythm of the on-off keying of the RF
carrier.
RF
NO RF
RF SIGNAL
V
+ V
DETECTED
OS
V
OUT OPAMP
(A = 1)
V
V
OS
Figure 52. Offset Voltage Variation Due to an Interfering RF Signal
EMIRR Definition
To identify EMI hardened op amps, a parameter is needed that quantitatively describes the EMI performance of
op amps. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness.
Therefore the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred
offset voltage shift of an op amp as a result of an applied RF carrier (interference) with a certain frequency and
level. The definition of EMIRR is given by:
≈
∆
∆
«
’
÷
÷
◊
VRF_PEAK
EMIRRV
RF_PEAK = 20 log
DVOS
(1)
In which VRF_PEAK is the amplitude of the applied un-modulated RF signal (V) and ΔVOS is the resulting input-
referred offset voltage shift (V). The offset voltage depends quadratically on the applied RF level, and therefore,
the RF level at which the EMIRR is determined should be specified. The standard level for the RF signal is 100
mVP. Application Note AN-1698(SNOA497) addresses the conversion of an EMIRR measured for an other signal
level than 100 mVP. The interpretation of the EMIRR parameter is straightforward. When two op amps have an
EMIRR which differ by 20 dB, the resulting error signals when used in identical configurations, differs by 20 dB
as well. So, the higher the EMIRR, the more robust the op amp.
Coupling an RF Signal to the IN+ Pin
Each of the op amp pins can be tested separately on EMIRR. In this section the measurements on the IN+ pin
(which, based on symmetry considerations, also apply to the IN− pin) are discussed. In Application Note AN-
1698(SNOA497) the other pins of the op amp are treated as well. For testing the IN+ pin the op amp is
connected in the unity gain configuration. Applying the RF signal is straightforward as it can be connected
directly to the IN+ pin. As a result the RF signal path has a minimum of components that might affect the RF
signal level at the pin. The circuit diagram is shown in Figure 53. The PCB trace from RFIN to the IN+ pin should
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be a 50Ω stripline in order to match the RF impedance of the cabling and the RF generator. On the PCB a 50Ω
termination is used. This 50Ω resistor is also used to set the bias level of the IN+ pin to ground level. For
determining the EMIRR, two measurements are needed: one is measuring the DC output level when the RF
signal is off; and the other is measuring the DC output level when the RF signal is switched on. The difference of
the two DC levels is the output voltage shift as a result of the RF signal. As the op amp is in the unity gain
configuration, the input referred offset voltage shift corresponds one-to-one to the measured output voltage shift.
C
2
V
DD
10 µF
C
3
100 pF
RFin
+
-
Out
R
1
50W
C
4
C
1
100 pF
22 pF
C
5
V
SS
10 µF
Figure 53. Circuit for Coupling the RF Signal to IN+
Cell Phone Call
The effect of electromagnetic interference is demonstrated in a setup where a cell phone interferes with a
pressure sensor application (Figure 55). This application needs two op amps and therefore a dual op amp is
used. The experiment is performed on two different dual op amps: a typical standard op amp and the LMV852,
EMI hardened dual op amp. The op amps are placed in a single supply configuration. The cell phone is placed
on a fixed position a couple of centimeters from the op amps.
When the cell phone is called, the PCB and wiring connected to the op amps receive the RF signal.
Subsequently, the op amps detect the RF voltages and currents that end up at their pins. The resulting effect on
the output of the second op amp is shown in Figure 54.
Typical Opamp
LMV852
TIME (0.5s/DIV)
Figure 54. Comparing EMI Robustness
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The difference between the two types of dual op amps is clearly visible. The typical standard dual op amp has an
output shift (disturbed signal) larger than 1V as a result of the RF signal transmitted by the cell phone. The
LMV852, EMI hardened op amp does not show any significant disturbances.
DECOUPLING AND LAYOUT
Care must be given when creating a board layout for the op amp. For decoupling the supply lines it is suggested
that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between
V+ and V−. For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor
between ground and V−. Even with the LMV851/LMV852/LMV854 inherent hardening against EMI, it is still
recommended to keep the input traces short and as far as possible from RF sources. Then the RF signals
entering the chip are as low as possible, and the remaining EMI can be, almost, completely eliminated in the chip
by the EMI reducing features of the LMV851/LMV852/LMV854.
PRESSURE SENSOR APPLICATION
The LMV851/LMV852/LMV854 can be used for pressure sensor applications. Because of their low power the
LMV851/LMV852/LMV854 are ideal for portable applications, such as blood pressure measurement devices, or
portable barometers. This example describes a universal pressure sensor that can be used as a starting point for
different types of sensors and applications.
Pressure Sensor Characteristics
The pressure sensor used in this example functions as a Wheatstone bridge. The value of the resistors in the
bridge change when pressure is applied to the sensor. This change of the resistor values will result in a
differential output voltage, depending on the sensitivity of the sensor and the applied pressure. The difference
between the output at full scale pressure and the output at zero pressure is defined as the span of the pressure
sensor. A typical value for the span is 100 mV. A typical value for the resistors in the bridge is 5 kΩ. Loading of
the resistor bridge could result in incorrect output voltages of the sensor. Therefore the selection of the circuit
configuration, which connects to the sensor, should take into account a minimum loading of the sensor.
Pressure Sensor Example
The configuration shown in Figure 55 is simple, and is very useful for the read out of pressure sensors. With two
op amps in this application, the dual LMV852 fits very well.
The op amp configured as a buffer and connected at the negative output of the pressure sensor prevents the
loading of the bridge by resistor R2. The buffer also prevents the resistors of the sensor from affecting the gain of
the following gain stage. Given the differential output voltage VS of the pressure sensor, the output signal of this
op amp configuration, VOUT, equals:
VDD VS
=
-
≈
’
R1
R2
1 + 2 ×
÷
÷
∆
VOUT
∆
2
2
«
◊
(2)
To align the pressure range with the full range of an ADC, the power supply voltage and the span of the pressure
sensor are needed. For this example a power supply of 5V is used and the span of the sensor is 100 mV.
When a 100Ω resistor is used for R2, and a 2.4 kΩ resistor is used for R1, the maximum voltage at the output is
4.95V and the minimum voltage is 0.05V. This signal is covering almost the full input range of the ADC. Further
processing can take place in the microprocessor following the ADC.
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R1
2.4 kW
V
DD
V
DD
R2
100W
PRESSURE
SENSOR
-
LMV852
+
-
-
+
ADC
LMV852
V
OUT
+
V
S
Figure 55. Pressure Sensor Application
THERMOCOUPLE AMPLIFIER
The following circuit is a typical example for a thermocouple amplifier application using an LMV851/LMV852, or
LMV854. A thermocouple converts a temperature into a voltage. This signal is then amplified by the
LMV851/LMV852, or LMV854. An ADC can convert the amplified signal to a digital signal. For further processing
the digital signal can be processed by a microprocessor and used to display or log the temperature. The
temperature data can for instance be used in a fabrication process.
Characteristics of a Thermocouple
A thermocouple is a junction of two different metals. These metals produce a small voltage that increases with
temperature.
The thermocouple used in this application is a K-type thermocouple. A K-type thermocouple is a junction
between Nickel-Chromium and Nickel-Aluminum. This is one of the most commonly used thermocouples. There
are several reasons for using the K-type thermocouple, these include: temperature range, the linearity, the
sensitivity, and the cost.
A K-type thermocouple has a wide temperature range. The range of this thermocouple is from approximately
−200°C to approximately 1200°C, as can be seen in Figure 56. This covers the generally used temperature
ranges.
Over the main part of the temperature range the output voltage depends linearly on the temperature. This is
important for easily converting the measured signal levels to a temperature reading.
The K-type thermocouple has good sensitivity when compared to many other types; the sensitivity is about 41
uV/°C. Lower sensitivity requires more gain and makes the application more sensitive to noise.
In addition, a K-type thermocouple is not expensive, many other thermocouples consist of more expensive
materials or are more difficult to produce.
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50
40
30
20
10
0
-10
-200
0
200 400 600 800 1000 1200
TEMPERATURE (°C)
Figure 56. K-Type Thermocouple Response
Thermocouple Example
For this example, suppose the range of interest is 0°C to 500°C, and the resolution needed is 0.5°C. The power
supply for both the LMV851/LMV852, or LMV854 and the ADC is 3.3V.
The temperature range of 0°C to 500°C results in a voltage range from 0 mV to 20.6 mV produced by the
thermocouple. This is indicated in Figure 56 by the dotted lines.
To obtain the highest resolution, the full ADC range of 0 to 3.3V is used. The gain needed for the full range can
be calculated as follows:
AV = 3.3V / 0.0206V = 160
(3)
If RG is 2 kΩ, then the value for RF can be calculated for a gain of 160. Since AV = RF / RG, RF can be calculated
as follows:
RF = AV x RG = 160 x 2 kΩ = 320 kΩ
(4)
To get a resolution of 0.5°C, the LSB of the ADC should be smaller then 0.5°C / 500°C = 1/1000. A 10-bit ADC
would be sufficient as this gives 1024 steps. A 10-bit ADC such as the two channel 10-bit ADC102S021 can be
used.
Unwanted Thermocouple Effect
At the point where the thermocouple wires are connected to the circuit, usually copper wires or traces, an
unwanted thermocouple effect will occur.
At this connection, this could be the connector on a PCB, the thermocouple wiring forms a second thermocouple
with the connector. This second thermocouple disturbs the measurements from the intended thermocouple.
Using an isothermal block as a reference enables correction for this unwanted thermocouple effect. An
isothermal block is a good heat conductor. This means that the two thermocouple connections both have the
same temperature. The temperature of the isothermal block can be measured, and thereby the temperature of
the thermocouple connections. This is usually called the cold junction reference temperature.
In the example, an LM35 is used to measure this temperature. This semiconductor temperature sensor can
accurately measure temperatures from −55°C to 150°C.
The two channel ADC in this example also converts the signal from the LM35 to a digital signal. Now the
microprocessor can compensate the amplified thermocouple signal, for the unwanted thermocouple effect.
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LMV851, LMV852, LMV854
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SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
Cold Junction Temperature
R
R
F
LM35
T
G
Metal A
Metal B
-
Copper
Copper
R
G
LMV851
+
Amplified
Thermocouple
Output
Thermocouple
R
F
Cold Junction Reference
Figure 57. Thermocouple Read Out Circuit
Copyright © 2007–2013, Texas Instruments Incorporated
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21
Product Folder Links: LMV851 LMV852 LMV854
LMV851, LMV852, LMV854
SNOSAW1A –OCTOBER 2007–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Original (March 2013) to Revision D
Page
22
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Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMV851 LMV852 LMV854
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV851MG/NOPB
LMV851MGE/NOPB
LMV851MGX/NOPB
LMV852MM/NOPB
LMV852MME/NOPB
LMV852MMX/NOPB
LMV854MT/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
DCK
DCK
DCK
DGK
DGK
DGK
PW
5
5
1000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
A98
SN
A98
SC70
5
3000 RoHS & Green
1000 RoHS & Green
SN
A98
VSSOP
VSSOP
VSSOP
TSSOP
8
NIPDAUAG | SN
NIPDAUAG | SN
NIPDAUAG | SN
SN
AB5A
AB5A
AB5A
8
250
3500 RoHS & Green
94 RoHS & Green
2500 RoHS & Green
RoHS & Green
8
14
LMV854
MT
LMV854MTX/NOPB
ACTIVE
TSSOP
PW
14
SN
Level-1-260C-UNLIM
-40 to 125
LMV854
MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV851MG/NOPB
LMV851MGE/NOPB
LMV851MGX/NOPB
LMV852MM/NOPB
LMV852MME/NOPB
LMV852MMX/NOPB
LMV854MTX/NOPB
SC70
SC70
DCK
DCK
DCK
DGK
DGK
DGK
PW
5
5
1000
250
178.0
178.0
178.0
178.0
178.0
330.0
330.0
8.4
8.4
2.25
2.25
2.25
5.3
2.45
2.45
2.45
3.4
1.2
1.2
1.2
1.4
1.4
1.4
1.6
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q1
Q1
Q1
Q1
SC70
5
3000
1000
250
8.4
8.0
VSSOP
VSSOP
VSSOP
TSSOP
8
12.4
12.4
12.4
12.4
12.0
12.0
12.0
12.0
8
5.3
3.4
8
3500
2500
5.3
3.4
14
6.95
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV851MG/NOPB
LMV851MGE/NOPB
LMV851MGX/NOPB
LMV852MM/NOPB
LMV852MME/NOPB
LMV852MMX/NOPB
LMV854MTX/NOPB
SC70
SC70
DCK
DCK
DCK
DGK
DGK
DGK
PW
5
5
1000
250
208.0
208.0
208.0
208.0
208.0
367.0
367.0
191.0
191.0
191.0
191.0
191.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
SC70
5
3000
1000
250
VSSOP
VSSOP
VSSOP
TSSOP
8
8
8
3500
2500
14
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMV854MT/NOPB
14
94
495
8
2514.6
4.06
Pack Materials-Page 3
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
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such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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