LMX1601_技术文档

OBSOLETE

LMX1600, LMX1601, LMX1602

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SNAS017F –MARCH 1998–REVISED APRIL 2013

LMX1600 2.0 GHz/500 MHz, LMX1601 1.1 GHz/500 MHz, LMX1602 1.1 GHz/1.1 GHz

PLLatinum™ Low Cost Dual Frequency Synthesizer

Check for Samples: LMX1600, LMX1601, LMX1602

1

FEATURES

DESCRIPTION

The LMX1600/01/02 is part of a family of monolithic

integrated dual frequency synthesizers designed to

be used in a local oscillator subsystem for a radio

transceiver. It is fabricated using TI's 0.5u ABiC V

silicon BiCMOS process.

23

•

V_CC= 2.7V to 3.6V Operation

Low Current Consumption:

•

–

4 mA @ 3V (Typ) for LMX1601

5 mA @ 3V (Typ) for LMX1600 or LMX1602

•

PLL Powerdown Mode: I_CC= 1 µA Typical

Digital Filtered Lock Detects

The LMX1600/01/02 contains two dual modulus

prescalers, four programmable counters, two phase

detectors and two selectable gain charge pumps

necessary to provide the control voltage for two

external loop filters and VCO loops. Digital filtered

lock detects for both PLLs are included. Data is

Dual Modulus Prescaler:

–

2 GHz/500 MHz Option: (Main) 32/33 (Aux)

8/9

transferred into the LMX1600/01/02 via

MICROWIRE serial interface (Data, Clock, LE).

a

1.1 GHz/500 MHz Option: (Main) 16/17 (Aux)

8/9

V_CCsupply voltage can range from 2.7V to 3.6V. The

LMX1600/01/02 features very low current

consumption - typically 4.0 mA at 3V for LMX1601,

5.0 mA at 3V for LMX1600 or LMX1602. Powerdown

for the PLL is hardware controlled.

1.1 GHz/1.1 GHz Option: (Main) 16/17 (Aux)

16/17

APPLICATIONS

•

Cordless / Cellular / PCS Phones

Other Digital Mobile Phones

The LMX1600/01/02 is available in a 16 pin TSSOP

surface mount plastic package.

Functional Block Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PLLatinum is a trademark of Texas Instruments.

2

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

OBSOLETE

LMX1600, LMX1601, LMX1602

SNAS017F –MARCH 1998–REVISED APRIL 2013

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Connection Diagrams

16 Pin PLGA

See Package Number NPG

16 Pin TSSOP

See Package Number PW

2

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PIN DESCRIPTIONS

Pin No. for

16-pin

PLGA

Pin No. for

16-pin

TSSOP

Pin Name

I/O

Description

Package

16

1

FoLD

O

I

Multiplexed output of the Main/Aux programmable or reference dividers and

Main/Aux lock detect. CMOS output. (See Programming Description)

1

2

OSC_IN

PLL reference input which drives both the Main and Aux R counter inputs. Has

about 1.2V input threshold and can be driven from an external CMOS or TTL

logic gate. Typically connected to a TCXO output. Can be used with an

external resonator (See Programming Description).

2

3

4

5

3

4

5

6

OSC_OUT

GND

O

—

I

Oscillator output. Used with an external resonator.

Aux PLL ground.

fin_AUX

Aux prescaler input. Small signal input from the VCO.

V_CC

—

Aux PLL power supply voltage input. Must be equal to V_CC_MAIN. May range from

2.7V to 3.6V. Bypass capacitors should be placed as close as possible to this

pin and be connected directly to the ground plane.

AUX

6

7

8

CPo_AUX

EN_AUX

O

I

Aux PLL Charge Pump output. Connected to a loop filter for driving the control

input of an external VCO.

Powers down the Aux PLL when LOW (N and R counters, prescaler, and

tristates charge pump output). Bringing EN_AUXHIGH powers up the Aux PLL.

8

9

EN_MAIN

CPo_MAIN

I

Powers down the Main PLL when LOW (N and R counters, prescaler, and

tristates charge pump output). Bringing EN_MAINHIGH powers up the Main PLL.

9

10

11

O

—

Main PLL Charge Pump output. Connected to a loop filter for driving the

control input of an external VCO.

10

V_CC

Main PLL power supply voltage input. Must be equal to V_CC_AUX. May range

from 2.7V to 3.6V. Bypass capacitors should be placed as close as possible to

this pin and be connected directly to the ground plane.

MAIN

11

12

13

12

13

14

fin_MAIN

GND

LE

I

—

I

Main prescaler input. Small signal input from the VCO.

Main PLL ground.

Load enable high impedance CMOS input. Data stored in the shift registers is

loaded into one of the 4 internal latches when LE goes HIGH (control bit

dependent).

14

15

16

Data

I

High impedance CMOS input. Binary serial data input. Data entered MSB first.

The last two bits are the control bits.

Clock

High impedance CMOS Clock input. Data for the various counters is clocked in

on the rising edge, into the 18-bit shift register.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings^(1)(2)(3)

Value

Parameter

Symbol

Min

−0.3

−65

Typical

Max

6.5

Unit

V

V_CC

MAIN

Power Supply Voltage

V_CC

6.5

V

AUX

Voltage on any pin with GND=0V

Storage Temperature Range

Lead Temp. (solder 4 sec)

ESD-Human Body Model⁽²⁾

V_I

T_S

T_L

V_CC+ 0.3

+150

+260

V

°C

eV

2000

(1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Recommended Operating Conditions

indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. "Electrical

Characteristics" document specific minimum and/or maximum performance values at specified test conditions and are ensured. Typical

values are for informational purposes only - based on design parameters or device characterization and are not ensured.

(2) This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done

on ESD-free workstations.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

Recommended Operating Conditions

Value

Parameter

Symbol

Min

Typical

Max

Unit

V

V_CC

2.7

3.6

MAIN

Power Supply Voltage

Operating Temperature

V_CC

V

AUX

MAIN

T_A

−40

+85

°C

4

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Electrical Characteristics

(V_CC= V_CC= 3.0V; T_A= 25°C except as specified)

MAIN

AUX

Symbol

Parameter

Conditions

Min

Typ

Max

Units

GENERAL

I_CC

Power

Supply

Current

2 GHz + 500 MHz

Crystal Mode⁽¹⁾

5.0

4.0

5.0

3.5

2.5

1.5

1

mA

1.1 GHz + 500 MHz

1.1 GHz + 1.1 GHz

2 GHz Only

mA

1.1 GHz Only

mA

500 MHz Only

mA

I_CC-PWDN

fin

Power Down Current

EN_MAIN= LOW, EN_AUX= LOW

fin Main 2 GHz Option

fin Main and Aux 1.1 GHz Option

fin Aux 500 MHz Option

Logic Mode⁽¹⁾

µA

fin Operating Frequency

200

100

40

1

2000

1100

500

40

MHz

V_PP

MHz

dBm

OSC_IN

Oscillator Operating Frequency

Crystal Mode⁽¹⁾

1

20

V_OSC

fφ

Oscillator Input Sensitivity

0.5

V_CC

Maximum Phase Detector Frequency

Main and Aux RF Input Sensitivity

10

Pfin

−15

0

CHARGE PUMP

ICP_o-source

ICP_o-sink

RF Charge Pump Output Current (See

Programming Description)

VCPo = V_CC/2, High Gain Mode

VCPo = V_CC/2, Low Gain Mode

0.5 ≤ VCP_o≤ V_CC−0.5

−1600

1600

−160

160

µA

nA

ICP_o-source

ICP_o-sink

ICP_o-Tri

Charge Pump Tri-state Current

1

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)

V_IH

V_IL

I_IH

I_IL

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

OSC_INInput Current

0.8V_CC

V

0.2V_CC

1.0

V

V_IH= V_CC= 3.6V⁽²⁾

V_IL= 0V; V_CC= 3.6V⁽²⁾

V_IH= V_CC= 3.6V

−1.0

µA

1.0

I_IH

I_IL

100

OSC_INInput Current

V_IL= 0V; V_CC= 3.6V

−100

I_O

OSC_OUTOutput Current Magnitude

(sink/source)⁽³⁾

Logic Mode V_CC

|200|

0.4

= 3.6V⁽¹⁾

V_OUT= V_CC/2

Crystal Mode

V_CC= 2.7V⁽¹⁾

|300|

µA

V_OH

V_OL

High-Level Output Voltage

Low-Level Output Voltage

I_OH= −500 µA

V_CC−0.4

V

I_OL= 500 µA

MICROWIRE TIMING

t_CS

Data to Clock Set Up Time

See SERIAL DATA INPUT TIMING

50

10

50

ns

t_CH

Data to Clock Hold Time

Clock Pulse Width High

t_CWH

t_CWL

t_ES

Clock Pulse Width Low

Clock to Load Enable Set Up Time

Load Enable Pulse Width

t_EW

(1) Refer to Programming Description.

(2) Except fin.

(3) The OSCout Output Current Magnitude is lass than or equal to 200µA when the Logic Mode is selected. The OSCout Output Current

Magnitude is greater than or equal to 300µA when the Crystal Mode is selected.

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Electrical Characteristics (continued)

(V_CC= V_CC= 3.0V; T_A= 25°C except as specified)

MAIN

AUX

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CLOSED LOOP SYNTHESIZER PERFORMANCE (TI evaluation board only)

RFφ_nMain PLL Phase Noise Floor

See⁽⁴⁾

−160

dBc/Hz

(4) Offset frequency = 1 kHz, fin = 900 MHz, fφ = 25 kHz, N = 3600, f_OSC= 10 MHz, V_OSC> 1.2 V_PP. Refer to the Application Note, AN-

1052, for description of phase noise floor measurement.

Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency

synthesizer such as the Texas Instruments LMX1600/01/02, a voltage controlled oscillator (VCO), and a passive

loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well as

programmable reference [R], and feedback [N] frequency dividers. The VCO frequency is established by dividing

the crystal reference signal down via the R counter to obtain the comparison frequency. This reference signal, fr,

is then presented to the input of a phase/frequency detector and compared with another signal, fp, the feedback

signal, which was obtained by dividing the VCO frequency down using the N counter. The phase/frequency

detector's current source outputs pump charge into the loop filter, which then converts the charge into the VCO's

control voltage. The phase/frequency comparator's function is to adjust the voltage presented to the VCO until

the feedback signal's frequency (and phase) match that of the reference signal. When this “phase-locked”

condition exists, the VCO's frequency will be N times that of the comparison frequency, where N is the divider

ratio.

REFERENCE OSCILLATOR INPUTS

The reference oscillator frequency for the Main and Aux PLL's is provided by either an external reference through

the OSC_INpin with the OSC_OUTpin not connected or connected to a 30 pF capacitor to ground in Logic Mode, or

an external crystal resonator across the OSC_INand OSC_OUTpins in Crystal Mode (See Programming

Description). The OSC_INinput can operate to 40 MHz in Logic Mode or to 20 MHz in Crystal Mode with an input

sensitivity of 0.5 V_PP. The OSC_INpin drives the Main and Aux R counters. The inputs have a ∼ 1.2V input

threshold and can be driven from an external CMOS or TTL logic gate. The OSC_INpin is typically connected to

the output of a Temperature Compensated Crystal Oscillator (TCXO).

REFERENCE DIVIDERS (R COUNTERS)

The Main and Aux R Counters are clocked through the oscillator block in common. The maximum frequency is

40 MHz in Logic Mode or 20 MHz in crystal Mode. Both R Counters are 12-bit CMOS counters with a divide

range from 2 to 4,095. (See Programming Description)

FEEDBACK DIVIDERS (N COUNTERS)

The Main and Aux N Counters are clocked by the small signal fin Main and fin Aux input pins respectively. These

inputs should be AC coupled through external capacitors. The Main N counter has an 16-bit equivalent integer

divisor configured as a 5-bit A Counter and an 11-bit B Counter offering a continuous divide range from 992 to

65,535 (2 GHz option) or a 4-bit A Counter and a 12-bit B Counter offering a continuous divide range from 240 to

65,535 (1.1 GHz option). The Main N divider incorporates a 32/33 dual modulus prescaler capable of operation

from 200 MHz to 2.0 GHz or a 16/17 dual modulus prescaler capable of operation from 100 MHz to 1.1 GHz.

The Aux N divider operates from 100 MHz to 1.1 GHz with a 16/17 prescaler or from 40 MHz to 500 MHz with a

8/9 prescaler. The Aux N counter is a 16-bit integer divider fully programmable from 240 to 65,535 over the

frequency range of 100 MHz to 1.1 GHz or from 56 to 32,767 over the frequency range of 40 MHz to 550 MHz.

The Aux N counter is configured as a 4-bit A Counter and a 12-bit B Counter. These inputs should be AC

coupled through external capacitors. (See Programming Description)

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Prescalers

The RF input to the prescalers consists of the fin pins which are one of two complimentary inputs to a differential

pair amplifier. The complimentary inputs are internally coupled to ground with a 10 pF capacitor and not brought

out to a pin. The input buffer drives the A counter's ECL D-type flip flops in a dual modulus configuration. A 32/33

for 2.0 GHz option, 16/17 for 1.1 GHz option, or 8/9 for 500 MHz option prescale ratio is provided for the

LMX1600/01/02. The prescaler clocks the subsequent CMOS flip-flop chain comprising the fully programmable A

and B counters.

PHASE/FREQUENCY DETECTOR

The Main and Aux phase(/frequency) detectors are driven from their respective N and R counter outputs. The

maximum frequency at the phase detector inputs is 10 MHz (unless limited by the minimum continuous divide

ratio of the multi modulus prescalers). The phase detector outputs control the charge pumps. The polarity of the

pump-up or pump-down control is programmed using Main_PD_Pol or Aux_PD_Pol depending on whether

Main or Aux VCO characteristics are positive or negative. (See Programming Description) The phase detector

also receives a feedback signal from the charge pump in order to eliminate dead zone.

CHARGE PUMP

The phase detector's current source outputs pump charge into an external loop filter, which then converts the

charge into the VCO's control voltage. The charge pumps steer the charge pump output, CPo, to V_CC(pump-up)

or ground (pump-down). When locked, CPo is primarily in a tri-state mode with small corrections. The charge

pump output current magnitude can be selected as 160 µA or 1600 µA using bits AUX_CP_GAIN and

MAIN_CP_GAIN as shown in Programming Description.

MICROWIRE SERIAL INTERFACE

The programmable functions are accessed through the MICROWIRE serial interface. The interface is made of 3

functions: clock, data, and latch enable (LE). Serial data for the various counters is clocked in from data on the

rising edge of clock, into the 18-bit shift register. Data is entered MSB first. The last two bits decode the internal

register address. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate

latches (selected by address bits). Data is loaded from the latch to the counter when counter reaches to zero. A

complete programming description is included in the following sections.

FoLD MULTIFUNCTION OUTPUT

The LMX1600/01/02 programmable output pin (FoLD) can deliver the internal counter outputs, digital lock

detects, or CMOS high/low levels.

Lock Detect

A digital filtered lock detect function is included with each phase detector through an internal digital filter to

produce a logic level output available on the Fo/LD output pin, if selected. The lock detect output is high when

the error between the phase detector inputs is less than 15 ns for 4 consecutive comparison cycles. The lock

detect output is low when the error between the phase detector outputs is more than 30 ns for one comparison

cycle. The lock detect output is always low when the PLL is in power down mode. For further description see

Programming Description.

POWER CONTROL

Each PLL is individually power controlled by the device EN pin. The EN_MAINcontrols the Main PLL, and the

EN_AUXcontrols the Aux PLL. Activation of EN = LOW (power down) condition results in the disabling of the

respective N and R counters and de-biasing of their respective fin inputs (to a high impedance state). The

reference oscillator input block powers down and the OSC_INpin reverts to a high impedance state only when

both EN pins are LOW. Power down forces the respective charge pump and phase comparator logic to a tri-state

condition as well as disabling the bandgap reference block. Power up occurs immediately when the EN pin is

brought high. Power up sequence: Bandgap and Oscillator blocks come up first, with the remaining PLL functions

becoming active approx. 1 µs later. All programming information is retained internally in the chip when in power

down mode. The MICROWIRE control register remains active and capable of loading and latching in data during

power down mode.

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Programming Description

MICROWIRE INTERFACE

The descriptions below detail the 18-bit data register loaded through the MICROWIRE Interface. The 18-bit shift

register is used to program the 12-bit Main and Aux R counter registers and the 16-bit Main and Aux N counter

registers. The shift register consists of a 16-bit DATA field and a 2-bit control (CTL [1:0]) field as shown below.

The control bits decode the internal register address. On the rising edge of LE, data stored in the shift register is

loaded into one of the 4 appropriate latches (selected by address bits). Data is shifted in MSB first.

MSB

LSB

0

DATA [15:0]

CTL [1:0]

18

2 1

Register Location Truth Table

When LE transitions high, data is transferred from the 18-bit shift register into one of the 4 appropriate internal

latches depending upon the state of the control (CTL) bits. The control bits decode the internal register address

CTL [1:0]

DATA Location

AUX_R Register

AUX_N Register

MAIN_R Register

MAIN_N Register

0

1

0

1

0

1

Register Content Truth Table

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

AUX_R

AUX_N

MAIN_R

MAIN_N

FoLD

AUX_R_CNTR

AUX_B_CNTR

CP_WORD

AUX_A_CNTR

MAIN_R_CNTR

MAIN_B_CNTR and MAIN_A_CNTR

PROGRAMMABLE REFERENCE DIVIDERS

AUX_R Register

If the Control Bits (CTL [1:0]) are 0 0 when LE transitions high, data is transferred from the 18-bit shift register

into a latch which sets the Aux PLL 12-bit R counter divide ratio. The divide ratio is programmed using the bits

AUX_R_CNTR as shown in 12-Bit Programmable Main and Auxiliary Reference Divider Ratio (MAIN/AUX R

Counter). The divider ratio must be ≥ 2. The FoLD word bits controls the multifunction FoLD output as described

in Programming Description.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

FoLD[3:0]

9

8

7

6

5

4

3

2

1

0

AUX_R

AUX_R_CNTR[11:0]

8

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MAIN_R REGISTER

If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register

into a latch which sets the Main PLL 12-bit R counter divide ratio and various control functions. The divide ratio is

programmed using the bits MAIN_R_CNTR as shown in 12-Bit Programmable Main and Auxiliary Reference

Divider Ratio (MAIN/AUX R Counter). The divider ratio must be ≥ 2. The charge pump control word

(CP_WORD[3:0]) sets the charge pump gain and the phase detector polarity as detailed in CHARGE PUMP

CONTROL WORD (CP_WORD).

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

CP_WORD[3:0]

9

8

7

6

5

4

3

2

1

0

MAIN_R

MAIN_R_CNTR[11:0]

12-Bit Programmable Main and Auxiliary Reference Divider Ratio (MAIN/AUX R Counter)

MAIN_R_CNTR/AUX_R_CNTR

Divide Ratio⁽¹⁾

11

0

10

0

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

•

1

•

0

2

0

1

•

3

•

0

•

4,095

1

(1) Legal divide ratio: 2 to 4,095.

PROGRAMMABLE FEEDBACK (N) DIVIDERS

AUX_N Register

If the Control Bits (CTL[1:0]) are 0 1 when LE transitions high, data is transferred from the 18-bit shift register

into the AUX_N register latch which sets the Aux PLL 16-bit programmable N counter value. The AUX_N counter

is a 16-bit counter which is fully programmable from 240 to 65,535 for 1.1 GHz option or from 56 to 32,767 for

500 MHz option. The AUX_N register consists of the 4-bit swallow counter (AUX_A_CNTR), the 12-bit

programmable counter (AUX_B_CNTR). Serial data format is shown below. The divide ratio (AUX_N_CNTR

[13:0]) must be ≥ 240 (1.1 GHz option) or ≥ 56 (500 MHz option) for a continuous divide range. The Aux PLL N

divide ratio is programmed using the bits AUX_A_CNTR, AUX_B_CNTR as shown in 4-BIT Swallow Counter

Divide Ratio (Aux A COUNTER).

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

AUX_B_CNTR[11:0]

9

8

7

6

5

4

3

2

1

0

1

AUX_N

AUX_A_CNTR[3:0]

4-BIT Swallow Counter Divide Ratio (Aux A COUNTER)

Table 1. 1.1 GHz Option

Swallow

AUX_A_CNTR

Count⁽¹⁾

(A)

0

3

0

•

2

0

•

1

0

•

0

1

•

1

•

15

1

(1) Swallow Counter Value: 0 to 15

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Table 2. 500 MHz Option⁽¹⁾

Swallow

AUX_A_CNTR

Count⁽²⁾

(A)

0

3

X

•

2

0

•

1

0

•

0

1

•

1

•

7

X

1

(1) X = Don't Care condition

(2) Swallow Counter Value: 0 to 7

12-BIT Programmable Counter Divide Ratio (Aux B COUNTER)

AUX_B_CNTR⁽¹⁾⁽²⁾

Divide Ratio⁽³⁾

11

0

10

0

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

1

•

1

0

•

0

1

0

•

3

4

•

0

•

4,095

1

(1) AUX_B_CNTR ≥ AUX_A_CNTR

(2) See PROGRAMMABLE FEEDBACK (N) DIVIDERS for calculation of VCO output frequency

(3) Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)

MAIN_N Register

If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register

into the MAIN_N register latch which sets 16-bit programmable N divider value. The Main N divider is a 16-bit

counter which is fully programmable from 992 to 65,535 for 2 GHz option and from 240 to 65,535 for 1.1 GHz

option. The MAIN_N register consists of the 5-bit (2 GHz option) or 4-bit (1.1 GHz option) swallow counter

(MAIN_A_CNTR) and the 11-bit (2 GHz option) or 12-bit (1.1 GHz option) programmable counter

(MAIN_B_CNTR). Serial data format for the MAIN_N register latch shown below. The divide ratio must be ≥ 992

(2 GHz option) or > 240 (1.1 GHz option) for a continuous divide range. The divide ratio is programmed using the

bits MAIN _A_CNTR and MAIN_B_CNTR as shown in Swallow Counter Divide Ratio (Main A COUNTER) and

Programmable Counter Divide Ratio (Main B COUNTER). The pulse swallow function which determines the

divide ratio is described in Pulse Swallow Function.

Table 3. 2 GHz Option

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

AUX_B_CNTR[10:0]

9

8

7

6

5

4

3

2

1

0

1

MAIN_N

AUX_A_CNTR[4:0]

Table 4. 1.1 GHz Option

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17 16 15 14 13 12 11 10

AUX_B_CNTR[11:0]

9

8

7

6

5

4

3

2

1

0

1

AUX_A_CNTR[3:0]

10

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Swallow Counter Divide Ratio (Main A COUNTER)

Table 5. 2 GHz Option (5 Bit)

Table 6. 1.1 GHz Option (4 Bit)

Swallow

Count⁽¹⁾

MAIN_A_CNTR

Swallow

MAIN_A_CNTR

Count⁽¹⁾

(A)

0

3

0

•

2

0

•

1

0

•

0

1

•

(A)

0

4

0

•

3

0

•

2

0

•

1

0

•

0

1

•

1

•

15

1

31

1

(1) Swallow Counter Value: 0 to 31

(1) Swallow Counter Value: 0 to 15

Programmable Counter Divide Ratio (Main B COUNTER)

Table 7. 2 GHz Option (11 Bit)⁽¹⁾

MAIN_B_CNTR⁽²⁾

Divide Ratio⁽³⁾

10

0

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

0

1

•

1

0

•

0

1

0

•

3

4

•

0

•

2,047

1

(1) See Pulse Swallow Function for calculation of VCO output frequency

(2) MAIN_B_CNTR ≥ MAIN_A_CNTR

(3) Divide ratio: 3 to 2,047 (Divide ratios less than 3 are prohibited)

Table 8. 1.1 GHz Option (12 Bit)⁽¹⁾

MAIN_B_CNTR⁽²⁾

Divide Ratio⁽³⁾

11

0

10

0

9

0

•

8

0

•

7

0

•

6

0

•

5

0

•

4

0

•

3

0

•

2

1

0

1

0

•

3

0

1

•

1

0

•

4

•

0

•

4,095

1

(1) See Pulse Swallow Function for calculation of VCO output frequency.

(2) MAIN_B_CNTR ≥ MAIN_A_CNTR

(3) Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)

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Pulse Swallow Function

The N divider counts such that it divides the VCO RF frequency by (P+1) for A times, and then divides by P for

(B – A) times. The B value (B_CNTR) must be ≥ 3. The continuous divider range for the Main PLL N divider is

from 992 to 65,535 for 2 GHz option, from 240 to 65,535 for 1.1 GHz option, and from 56 to 32,767 for 500 MHz

option. Divider ratios less than the minimum value are achievable as long as the binary counter value is greater

than or equal to the swallow counter value (B_CNTR ≥ A_CNTR).

f_VCO= N x ( f_OSC/ R )

where

•

f_VCO: Output frequency of external voltage controlled oscillator (VCO)

f_OSC: Output frequency of the external reference frequency oscillator (input to OSC_IN).

R: Preset divide ratio of binary programmable reference counter (R_CNTR)

(1)

N = (P x B) + A

where

•

N: Preset divide ratio of main programmable integer N counter (N_CNTR)

B: Preset divide ratio of binary programmable B counter (B_CNTR)

A: Preset value of binary 4-bit swallow A counter (A _CNTR)

P: Preset modulus of dual modulus prescaler (P = 32 for 2 GHz option, P=16 for 1.1 GHz option, and P=8 for 500

MHz option) (2)

CHARGE PUMP CONTROL WORD (CP_WORD)

MSB

LSB

AUX_CP_GAIN

MAIN_CP_GAIN

AUX_PD_POL

MAIN_PD_POL

BIT

LOCATION

FUNCTION

0

1

AUX_CP_GAIN

MAIN_CP_GAIN

AUX_PD_POL

MAIN_PD_POL

MAIN_R[17]

MAIN_R[16]

MAIN_R[15]

MAIN_R[14]

Aux Charge Pump Current Gain

Main Charge Pump Current Gain

Aux Phase Detector Polarity

Main Phase Detector Polarity

LOW

HIGH

LOW

HIGH

Negative

Positive

AUX_CP_GAIN (MAIN_R[17]) and MAIN_CP_GAIN (MAIN_R[16]) are used to select charge pump current

magnitude either low gain mode (160 µA typ) or high gain mode (1600 µA typ)

AUX_ PD_POL (MAIN_R[15]) and MAIN_ PD_POL (MAIN_R[14]) are respectively set to one when Aux or Main

VCO characteristics are positive as in (1) below. When VCO frequency decreases with increasing control voltage

(2) PD_POL should set to zero.

VCO Characteristics

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Phase Comparator and Internal Charge Pump Characteristics

(AUX_PD_POL/MAIN_PD_POL = 1)

fr is phase detector input from reference counter. fp is phase detector input from programmable N counter.

Phase difference detection range: - 2π to + 2pπ.

The minimum width pump up and pump down current pulses occur at the CPo pin when the loop is locked.

F_OUT/LOCK DETECT PROGRAMMING TRUTH TABLE (FoLD)

FoLD

Fo/LD OUTPUT STATE

3

2

1

0

AUX_R[17] AUX_R[16]

AUX_R[15]

AUX_R[14]⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

“0”

“1”

X

x

Main Lock Detect

Aux Lock Detect

X

Main “and” Aux Lock Detect

Main Reference Counter Output

Aux Reference Counter Output

Main Programmable Counter Output

Aux Programmable Counter Output

(1) See OSC Mode Programming for AUX_R[14] description.

Lock Detect Digital Filter

The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a

RC generated delay of approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be

less than the 15 ns RC delay for 4 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is

changed to approximately 30 ns. To exit the locked state (Lock = LOW), the phase error must become greater

than the 30 ns RC delay. When the PLL is in the powerdown mode, Lock is forced LOW. A flow chart of the

digital filter is shown below.

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Typical Lock Detect Timing (AUX_PD_POL/MAIN_PD_POL = 1)

OSC Mode Programming

The OSC_outpin can be optimized for operating with an external crystal resonator or an external reference

frequency source (i.e. TCXO). If the application uses an external reference frequency source, the current

dissipation of the LMX1600/01/02 can be reduced with the Logic Mode (0.5 mA typ.). Crystal Mode should be

used when an external crystal resonator is used. Logic Mode is used when an external reference frequency

source is used. In Logic Mode, OSC_OUTshould be connected to a 30 pF capacitor to ground for optimum

performance.

When the FoLD output state is selected to CMOS high/low levels, the OSC Mode is forced to Crystal Mode.

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FoLD

OSC_OUT

3

2

1

0

AUX_R[17]

AUX_R[16]

AUX_R[15]

AUX_R[14]

0

1

0

1

Crystal Mode

Logic Mode

0

All Other States

Crystal Mode

Typical Crystal Oscillator Circuit

A typical implementation of a 10 MHz crystal oscillator with the OSC_OUTpin in Crystal Mode is shown below.

SERIAL DATA INPUT TIMING

Data shifted into register on clock rising edge.

Data is shifted in MSB first.

TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around V_CC/2. The

test waveform has an edge rate of 0.6 V/ns with amplitudes of 2.2V @ V_CC= 2.7V.

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TYPICAL APPLICATION EXAMPLE

OPERATIONAL NOTES:

*

VCO is assumed AC coupled.

**

R_INincreases impedance so that VCO output power is provided to the load rather than the PLL. Typical

values are 10Ω to 200Ω depending on the VCO power level. The fin RF impedance ranges from 40Ω to

100Ω. The fin IF impedances are higher.

***

50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical

products, a CMOS clock is used and no terminating resistor is required. OSC_INmay be AC or DC coupled.

AC coupling is recommended because the input circuit provides its own bias. (See Figure 1)

Figure 1.

**** Adding RC filter to the V_CCline is recommended to reduce loop-to-loop noise coupling.

— Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk

between pins can be reduced by careful board layout.

— This is a static sensitive device. It should be handled only at static free work stations.

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REVISION HISTORY

Changes from Revision E (April 2013) to Revision F

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 16

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型号：	LMX1601
厂家：	TEXAS INSTRUMENTS
描述：	LMX1600 2.0 GHz/500 MHz, LMX1601 1.1 GHz/500 MHz, LMX1602 1.1 GHz/1.1 GHz PLLatinumâ¢ Low Cost Dual Frequency Synthesizer LMX1600 2.0主频/ 500MHz的， LMX1601 1.1千兆赫/ 500兆赫， LMX1602 1.1千兆赫/ 1.1 GHz的PLLatinumâ ?? ¢低成本双频合成器信号电路锁相环或频率合成电路光电二极管信息通信管理
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