LMX2332LSLBX [TI]
PLL FREQUENCY SYNTHESIZER;
| 型号： | LMX2332LSLBX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PLL FREQUENCY SYNTHESIZER 信息通信管理 |
| 文件： | 总28页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMX2330L,LMX2331L,LMX2332L
LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer
for RFPersonal Communications LMX2330L 2.5 GHz/510 MHz, LMX2331L 2.0
GHz/510 MHz,LMX2332L 1.2 GHz/510 MHz
Literature Number: SNAS111B
OBSOLETE
LMX2330L/LMX2331L/
LMX2332L
July 11, 2011
PLLatinum™ Low Power Dual Frequency Synthesizer for
RF Personal Communications
LMX2330L 2.5 GHz/510 MHz
LMX2331L 2.0 GHz/510 MHz
LMX2332L 1.2 GHz/510 MHz
General Description
The LMX233XL family of monolithic, integrated dual frequen-
cy synthesizers, including prescalers, is to be used as a local
oscillator for RF and first IF of a dual conversion transceiver.
It is fabricated using National's 0.5μ ABiC V silicon BiCMOS
process.
Features
Ultra low current nsumption
■
■
■
2.7V to 5.5V oatio
Selectable synchs oynchronous powerdown
mode:
ICC = 1 pical at 3V
The LMX233XL contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330L) can be selected for the RF synthesizer and a 8/9
or a 16/17 prescaler can be selected for the IF synthesizer.
LMX233XL, which employs a digital phase locked loop tech-
nique, combined with a high quality reference oscillator, pro-
vides the tuning voltages for voltage controlled oscillators to
generate very stable, low noise signals for RF and IF loca
oscillators. Serial data is transferred into the LMX233XL via
a three wire interface (Data, Enable, Clock). Supply voltage
can range from 2.7V to 5.5V. The LMX233XL family f
very low current consumption;
Dual dulescaler:
LMX2330L
MX2331L/32L
MX30L/31L/32L (IF) 8/9 or 16/17
Sble rge pump TRI-STATE® mode
Selecharge pump current levels
Selectable Fastlock™ mode
■
(RF) 32/33 or 64/65
(RF) 64/65 or 128/129
■
■
■
Upge and compatible to LMX233XA family
Applications
Portable Wireless Communications
LMX2330L—5.0 mA at 3V, LMX2331L—4.0 mA
LMX2332L—3.0 mA at 3V.
(PCS/PCN, cordless)
Cordless and cellular telephone systems
■
■
■
■
The LMX233XL are available in a TSSOP 20, CSP 24-pin
surface mount plastic package, and thin CS20-pface
mount plastic package.
Wireless Local Area Networks (WLANs)
Cable TV tuners (CATV)
Other wireless communication systems
PLLatinum™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE™ is a trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
12806
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Functional Block Diagram
1280601
Connection Diagrams
Chip Scale Package (SLB)
(Top View)
hin Shrink Small Outline Package (TM)
(Top View)
1280602
Order Number LMX2330LTM, LMX2331LTM or LMX2332LTM
Order Number LMX2330LTMX, LMX2331LTMX, or
LMX2332LTMX
NS Package Number MTC20
1280639
Order Number LMX2330LSBX, LMX2331LSLBX or
LMX2332LSLBX
NS Package Number SLB24A
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
20-Pin Thin Chipscale Package (SLD)
(Top View)
1280640
Order Number LMX2330LSLDX, LMX2331LSLDX, or
LMX2332LSLDX
NS Package Number SLD20A
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Pin Descriptions
Pin No.
LMX233XLSL LMX233XLSL LMX233XLTM
D 20-pin Thin B 24-pin CSP 20-pin TSSOP Name
Pin No.
Pin No.
Pin
I/O
Description
CSP Package
Package
Package
20
24
1
VCC
1
Power supply voltage input for RF analog and RF digital circuits.
Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass
capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
—
1
2
2
3
2
3
VP1
—
Power Supply for RF charge pump. Must be ≥ VCC
Internal charge pump output. For connection to a loop filter for
.
Do RF
O
driving the input of an external VCO.
3
4
5
4
5
6
4
5
6
GND
Ground for RF digital circuitry.
—
I
fIN RF
fIN RF
RF prescaler input. Sall signal input from the VCO.
I
RF prescaler comeny input. A bypass capacitor should be
placed as close as pe to s pin and be connected directly
to the ground ne. Capis optional with some loss of
sensitivity.
6
7
7
8
7
8
GND
Ground for RF ancircuitry.
—
I
OSCin
Oscillr input. The input has a VCC/2 input threshold and can be
drivrom n external CMOS or TTL logic gate.
8
9
10
11
9
GND
FoLD
GrounF dal, MICROWIRE™, FoLD, and oscillator circuits.
—
O
10
Multiplexed put of the RF/IF programmable or reference
ividers, RF/IF lock detect signals and Fastlock mode. CMOS
ut (e Programmable Modes).
10
11
12
12
14
15
11
12
13
Clock
Data
LE
I
High pedance CMOS Clock input. Data for the various counters
clocked in on the rising edge, into the 22-bit shift register.
nary serial data input. Data entered MSB first. The last two bits
re the control bits. High impedance CMOS input.
Load enable high impedance CMOS input. When LE goes HIGH,
data stored in the shift registers is loaded into one of the 4
appropriate latches (control bit dependent).
13
14
16
17
GND
IF
Ground for IF analog circuitry.
—
I
IF prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected directly
to the ground plane. Capacitor is optional with some loss of
sensitivity.
15
16
17
18
19
20
18
fIN RF
GND
Do IF
I
IF prescaler input. Small signal input from the VCO.
Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits.
—
O
IF charge pump output. For connection to a loop filter for driving
the input of an external VCO.
18
19
22
23
19
20
VP2
—
—
Power Supply for IF charge pump. Must be ≥ VCC
.
VCC
2
Power supply voltage input for IF analog, IF digital, MICROWIRE,
FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V.
VCC2 must equal VCC1. Bypass capacitors should be placed as
close as possible to this pin and be connected directly to the ground
plane.
X
1, 9, 13, 21
X
NC
No connect.
—
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Block Diagram
1280603
Note: The RF prescaler for the LMX2331L/32L i64/65 or 129, while the prescaler for the LMX2330L is 32/33 or 64/65.
Note: VCC1 supplies power to the RF prescalee-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter, phase detector,
R-counter along with the OSCin buffer, MICRVCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level.
Note: VP1 and VP2 can be run separately as lon
5
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Absolute Maximum Ratings (Note 1, Note
2)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
VCC
2.7V to 5.5V
VCC to +5.5V
VP
Power Supply Voltage
Operating Temperature (TA)
−40°C to +85°C
VCC
−0.3V to +6.5V
−0.3V to +6.5V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed.
VP
Voltage on Any Pin
with GND = 0V (VI)
Storage Temperature Range (TS)
−0.3V to VCC+0.3V
−65°C to +150°C
Note 2: This device is a high performance RF integrated circuit with an ESD
rating <2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected work stations.
Lead Temperature (solder 4 sec.)
(TL)
+260°C
Electrical Characteristics
VCC = 3.0V, VP = 3.0V; −40°C < TA < 85°C, except as specified
Value
Symbol
Parameter
LMX2330L RF + IF
Condns
Units
Min
Typ
5.0
4.0
4.0
3.0
3.0
2.0
1.0
1
Max
6.6
5.2
5.4
4.0
4.1
2.7
1.4
10
ICC
Power
Supply
Current
VCC = 2.7to 5.
LMX2330L RF Only
LMX2331L RF + IF
LMX2331L RF Only
LMX2332L IF + RF
LMX2332L RF Only
LMX233xL IF Only
mA
ICC-PWDN Powerdown Current
(Not)
μA
fIN RF
Operating
Frequency
LMX2330L
LMX2331L
LMX22L
LMX3xL
0.5
0.2
0.1
45
2.5
2.0
1.2
510
GHz
MHz
fIN IF
Operating
Frequency
fOSC
fφ
Oscillator Frequency
Maximum Phase Detector
Frequency
5
40
MHz
MHz
10
PfIN RF
RF Input Sensitivity
VCC = 3.0V
VCC = 5.0V
VCC = 2.7V to 5.5V
OSCin
−15
−10
0
0
0
dBm
dBm
dBm
VPP
V
PfIN IF
VOSC
VIH
IF Input Sensitivity
−10
Oscillator Sensitivity
0.5
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
(Note 4)
0.8 VCC
VIL
(Note 4)
0.2 VCC
1.0
V
IIH
VIH = VCC = 5.5V (Note
4)
−1.0
−1.0
μA
IIL
Low-Level Input Current
VIL = 0V, VCC = 5.5V
(Note 4)
1.0
μA
IIH
Oscillator Input Current
Oscillator Input Current
VIH = VCC = 5.5V
100
μA
μA
V
IIL
VIL = 0V, VCC = 5.5V
−100
VOH
High-Level Output Voltage (for
FoLD, pin number 10)
VCC − 0.4
IOH = −500 μA
VOL
tCS
Low-Level Output Voltage (for
FoLD, pin number 10)
0.4
V
IOL = 500 μA
Data to Clock Set Up Time
See Data Input Timing
50
ns
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Value
Typ
Symbol
Parameter
Data to Clock Hold Time
Conditions
Units
Min
10
50
50
50
50
Max
tCH
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
ns
ns
ns
ns
ns
tCWH
tCWL
tES
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Set Up Time
Load Enable Pulse Width
tEW
Note 3: Clock, Data and LE = GND or Vcc
.
Note 4: Clock, Data and LE does not include fIN RF, fIN IF and OSCIN
.
Charge Pump Characteristics
VCC = 3.0V, VP = 3.0V; −40°C < TA ≤ 85°C, except as specified
Value
Typ
−4.0
4.0
Symbol
Parameter
Conditions
Units
Min
Max
IDo-SOURCE
IDo-SINK
Charge Pump Output
Current
VDo = VP/2, ICPo = HIGH (Note 5)
mA
mA
mA
mA
VDo = VP/2, ICPo = HIGH (Note
VDo = VP/2, ICPo = LOW (No
VDo = VP/2, ICPo = LOW (Ne 5)
IDo-SOURCE
IDo-SINK
−1
1
IDo-TRI
Charge Pump
−2.5
2.5
0.5V ≤ VDo ≤ VP − 0.5
−40°C < TA < 85°C
VDo = VP/2
nA
%
TRI-STATE Current
CP Sink vs
IDo-SINK vs
IDo-SOURCE
IDo vs VDo
10
15
3
Source Mismatch (Note 7)
CP Current vs Voltage
TA = 25°C
%
%
10
10
0.5 ≤ VDo ≤ VP .5V
TA = 25°C
(Note 6)
IDo vs TA
CP Current vs
Temperature (Note 8)
VDo =
−40C
Note 5: See PROGRAMMABLE MODES for ICPo descript
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Charge Pump Current Specification Definitions
1280637
I1 = CP sink current at VDo = VP − ΔV
I2 = CP sink current at VDo = VP/2
I3 = CP sink current at VDo = ΔV
I4 = CP source current at VDo = VP − ΔV
I5 = CP source current at VDo = VP/2
I6 = CP source current at VDo = ΔV
ΔV = Voltage offset from positive and negative rails. Depnt on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V.
Note 6: IDo vs VDo
[½ * {|I1| − |I3|}]/[½ * {|I1| + |I3|}] * 100% and [½ * {|I4| − |/[½ * {|I4| + |I6|}] * 100%
Note 7: IDo-sink vs IDo-source Charge Pump Ourent Sink ource Mismatch =
[|I2| − |I5|]/[½ * {|I2| + |I5|}] * 100%
= Charge Pump Output Current mariavs Voltage =
=
Note 8: IDo vs TA
=
Charge Pump Output Cuariation vs Temperature =
[|I2 @ temp| − |I2 @ 25°C|]/|I2 @ 25°C| * [|I5 @ temp| − |I5 @ 25°C|]/|I5 @ 25°C| * 100%
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
RF Sensitivity Test Block Diagram
1280638
Note 1: N = 10,000
R = 50
P = 64
Note 2: Sensitivity limit is reached when the error of the divided RF output, FoLD, is ≥ 1 Hz.
Typical Performance
Characteristics
ICC vs VCC
LMX2330L
ICC vs VCC
LMX2331L
1280619
1280620
9
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
ICC vs VCC
LMX2332L
IDo TRI-STATE
vs Do Voltage
1280621
1280622
Charge Pump Current vs Do Voltage
ICP = HIGH
rge Pump rrent vs Do Voltage
ICP = LOW
123
1280624
Charge Pump Curre
Sink vs Source Mismatch
(See (Note 7) under Charge Pump Current
Specification Definitions)
(See (Note 6) under Charge rent
Specificationition
1280625
1280626
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
RF Input Impedance
VCC = 2.7V to 5.5V, fIN = 50 MHz to 3 GHz
IF Input Impedance
VCC = 2.7V to 5.5V, fIN = 50 MHz to 1000 MHz
1280628
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
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LMX233xSLD RF Input Impedance
LMX233xSLD IF Input Impedance
VCC = 2.7V to 5.5V, fIN = 500 MHz to 3 GHz, fINRF CAP = 100 VCC = 2.7V to 5.5V, fINIF = 100 MHz to 400 MHz, fINIF CAP = 100
pF
pF
1280641
1280642
Marker 1 = 500 MHz, Real = 202.98, Imaginary = −200.09
Marker 1 =
Marker 2 = 200 z,
arker 3 = 300 MHz,
er 4 = MHz,
Real = 374.33,
Imaginary = −301.45
Imaginary = −245.79
Imagniary = −224.24
Imaginary = −131.21
Marker 2 = 1.8 GHz,
Marker 3 = 2.5GHz,
Marker 4 = 3.0 GHz,
Real = 32.36, Imaginary = −91.42
Real = 257.14,
Real = 194.08,
Real = 89.03,
Real = 25.51,
Real = 30.46,
Imaginary = −46.41
Imaginary = −9.50
LMX2330L RF Sensitivity vs Frequency
LMX2331L RF Sensitivity vs Frequency
1280629
1280630
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
LMX2332L RF Sensitivity vs Frequency
IF Input Sensitivity vs Frequency
1280631
1280632
Oscillator Input Sensitivity vs Frequency
Functional Description
The simplified block diagram below shows t22-a register, two 15-bit R Counters and the 15- and 18-bit N Counters
(intermediate latches are not shown). The datam iocked (on the rising edge of Clock) into the DATA register, MSB first.
The data stored in the shift register is load into one oappropriate latches on the rising edge of LE. The last two bits are the
Control Bits. The DATA is transferred counteras follows:
rol Bits
DATA Location
0
C2
0
IF R Counter
0
1
RF R Counter
IF N Counter
RF N Counter
1
0
1
1
13
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
1280606
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferrem t22-bit shift register into a latch which sets the
15-bit R Counter. Serial data format is shown below.
1280607
15-BIT PROGRAMMABLE REFERENVIDER RTIO (R COUNTER)
Divide
R
R
R
R
9
0
0
R
8
0
0
R
7
0
0
R
6
0
0
R
5
0
0
R
4
0
0
R
3
0
1
R
2
1
0
R
1
1
0
Ratio 15 12 11 10
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
•
•
•
•
•
•
•
•
•
327
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don't care bits. The RF N counter does not have don't care
bits.
1280608
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
RF
IF
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ivide
7
N
5
N
4
N
3
N
2
N
1
Ratio
Ratio
A
0
1
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
X
X
•
X
X
•
X
X
•
0
0
•
0
0
•
0
0
•
0
1
•
•
•
127
1
1
1
1
1
1
1
15
X
X
X
1
1
1
1
Notes: Divide ratio: 0 to 127
B ≥ A
X = DON'T CARE condition
11-BIT PROGRAMMABLE TER DE RATIO (B COUNTER)
Divide
N
N
N
N
N
N
N
9
N
8
18 17 13 12 11 10
Ratio
B
3
4
0
•
0
•
0
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
•
20
1
1
1
1
1
1
1
1
1
Note: Divide ratio: 3 to 2047 (Divide ratios less bited)
B ≥ A
PULSE SWALLOW FUNCT
fVCO = [(P × B) + A] × fOSC/R
fVCO
:
Output frequency of external voltage controlled oscillator (VCO)
B:
Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
Preset divide ratio of binary 7-bit swallow counter
A:
(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)
fOSC
R:
:
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P:
Preset modulus of dual moduIus prescaler (for IF; P = 8 or 16;
for RF; LMX2330L: P = 32 or 64
LMX2331L/32L: P = 64 or 128)
15
12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
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PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump TRI-STATE
and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable
modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and Table 3.
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
IF Do
R19
R20
IF Phase
IF ICPo
IF Fo
0
0
IF LD
Detector Polarity
RF Phase
TRI-STATE
RF Do
RF ICPo
RF Fo
0
1
RF LD
Detector Polarity
TRI-STATE
C1
1
C2
0
N19
N20
Pwdn IF
Pwdn R
IF Prescaler
RF Prescaler
1
1
TABLE 2. Mode Select Truth Ta
Phase Detector Polarity
(Note 11)
Do TRI-STATE
(Note 9)
ICPo
IF
330L RF
2331L/32L RF
Prescaler
64/65
Pwdn
(Note 10) Prescaler Paler
(Note 9)
Pwrd Up
Pwrd Dn
0
1
Negative
Normal Operation
TRI-STATE
LOW
HIGH
/9
32/33
64/65
Positive
6/1
128/129
Note 9: Refer to POWERDOWN OPERATION in Functional Description.
Note 10: The ICPo LOW current state = 1/4 × ICPo HIGH current.
Note 11: PHASE DETECTOR POLARITY
Depending upon VCO characteristics, R16 bit should be set accordingly: (srht)
When VCO characteristics are positive like (1), R16 should be
When VCO characteristics are negative like (2), R16 should
eristics
1280609
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
TABLE 3. The FoLD (Pin 10) Output Truth Table
RF R[19]
(RF LD)
IF R[19]
(IF LD)
RF R[20]
(RF Fo)
IF R[20]
(IF Fo)
Fo Output State
Disabled (Note 12)
0
0
1
1
X
X
X
X
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
1
IF Lock Detect (Note 13)
RF Lock Detect (Note 13)
RF/IF Lock Detect (Note 13)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
Fastlock (Note 14)
IF Coter Reset (Note 15)
RF ountReset (Note 15)
IF aCouer Reset (Note 15)
X = don't care condition
Note 12: When the FoLD output is disabled, it is actively pulled to a low logic state.
Note 13: Lock detect output provided to indicate when the VCO frequency is in “lock.” Whethe loop is locnd a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is inted when RF anIF are both locked.
Note 14: The Fastlock mode utilizes the FoLD output pin to switch a second loop filter ping stor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop's lcpo magnitude bit #17 is selected HIGH (while the #1modts are set for Fastlock).
Note 15: The IF Counter Reset mode resets IF PLL's R and N counters and brings IF charmtput to a TRI-STATE condition. The RF Counter Reset
mode resets RF PLL's R and N counters and brings RF charge pump output to a TRI-STATE on. The IF and RF Counter Reset mode resets all counters
and brings both charge pump outputs to a TRI-STATE condition. Upon remoof the Reset bits then N counter resumes counting in “close” alignment with the
R counter. (The maximum error is one prescaler cycle.)
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes able by MICROWIRE selection. Synchronously powerdown
occurs if the respective loop's R18 bit (Do TRI-STATn its N20 bit (Pwdn) becomes HI. Asynchronous powerdown
occurs if the loop's R18 bit is HI when its N20 bit becom
In the synchronous powerdown mode, the powdown function is gated by the charge pump to prevent unwanted frequency jumps.
Once the powerdown program bit N20 is loa, will go into powerdown mode when the charge pump reaches a TRI-
STATE condition.
In the asynchronous powerdown moddevice pers down immediately after the LE pin latches in a HI condition on the
powerdown bit N20.
Activation of either the IF or RF PLL poonditions in either synchronous or asynchronous modes forces the respective
loop's R and N dividers to their lotate con and debiasing of its respective fIN input to a high impedance state. The oscillator
circuitry function does not beed until both IF and RF powerdown bits are activated. The MICROWIRE control register
remains active and capable latching data during all of the powerdown modes.
The device returns to an activup condition in either synchronous or asynchronous modes immediately upon LE latching
LOW data into bit N20.
Powerdown Mode Select Table
R18
0
N20
0
Powerdown Status
PLL Active
PLL Active
1
0
(Charge Pump Output TRI-STATE)
Synchronous Powerdown Initiated
Asynchronous Powerdown Initiated
0
1
1
1
17
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
SERIAL DATA INPUT TIMING
1280610
Note 1: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Note 2: tcs = Data to Clock Set-Up Time
tCH = Data to Clock Hold Time
tCWH = Clock Pulse Width High
tCWL = Clock Pulse Width Low
tES = Clock to Load Enable Set-Up Time
tEW = Load Enable Pulse Width
Test Conditions: The Serial Data Input Timing is tested using a symmetrical wavefod VThe test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CACTERTICS
1280611
Notes: Phase difference detection π
The minimum width pump wn current pulses occur at the Do pin when the loop is locked.
R16 = HIGH
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18
12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Typical Application Example
1280612
Operational Notes:
*
VCO is assumed AC coupled.
** RIN increases impedance so that VCO oued to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO power
level. fIN RF impedance ranges from 40Ω to 100ances are higher.
*** Adding RC filters to the VCC lines is recommendduce loop-to-loop noise coupling.
1280613
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful
board layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
19
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1.
1280614
FIGURE 1. Basic Charge PumaLoced Loop
LOOP GAIN EQUATIONS
(2)
A linear control system model of the phase feedback for a PLL
in the locked state is shown in Figure 2. The open loop gain
is the product of the phase comparator gain (Kφ), the
gain (KVCO/s), and the loop filter gain Z(s) divided by t
of the feedback counter modulus (N). The passive lo
configuration used is displayed in Figure 3, while the co
impedance of the filter is given in Equation 1.
T2 = R2 • C2
(3)
The 3rd order PLL Open Loop Gain can be calculated in terms
of frequency, ω, the filter time constants T1 and T2, and the
design constants Kφ, KVCO, and N.
(4)
From Equations 2, 3 we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in Equation 5.
1280615
φ(ω) = tan −1 (ω • T2) − tan−1 (ω • T1) + 180°
(5)
FIGURE 2. Pdel
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
φp shows the amount of phase margin that exists at the point
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp', as dou-
ble the frequency which gave us our original loop bandwidth,
wp, the loop response time would be approximately halved.
Because the filter attenuation at the comparison frequency
also diminishes, the spurs would have increased by approxi-
mately 6 dB. In the proposed Fastlock scheme, the higher
spur levels and wider loop filter conditions would exist only
during the initial lock-on phase—just long enough to reap the
benefits of locking faster. The objective would be to open up
the loop bandwidth but not introduce any additional compli-
cations or compromises related to our original design criteria.
We would ideally like to momentarily shift the curve of Figure
4 over to a different cutoff frequency, illustrated by the dotted
line, without affecting the relative open loop gain and phase
1280616
FIGURE 3. Passive Loop Filter
(1)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
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20
12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
relationships. To maintain the same gain/phase relationship
at twice the original cutoff frequency, other terms in the gain
and phase Equation 4 and Equation 5 will have to compen-
sate by the corresponding “1/w” or “1/w2” factor. Examination
of equations Equations 2, 3 and Equation 5 indicates the
damping resistor variable R2 could be chosen to compensate
the “w”' terms for the phase margin. This implies that another
resistor of equal value to R2 will need to be switched in par-
allel with R2 during the initial lock period. We must also insure
that the magnitude of the open loop gain, H(s)G(s) is equal to
zero at wp' = 2wp. Kvco, Kφ, N, or the net product of these
terms can be changed by a factor of 4, to counteract the w2
term present in the denominator of Equation 2 and Equation
3. The Kφ term was chosen to complete the transformation
because it can readily be switched between 1X and 4X val-
ues. This is accomplished by increasing the charge pump
output current from 1 mA in the standard mode to 4 mA in
Fastlock.
1280617
FIGURE 4. Open Loop Response Bode P
FASTLOCK CIRCUIT IMPLEMENTATION
diresisr is wired in appropriately, the loop will lock
fastethoany additional stability considerations to ac-
count foce locked on the correct frequency, the user can
return the PLL to standard low noise operation by sending a
MICRWIRE instruction with the RF Icpo bit set low. This
on does not affect the charge on the loop filter capac-
itorand is enacted synchronous with the charge pump out-
put. This creates a nearly seamless change between Fastlock
and standard mode.
A diagram of the Fastlock scheme as implemented in National
Semiconductors LMX233XL PLL is shown in Figure 5. When
a new frequency is loaded, and the RF Icpo bit is set high the
charge pump circuit receives an input to deliver 4 times the
normal current per unit phase error while an open drai
NMOS on chip device switches in a second R2 resisto
ment to ground. The user calculates the loop filter com
values for the normal steady state considerations. The
configuration ensures that as long as a second ide
1280618
FIGURE 5. Fastlock PLL Architecture
21
12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead (0.173″ Wide) Thin Sk Small utline Package (TM)
Order Number LMX2330LTM, L331M or LMX2332LTM
*For Tape and Reel (250s per reel)
Order Number LMX233X233LTMX or LMX2332LTMX
NS ber MTC20
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22
12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
24-Pin Chip Scalage
For Tape an500 Uits per Reel)
Order Number LMX23302331LSLBX or LMX2332LSLBX
NS Per SLB24A
23
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
20-Pin Thin Chip Scacge (SLD)
Order Number LMX2330LSMX23SLDX or LMX2332LSLDX
NS Pber SLD20A
www.national.com
24
12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Notes
25
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12806 Version 9 Revision 2 Print Date/Time: 2011/07/11 15:54:42
Notes
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