LMX2486 [TI]
用于射频个人通信的 1GHz 至 4.5GHz Δ-Σ 低功耗双路 PLL;
| 型号： | LMX2486 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于射频个人通信的 1GHz 至 4.5GHz Δ-Σ 低功耗双路 PLL 通信 射频 个人通信 |
| 文件： | 总48页 (文件大小：1134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMX2486
SNAS324B –JANUARY 2006–REVISED JANUARY 2016
LMX2486 1-GHz to 4.5-GHz High-Performance Delta-Sigma Low-Power Dual PLLatinum™
Frequency Synthesizers With 3-GHz Integer PLL
1
1 Features
•
Quadruple Modulus Prescaler for Lower Divids
3 Description
The LMX2486 device is
a
low-power, high
–
–
RF PLL: 16/17/20/21 or 32/33/36/37
IF PLL: 8/9 or 16/17
performance delta-sigma fractional-N PLL with an
auxiliary integer-N PLL. The device is fabricated
using TI’s advanced process.
•
Advanced Delta Sigma Fractional Compensation
–
–
12-Bit or 22-Bit Selectable Fractional Modulus
With delta-sigma architecture, fractional spurs at
lower offset frequencies are pushed to higher
frequencies outside the loop bandwidth. The ability to
push close in spur and phase noise energy to higher
frequencies is a direct function of the modulator
order. Unlike analog compensation, the digital
feedback technique used in the LMX2486 is highly
resistant to changes in temperature and variations in
wafer processing. The LMX2486 delta-sigma
modulator is programmable up to fourth order, which
allows the designer to select the optimum modulator
order to fit the phase noise, spur, and lock time
requirements of the system.
Up to 4th Order Programmable Delta-Sigma
Modulator
•
Improved Lock Times and Programming
–
Fastlock / Cycle Slip Reduction Which
Requires Only a Single-Word Write
–
Integrated Time-Out Counter
•
•
Wide Operating Range
LMX2486 RF PLL: 1.0 GHz to 4.5 GHz
Useful Features
–
–
–
–
–
–
Digital Lock Detect Output
Hardware and Software Power-Down Control
On-Chip Crystal Reference Frequency Doubler
RF Phase Detector Frequency Up to 50 MHz
2.5-V to 3.6-V Operation With ICC = 8.5 mA
Serial data for programming the LMX2486 is
transferred through a three-line, high-speed (20-MHz)
MICROWIRE interface. The LMX2486 offers fine
frequency resolution, low spurs, fast programming
speed, and a single-word write to change the
frequency. This makes it ideal for direct digital
modulation applications, where the N-counter is
directly modulated with information. The LMX2486 is
available in a 24-lead 4.0 × 4.0 × 0.8 mm WQFN
package.
2 Applications
•
•
•
•
Cellular Phones and Base Stations
Direct Digital Modulation Applications
Satellite and Cable TV Tuners
WLAN Standards
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMX2486
WQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMX2486
SNAS324B –JANUARY 2006–REVISED JANUARY 2016
www.ti.com
Table of Contents
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 24
8.5 Programming........................................................... 25
8.6 Register Maps......................................................... 27
Application and Implementation ........................ 38
9.1 Application Information............................................ 38
9.2 Typical Application .................................................. 38
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics.............................................. 8
Parameter Measurements Information .............. 14
7.1 Bench Test Set-Ups................................................ 14
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
9
10 Power Supply Recommendations ..................... 40
11 Layout................................................................... 40
11.1 Layout Guidelines ................................................. 40
11.2 Layout Example .................................................... 40
12 Device and Documentation Support ................. 41
12.1 Community Resources.......................................... 41
12.2 Trademarks........................................................... 41
12.3 Electrostatic Discharge Caution............................ 41
12.4 Glossary................................................................ 41
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2013) to Revision B
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
Changes from Original (March 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 37
2
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SNAS324B –JANUARY 2006–REVISED JANUARY 2016
5 Pin Configuration and Functions
RTW Package
24-Pin WQFN
Top View
24 23 22 21 20 19
CPoutRF
1
18 OSCout
17 VddIF2
GND
2
VddRF1
3
CPoutIF
GND
16
15
Pin 0
(Ground Substrate)
FinRF
FinRF*
LE
4
5
6
14 VddIF1
FinIF
13
7
8
9
10 11 12
Pin Functions
PIN
I/O
DESCRIPTION
NO.
0
NAME
GND
—
O
—
—
I
Ground substrate; this is on the bottom of the package and must be grounded.
RF PLL charge pump output
1
CPoutRF
GND
2
RF PLL analog ground
3
VddRF1
FinRF
RF PLL analog power supply
4
RF PLL high-frequency input pin
5
FinRF*
I
RF PLL complementary high-frequency input pin; shunt to ground with a 100-pF capacitor.
MICROWIRE Load Enable; high-impedance CMOS input. Data stored in the shift registers is loaded
into the internal latches when LE goes HIGH.
6
7
8
LE
I
I
I
DATA
CLK
MICROWIRE Data; high-impedance binary serial data input.
MICROWIRE Clock; high-impedance CMOS Clock input. Data for the various counters is clocked into
the 24-bit shift register on the rising edge.
9
VddRF2
CE
—
I
Power supply for RF PLL digital circuitry
Chip Enable control pin; must be pulled high for normal operation.
Power supply for RF PLL digital circuitry
Test frequency output / Lock Detect
IF PLL high-frequency input pin
10
11
12
13
14
15
16
17
18
VddRF5
Ftest/LD
FinIF
I
O
I
VddIF1
GND
—
—
O
—
O
IF PLL analog power supply
IF PLL digital ground
CPoutIF
VddIF2
OSCout
IF PLL charge pump output
IF PLL power supply
Buffered output of the OSCin signal
Oscillator enable; when this is set to high, the OSCout pin is enabled regardless of the state of other
pins or register bits.
19
ENOSC
I
20
21
22
23
24
OSCin
NC
I
Reference input
I
This pin must be left open.
VddRF3
FLoutRF
VddRF4
—
O
—
Power supply for RF PLL digital circuitry
RF PLL fastlock output; also functions as programmable TRI-STATE CMOS output.
RF PLL analog power supply
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SNAS324B –JANUARY 2006–REVISED JANUARY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
4.25
UNIT
V
VCC
VI
Power supply voltage
Voltage on any pin with GND = 0 V
Lead temperature (solder 4 sec.)
Storage temperature
VCC + 0.3
260
V
TL
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM)
Charged-device model (CDM)
Machine model (MM)
V(ESD)
Electrostatic discharge(1)
V
±200
(1) This is a high performance RF device is ESD-sensitive. Handling and assembly of this device should be done at an ESD free
workstation.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
3
MAX
3.6
UNIT
V
(1)
VCC
TA
Power supply voltage
Operating temperature
–40
25
85
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications
and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. The voltage at
all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC will be used to
refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.
6.4 Thermal Information
LMX2486
THERMAL METRIC(1)
RTW (WQFN)
UNIT
24 PINS
47.2
43
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
24
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
24
RθJC(bot)
7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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SNAS324B –JANUARY 2006–REVISED JANUARY 2016
6.5 Electrical Characteristics
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
PARAMETER
Icc PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IF PLL OFF
RF PLL ON
Charge pump TRI-STATE
Power supply current, RF
synthesizer
ICCRF
ICCIF
5.7
2.5
mA
mA
IF PLL ON
RF PLL OFF
Charge pump TRI-STATE
Power supply current, IF
synthesizer
IF PLL ON
RF PLL ON
Charge pump TRI-STATE
Power supply current, entire
synthesizer
ICCTOTAL
ICCPD
8.5
< 1
mA
µA
CE = ENOSC = 0 V
CLK, DATA, LE = 0 V
Power-down current
RF SYNTHESIZER PARAMETERS
RF_P = 16
RF_P = 32
1000
1000
-15
4000
4500
0
fFinRF
Operating frequency
MHz
pFinRF
fCOMP
Input sensitivity
Phase detector frequency(1)
dBm
MHz
50
RF_CPG = 0
VCPoutRF = VCC/2
95
190
µA
µA
µA
µA
µA
µA
nA
RF charge pump source
current(2)
RF_CPG = 1
VCPoutRF = VCC/2
ICPoutRFSRCE
RF_CPG = 15
VCPoutRF = VCC/2
1520
–95
RF_CPG = 0
VCPoutRF = VCC/2
RF charge pump sink
current(2)
RF_CPG = 1
VCPoutRF = VCC/2
ICPoutRFSINK
–190
–1520
2
RF_CPG = 15
VCPoutRF = VCC/2
RF charge pump TRI-STATE
current magnitude
ICPoutRFTRI
0.5 ≤ VCPoutRF ≤ VCC – 0.5
10
RF_CPG > 2
3%
3%
10%
13%
Magnitude of RF CP sink vs
CP source mismatch
VCPoutRF = VCC/2
TA = 25°C
| ICPoutRF%MIS |
RF_CPG ≤ 2
Magnitude of RF CP current vs 0.5 ≤ VCPoutRF ≤ VCC – 0.5
| ICPoutRF%V |
| ICPoutRF%T |
2%
4%
8%
CP voltage
TA = 25°C
Magnitude of RF CP current vs
temperature
VCPoutRF = VCC/2
(1) For Phase Detector Frequencies greater than 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also
required.
(2) Refer to table in section RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
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Electrical Characteristics (continued)
(VCC = 3.0V; -40°C ≤ TA ≤ +85°C unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IF SYNTHESIZER PARAMETERS
IF_P = 8
250
250
–10
2000
3000
5
fFinIF
Operating frequency
MHz
IF_P = 16
pFinIF
IF input sensitivity
dBm
MHz
mA
fCOMP
Phase detector frequency
10
ICPoutIFSRCE
ICPoutIFSINK
IF charge pump source current VCPoutIF = VCC/2
3.5
IF charge pump sink current
VCPoutIF = VCC/2
–3.5
mA
IF charge pump TRI-STATE
current magnitude
ICPoutIFTRI
0.5 ≤ VCPoutIF ≤ VCC RF – 0.5
2
1%
4%
4%
10
8%
nA
Magnitude of IF CP sink vs CP VCPoutIF = VCC/2
source mismatch TA = 25°C
| ICPoutIF%MIS |
| ICPoutIF%V |
| ICPoutIF%TEMP|
Magnitude of IF CP current vs 0.5 ≤ VCPoutIF ≤ VCC – 0.5
CP voltage
10%
TA = 25°C
Magnitude of IF CP current vs
temperature
VCPoutIF = VCC/2
OSCILLATOR PARAMETERS
OSC2X = 0
OSC2X = 1
5
5
110
20
MHz
MHz
VP-P
µA
fOSCin
Oscillator operating frequency
vOSCin
IOSCin
Oscillator input sensitivity
Oscillator input current
0.5
VCC
100
–100
SPURS
(3)
Spurs in band
See
–55
dBc
PHASE NOISE
RF_CPG = 0
RF_CPG = 1
RF_CPG = 3
RF_CPG = 7
RF_CPG = 15
–202
–204
–206
–210
–210
RF synthesizer normalized
phase noise contribution(4)
LF1HzRF
dBc/Hz
dBc/Hz
IF synthesizer normalized
phase noise contribution
LF1HzIF
–209
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
1.6
VCC
0.4
1
V
V
VIH = VCC
–1
–1
µA
µA
V
IIL
VIL = 0 V
1
VOH
VOL
IOH = –500 µA
IOL = 500 µA
VCC – 0.4
0.4
V
(3) To measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one.
The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth
must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop
Bandwidth = 100 kHz, Fraction = ½000, VCO Frequency = 3 GHz, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, and a 4th
Order Modulator (FM = 0). These are relatively consistent over tuning range.
(4) Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band
phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than
the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement
conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = ½000, VCO Frequency = 3 GHz,
Comparison Frequency = 20 MHz, FM = 0, and DITH = 0.
6
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SNAS324B –JANUARY 2006–REVISED JANUARY 2016
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
MICROWIRE INTERFACE TIMING
tCS
Data to clock set-up time
Data to clock hold time
Clock pulse width high
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
25
8
ns
ns
ns
ns
ns
ns
tCH
tCWH
tCWL
tES
25
25
25
25
Clock pulse width low
Clock to load enable set-up time
Load enable pulse width
tEW
MSB
LSB
C0
DATA
CLK
LE
D19
D18
D17
D16
D15
D0
C3
C2
C1
t
t
CWH
CS
t
ES
t
CH
t
CWL
t
EW
Figure 1. Microwire Input Timing Diagram
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6.7 Typical Characteristics
6.7.1 Sensitivity
Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in the Electrical
Characteristics section.
20
10
20
10
V
CC
= 2.5V
T
A
= -40°C, 25°C, and 85°C
V
CC
= 3.0V and 3.6V
0
0
-10
-20
-30
-40
-10
-20
-30
-40
T
= 85°C
V
CC
= 2.5V
A
T
= -40°C
A
V
= 3.6V
CC
T
= 25°C
3000
A
V
CC
= 3.0V
0
1000
2000
4000
5000
4000
150
0
1000
2000
3000
4000
5000
fFinRF (MHz)
f
(MHz)
FinRF
VCC = 3.0 V, RF_P = 32
Figure 3. RF PLL Fin Sensitivity
TA = 25°C, RF_P = 32
Figure 2. RF PLL Fin Sensitivity
20
20
10
T
= -40oC
10
0
A
T
= 25oC, and 85oC
A
0
V
= 3.0 and 3.6V
CC
V
= 2.5V
CC
-10
-20
-30
-40
-50
-10
-20
-30
-40
V
CC
= 3.0V
T
= 25oC
A
V
= 3.6V
CC
T
A
= -40oC
T
= 85oC
A
V
CC
= 2.5V
2000
(MHz)
0
1000
3000
3000
0
1000
2000
(MHz)
4000
f
FinIF
f
FinIF
VCC = 3.0 V, IF_P = 16
Figure 5. IF PLL Fin Sensitivity
TA = 25°C, IF_P = 16
Figure 4. IF PLL Fin Sensitivity
20
20
10
10
V
CC
= 2.5V, 3.0V, and 3.6V
T
= -40°C, 25°C, and 85°C
A
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
V
CC
= 3.6V
V
= 3.0V
CC
T
= 25°C
A
V
CC
= 2.5V
T
= 85°C
A
T
A
= -40°C
0
30
60
120
150
ꢀ0
10
120
10
0
30
60
90
f
(MHz)
OSCin
f
(MHz)
OSCin
TA = 25°C, OSC_2X = 0
Figure 6. OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 0
Figure 7. OSCin Sensitivity
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Sensitivity (continued)
Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in the Electrical
Characteristics section.
20
20
10
10
= -40oC, 25oC, and 85oC
V
= 2.5V, 3.0V, and 3.6V
CC
T
A
0
-10
-20
-30
-40
-50
0
V
CC
= 3.6V
-10
-20
-30
-40
-50
T
= 85oC
A
V
CC
= 3.0V
V
CC
=2.5V
T
A
= -40oC
T
= 25oC
A
10
0
5
15
20
25
10
0
5
15
20
25
f
(MHz)
OSCin
f
(MHz)
OSCin
TA = 25°C, OSC_2X =1
VCC = 3.0 V, OSC_2X = 1
Figure 9. OSCin Sensitivity
Figure 8. OSCin Sensitivity
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6.7.2 FinRF Input Impedance
Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in the Electrical
Characteristics section.
Marker 1:
1.0 GHz
Marker 2:
2.0 GHz
Marker 3:
3.0 GHz
Marker 4:
4.0 GHz
1
Marker 4:
4.5 GHz
2
4
Start 1.0 GHz
Stop 5.0 GHz
3
5
Figure 10. FinRF Input Impedance
Table 1. RF PLL Input Impedance
FREQUENCY (MHz)
1000
REAL (Ω)
192
172
154
139
127
114
104
96
IMAGINARY (Ω)
–221
–218
–209
–200
–192
–184
–175
–168
–160
–153
–147
–134
–123
–113
–103
–94
1100
1200
1300
1400
1500
1600
1700
1800
88
1900
80
2000
74
2200
64
2400
56
2600
50
2800
45
3000
39
3200
37
–86
3400
33
–78
3600
30
–72
3800
28
–69
4000
26
–66
4250
24
–63
4500
23
–60
4750
22
–57
5000
20
–54
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6.7.3 FinIF Input Impedance
ꢀarker 1:
100 ꢀIz
ꢀarker 2:
250 ꢀIz
ꢀarker 3:
2300 ꢀIz
2
1
ꢀarker 4:
3000 ꢀIz
3
{tart 100 ꢀIz
{top 3000 ꢀIz
4
Figure 11. FinIF Input Impedance
Table 2. IF PLL Input Impedance
FREQUENCY (MHz)
REAL (Ω)
508
456
420
403
370
344
207
274
242
242
214
171
137
112
91
IMAGINARY (Ω)
–233
–215
–206
–205
–207
–215
–223
–225
–225
–225
–222
–208
–191
–176
–158
–139
–122
–105
–96
100
150
200
250
300
400
500
600
700
800
900
1000
1200
1400
1600
1800
2000
2200
2300
2400
2600
2800
3000
76
62
51
46
42
–88
37
–74
29
–63
25
–54
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6.7.4 OSCin Input Impedance
Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in the Electrical
Characteristics section.
6000
5000
4000
3000
toꢀered
ꢁoꢀn
2000
1000
toꢀered
Üp
0
100
0
25
50
75
125
150
Cw9vÜ9b/ò (aIz)
Figure 12. OSCin Input Impedance
Table 3. OSCin Input Impedance
POWERED-UP
POWERED-DOWN
IMAGINARY
–8137
–4487
–2215
–1495
–1144
–912
FREQUENCY
(MHz)
REAL
1730
846
466
351
316
278
261
252
239
234
230
225
219
214
208
207
IMAGINARY
–3779
–2236
–1196
–863
MAGNITUDE
4157
2391
1284
932
REAL
392
155
107
166
182
155
153
154
147
145
140
138
133
133
132
133
MAGNITUDE
5
8146
4490
2217
–1504
1158
925
10
20
30
40
–672
742
50
–566
631
60
–481
547
–758
774
70
–425
494
–652
669
80
–388
456
–576
595
90
–358
428
–518
538
100
110
120
130
140
150
–337
407
–471
492
–321
392
–436
458
–309
379
–402
123
–295
364
–374
397
–285
353
–349
373
–279
348
–329
355
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6.7.5 Currents
Typical characteristics do not imply any sort of ensured specification. Ensured specifications are in the Electrical
Characteristics section.
2000
1500
1000
500
10
9.0
8.0
7.0
6.0
5.0
4.0
T
A
= 85oC
RF_CPG = 15
T
A
= 25oC
T
= -40oC
A
RF_CPG = 8
0
-500
RF_CPG = 0
3.0
-1000
-1500
-2000
RF_CPG = 1
2.0
1.0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
2.5
3.3
3.6
2.75
3.0
V
CC
(V)
V
(V)
CPoutRF
CE = High
VCC = 3 V
Figure 13. Power Supply Current
Figure 14. RF PLL Charge Pump Current
5.0
4.0
3.0
2.0
1.0
0
10
8
6
4
TA = 85o
C
2
0
TA = -40o
C
-1.0
-2
-4
TA = 25o
C
-2.0
-3.0
-4.0
-6
-8
-5.0
0
-10
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
3.0
2.5
V
(V)
CPoutIF
V
(V)
CPoutRF
VCC = 3 V
VCC = 3 V
Figure 15. IF PLL Charge Pump Current
Figure 16. Charge Pump Leakage RF PLL
10
8
6
TA = 85o
C
4
2
0
-2
-4
TA = -40o
C
TA = 25o
C
-6
-8
-10
2.5
0
0.5
1.0
1.5
2.0
3.0
VCPoutIF (V)
VCC = 3 V
Figure 17. Charge Pump Leakage IF PLL
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7 Parameter Measurements Information
7.1 Bench Test Set-Ups
7.1.1 Charge Pump Current Measurement
5/
.locking
/apacitor
10 ꢁIz
{ꢁ! /able
Crequency
Lnput ꢀin
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Figure 18. Setup for Charge Pump Current Measurement
Figure 18 shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current
level, mismatch, and leakage measurement. To measure the charge pump currents, a signal is applied to the
high frequency input pins. The reason for this is to ensure that the phase detector gets enough transitions to be
able to change states. If no signal is applied, it is possible that the charge pump current reading will be low due
to the fact that the duty cycle is not 100%. The OSCin Pin is tied to the supply. The charge pump currents can be
measured by simply programming the phase detector to the necessary polarity. For instance, To measure the RF
charge pump, a 10-MHz signal is applied to the FinRF pin. The source current can be measured by setting the
RF PLL phase detector to a positive polarity, and the sink current can be measured by setting the phase detector
to a negative polarity. The IF PLL currents can be measured in a similar way.
NOTE
The magnitude of the RF PLL charge pump current is controlled by the RF_CPG bit. Once
the charge pump currents are known, the mismatch can be calculated as well.
To measure leakage, the charge pump is set to a TRI-STATE mode by enabling the RF_CPT and IF_CPT bits.
The table below shows a summary of the various charge pump tests.
Table 4. Charge Pump Current Measurement Programmable Settings
CURRENT TEST
RF Source
RF Sink
RF_CPG
RF_CPP
RF_CPT
IF_CPP
IF_CPT
0 to 15
0
1
0
0
X
X
X
0
X
X
X
0
0
1
0 to 15
RF TRI-STATE
IF Source
X
X
X
X
X
X
X
X
1
X
X
X
IF Sink
1
IF TRI-STATE
X
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7.1.2 Charge Pump Current Specification Definitions
Figure 19. Charge Pump Current Definitions
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this part.
vCPout refers to either VCPoutRF or VCPoutIF
ICPout refers to either ICPoutRF or ICPoutIF
7.1.2.1 Charge Pump Output Current Variation vs Charge Pump Output Voltage
Use Equation 1 to calculate the charge pump output current variation versus charge pump output voltage.
(1)
7.1.2.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch
Use Equation 2 to calculate the charge pump sink current versus charge pump output source current mismatch.
(2)
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7.1.2.3 Charge Pump Output Current Variation vs Temperature
Use Equation 3 to calculate the charge pump output current variation versus temperature.
(3)
7.1.3 Sensitivity Measurement
{a! /ꢀꢂle
aꢀtching
betwork
Crequency
Lnput ꢁin
Signal Generator
5/
.locking
/ꢀpꢀcitor
5evice
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Çest
{a! /ꢀꢂle
Ctestꢃ[5
ꢁin
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9vꢀluꢀtion .oꢀrd
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Figure 20. Setup for Sensitivity Measurement
Table 5. Settings for Sensitivity Measurement
DC-BLOCKING
CAPACITOR
CORRESPONDING
COUNTER
DEFAULT COUNTER
VALUE
FREQUENCY INPUT PIN
MUX VALUE
OSCin
1000 pF
RF_R / 2
RF_N / 2
50
14
RF_P = 16/17/20/21
1023 + 2097150 /
4194301
FinRF
47 pF || 1000 pF
15
RF_P = 32/33/36/37
2039 + 2097150/4194301
FinIF
47 pF || 1000 pF
1000 pF
IF_N / 2
IF_R / 2
1533
50
13
12
OSCin
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz
or more of its expected value. It is typically measured over frequency, voltage, and temperature. To test
sensitivity, the MUX[3:0] word is programmed to the appropriate value. The counter value is then programmed to
a fixed value and a frequency counter is set to monitor the frequency of this pin. The expected frequency at the
Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The
factor of two comes in because the LMX2486 has a flip-flop which divides this frequency by two to make the duty
cycle 50% to make it easier to read with the frequency counter. The frequency counter input impedance should
be set to high impedance. To perform the measurement, the temperature, frequency, and voltage is set to a fixed
value and the power level of the signal is varied.
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NOTE
The power level at the part is assumed to be 4 dB less than the signal generator power
level. This accounts for 1 dB for cable losses and 3 dB for the pad.
The power level range where the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for
the sensitivity limits. The temperature, frequency, and voltage can be varied to produce a family of sensitivity
curves. Because this is an open-loop test, the charge pump is set to TRI-STATE and the unused side of the PLL
(RF or IF) is powered down when not being tested. For this part, there are actually four frequency input pins,
although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown in above
table.
NOTE
For the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a
fraction of 2097150 / 4194301 is used. The reason for this long fraction is to test the RF N
counter and supporting fractional circuitry as completely as possible.
7.1.4 Input Impedance Measurement
Crequency
Lnput ꢀin
betwork !nalyzer
5evice
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Çest
9valuation .oard
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Figure 21. Input Impedance Measurement
Figure 21 shows the test set-up used for measuring the input impedance for the LMX2486. The DC-blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a 0-Ω
resistor. This procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the
network analyzer, ensure that the part is powered up, and then measure the input impedance. The network
analyzer can be calibrated by using either calibration standards or by soldering resistors directly to the evaluation
board. An open can be implemented by putting no resistor, a short can be implemented by soldering a 0-Ω
resistor as close as possible to the pin being measured, and a short can be implemented by soldering two 100-Ω
resistors in parallel as close as possible to the pin being measured. Calibration is done with the PLL removed
from the PCB. This requires the use of a clamp down fixture that may not always be generally available. If no
clamp down fixture is available, then this procedure can be done by calibrating up to the point where the DC-
blocking capacitor usually is, and then implementing port extensions with the network analyzer. The 0-Ω resistor
is added back for the actual measurement. Once the set-up is calibrated, it is necessary to ensure that the PLL is
powered up. This can be done by toggling the power-down bits (RF_PD and IF_PD) and observing that the
current consumption indeed increases when the bit is disabled. Sometimes it may be necessary to apply a signal
to the OSCin pin to program the part. If this is necessary, disconnect the signal once it is established that the
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part is powered up. It is useful to know the input impedance of the PLL for the purposes of debugging RF
problems and designing matching networks. Another use of knowing this parameter is make the trace width on
the PCB such that the input impedance of this trace matches the real part of the input impedance of the PLL
frequency of operation. In general, it is good practice to keep trace lengths short and make designs that are
relatively resistant to variations in the input impedance of the PLL.
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8 Detailed Description
8.1 Overview
The LMX2486 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter
are supplied external to the chip.
8.2 Functional Block Diagram
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LC b ꢂivider
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16ꢁ17
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LC
[ꢂ
LC w
ꢂivider
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ëddwC2
ëddwC3
ëddwC4
ëddwC5
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Cꢀesꢀꢁ[ꢂ
wC w
ꢂivider
1X / 2X
wC [ꢂ
wC b ꢂivider
/ /ounꢀer
16ꢁ17ꢁ20ꢁ21
or
32ꢁ33ꢁ36ꢁ37
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tump
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8.3 Feature Description
8.3.1 TCXO, Oscillator Buffer, and R Counter
The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is
included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The
ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the
registers in the LMX2486.
The R counter divides this TCXO frequency down to the comparison frequency.
8.3.2 Phase Detector
The maximum phase detector operating frequency for the IF PLL is straightforward, but it is a little more involved
for the RF PLL because it is fractional. The maximum phase detector frequency for the LMX2486 RF PLL is 50
MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The crystal
reference frequency also limits the phase detector frequency, although the doubler helps with this limitation.
There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then phase noise
will be lower, but lock time may be increased due to cycle slipping and the capacitors in the loop filter may
become rather large.
8.3.3 Charge Pump
For the majority of the time, the charge pump output is high impedance, and the only current through this pin is
the TRI-STATE leakage. However, it does put out fast correction pulses that have a width that is proportional to
the phase error presented at the phase detector.
The charge pump converts the phase error presented at the phase detector into a correction current. The
magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF
PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL
allows for a higher charge pump current to be used when the PLL is locking to reduce the lock time.
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Feature Description (continued)
8.3.4 Loop Filter
The loop filter design can be rather involved. In addition to the regular constraints and design parameters, delta-
sigma PLLs have the additional constraint that the order of the loop filter should be one greater than the order of
the delta sigma modulator. This rule of thumb comes from the requirement that the loop filter must roll off the
delta sigma noise at 20 dB/decade faster than it rises. However, because the noise can not have infinite power, it
must eventually roll off. If the loop bandwidth is narrow, this requirement may not be necessary. For the purposes
of discussion in this data sheet, the pole of the loop filter at 0 Hz is not counted. So a second order filter has 3
components, a 3rd order loop filter has 5 components, and the 4th order loop filter has 7 components. Although a
5th order loop filter is theoretically necessary for use with a 4th order modulator, typically a 4th order filter is used
in this case. The loop filter design, especially for higher orders can be rather involved, but there are many
simulation tools and references available, such as the one given at the end of the functional description block.
8.3.5 N Counters and High Frequency Input Pins
The N counter divides the VCO frequency down to the comparison frequency. Because prescalers are used,
there are limitations on how small the N value can be. The N counters are discussed in greater depth in the
programming section. Because the input pins to these counters (FinRF and FinIF) are high frequency, layout
considerations are important.
8.3.5.1 High Frequency Input Pins, FinRF and FinIF
It is generally recommended that the VCO output go through a resistive pad and then through a DC-blocking
capacitor before it gets to these high frequency input pins. If the trace length is sufficiently short (< 1/10th of a
wavelength), then the pad may not be necessary, but a series resistor of about 39 Ω is still recommended to
isolate the PLL from the VCO. The DC-blocking capacitor should be chosen at least to be 27 pF. It may turn out
that the frequency is above the self-resonant frequency of the capacitor, but because the input impedance of the
PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad and the DC-blocking
capacitor should be placed as close to the PLL as possible
8.3.5.2 Complementary High Frequency Pin, FinRF*
These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended
fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such
that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating
frequency of the PLL. 100 pF is a typical value.
8.3.6 Digital Lock Detect Operation
The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase
detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less
than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to
approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The
values of ε and δ are dependent on which PLL is used and are shown in the table below:
Table 6. Programmable Lock Detect Settings
PLL
RF
IF
ε
δ
10 ns
15 ns
20 ns
30 ns
When the PLL is in the power-down mode and the Ftest/LD pin is programmed for the lock detect function, it is
forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the
DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to
divide the comparison frequency presented to the lock detect circuit by 4.
NOTE
If the MUX[3:0] word is set such as to view lock detect for both PLLs, an unlocked (LOW)
condition is shown whenever either one of the PLLs is determined to be out of lock.
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{Ç!wÇ
[5 = [hí
(bot [ocked)
bh
bh
bh
bh
Phase Error < e
ò9{
Phase Error < e
ò9{
Phase Error < e
ò9{
Phase Error < e
ò9{
bh
Phase Error < e
ò9{
[5 = ILDI
([ocked)
bh
ò9{
Phase Error > d
Figure 22. Digital Lock Detect Flowchart
8.3.7 Cycle Slip Reduction and Fastlock
The LMX2486 offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that
it requires no additional programming overhead to use them. It is generally recommended that the charge pump
current in the steady-state be 8X or less to use cycle slip reduction, and 4X or less in steady-state to use
Fastlock. The next step is to decide between using Fastlock or CSR. This determination can be made based on
the ratio of the comparison frequency (fCOMP) to loop bandwidth (BW).
Table 7. Fastlock/Cycle Slip Reduction Usage
COMPARISON FREQUENCY
(fCOMP
CYCLE SLIP REDUCTION
(CSR)
FASTLOCK
)
fCOMP ≤ 1.25 MHz
1.25 MHz < fCOMP ≤ 2 MHz
fCOMP > 2 MHz
Noticeable better than CSR
Marginally better than CSR
Same or worse than CSR
Likely to provide a benefit, provided that
fCOMP > 100 X BW
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8.3.7.1 Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the
same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases
where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can
occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically
the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR
provides no benefit. There is a glitch when CSR is disengaged, but because CSR should be disengaged long
before the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to
do this at the peak time of the transient response. Because this time is typically much sooner than Fastlock
should be disengaged, it does not make sense to use CSR and Fastlock in combination.
8.3.7.2 Fastlock
Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the
comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can
offer. Because Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide
a significant benefit in cases where the comparison frequency is above 2 MHz. However, CSR can usually
provide an equal or larger benefit in these cases, and can be implemented without using an additional resistor.
The reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits
the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option
of reducing the comparison frequency at the expense of phase noise to satisfy this constraint on comparison
frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these circumstances.
When using Fastlock, it is also recommended that the steady-state charge pump state be 4X or less. Also,
Fastlock was originally intended only for second order filters, so when implementing it with higher order filters,
the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well optimized
when the higher charge pump current and Fastlock resistor are engaged.
8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available
factors are 1/2, 1/4, and 1/16. To preserve the same loop characteristics, TI recommends that Equation 4 be
satisfied:
(Fastlock Charge Pump Current) / (Steady-State Charge Pump Current) = CSR
(4)
To satisfy this constraint, the maximum charge pump current in steady-state is 8X for a CSR of 1/2, 4X for a
CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump currents, it
makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger than this
will not improve lock time, and will result in worse phase noise.
Consider an example where the desired loop bandwidth in steady-state is 100 kHz and the comparison
frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it
was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is
probably sufficient. A charge pump current of 8X could be used in steady-state, and a factor of 16X could be
used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies
the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the
time, because it would probably have better phase noise, and the degradation in lock time would not be too
severe.
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8.3.7.4 Using Fastlock to Improve Lock Times
Figure 23. Loop Filter with Fastlock Resistor
Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed to determine the
theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel
during Fastlock. This ratio is calculated in Equation 5:
K = (Fastlock Charge Pump Current) / (Steady-State Charge Pump Current)
(5)
Table 8. Fastlock Usage
K
1
LOOP BANDWIDTH
1.00 X
R2P VALUE
Open
LOCK TIME
100 %
71 %
2
1.41 X
R2/0.41
R2/0.73
R2
3
1.73 X
58%
4
2.00 X
50%
8
2.83 X
R2/1.83
R2/2
35%
9
3.00 X
33%
16
4.00 X
R2/3
25%
The above table shows how to calculate the Fastlock resistor and theoretical lock time improvement, once the
ratio , K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, it is generally
recommended that the loop filter order be one greater than the order of the delta sigma modulator, which means
that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it
would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep
the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but
not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation
tools, or trial and error.
8.3.7.5 Capacitor Dielectric Considerations for Lock Time
The LMX2486 has a high fractional modulus and high charge pump gain for the lowest possible phase noise.
One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop
filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor
dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock
times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general
tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor
dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances,
allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase
noise and spurs.
8.3.8 Fractional Spur and Phase Noise Controls
Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be
made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at
increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than
the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional
spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The
bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order.
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The first step to do is choose FM, for the delta sigma modulator order. TI recommends to start with FM = 3 for a
third order modulator and use strong dithering. In general, there is a trade-off between primary and sub-fractional
spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary fractional
spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order), typically
gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd order
modulator is a compromise.
The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs,
but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or
even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but
the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best).
Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them
completely, but adds the most phase noise. Weak dithering (DITH = 1) is a compromise.
The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same,
expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the
fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional
denominator as large as possible, but not to exceed 4095, so it is not necessary to use the extended fractional
numerator or denominator.
NOTE
For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction,
Fastlock, and many other topics, visit http://www.ti.com. Here there is the EasyPLL
simulation tool and an online reference called PLL Performance, Simulation, and Design.
8.4 Device Functional Modes
8.4.1 Power Pins, Power-Down, and Power-Up Modes
TI recommends that all of the power pins be filtered with a series 18-Ω resistor and then placing two capacitors
shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values in theory,
the ESR (Equivalent Series Resistance) is greater for larger capacitors. For optimal filtering minimize the sum of
the ESR and theoretical impedance of the capacitor. It is therefore recommended to provide two capacitors of
very different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor should be
placed as close as possible to the pin.
The power down state of the LMX2486 is controlled by many factors. The one factor that overrides all other
factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is
necessary to power up the chip, however, there are other bits in the programming registers that can override this
and put the PLL back in a power down state. Provided that the voltage on the CE pin is high, programming the
RF_PD and IF_PD bits to zero ensures that the part will be powered up. Programming either one of these bits to
one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this.
Table 9. Powerdown Modes
ATPU
CE PIN
RF_PD
PLL STATE
BIT ENABLED + N COUNTER WRITE
Powered Down
(Asynchronous)
Low
X
X
High
High
X
0
Yes
No
Powered Up
Powered Up
Powered Down
(Asynchronous)
High
1
No
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8.5 Programming
8.5.1 General Programming Information
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program
the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data
register is shown below. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data
stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is shifted
in MSB first.
NOTE
It is best to program the N counter last, because doing so initializes the digital lock
detector and Fastlock circuitry. Initialize means it resets the counters, but it does NOT
program values into these registers. The exception is when 22-bit is not being used. In this
case, it is not necessary to program the R7 register.
Table 10. Programmable Register Structure
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4
3
2
1
0
8.5.1.1 Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are
mapped to the target control register.
Table 11. Programmable Registers
C3
x
C2
x
C1
x
C0
0
DATA LOCATION
R0
R1
R2
R3
R4
R5
R6
R7
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
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8.5.1.2 Control Register Content Map
Because the LMX2486 registers are complicated, they are organized into two groups, basic and advanced. The
first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The
last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page
shows these registers.
Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2486, the
quick start register map is shown in order for the user to get the part up and running quickly using only those bits
critical for basic functionality. The following default conditions for this programming state are a third order delta-
sigma modulator in 12-bit mode with strong dithering and no Fastlock.
Table 12. Quick Start Register Map
REGISTER
23
22
21
20
19
18
DATA[19:0] (Except for the RF_N Register, which is [22:0])
RF_N[10:0]
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C0
0
C3
C2
C1
R0
R1
RF_FN[11:0]
RF_P
D
RF_P
RF_R[5:0]
RF_FD[11:0]
0
0
1
1
R2
R3
IF_PD
IF_N[18:0]
0
0
1
1
0
1
1
1
0000
RF_CPG[3:0]
IF_R[11:0]
The complete register map shows all the functionality of all registers, including the last five.
Table 13. Complete Register Map
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0] (Except for the RF_N Register, which is [22:0])
C3 C2 C1 C0
0
R0
R1
R2
R3
RF_N[10:0]
RF_R[5:0]
RF_FN[11:0]
RF_PD RF_P
IF_PD
RF_FD[11:0]
IF_R[11:0]
0
0
0
0
1
1
1
0
1
1
1
1
IF_N[18:0]
ACCESS[3:0]
RF_CPG[3:0]
OSC
_OU
T
DITH
[1:0]
FM
[1:0]
OSC
_2X
IF_
CPP CPP
RF_
MUX
[3:0]
R4
ATPU
0
1
0
0
0
0
IF_P
1
0
0
1
R5
R6
RF_FD[21:12]
RF_CPF[3:0]
RF_FN[21:12]
RF_TOC[13:0]
1
1
0
1
1
0
1
1
CSR[1:0]
IF_R RF_ IF_C RF_
ST RST PT CPT
R7
0
0
0
0
0
0
0
0
0
0
DIV4
0
1
0
0
1
1
1
1
1
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8.6 Register Maps
8.6.1 R0 Register
NOTE
This register has only one control bit, so the N counter value to be changed with a single
write statement to the PLL.
Table 14. R0 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C0
0
DATA[22:0]
R0
RF_N[10:0]
RF_FN[11:0]
8.6.1.1 RF_FN[11:0] -- Fractional Numerator for RF PLL
Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] } for a more detailed
description of this control word.
8.6.1.2 RF_N[10:0] -- RF N Counter Value
The RF N counter contains an 16/17/20/21 and a 32/33/36/37 prescaler. The N counter value can be calculated
as follows:
N = RF_P·RF_C + 4·RF_B + RF_A
RF_C ≥Max{RF_A, RF_B} , for N-2FM-1 ... N+2FM is a necessary condition. This rule is slightly modified in the
case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for
the purposes of modulation. Consult the tables below for valid operating ranges for each prescaler.
Table 15. Operation With the 16/17/20/21 Prescaler (RF_P=0)
RF_N [10:0]
RF_N
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
<49
N Values less than 49 are illegal.
Legal Divide Ratios are:
2nd Order Modulator: 49-61
3rd Order Modulator: 51-59
4th Order Modulator: 55
49-63
Legal Divide Ratios are:
2nd and 3rd Order Modulator: All
4th Order Modulator: 64-75
64-79
80
...
0
.
0
.
0
1
.
0
.
1
.
0
0
0
0
.
0
.
0
0
.
.
.
1023
>1023
1
1
1
1
1
1
1
1
1
1
N values greater than 1023 are prohibited.
Table 16. Operation With the 32/33/36/37 Prescaler (RF_P=1)
RF_N [10:0]
RF_N
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
<97
N Values less than 97 are illegal.
Legal Divide Ratios are:
2nd Order Modulator: 97-109, 129-145, 161-181, 193-217, 225-226
3rd Order Modulator: 99-107, 131-143, 163-179, 195-215
4th Order Modulator: 103, 135-139, 167-175, 199-211
97-226
Legal Divide Ratios are:
2nd and 3rd Order Modulator: All
4th Order Modulator: None
227-230
231
0
0
0
1
1
1
0
0
1
1
1
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Table 16. Operation With the 32/33/36/37 Prescaler (RF_P=1) (continued)
RF_N [10:0]
RF_N
RF_C [5:0]
RF_B [2:0]
RF_A [1:0]
...
.
.
.
.
.
.
.
.
.
.
.
2039
1
1
1
1
1
1
1
0
1
1
1
2040-
2043
Possible with a second or third order delta-sigma engine.
2044-
2045
Possible only with a second order delta-sigma engine.
N values greater than 2045 are prohibited.
>2045
8.6.2 R1 Register
Table 17. R1 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3 C2 C1 C0
RF_P RF_
R1
RF_R[5:0]
RF_FD[11:0]
0
0
1
1
0
D
P
8.6.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator
The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0],
Access[1]}.
8.6.2.2 RF_R [5:0] -- RF R Divider Value
The RF R Counter value is determined by this control word.
NOTE
This counter does allow values down to one.
Table 18. RF R Divider
R VALUE
RF_R[5:0]
1
0
.
0
.
0
.
0
.
0
.
1
.
...
63
1
1
1
1
1
1
8.6.2.3 RF_P -- RF Prescaler bit
The prescaler used is determined by this bit.
Table 19. RF PLL Prescaler Select Bit and Frequencies
RF_P
PRESCALER
16/17/20/21
32/33/36/37
MAXIMUM FREQUENCY
4000 MHz
0
1
4500 MHz
8.6.2.4 RF_PD -- RF Power Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and
the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions,
and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL
will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so,
regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit
then takes control of the power down function for the RF PLL.
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8.6.3 R2 Register
Table 20. R2 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
DATA[19:0]
IF_N[18:0]
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R2
IF_PD
0
1
0
1
8.6.3.1 IF_N[18:0] -- IF N Divider Value
Table 21. IF_N Counter Programming With the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
N VALUE
IF_B
IF_A
≤23
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
24-55
56
57
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
0
0
.
0
0
.
0
0
.
0
1
.
...
262143
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Table 22. Operation With the 16/17 Prescaler (IF_P=1)
N VALUE
IF_B
IF_A
≤47
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
48-239
240
241
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
1
1
.
1
1
.
1
1
.
0
0
.
0
0
.
0
0
.
0
1
.
...
524287
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8.6.3.2 IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the
output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written
to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be
powered down, overriding the IF_PD bit.
8.6.4 R3 Register
Table 23. R3 Register
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3 C2 C1 C0
R3
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
0
1
1
1
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8.6.4.1 IF_R[11:0] -- IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for
IF_R is 3.
Table 24. IF PLL R Divider
R VALUE
IF_R[11:0]
3
...
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
1
.
4095
1
1
1
1
1
1
1
1
1
1
1
1
8.6.4.2 RF_CPG -- RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady-state operation.
Table 25. RF PLL Charge Pump Gain
TYPICAL RF CHARGE PUMP CURRENT
AT 3 V (µA)
RF_CPG
CHARGE PUMP STATE
0
1
1X
2X
95
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
11X
12X
13X
14X
15X
16X
950
10
11
12
13
14
15
1045
1140
1235
1330
1425
1520
8.6.4.3 Access -- Register Access Word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional.
The ACCESS[3:0] bits determine which additional registers must be programmed. Any one of these registers can
be individually programmed. According to the table below, when the state of a register is in default mode, all the
bits in that register are forced to a default state and it is not necessary to program this register. When the register
is programmable, it needs to be programmed through the MICROWIRE. Using this register access technique, the
programming required is reduced up to 50%.
Table 26. Access Word
ACCESS BIT
ACCESS[0]
ACCESS[1]
ACCESS[2]
ACCESS[3]
REGISTER LOCATION
REGISTER CONTROLLED
R3[20]
R3[21]
R3[22]
R3[23]
R4
R5
R6
R7
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The default conditions the registers is shown in Table 27:
Table 27. Default Register Conditions
REGISTER
23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data[19:0]
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
R4
R5
R6
R7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
This corresponds to the bit settings in Table 28.
Table 28. Default Register Word Descriptions
REGISTER
BIT LOCATION
R4[23]
BIT NAME
ATPU
BIT DESCRIPTION
Autopowerup
BIT VALUE
BIT STATE
Disabled
Strong
0
2
3
0
0
1
1
1
0
R4[17:16]
R4[15:14]
R4[12]
DITH
Dithering
FM
Modulator Order
3rd Order
Disabled
Disabled
Positive
Positive
16/17
OSC_2X
OSC_OUT
IF_CPP
RF_CPP
IF_P
Oscillator Doubler
OSCout Pin Enable
IF Charge Pump Polarity
RF Charge Pump Polarity
IF PLL Prescaler
Ftest/LD Output
R4
R4[11]
R4[10]
R4[9]
R4[8]
R4[7:4]
MUX
Disabled
Extended Fractional
Denominator
R5[23:14]
RF_FD[21:12]
0
Disabled
R5
R6
Extended Fractional
Numerator
R5[13:4]
R6[23:22]
R6[21:18]
RF_FN[21:12]
CSR
0
0
0
Disabled
Disabled
Disabled
Disabled
Cycle Slip Reduction
Fastlock Charge Pump
Current
RF_CPF
R6[17:4]
R7[13]
R7[7]
RF_TOC
DIV4
RF Time-Out Counter
Lock Detect Adjustment
IF PLL Counter Reset
RF PLL Counter Reset
IF PLL TRI-STATE
0
0
0
0
0
0
Disabled (Fcomp ≤ 20 MHz)
Disabled
IF_RST
RF_RST
IF_CPT
RF_CPT
R7
R7[6]
Disabled
R7[5]
Disabled
R7[4]
RF PLL TRI-STATE
Disabled
8.6.5 R4 Register
This register controls the conditions for the RF PLL in Fastlock.
Table 29. R4 Register
REGISTER
23 22 21 20 19 18 17 16 15 14 13
DATA[19:0]
OSC_ OSC_
12
11
10
9
8
7
6
5
4
3
2
1
0
C3 C2 C1 C0
AT
PU
DITH
[1:0]
FM
IF_
CPP
RF_
CPP
IF_
P
MUX
[3:0]
R4
0
1
0
0
0
0
1
0
0
1
[1:0]
2X OUT
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8.6.5.1 MUX[3:0] Frequency Out and Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
Table 30. MUX/Lock Detect Programming Settings
MUX[3:0]
OUTPUT TYPE
High Impedance
Push-Pull
OUTPUT DESCRIPTION
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disabled
General-purpose output, Logical “High” State
General-purpose output, Logical “Low” State
RF and IF Digital Lock Detect
RF Digital Lock Detect
Push-Pull
Push-Pull
Push-Pull
Push-Pull
IF Digital Lock Detect
Open-Drain
Open-Drain
Open-Drain
Push-Pull
RF and IF Analog Lock Detect
RF Analog Lock Detect
IF Analog Lock Detect
RF and IF Analog Lock Detect
RF Analog Lock Detect
Push-Pull
Push-Pull
IF Analog Lock Detect
Push-Pull
IF R Divider divided by 2
Push-Pull
IF N Divider divided by 2
Push-Pull
RF R Divider divided by 2
RF N Divider divided by 2
Push-Pull
8.6.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
Table 31. IF PLL Programmable Settings and Frequencies
IF_P
IF PRESCALER
MAXIMUM FREQUENCY
2300 MHz
0
1
8/9
16/17
3000 MHz
8.6.5.3 RF_CPP -- RF PLL Charge Pump Polarity
Table 32. RF PLL Charge Pump Polarity
RF_CPP
RF CHARGE PUMP POLARITY
0
1
Negative
Positive (Default)
8.6.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a
negative phase detector polarity.
Table 33. IF PLL Charge Pump Polarity
IF_CPP
IF CHARGE PUMP POLARITY
0
1
Negative
Positive
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8.6.5.5 OSC_OUT Oscillator Output Buffer Enable
Table 34. OSCout Pin Programmable Settings
OSC_OUT
OSCout PIN
0
1
Disabled (High Impedance)
Buffered output of OSCin pin
8.6.5.6 OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF
R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency
presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.
Table 35. Doubler Settings
FREQUENCY PRESENTED TO RF R
COUNTER
FREQUENCY PRESENTED TO IF R
COUNTER
OSC2X
0
1
fOSCin
fOSCin
2 x fOSCin
8.6.5.7 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels
closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the
loop filter should be at least one greater than the order of the delta-sigma modulator to allow for sufficient roll-off.
Table 36. Programmable Modulator Order
FM
0
FUNCTION
Fractional PLL mode with a 4th order delta-sigma modulator
Disable the delta-sigma modulator. Recommended for test use only.
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
1
2
3
8.6.5.8 DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional
spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific.
Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero,
dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often
occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends
not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is
decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.
Table 37. Dithering Settings
DITH
DITHERING MODE USED
Disabled
0
1
2
3
Weak Dithering
Strong Dithering
Reserved
8.6.5.9 ATPU -- PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0
register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case
is when the CE pin is low. In this case, the ATPU function is disabled.
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8.6.6 R5 Register
Table 38. R5 Register
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
REGISTER
DATA[19:0]
C3 C2 C1 C0
R5
RF_FD[21:12]
RF_FN[21:12]
1
0
1
1
8.6.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] }
In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12]
bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the
fractional numerator is expanded from 12 to 22-bits.
Table 39. Fractional Numerator Calculation
FRACTIONAL
RF_FN[21:12]
RF_FN[11:0]
NUMERATOR
(These bits only apply in 22-bit mode)
0
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
In 12-bit mode, these are do not care.
In 22-bit mode, for N <4096,
...
these bits should be all set to 0.
4095
4096
...
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8.6.6.2 Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], Access[1]}
In the case that the ACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the
RF_FD[21:12] bits become do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode
and the fractional denominator is expanded from 12 to 22-bits.
Table 40. Fractional Denominator Calculation
FRACTIONAL
RF_FD[21:12]
RF_FD[11:0]
DENOMINATOR
(These bits only apply in 22-bit mode)
0
1
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
In 12-bit mode, these are do not care.
In 22-bit mode, for N <4096,
...
these bits should be all set to 0.
4095
4096
...
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
0
.
1
.
4194303
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8.6.7 R6 Register
Table 41. R6 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3 C2 C1 C0
R6
CSR[1:0]
RF_CPF[3:0]
RF_TOC[13:0]
1
1
0
1
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8.6.7.1 RF_TOC -- RF Time-Out Counter and Control for FLoutRF Pin
The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the
FLoutRF output pin. When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and
the FLoutRF pin operates as a general-purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value
between 4 and 16383, the RF Fastlock mode is enabled and the FLoutRF pin is used as the RF Fastlock output
pin. The value programmed into the RF_TOC[13:0] word represents two times the number of phase detector
comparison cycles the RF synthesizer will spend in the Fastlock state.
Table 42. RF PLL Timout Counter
RF_TOC
FASTLOCK MODE
FASTLOCK PERIOD [CP EVENTS]
FLoutRF PIN FUNCTIONALITY
0
Disabled
N/A
High Impedance
Logic “0” State.
Forces all Fastlock conditions
1
Manual
N/A
2
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
N/A
N/A
Logic “0” State
Logic “1” State
Fastlock
3
4
4X2 = 8
5X2 = 10
…
5
Fastlock
…
Fastlock
16383
16383X2 = 32766
Fastlock
8.6.7.2 RF_CPF -- RF PLL Fastlock Charge Pump Current
Specify the charge pump current for the Fastlock operation mode for the RF PLL.
NOTE
The Fastlock charge pump current, steady-state current, and CSR control are all
interrelated.
Table 43. RF PLL Fastlock Charge Pump Current
TYPICAL RF CHARGE PUMP CURRENT
AT 3 V (µA)
RF_CPF
RF CHARGE PUMP STATE
0
1
1X
2X
95
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
11X
12X
13X
14X
15X
16X
950
10
11
12
13
14
15
1045
1140
1235
1330
1425
1520
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8.6.7.3 CSR[1:0] -- RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence
of phase detector cycle slips.
NOTE
The Fastlock charge pump current, steady-state current, and CSR control are all
interrelated. Refer to Cycle Slip Reduction and Fastlock for information on how to use this.
Table 44. RF PLL Cycle Slip Reduction
CSR
CSR STATE
Disabled
Enabled
SAMPLE RATE REDUCTION FACTOR
0
1
2
3
1
1/2
1/4
1/16
Enabled
Enabled
8.6.8 R7 Register
Table 45. R7 Register
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Data[19:0]
C3
C2
C1
C0
DIV
4
IF_R RF_ IF_C RF_
ST RST PT CPT
R7
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
8.6.8.1 DIV4 -- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked
condition for larger comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison
frequency (it does not apply to the IF comparison frequency) presented to the digital lock detect circuitry by 4.
This enables this circuitry to work at higher comparison frequencies. TI recommends that this bit be enabled
whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is being used.
8.6.8.2 IF_RST -- IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a TRI-STATE
condition. This feature should be disabled for normal operation.
NOTE
a counter reset is applied whenever the chip is powered up through software or CE pin.
Table 46. IF PLL Counter Reset
IF_RST
0 (Default)
1
IF PLL N AND R COUNTERS
Normal Operation
IF PLL CHARGE PUMP
Normal Operation
TRI-STATE
Counter Reset
8.6.8.3 RF_RST -- RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a TRI-STATE
condition. This feature should be disabled for normal operation. This feature should be disabled for normal
operation.
NOTE
A counter reset is applied whenever the chip is powered up through software or CE pin.
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Table 47. RF PLL Counter Reset
RF_RST
0 (Default)
1
RF PLL N and R Counters
Normal Operation
RF PLL Charge Pump
Normal Operation
TRI-STATE
Counter Reset
8.6.8.4 RF_TRI -- RF Charge Pump TRI-STATE
When this bit is enabled, the RF PLL charge pump is put in a TRI-STATE condition, but the counters are not
reset. This feature is typically disabled for normal operation.
Table 48. RF PLL Charge Pump TRI-STATE
RF_TRI
0 (Default)
1
RF PLL N and R Counters
Normal Operation
RF PLL Charge Pump
Normal Operation
TRI-STATE
Normal Operation
8.6.8.5 IF_TRI -- IF Charge Pump TRI-STATE
When this bit is enabled, the IF PLL charge pump is put in a TRI-STATE condition, but the counters are not
reset. This feature is typically disabled for normal operation.
Table 49. IF PLL Charge Pump TRI-STATE
IF_TRI
0 (Default)
1
IF PLL N and R Counters
Normal Operation
IF PLL Charge Pump
Normal Operation
TRI-STATE
Normal Operation
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This device ideal for use in a broad class of applications, especially those requiring low current consumption and
low fractional spurs. For applications that only need a single PLL, the unused PLL can be powered down and will
not draw any extra current or generate any spurs or crosstalk.
9.2 Typical Application
3.3 V
+3.3 V
R5
10
C7 R6
10 uF10
R4
10
R3
10
R2
10
R1
10
VddRF5
VddRF4
VddRF3
VddRF2
VddRF1
C6
C3p
C5
1μF
C4p C4
100 pF 1μF
C3
1μF
C2
1μF
C2p
100 pF
C1
1μF
C1p
100 pF
C5p
100 pF
1μF
100 pF
U1
13
16
FINIF
CPOUTIF
OSCOUT
FTEST/LD
CPOUTRF
FLOUTRF
19
20
18
12
1
C8
ENOSC
OSCIN
C9
OSCin
Ftest/LD
R7
470
0.1μF
4
5
1
12
11
10
9
FINRF
FINRF
GND
GND
R3_LF
R4_LF
2
3
4
C11
Vtune
GND
GND
GND
RFout
GND
R8
18
R9
18
0.1μF
RFout
C1_LF
C2_LF
C4_LF
C10
100pF
10
8
7
23
C3_LF
CE
CLK
DATA
LE
CE
100pF
CLK
DATA
LE
6
R2_LF
R10
18
+3.3 V
14
17
VDDIF1
VDDIF2
21
U2
NC
3
9
22
24
11
VddRF1
VddRF2
VddRF3
VddRF4
VddRF5
VDDRF1
VDDRF2
VDDRF3
VDDRF4
VDDRF5
2
15
GND
GND
25
GND
LMX248x
Figure 24. Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
Table 50 lists the design parameters of the LMX2486.
Table 50. Design Parameters
PARAMETER
Phase Margin
VALUE
46.5 degrees
9.8 KHz
4.50%
PM
BW
Loop Bandwidth
T3/T1
T4/T3
KPD
Pole Ratio
57.70%
8X (760 µA)
20 MHz
3200 – 3250
3 V
Charge Pump Gain
Phase Detector Frequency
VCO Frequency
Supply
fPD
fVCO
Vcc
KVCO
CVCO
C1_LF
C2_LF
C3_LF
C4_LF
R2_LF
R3_LF
R4_LF
VCO Gain
90 MHz/V
22 pF
VCO Input Capacitance
6.8 nF
220 nF
4.7 nF
Loop Filter Components
15 nF
150 Ω
56 Ω
33 Ω
9.2.2 Detailed Design Procedure
The design of the loop filter involves balancing requirements of lock time, spurs, and phase noise. This design is
fairly involved, but the TI website has references, design tools, and simulation tools cover the loop filter design
and simulation in depth.
9.2.3 Application Curves
Figure 26. Fractional Spurs at 200-kHz Offset
Figure 25. Phase Noise
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10 Power Supply Recommendations
Low noise regulators are generally recommended for the supply pins. It is OK to have one regulator supply the
part, although it is best to put individual bypassing as shown in the Layout Guidelines for the best spur
performance. If only using one PLL and not both DO NOT DISCONNECT OR GROUND power pins! For
instance, the IF PLL supply pins also supply other blocks than just the IF PLL and they must be connected.
However, if the IF PLL is disabled, then one can eliminate all bypass capacitors from these pins.
11 Layout
11.1 Layout Guidelines
The critical pin is the high freqeuncy input pin that should have a short trace. In general, try to keep the ground
and power planes 20 mils or more farther away from vias to supply pins to ensure that no spur energy can
couple to them.
11.2 Layout Example
High
Frequency
Input Pin
Figure 27. Simplified Layout for Only RF PLL Used
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
PLLatinum, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMX2486SQ/NOPB
ACTIVE
WQFN
RTW
24
1000 RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
L2486SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX2486SQ/NOPB
WQFN
RTW
24
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RTW 24
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LMX2486SQ/NOPB
1000
Pack Materials-Page 2
PACKAGE OUTLINE
RTW0024A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.1) TYP
EXPOSED
THERMAL PAD
7
12
20X 0.5
6
13
2X
25
2.5
2.6 0.1
1
18
0.3
24X
0.2
24
19
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
24X
4222815/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(1.05)
SYMM
25
(3.8)
20X (0.5)
(R0.05)
TYP
6
13
(
0.2) TYP
VIA
7
12
(1.05)
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222815/A 03/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
(0.675) TYP
19
(R0.05) TYP
24
24X (0.6)
1
18
24X (0.25)
(0.675)
TYP
SYMM
20X (0.5)
25
(3.8)
6
13
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222815/A 03/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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