LMX2491 [TI]
具有斜坡/线性调频脉冲生成功能的 6.4GHz 低噪声分数 N PLL;
| 型号： | LMX2491 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有斜坡/线性调频脉冲生成功能的 6.4GHz 低噪声分数 N PLL 脉冲 |
| 文件： | 总49页 (文件大小：2614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
LMX2491 具有斜坡/线性调频生成功能的 6.4GHz 低噪声 RF PLL
1 特性
3 说明
1
•
-227dBc/Hz 标准化锁相环 (PLL) 噪声
500MHz 至 6.4GHz 宽带 PLL
3.15V 至 5.25V 电荷泵 PLL 电源
多用途斜坡/超宽带信号源生成功能
200MHz 最大相位检测器频率
频移键控/相移键控 (FSK/PSK) 调制引脚
数字锁检测
LMX2491 器件是一款具有斜坡/线性调频生成功能的低
噪声 6.4GHz 宽带 Δ-Σ 分数 N PLL。它由一个相位频
率检测器、可编程电荷泵以及适用于外部 VCO 的高频
输入组成。LMX2491 广泛支持各类灵活的斜坡功能，
包括 FSK、PSK 和多达 8 段的可配置分段线性 FM 调
制配置文件。该器件具有精密 PLL 分辨率和快速斜升
功能，相位检测器速率高达 200MHz。LMX2491 允许
读回其任一寄存器。LMX2491 可由 3.3V 单电源供电
运行。此外，该器件支持电压高达 5.25V 的电荷泵，
无需使用外部放大器即可提供相位噪声性能得到改善的
简易解决方案。
•
•
•
•
•
•
•
3.3V 单电源供电
2 应用
•
•
•
•
•
•
•
调频连续波 (FMCW) 雷达
军用雷达
器件信息
微波回程
器件编号
LMX2491
封装
WQFN (24)
封装尺寸（标称值）
测试和测量
卫星通信
4.00mm x 4.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
无线基础设施
适用于高速模数转换器/数模转换器 (ADC/DAC) 的
采样时钟
简化原理图
OSCin
2X
R Divider
(16 bit)
CPout
Phase
Comp
Charge
Pump
51 Ω
GND/OSCin*
GND (x3)
C2_LF
R2_LF
51 Ω
C1_LF
Vcp
18 Ω
18 Ω
Vcc (x5)
Fin
CE
CLK
DATA
MICROWIRE
Interface
36 Ω
18 Ω
To Circuit
N Divider
(18 bit)
LE
Fin*
68 Ω
TRIG1
51 Ω
ꢀû
TRIG2
MOD
Modulation
Generator
Compensation
(24 bit)
MUX
MUXout
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNAS711
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
7.5 Programming........................................................... 14
7.6 Register Maps......................................................... 14
Applications and Implementation ...................... 27
8.1 Application Information............................................ 27
8.2 Typical Application .................................................. 27
Power Supply Recommendations...................... 39
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Storage Conditions.................................................... 4
6.3 ESD Ratings.............................................................. 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics .......................................... 5
8
9
10 Layout................................................................... 39
10.1 Layout Guidelines ................................................. 39
10.2 Layout Example .................................................... 40
11 器件和文档支持 ..................................................... 41
11.1 器件支持 ............................................................... 41
11.2 文档支持 ............................................................... 41
11.3 接收文档更新通知 ................................................. 41
11.4 社区资源................................................................ 41
11.5 商标....................................................................... 41
11.6 静电放电警告......................................................... 41
11.7 Glossary................................................................ 41
12 机械、封装和可订购信息....................................... 41
6.7 Timing Requirements, Programming Interface (CLK,
DATA, LE).................................................................. 6
6.8 Typical Characteristics ............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7
4 修订历史记录
Changes from Original (October 2016) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Deleted Charge pump output pin from the table ................................................................................................................... 4
Changed to Supply voltage ................................................................................................................................................... 4
Changed to I/O input voltage ................................................................................................................................................. 4
Changed to Power down current ........................................................................................................................................... 5
Changed DATA field bit description........................................................................................................................................ 6
Added new plots in Typical Characteristics ........................................................................................................................... 7
Changed Table 1 title ............................................................................................................................................................. 9
Added CMP0 and CMP1 definition. Changed Equation 1 description. ................................................................................ 12
Added Register Readback ................................................................................................................................................... 13
Added MSB bit description .................................................................................................................................................. 14
Changed the format in Window and fPD Frequency column ................................................................................................ 21
Changed to correct register bits location ............................................................................................................................. 23
Changed to correct value .................................................................................................................................................... 25
Added correct start time ...................................................................................................................................................... 26
Added design details and plots in Typical Application ........................................................................................................ 27
2
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
5 Pin Configuration and Functions
RTW Package
24-Pin VQFN
Top View
24 23 22 21 20 19
GND
1
18 Vcc
17 MUXout
GND
2
GND
3
LE
16
15
Pin 0
(Ground Substrate)
Fin
Fin*
Vcc
4
5
6
DATA
14 CLK
CE
13
7
8
9
10 11 12
Pin Functions
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
0
DAP
GND
GND
GND
GND
GND
Die Attach Pad. Connect to PCB ground plane.
Ground for charge pump.
1
2, 3
Ground for Fin Buffer
Complimentary high frequency input pins. Should be AC-coupled. If driving single-ended,
impedance as seen from Fin and Fin* pins looking outwards from the part should be roughly the
same.
Fin
Fin*
4, 5
Input
6
7
8
9
Vcc
Vcc
Supply
Supply
Supply
Input
Power Supply for Fin Buffer
Supply for On-chip LDOs
Supply for OSCin Buffer
Vcc
OSCin
Reference Frequency Input
Complimentary input for OSCin.
GND/
OSCin*
10
GND/Input If not used, it is recommended to match the termination as seen from the OSCin terminal looking
outwards. However, this may also be grounded as well.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
MOD
CE
GND
Ground for OSCin Buffer
Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
Input
GND
GND
Input
Chip Enable
CLK
DATA
LE
Serial Programming Clock.
Serial Programming Data
Serial Programming Latch Enable
MUXout Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
Vcc
Vcc
Supply
Supply
Supply for delta sigma engine.
Supply for general circuitry.
TRIG1
TRIG2
Vcp
Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics
Supply
NC
Power Supply for the charge pump.
No connect.
Rset
CPout
Output
Charge Pump Output
Copyright © 2016–2017, Texas Instruments Incorporated
3
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
VCC
–0.3
–0.3
MAX
5.5
UNIT
V
VCP
Supply voltage for charge pump
Supply voltage
VCC
3.6
V
VIN
I/O input voltage
VCC + 0.3
260
V
TSolder
TJunction
Lead temperature (solder 4 seconds)
Junction temperature
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Storage Conditions
applicable before the DMD is installed in the final product
MIN
MAX
150
3
UNIT
°C
Tstg
TDP
DMD storage temperature
Storage dew point
–65
°C
6.3 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±2500
±1500
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage
MIN
3.15
VCC
–40
–40
NOM
MAX
3.45
5.25
85
UNIT
VCC
VCP
TA
3.3
V
V
Charge pump supply voltage
Ambient temperature
°C
°C
TJ
Junction temperature
125
6.5 Thermal Information
LMX2491
THERMAL METRIC(1)
RTW (VQFN)
24 PINS
39.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
ψJB
Junction-to-case (top) thermal resistance
Junction-to-board characterization parameter
7.1
20
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
6.6 Electrical Characteristics
3.15 V ≤ VCC ≤ 3.45 V, VCC ≤ VCP ≤ 5.25 V, –40 °C ≤ TA ≤ 85 °C, except as specified. Typical values are at VCC = VCP = 3.3 V,
25 °C.
PARAMETER
TEST CONDITIONS
MIN
TYP
45
50
55
2
MAX
UNIT
fPD = 10 MHz
All Vcc pins
fPD = 100 MHz
fPD = 200 MHz
KPD = 0.1 mA
KPD = 1.6 mA
KPD = 3.1 mA
ICC
Current consumption
Power down current
mA
Vcp pin
10
19
3
ICCPD
POWERDOWN
OSC_DIFFR = 0, doubler disabled
OSC_DIFFR = 0, doubler enabled
OSC_DIFFR = 1, doubler disabled
OSC_DIFFR = 1, doubler enabled
10
10
600
300
Frequency for OSCin
terminal
fOSCin
MHz
10
1200
600
10
VOSCin
fFin
Voltage for OSCin pin(1)
Frequency for Fin pin
Power for Fin pin
0.5
500
–5
VCC – 0.5
6400
5
VPP
MHz
PFin
Single-ended operation
dBm
fPD
Phase detector frequency
PLL figure of merit(2)
200
MHz
PN1Hz
–227
–120
dBc/Hz
Normalized to 10-kHz offset for a 1-
GHz carrier.
PN10kHz
Normalized PLL 1/f noise(2)
dBc/Hz
nA
Charge pump leakage tri-
state leakage
Charge pump mismatch(3) VCPout = VCP / 2
ICPoutTRI
ICPoutMM
10
5%
0.1
CPG = 1X
…
ICPout
Charge pump current
VCPout = VCP / 2
mA
CPG = 31X
3.1
LOGIC OUTPUT TERMINALS (MUXout, TRIG1, TRIG2, MOD)
VOH
VOL
Output high voltage
Output low voltage
0.8 × VCC
VCC
0
V
V
0.2 × VCC
LOGIC INPUT TERMINALS (CE, CLK, DATA, LE, MUXout, TRIG1, TRIG2, MOD)
VIH
Input high voltage
1.4
0
VCC
0.6
5
V
V
VIL
Input low voltage
IIH
Input leakage current
Chip enable low time
Chip enable high time
–5
5
1
µA
µs
µs
tCELOW
tCEHIGH
5
(1) For optimal phase noise performance, higher input voltage and a slew rate of at least 3 V/ns is recommended
(2) PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model
the PLL noise for an infinite loop bandwidth as:
PLL_Total = 10 × log( 10PLL_Flat / 10 + 10PLL_Flicker(Offset) / 10
PLL_Flat = PN1Hz + 20 × log(N) + 10 × log(fPD / 1 Hz)
)
PLL_Flicker = PN10kHz - 10 × log(Offset / 10 kHz) + 20 × log(fVCO / 1 GHz)
(3) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation.
Copyright © 2016–2017, Texas Instruments Incorporated
5
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
6.7 Timing Requirements, Programming Interface (CLK, DATA, LE)
MIN
TYP
MAX
UNIT
ns
tCE
Clock to LE low time
10
4
tCS
Data to clock setup time
Data to clock hold time
Clock pulse width high
Clock pulse width low
Enable to clock setup time
Enable pulse width high
ns
tCH
4
ns
tCWH
tCWL
tCES
tEWH
10
10
10
10
ns
ns
ns
ns
DATA
MSB
LSB
tCS
tCH
CLK
tCES
tCWH
tCE
tEWH
tCWL
LE
Figure 1. Serial Data Input Timing
There are several other considerations for programming:
•
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE
signal, the data is sent from the shift register to an actual counter.
•
If no LE signal is given after the last data bit and the clock is kept toggling, then these bits are read into the
next lower register. This eliminates the need to send the address each time.
•
•
A slew rate of at least 30 V/µs is recommended for the CLK, DATA, and LE signals
Timing specs also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD
terminals.
6.8 Typical Characteristics
5
4
5
4
3
3
2
2
1
1
0
0
œ1
œ2
œ3
œ4
œ5
œ1
œ2
œ3
œ4
œ5
Kpd = 8x
Kpd = 16x
Kpd = 31x
Kpd = 8x
Kpd = 16x
Kpd = 31x
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Charge Pump Voltage (V)
Charge Pump Voltage (V)
C001
C002
Optimal performance is for a typical charge pump output voltage
between 0.5 and 2.8 volts.
Optimal performance is typically for a charge pump output voltage
between 0.5 and 4.5 volts.
Figure 2. Charge Pump Current for VCP = 3.3 V
Figure 3. Charge Pump Current for VCP = 5.5 V
6
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
Typical Characteristics (continued)
See Frequency Shift Keying Example for the detail of
configuration.
See Single Sawtooth Ramp Example for the detail of
configuration.
Figure 4. Frequency Shift Keying
Figure 5. Single Sawtooth Ramp
See Continuous Sawtooth Ramp Example for the detail of
configuration.
See Continuous Sawtooth Ramp with FSK Example for the detail
of configuration.
Figure 6. Continuous Sawtooth Ramp
Figure 7. Continuous Sawtooth Ramp with FSK
Copyright © 2016–2017, Texas Instruments Incorporated
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LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
Typical Characteristics (continued)
See Continuous Triangular Ramp Example for the detail of
configuration.
See Continuous Trapezoid Ramp Example for the detail of
configuration.
Figure 8. Continuous Triangular Ramp
Figure 9. Continuous Trapezoid Ramp
See Arbitrary Waveform Ramp Example for the detail of
configuration.
See Arbitrary Waveform Ramp Example for the detail of
configuration.
Figure 11. Output Flags
Figure 10. Arbitrary Waveform Ramp
8
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
7 Detailed Description
7.1 Overview
The LMX2491 is a microwave PLL, consisting of a reference input and divider, high frequency input and divider,
charge pump, ramp generator, and other digital logic. The Vcc power supply pins run at a nominal 3.3 volts,
while the charge pump supply pin, Vcp, operates anywhere from VCC to 5 volts. The device is designed to
operate with an external loop filter and VCO. Modulation is achieved by manipulating the MASH engine.
7.2 Functional Block Diagram
GND
(x3)
Vcc (x5)
Vcp
2X
OSCin
R Divider
(16 bit)
Charge
Pump
CPout
GND/OSCin*
Lock
Detect
Fin
Fin*
CE
N Divider
(18 bit)
4/5
Prescaler
TRIG1
TRIG2
MOD
CLK
DATA
ꢀû
Modulation
Generator
MUX
MICROWIRE
Interface
Compensation
(24 bit)
LE
MUXout
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 OSCin Input
The reference can be applied in several ways. If using a differential input, this must be terminated differentially
with a 100-Ω resistance and AC-coupled to the OSCin and GND/OSCin* terminals. If driving this single-ended,
then the GND/OSCin* terminal may be grounded, although better performance is attained by connecting the
GND/OSCin* terminal through a series resistance and capacitance to ground to match the OSCin terminal
impedance.
7.3.2 OSCin Doubler
The OSCin doubler allows the input signal to the OSCin to be doubled to have higher phase detector
frequencies. This works by clocking on both the rising and falling edges of the input signal, so it therefore
requires a 50% input duty cycle.
7.3.3 R Divider
The R counter is 16 bits divides the OSCin signal from 1 to 65535. If DIFF_R = 0, then any value can be chosen
in this range. If DIFF_R = 1, then the divide is restricted to 2, 4, 8, and 16, but allows for higher OSCin
frequencies.
7.3.4 PLL N Divider
The 16-bit N divider divides the signal at the Fin terminal down to the phase detector frequency. It contains a 4/5
prescaler that creates minimum divide restrictions, but allows the N value to increment in values of one.
Table 1. Allowable Minimum N Divider Values
MODULATOR ORDER
Integer Mode, 1st-Order Modulator
2nd-Order Modulator
MINIMUM N DIVIDE
16
17
19
25
3rd-Order Modulator
4th-Order Modulator
Copyright © 2016–2017, Texas Instruments Incorporated
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LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
7.3.5 Fractional Circuitry
The fractional circuitry controls the N divider with delta sigma modulation that supports a programmable first,
second, third, and fourth-order modulator. The fractional denominator is a fully programmable 24-bit denominator
that can support any value from 1, 2, ..., 224, with the exception when the device is running one of the ramps,
and in this case it is a fixed size of 224.
7.3.6 PLL Phase Detector and Charge Pump
The phase detector compares the outputs of the R and N dividers and generates a correction voltage
corresponding to the phase error. This voltage is converted to a correction current by the charge pump. The
phase detector frequency, fPD, can be calculated as follows: fPD = fOSCin × OSC_2X / R.
The charge pump supply voltage on this device, VCP, can be either run at the VCC voltage, or up to 5.25 volts to
get higher tuning voltages to present to the VCO.
7.3.7 External Loop Filter
The loop filter is external to the device and is application specific. Texas Instruments website has details on this
at www.ti.com.
7.3.8 Fastlock and Cycle Slip Reduction
This PLL has a Fastlock and a cycle slipping reduction feature. The user can enable these two features by
programming FL_TOC to a non-zero value. Every time PLL_N (the feedback divider, register R17 and R16) is
written, the Fastlock feature engages for the prescribed time set in FL_TOC. There are 3 actions that can be
enabled while the counter is running:
1. Change the charge pump current to the desired higher value FL_CPG. Typically this value would be set to
the maximum at 31x. This increases the loop bandwidth and hence reduces lock time.
2. Change the phase detector frequency with FL_CSR to reduce cycle slipping. The phase detector frequency
can be reduced by a factor 2 or 4 to reduce cycle slipping.
3. The loop filter can be configured to have a switchable R2 resistor to increase loop bandwidth and hence
reduce lock time. A resistor R2pLF is added in parallel to R2_LF and connected to the a terminal on the PLL
to use the internal switch. Any of the terminal MUXout, MOD, TRIG1,or TRIG2 can be configured for the
function. The terminal configuration is set as Output TOC Running. Also set the terminal as output inverted
OD (OD for open-drain) so the output will be high impedance in normal operation and act as ground in
Fastlock. The suggested schematic for that feature is shown in Figure 12.
/harge
/touꢀ
tump
/2_[C
ÇwLD2
/1_[C
w2p[C
w2_[C
Casꢀlock
/onꢀrol
Figure 12. Suggested Schematic to Enable the Variable Loop Bandwidth Filter In Fastlock Mode
Table 2. Fastlock Settings: Charge Pump Gain and Fastlock Pin Status
PARAMETER
NORMAL OPERATION
FASTLOCK OPERATION
Charge Pump Gain
CPG
FL_CPG
Device Pin
(TRIG1, TRIG2, MOD, or MUXout)
High Impedance
Grounded
10
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
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ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
The resistor and the charge pump current are changed simultaneously so that the phase margin remains the
same while the loop bandwidth is by a factor of K as shown in the following table:
Table 3. Suggested Equations to Calculate R2pLF
PARAMETER
Charge Pump Gain in Fastlock
Loop Bandwidth Multiplier
External Resistor
CALCULATION
Typically use the highest value.
K = sqrt(FL_CPG / CPG)
R2 / (K - 1)
FL_CPG
K
R2pLF
Cycle slip reduction is another method that can also be used to speed up lock time by reducing cycle slipping.
Cycle slipping typically occurs when the phase detector frequency exceeds about 100x the loop bandwidth of the
PLL. Cycle slip reduction works in a different way than fastlock. To use this, the phase detector frequency is
decreased while the charge pump current is simultaneously increased by the same factor. Although the loop
bandwidth is unchanged, the ratio of the phase detector frequency to the loop bandwidth is, and this is helpful for
cases when the phase detector frequency is high. Because cycle slip reduction changes the phase detector rate,
it also impacts other things that are based on the phase detector rate, such as the fastlock timeout-counter and
ramping controls.
7.3.9 Lock Detect and Charge Pump Voltage Monitor
The LMX2491 offers two methods to determine if the PLL is in lock: charge pump voltage monitoring and digital
lock detect. These features can be used individually or in conjunction to give a reliable indication of when the
PLL is in lock. The output of this detection can be routed to the TRIG1, TRIG2, MOD, or MUXout terminals.
7.3.9.1 Charge Pump Voltage Monitor
The charge pump voltage monitor allows the user to set low (CMP_THR_LOW) and high (CMP_THR_HIGH)
thresholds for a comparator that monitors the charge pump output voltage.
Table 4. Desired Comparator Threshold Register Settings for Two Charge Pump Supplies
VCP
THRESHOLD
SUGGESTED LEVEL
CPM_THR_LOW
= (Vthresh + 0.08) / 0.085
6 for 0.5-V limit
3.3 V
CPM_THR_HIGH
42 for 2.8-V limit
4 for 0.5-V limit
46 for 4.5-V limit
= (Vthresh - 0.96) / 0.044
CPM_THR_LOW
= (Vthresh + 0.056) / 0.137
5.0 V
CPM_THR_HIGH
= (Vthresh -1.23) / 0.071
7.3.9.2 Digital Lock Detect
Digital lock detect works by comparing the phase error as presented to the phase detector. If the phase error
plus the delay as specified by the PFD_DLY bit is outside the tolerance as specified by DLD_TOL, then this
comparison would be considered to be an error, otherwise passing. The DLD_ERR_CNT specifies how may
errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT specifies
how many passing comparisons are necessary to cause the PLL to be considered to be locked and also resets
the count for the errors. The DLD_TOL value should be set to no more than half of a phase detector period plus
the PFD_DLY value. The DLD_ERR_CNT and DLD_PASS_CNT values can be decreased to make the circuit
more sensitive. If the circuit is too sensitive, then chattering can occur and the DLD_ERR_CNT,
DLD_PASS_CNT, or DLD_TOL values should be increased.
NOTE
If the OSCin signal goes away and there is no noise or self-oscillation at the OSCin pin,
then it is possible for the digital lock detect to indicate a locked state when the PLL really
is not in lock. If this is a concern, then digital lock detect can be combined with charge
pump voltage monitor to detect this situation.
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7.3.10 FSK/PSK Modulation
Two-level FSK or PSK modulation can be created whenever a trigger event, as defined by the FSK_TRIG field is
detected. This trigger can be defined as a transition on a terminal (TRIG1, TRIG2, MOD, or MUXout) or done
purely in software. The RAMP_PM_EN bit defines the modulation to be either FSK or PSK and the FSK_DEV
register determines the amount of the deviation. Remember that the FSK_DEV[32:0] field is programmed as the
2's complement of the actual desired FSK_DEV value. This modulation can be added to the modulation created
from the ramping functions as well.
Table 5. How to Obtain Deviation for Two Types of Modulation
RAMP_PM_EN
MODULATION TYPE
2 Level FSK
DEVIATION
0
1
fPD × FSK_DEV / 224
360° × FSK_DEV / 224
2 Level PSK
7.3.11 Ramping Functions
The LMX2491 supports a broad and flexible class of FMCW modulation formed by up to 8 linear ramps. When
the ramping function is running, the denominator is fixed to a forced value of 224 = 16777216. The waveform
always starts at RAMP0 when the LSB of the PLL_N (R16) is written to. After it is set up, it starts at the initial
frequency and have piecewise linear frequency modulation that deviates from this initial frequency as specified
by the modulation. Each of the eight ramps can be individually programmed. Various settings are as follows:
Table 6. Register Descriptions of the Ramping Function
RAMP
CHARACTERISTIC
PROGRAMMING FIELD
NAME
DESCRIPTION
The user programs the length of the ramp in phase detector cycles. If
RAMPx_DLY = 1, then each count of RAMPx_LEN is actually two phase
detector cycles.
RAMPx_LEN
RAMPx_DLY
Ramp Length
The user does not directly program slope of the line, but rather this is done by
defining how long the ramp is and how much the fractional numerator is
increased per phase detector cycle. The value for RAMPx_INC is calculated by
taking the total expected increase in the frequency, expressed in terms of how
much the fractional numerator increases, and dividing it by RAMPx_LEN. The
value programmed into RAMPx_INC is actually the two's complement of the
desired mathematical value.
RAMPx_LEN
RAMPx_DLY
RAMPx_INC
Ramp Slope
The event that triggers the next ramp can be defined to be the ramp finishing or
can wait for a trigger as defined by Trigger A, Trigger B, or Trigger C.
Trigger for Next Ramp
Next Ramp
RAMPx_NEXT_TRIG
RAMPx_NEXT
This sets the ramp that follows. Waveforms are constructed by defining a chain
ramp segments. To make the waveform repeat, make RAMPx_NEXT point to
the first ramp in the pattern.
Ramp Fastlock
Ramp Flags
RAMPx_FL
This allows the ramp to use a different charge pump current or use Fastlock
This allows the ramp to set a flag that can be routed to external terminals to
trigger other devices.
RAMPx_FLAG
7.3.11.1 Ramp Count
If it is desired that the ramping waveform keep repeating, then all that is needed is to make the RAMPx_NEXT of
the final ramp equal to the first ramp. This runs until the RAMP_EN bit is set to zero. If this is not desired, then
one can use the RAMP_COUNT to specify how may times the specified pattern is to repeat.
7.3.11.2 Ramp Comparators and Ramp Limits
The ramp comparators and ramp limits use programable thresholds to allow the device to detect whenever the
modulated waveform frequency crosses a limit as set by the user. The difference between these is that
comparators set a flag to alert the user while a ramp limits prevent the frequency from going beyond the
prescribed threshold. In either case, these thresholds are expressed by programming the
Extended_Fractional_Numerator. CMP0 and CMP1 are two separated comparators but they work in the same
fashion.
Extended_Fractional_Numerator = Fractional_Numerator + (N - N*) × 224
(1)
12
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In Equation 1, N* is the PLL feedback value without ramping. Fractional_Numerator and N are the new values as
defined by the threshold frequency. The actual value programmed is the 2's complement of
Extended_Fractional_Numerator.
Table 7. Register Descriptions of Ramp Comparators and Limits
TYPE
PROGRAMMING BIT
RAMP_LIMIT_LOW
RAMP_LIMIT_HIGH
THRESHOLD
Lower Limit
Upper Limit
Ramp Limits
For the ramp comparators, if the ramp is increasing and exceeds the value as specified
by RAMP_CMPx, then the flag goes high, otherwise it is low. If the ramp is decreasing
and goes below the value as specified by RAMP_CMPx, then the flag goes high,
otherwise it is low.
Ramp
Comparators
RAMP_CMP0
RAMP_CMP1
7.3.12 Power-on-reset (POR)
The power-on-reset circuitry sets all the registers to a default state when the device is powered up. This same
reset can be done by programming SWRST = 1. In the programming section, the power on reset state is given
for all the programmable fields.
7.3.13 Register Readback
The LMX2491 allows any of its registers to be read back. MOD, MUXout, TRIG1 or TRIG2 pin can be
programmed to support register-readback serial-data output. To read back a certain register value, follow the
following steps:
1. Set the R/W bit to 1; the data field contents are ignored.
2. Send the register to the device; readback serial data will be output starting at the 17th clock cycle.
R/W
= 1
Address
15-bit
Data
= Ignored
DATA
CLK
1st
2nd œ 16th
17th œ 24th
MOD
MUXout
TRIG1
Read back register value
8-bit
TRIG2
LE
Figure 13. Register Readback Timing Diagram
7.4 Device Functional Modes
The two primary ways to use the LMX2491 are to run it to generate a set of frequencies
7.4.1 Continuous Frequency Generator
In this mode, the LMX2491 generates a single frequency that only changes when the N divider is programmed to
a new value. In this mode, the RAMP_EN bit is set to 0 and the ramping controls are not used. The fractional
denominator can be programmed to any value from 1 to 16777216. In this kind of application, the PLL is tuned to
different channels, but at each channel, the goal is to generate a stable fixed frequency.
7.4.1.1 Integer Mode Operation
In integer mode operation, the VCO frequency needs to be an integer multiple of the phase detector frequency.
This can be the case when the output frequency or frequencies are nicely related to the input frequency. As a
rule of thumb, if this an be done with a phase detector of as high as the lesser of 10 MHz or the OSCin
frequency, then this makes sense. To operate the device in integer mode, disable the fractional circuitry by
programming the fractional order (FRAC_ORDER), dithering (FRAC_DITH), and numerator (FRAC_NUM) to
zero.
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Device Functional Modes (continued)
7.4.1.2 Fractional Mode Operation
In fractional mode, the output frequency does not need to be an integer multiple of the phase detector frequency.
This makes sense when the channel spacing is more narrow or the input and output frequencies are not nicely
related. There are several programmable controls for this such as the modulator order, fractional dithering,
fractional numerator, and fractional denominator. There are many trade-offs with choosing these, but here are
some guidelines
Table 8. Fractional Mode Register Descriptions and Recommendations
PARAMETER
FIELD NAME
HOW TO CHOOSE
The first step is to find the fractional denominator. To do this, find the frequency that
divides the phase detector frequency by the channel spacing. For instance, if the
output ranges from 5000 to 5050 in 5-MHz steps and the phase detector is 100
MHz, then the fractional denominator is 100 MHz / 5 = 20. So for a an output of
5015 MHz, the N divider would be 50 + 3/20. In this case, the fractional numerator is
3 and the fractional denominator is 20. Sometimes when dithering is used, it makes
sense to express this as a larger equivalent fraction.
Fractional Numerator and
Denominator
FRAC_NUM
FRAC_DEN
Note that if ramping is active, the fractional denominator is forced to 224
.
There are many trade-offs, but in general try either the 2nd or 3rd-order modulator
Fractional Order
Dithering
FRAC_ORDER as starting points. The 3rd-order modulator may give lower main spurs, but may
generate others. Also if dithering is involved, it can generate phase noise.
Dithering can reduce some fractional spurs, but add noise. Consult application note
FRAC_DITH
AN-1879 Fractional N Frequency Synthesis for more details on this.
7.4.2 Modulated Waveform Generator
In this mode, the device can generate a broad class of frequency sweeping waveforms. The user can specify up
to 8 linear segments to generate these waveforms. When the ramping function is running, the denominator is
fixed to a forced value of 224 = 16777216
In addition to the ramping functions, there is also the capability to use a terminal to add phase or frequency
modulation that can be done by itself or added on top of the waveforms created by the ramp generation
functions.
7.5 Programming
7.5.1 Loading Registers
The device is programmed using several 24-bit registers. Each register consists of a data field, an address field,
and a R/W bit. The MSB is the R/W bit. 0 means register write while 1 means register read. The following 15 bits
of the register are the address, followed by the next 8 bits of data. The user has the option to pull the LE terminal
high after this data, or keep sending data and it applies this data to the next lower register. So instead of sending
three registers of 24 bits each, one could send a single 40-bit register with the 16 bits of address and 24 bits of
data. For that matter, the entire device could be programmed as a single register if desired.
7.6 Register Maps
Registers are programmed in REVERSE order from highest to lowest. Registers NOT shown in this table or
marked as reserved can be written as all 0s unless otherwise stated. The POR value is the power on reset value
that is assigned when the device is powered up or the SWRST bit is asserted.
Table 9. Register Map
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
POR
0x18
0x00
0x00
-
0
1
0
0
0
0
1
1
0
0
0
0x1
0x2
Reserved
Reserved
2
0
0
0
0
0
SWRST
POWERDOWN[1:0]
3 - 15
16
0x3 - 0xF
0x10
PLL_N[7:0]
0x64
14
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Register Maps (continued)
Table 9. Register Map (continued)
REGISTER
17
D7
D6
D5
D4
PLL_N[15:8]
FRAC_DITHER[1:0]
D3
D2
D1
D0
POR
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x00
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
18
19
20
21
22
23
24
25
26
0
FRAC_ORDER[2:0]
PLL_N[17:16]
FRAC_NUM[7:0]
FRAC_NUM[15:8]
FRAC_NUM[23:16]
FRAC_DEN[7:0]
FRAC_DEN[15:8]
FRAC_DEN[23:16]
PLL_R[7:0]
PLL_R[15:8]
PLL_R_
DIFF
27
0x1B
0
0
FL_CSR[1:0]
PFD_DLY[1:0]
0
OSC_2X
0x08
28
29
0x1C
0x1D
0
CPPOL
CPG[4:0]
0x00
0x00
FL_TOC[10:8]
FL_CPG[4:0]
CPM_
FLAGL
30
31
0x1E
0x1F
0
0
CPM_THR_LOW[5:0]
CPM_THR_HIGH[5:0]
0x0A
0x32
CPM_
FLAGH
32
33
34
0x20
0x21
0x22
FL_TOC[7:0]
DLD_PASS_CNT[7:0]
DLD_ERR_CNTR[4:0]
0x00
0x0F
0x00
DLD_TOL[2:0]
1
MOD_
MUX[5]
MUXout
_MUX[5]
TRIG2
TRIG1
_MUX[5]
35
0x23
0
0
1
0x41
_MUX[5]
36
37
38
39
0x24
0x25
0x26
0x27
TRIG1_MUX[4:0]
TRIG2_MUX[4:0]
MOD_MUX[4:0]
TRIG1_PIN[2:0]
TRIG2_PIN[2:0]
MOD_PIN[2:0]
0x08
0x10
0x18
0x38
MUXout_MUX[4:0]
MUXout_PIN[2:0]
0x28 -
0x39
40 - 57
58
Reserved
-
RAMP_
PM_EN
RAMP_
CLK
0x3A
RAMP_TRIG_A[3:0]
RAMP_TRIG_C[3:0]
0
RAMP_EN
0x00
59
60
61
62
63
64
65
66
67
68
69
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
RAMP_TRIG_B[3:0]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RAMP_CMP0[7:0]
RAMP_CMP0[15:8]
RAMP_CMP0[23:16]
RAMP_CMP0[31:24]
RAMP_CMP0_EN[7:0]
RAMP_CMP1[7:0]
RAMP_CMP1[15:8]
RAMP_CMP1[23:16]
RAMP_CMP1[31:24]
RAMP_CMP1_EN[7:0]
RAMP_
LIMH[32]
RAMP_
LIML[32]
FSK_
DEV[32]
RAMP_
CMP1[32] CMP0[32]
RAMP_
70
0x46
0
FSK_TRIG[1:0]
0x08
71
72
73
74
0x47
0x48
0x49
0x4A
FSK_DEV[7:0]
0x00
0x00
0x00
0x00
FSK_DEV[15:8]
FSK_DEV[23:16]
FSK_DEV[31:24]
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Register Maps (continued)
Table 9. Register Map (continued)
REGISTER
75
D7
D6
D5
D4
D3
D2
D1
D0
POR
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0x00
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
RAMP_LIMIT_LOW[7:0]
RAMP_LIMIT_LOW[15:8]
RAMP_LIMIT_LOW[23:16]
RAMP_LIMIT_LOW[31:24]
RAMP_LIMIT_HIGH[7:0]
RAMP_LIMIT_HIGH[15:8]
RAMP_LIMIT_HIGH[23:16]
RAMP_LIMIT_HIGH[31:24]
RAMP_COUNT[7:0]
76
77
78
79
80
81
82
83
RAMP_
AUTO
84
0x54
RAMP_TRIG_INC[1:0]
RAMP_COUNT[12:8]
0x00
85
86
87
88
0x55
0x56
0x57
0x58
Reserved
0x00
0x00
0x00
0x00
RAMP0_INC[7:0]
RAMP0_INC[15:8]
RAMP0_INC[23:16]
RAMP0_
DLY
RAMP0_
FL
89
0x59
RAMP0_INC[29:24]
0x00
90
91
0x5A
0x5B
RAMP0_LEN[7:0]
RAMP0_LEN[15:8]
0x00
0x00
RAMP0_
NEXT_TRIG[1:0]
RAMP0_
RST
92
0x5C
RAMP0_NEXT[2:0]
RAMP0_FLAG[1:0]
RAMP1_FLAG[1:0]
RAMP2_FLAG[1:0]
RAMP3_FLAG[1:0]
0x00
93
94
95
0x5D
0x5E
0x5F
RAMP1_INC[7:0]
RAMP1_INC[15:8]
RAMP1_INC[23:16]
0x00
0x00
0x00
RAMP1_
DLY
RAMP1_
FL
96
0x60
RAMP1_INC[29:24]
RAMP1_LEN[7:0]
0x00
97
98
0x61
0x62
0x00
0x00
RAMP1_LEN[15:8]
RAMP1_
NEXT_TRIG[1:0]
RAMP1_
RST
99
0x63
RAMP1_NEXT[2:0]
0x00
100
101
102
0x64
0x65
0x66
RAMP2_INC[7:0]
RAMP2_INC[15:8]
RAMP2_INC[23:16]
0x00
0x00
0x00
RAMP2
DLY
RAMP2_
FL
103
0x67
RAMP2_INC[29:24]
RAMP2_LEN[7:0]
0x00
104
105
0x68
0x69
0x00
0x00
RAMP2_LEN[15:8]
RAMP2_
NEXT_TRIG[1:0]
RAMP2_
RST
106
0x6A
RAMP2_NEXT[2:0]
0x00
107
108
109
0x6B
0x6C
0x6D
RAMP3_INC[7:0]
RAMP3_INC[15:8]
RAMP3_INC[23:16]
0x00
0x00
0x00
RAMP3_
DLY
RAMP3_
FL
110
0x6E
RAMP3_INC[29:24]
RAMP3_LEN[7:0]
0x00
111
112
0x6F
0x70
0x00
0x00
RAMP3_LEN[15:8]
RAMP3_
NEXT_TRIG[1:0]
RAMP3_
RST
113
0x71
RAMP3_NEXT[2:0]
0x00
16
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Register Maps (continued)
Table 9. Register Map (continued)
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
POR
0x00
0x00
0x00
114
0x72
0x73
0x74
RAMP4_INC[7:0]
RAMP4_INC[15:8]
RAMP4_INC[23:16]
115
116
RAMP4_
DLY
RAMP4_
FL
117
0x75
RAMP4_INC[29:24]
RAMP4_LEN[7:0]
0x00
118
119
0x76
0x77
0x00
0x00
RAMP4_LEN[15:8]
RAMP4_
NEXT_TRIG[1:0]
RAMP4_
RST
120
0x78
RAMP4_NEXT[2:0]
RAMP4_FLAG[1:0]
RAMP5_FLAG[1:0]
RAMP6_FLAG[1:0]
RAMP7_FLAG[1:0]
0x00
121
122
123
0x79
0x7A
0x7B
RAMP5_INC[7:0]
RAMP5_INC[15:8]
RAMP5_INC[23:16]
0x00
0x00
0x00
RAMP5_
DLY
RAMP5_
FL
124
0x7C
RAMP5_INC[29:24]
RAMP5_LEN[7:0]
0x00
125
126
0x7D
0x7E
0x00
0x00
RAMP5_LEN[15:8]
RAMP5_
NEXT_TRIG[1:0]
RAMP5_
RST
127
0x7F
RAMP5_NEXT[2:0]
0x00
128
129
130
0x80
0x81
0x82
RAMP6_INC[7:0]
RAMP6_INC[15:8]
RAMP6_INC[23:16]
0x00
0x00
0x00
RAMP6_
DLY
RAMP6_
FL
131
0x83
RAMP6_INC[29:24]
RAMP6_LEN[7:0]
0x00
132
133
0x84
0x85
0x00
0x00
RAMP6_LEN[15:8]
RAMP6_
NEXT_TRIG[1:0]
RAMP6_
RST
134
0x86
RAMP6_NEXT[2:0]
0x00
135
136
137
0x87
0x88
0x89
RAMP7_INC[7:0]
RAMP7_INC[15:8]
RAMP7_INC[23:16]
0x00
0x00
0x00
RAMP7_
DLY
RAMP7_
FL
138
0x8A
RAMP7_INC[29:24]
RAMP7_LEN[7:0]
0x00
139
140
0x8B
0x8C
0x00
0x00
RAMP7_LEN[15:8]
RAMP7_
NEXT_TRIG[1:0]
RAMP7_
RST
141
0x8D
RAMP7_NEXT[2:0]
0x00
0x00
142 -
32767
0x8E -
0x7FFF
Reserved
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7.6.1 Register Field Descriptions
The following sections go through all the programmable fields and their states. Additional information is also
available in the applications and feature descriptions sections as well. The POR column is the power on reset
state that this field assumes if not programmed.
7.6.1.1 POWERDOWN and Reset Fields
Table 10. POWERDOWN and Reset Fields
FIELD
LOCATION POR
DESCRIPTION AND STATES
Value
POWERDOWN State
Power Down, ignore CE
Power Up, ignore CE
0
1
POWERDOWN
[1:0]
R2[1:0]
R2[2]
0
0
POWERDOWN Control
Power State Defined by CE
terminal state
2
3
Reserved
Reset State
Value
Software Reset. Setting this bit sets all
registers to their POR default values.
SWRST
0
1
Normal Operation
Register Reset
18
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7.6.1.2 Dividers and Fractional Controls
Table 11. Dividers and Fractional Controls
FIELD
LOCATION POR
DESCRIPTION AND STATES
PLL_N
[17:0]
R18[1] to
16
Feedback N counter Divide value. Minimum count is 16. Maximum is 262132. Writing of
the register R16 begins any ramp execution when RAMP_EN = 1.
R16[0]
Value
Dither
Weak
0
FRAC_ DITHER
[1:0]
R18[3:2]
R18[6:4]
0
0
Dither used by the fractional modulator
1
Medium
2
Strong
3
Disabled
Value
Modulator Order
Integer Mode
1st Order Modulator
2nd Order Modulator
3rd Order Modulator
4th Order Modulator
Reserved
0
1
FRAC_ ORDER
[2:0]
Fractional Modulator order
2
3
4
5-7
FRAC_NUM
[23:0]
R21[7] to
R19[0]
Fractional Numerator. This value should be less than or equal to the fractional
denominator.
0
0
1
FRAC_DEN
[23:0]
R24[7] to
R22[0]
Fractional Denominator. If RAMP_EN = 1, this field is ignored and the denominator is
fixed to 224
.
PLL_R
[15:0]
R26[7] to
R25[0]
Reference Divider value. Selecting 1 bypasses counter.
Value
Doubler
Disabled
Enables the Doubler before the Reference
divider
OSC_2X
R27[0]
R27[2]
0
0
0
1
Enabled
Enables the Differential R counter.
This allows for higher OSCin frequencies,
but restricts PLL_R to divides of 2, 4, 8 or
16.
Value
R Divider
Single-Ended
Differential
Pulse Width
Reserved
860 ps
0
PLL_R _DIFF
1
Value
Sets the charge pump minimum pulse
width. This could potentially be a trade-off
between fractional spurs and phase noise.
Setting 1 is recommended for general use.
0
PFD_DLY
[1:0]
R27[4:3]
R28[4:0]
1
0
1
2
1200 ps
3
1500 ps
Value
Charge Pump State
Tri-State
0
1
100 µA
CPG
[4:0]
Charge pump gain
2
200 µA
…
…
31
Value
0
3100 µA
Charge pump polarity is used to
accommodate VCO with either polarity so
that feedback of the PLL is always correct.
Charge Pump Polarity
Positive
SPACE
IF reference (R) output is faster than
feedback (N) output,
R28[5]==0 THEN charge pump will source
current
CPPOL
R28[5]
0
1
Negative
R28[5]==1 THEN charge pump will sink
current
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7.6.1.2.1 Speed Up Controls (Cycle Slip Reduction and Fastlock)
Table 12. FastLock and Cycle Slip Reduction
FIELD
LOCATION POR
DESCRIPTION AND STATES
Cycle Slip Reduction (CSR) reduces the
phase detector frequency by multiplying
both the R and N counters by the CSR
value while either the FastLock Timer is
counting or the RAMPx_FL = 1 and the
part is ramping. Care must be taken that
the R and N divides remain inside the
range of the counters. Cycle slip reduction
is generally not recommended during
ramping.
Value
CSR Value
0
1
2
Disabled
x 2
FL_ CSR
[1:0]
x 4
R27[6:5]
0
3
Reserved
Value
Fastlock Charge Pump Gain
0
1
Tri-State
100 µA
Charge pump gain only when Fast Lock
FL_ CPG
[4:0]
R29[4:0]
0
Timer is counting down or
running with RAMPx_FL = 1
a ramp is
2
200 µA
…
31
Value
0
…
3100 µA
Fast Lock Timer. This counter starts
counting when the user writes the
PLL_N(Register R16). During this time the
FL_CPG gain is sent to the charge pump,
Fastlock Timer Value
Disabled
1
1 x 32 = 32
R29[7:5]
and
R32[7:0]
FL_ TOC
[10:0]
0
and the FL_CSR shifts the R and N
...
counters if enabled. When the counter
terminates, the normal CPG is presented
and the CSR undo’s the shifts to give a
normal PFD frequency.
2047
2047 x 32 = 65504
20
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7.6.2 Lock Detect and Charge Pump Monitoring
Table 13. Lock Detect and Charge Pump Monitor
FIELD
LOCATION POR
DESCRIPTION AND STATES
Value
Threshold
Lowest
Charge pump voltage low threshold value.
0x0A When the charge pump voltage is below
0
…
CPM_THR _LOW
[5:0]
R30[5:0]
R30[6]
…
this threshold, the LD goes low.
63
Highest
Value
Flag Indication
This is a read only bit.
Charge pump is below
CPM_THR_LOW threshold
0
1
CPM_FLAGL
-
Low indicates the charge pump voltage is
below the minimum threshold.
Charge pump is above
CPM_THR_LOW threshold
Value
0
Threshold
Lowest
…
Charge pump voltage high threshold value.
0x32 When the charge pump voltage is above
this threshold, the LD goes low.
CPM_THR _HIGH
[5:0]
R31[5:0]
R31[6]
…
63
Highest
Threshold
Value
This is a read only bit.
Charge pump voltage high comparator
reading. High indicates the charge pump
voltage is above the maximum threshold.
Charge pump is below
CPM_THR_HIGH threshold
0
1
CPM_FLAGH
-
Charge pump is above
CPM_THR_HIGH threshold
Digital Lock Detect Filter amount. There must be at least DLD_PASS_CNT good edges
0xFF and less than DLD_ERR edges before the DLD is considered in lock. Making this number
smaller speeds the detection of lock, but also allows a higher chance of DLD chatter.
DLD_ PASS_CNT
[7:0]
R33[7:0]
R34[4:0]
Digital Lock Detect error count. This is the maximum number of errors greater than
DLD_ ERR_CNT
[4:0]
0
0
DLD_TOL that are allowed before DLD is de-asserted. Although the default is 0, the
recommended value is 4.
Value
Window and fPD Frequency
0
1 ns (fPD > 130 MHz)
Digital Lock detect edge window. If both N
and R edges are within this window, it is
considered a “good” edge. Edges that are
farther apart in time are considered “error”
edges. Window choice depends on phase
detector frequency, charge pump minimum
pulse width, fractional modulator order and
the users desired margin.
1.7 ns (80 MHz < fPD ≤ 130
1
MHz)
2
3
3 ns (60 MHz < fPD ≤ 80 MHz)
6 ns (45 MHz < fPD ≤ 60 MHz)
DLD _TOL
[2:0]
R34[7:5]
10 ns (30 MHz < fPD ≤ 45
4
MHz)
5
18 ns ( fPD ≤ 30 MHz)
6 and 7
Reserved
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7.6.3 TRIG1, TRIG2, MOD, and MUXout Pins
Table 14. TRIG1, TRIG2, MOD, and MUXout Terminal States
FIELD
LOCATION POR
DESCRIPTION AND STATES
Value
Pin Drive State
0
1
2
TRISTATE (default)
Open Drain Output
TRIG1 _PIN
[2:0]
R36[2:0]
0
Pullup / Pulldown Output
TRIG2 _PIN
[2:0]
R37[2:0]
R38[2:0]
0
0
3
Reserved
This is the terminal drive state for the
TRIG1, TRIG2, MOD, and MUXout Pins
MOD_ PIN
[2:0]
4
5
6
7
GND
Inverted Open Drain Output
MUXout_ PIN
[2:0]
Inverted Pullup / Pulldown
Output
R39[2:0]
0
Input
22
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Table 15. TRIG1, TRIG2, MOD, and MUXout Selections
FIELD
LOCATION POR
DESCRIPTION AND STATES
Value
MUX State
GND
0
1
2
3
Input TRIG1
Input TRIG2
Input MOD
Output TRIG1 after
synchronizer
4
5
6
Output TRIG2 after
synchronizer
Output MOD after
synchronizer
7
8
9
Output Read back
Output CMP0
Output CMP1
Output LD (DLD good AND
CPM good)
10
11
12
13
14
Output DLD
Output CPMON good
Output CPMON too High
Output CPMON too low
These fields control what signal is muxed
to or from the TRIG1, TRIG2, MOD, and
MUXout pins.
TRIG1_MUX
[5:0]
R36[7:3],
1
Output RAMP LIMIT
EXCEEDED
15
R35[3]
16
17
Output R Divide/2
Output R Divide/4
Output N Divide/2
Output N Divide/4
Reserved
TRIG2_MUX
[5:0]
R37[7:3],
2
Some of the abbreviations used are:
COMP0, COMP1: Comparators 0 and 1
LD, DLD: Lock Detect, Digital Lock Detect
CPM: Charge Pump Monitor
CPG: Charge Pump Gain
CPUP: Charge Pump Up Pulse
CPDN: Charge Pump Down Pulse
R35[4]
MOD_MUX
[5:0]
R38[7:3],
3
18
R35[7]
19
MUXout_MUX
[5:0]
R39[7:3],
7
20
R35[5]
21
Reserved
22
Output CMP0RAMP
Output CMP1RAMP
Reserved
23
24
25
Reserved
26
Reserved
27
Reserved
28
Output Faslock
Output CPG from RAMP
Output Flag0 from RAMP
Output Flag1 from RAMP
Output TRIGA
29
30
31
32
33
Output TRIGB
34
Output TRIGC
35
Output R Divide
Output CPUP
36
37
Output CPDN
38
Output RAMP_CNT Finished
Reserved
39 to 63
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7.6.4 Ramping Functions
Table 16. Ramping Functions
FIELD
LOCATION POR
DESCRIPTION AND STATES
Enables the RAMP functions. When this bit
is set, the Fractional Denominator is fixed
to 224. RAMP execution begins at RAMP0
upon the PLL_N[7:0] write. The Ramp
should be set up before RAMP_EN is set.
Value
Ramp
0
Disabled
RAMP_EN
R58[0]
0
1
Enabled
RAMP clock input source. The ramp can
be clocked by either the phase detector
clock or the MOD terminal based on this
selection.
Value
Source
0
Phase Detector
RAMP_CLK
R58[1]
R58[2]
0
0
1
MOD Terminal
Value
Modulation Type
RAMP_PM_EN
Phase modulation enable.
0
1
Frequency Modulation
Phase Modulation
Value
0
Source
Never Triggers (default)
TRIG1 terminal rising edge
TRIG2 terminal rising edge
MOD terminal rising edge
DLD Rising Edge
1
2
3
4
RAMP_TRIGA
[3:0]
5
CMP0 detected (level)
RAMPx_CPG Rising edge
RAMPx_FLAG0 Rising edge
Always Triggered (level)
TRIG1 terminal falling edge
TRIG2 terminal falling edge
MOD terminal falling edge
DLD Falling Edge
R58[7:4]
R59[3:0]
R59[7:4]
6
RAMP_TRIGB
[3:0]
0
Trigger A, B, and C Sources
7
8
RAMP_TRIGC
[3:0]
9
10
11
12
13
14
15
CMP1 detected (level)
RAMPx_CPG Falling edge
RAMPx_FLAG0 Falling edge
R70[0],
R63[7] to
R60[0]
RAMP_CMP0
[32:0]
Twos compliment of Ramp Comparator 0 value. Be aware of that the MSB is in Register
R70.
0
0
0
0
Comparator 0 is active during each RAMP corresponding to the bit. Place a 1 for ramps it
is active in and 0 for ramps it should be ignored. RAMP0 corresponds to R64[0], RAMP7
corresponds to R64[7]
RAMP_CMP0_EN
[7:0]
R64[7:0]
R70[1],
R68[7] to
R65[0]
RAMP_CMP1
[32:0]
Twos compliment of Ramp Comparator 1 value. Be aware of that the MSB is in Register
R70.
Comparator 1 is active during each RAMP corresponding to the bit. Place a 1 for ramps it
is active in and 0 for ramps it should be ignored. RAMP0 corresponds to R64[0], RAMP7
corresponds to R64[7].
RAMP_CMP1_EN
[7:0]
R69[7:0]
Value
Trigger
Always Triggered
Trigger A
0
1
2
3
Deviation trigger source. When this trigger
source specified is active, the FSK_DEV
value is applied.
FSK_TRIG
[1:0]
R76[4] to
R75[3]
0
0
Trigger B
Trigger C
R70[2],
R74[7] to
R71[0]
Twos compliment of the deviation value for frequency modulation and phase modulation.
This value should be written with 0 when not used. Be aware that the MSB is in Register
R70.
FSK_DEV
[32:0]
24
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Table 16. Ramping Functions (continued)
FIELD
LOCATION POR
DESCRIPTION AND STATES
Twos compliment of the ramp lower limit that the ramp can not go below . The ramp limit
occurs before any deviation values are included. Care must be taken if the deviation is
used and the ramp limit must be set appropriately. Be aware that the MSB is in Register
R70.
R70[3],
R78[7] to
R75[0]
RAMP_LIMIT_LOW
[32:0]
0
Twos compliment of the ramp higher limit that the ramp can not go above. The ramp limit
occurs before any deviation values are included. Care must be taken if the deviation is
used and the ramp limit must be set appropriately. Be aware that the MSB is in Register
R70.
R70[4],
R82[7] to
R79[0]
0x1FF
FFFF
FF
RAMP_LIMIT_HIGH
[32:0]
Number of RAMPs that is executed before a trigger or ramp enable is brought down. Load
zero if this feature is not used. Counter is automatically reset when RAMP_EN goes from
0 to 1.
RAMP_COUNT
[12:0]
R84[4] to
R83[0]
0
Value
Ramp
RAMP_EN unaffected by ramp
counter (default)
0
Automatically clear RAMP_EN when
RAMP Count hits terminal count.
RAMP_AUTO
R84[5]
0
RAMP_EN automatically
brought low when ramp
counter terminal counts
1
Value
Source
Increments occur on each
ramp transition
0
Increment Trigger source for RAMP
Counter. To disable ramp counter, load a
count value of 0.
RAMP_TRIG_INC
[1:0]
R84[7:6]
0
1
2
3
Increment occurs on Trigger A
Increment occurs on Trigger B
Increment occurs on Trigger C
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7.6.5 Individual Ramp Controls
These bits apply for all eight ramp segments. For the field names, x can be 0, 1, 2, 3, 4, 5, 6, or 7.
Table 17. Individual Ramp Controls
LOCATI
ON
FIELD
POR
DESCRIPTION AND STATES
RAMPx
_INC[29:0]
Varies
0
Signed ramp increment.
Value
CPG
RAMPx _FL
Varies
0
This enables fastlock and cycle slip reduction for ramp x.
0
1
Disabled
Enabled
Clocks
Value
During this ramp, each increment takes 2 fPD cycles per
LEN clock instead of the normal 1 fPD cycle. Slows the
ramp by a factor of 2.
RAMPx
_DLY
1 fPD clock per RAMP
tick.(default)
Varies
Varies
0
0
0
1
2 fPD clocks per RAMP tick.
RAMPx
_LEN
Number of fPD clocks (if DLY is 0) to continue to increment RAMP. 1 = 1 cycle, 2 = 2 cycles, etc.
Maximum of 65536 cycles.
Value
Flag
Both FLAG1 and FLAG0
are zero. (default)
0
FLAG0 is set, FLAG1 is
clear
RAMPx
_FLAG[1:0]
General purpose FLAGs sent out of RAMP at the start of a
ramp pattern.
1
2
3
Varies
Varies
0
0
FLAG0 is clear, FLAG1 is
set
Both FLAG0 and FLAG1
are set.
Value
Reset
Disabled
Forces a clear of the ramp accumulator at the start of a
ramp pattern. This is used to erase any accumulator creep
that can occur depending on how the ramps are defined.
RAMPx
_RST
0
1
Enabled
Value
Operation
RAMPx_LEN
Trigger A
Trigger B
Trigger C
RAMPx_
NEXT
_TRIG
[1:0]
Determines what event is necessary to cause the state
machine to go to the next ramp. It can be set to when the
RAMPx_LEN counter reaches zero or one of the events for
Triggers A, B, or C.
0
1
2
3
Varies
Varies
0
0
RAMPx
_NEXT[2:0]
The next RAMP to execute when the length counter times out
26
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8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMX2491 can be used in a broad class of applications such as generating a single frequency for a high
frequency clock, generating a tunable range of frequencies, or generating swept waveforms that can be used in
applications such as radar.
8.2 Typical Application
Figure 14 is an example that could be used in a typical application.
3.3 or 5 V
R3_LF
100 nF
C2_LF
C1_LF
3.3 V
C3_LF
R2_LF
100 nF
24
23
22
21
20
19
3.3 V
Vcc
GND
18
17
16
15
14
13
1
2
3
4
5
6
100 nF
GND
GND
MUXOUT
18 Ω
LE
10 pF
18 Ω
36 Ω
DATA
Fin
To Circuit
Fin*
CLK
CE
68 Ω
3.3 V
10 pF
Vcc
51 Ω
100 nF
7
8
9
10
11
12
3.3 V
3.3 V
18 Ω
100 nF
100 nF
68 Ω
18 Ω
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Typical Schematic
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Typical Application (continued)
8.2.1 Design Requirements
For these examples, it will be assumed that there is a 100 MHz input signal and the output frequency is between
1500 and 1520 MHz with various modulated waveforms.
Table 18. Design Requirements
PARAMETER
SYMBOL
VALUE
COMMENTS
Input frequency
fOSCin
100 MHz
Phase detector
frequency
fPD
50 MHz
There are many possibilities, but this choice gives good performance.
In the different examples, the VCO frequency is actually changing. However,
VCO frequency
VCO gain
fVCO
1500 - 1520 MHz the same loop filter design can be used for all examples. Unmodulated VCO
frequency or steady state VCO frequency without ramp is 1500 MHz.
This parameter has nothing to do with the LMX2491, but is rather set by the
KVCO
65 MHz/V
external VCO choice.
8.2.2 Detailed Design Procedure
The first step is to calculate the reference divider (PLL_R) and feedback divider (PLL_N) values as shown in the
table that follows.
Table 19. Detailed Design Procedure
PARAMETE
SYMBOL AND CALCULATIONS
VALUE
COMMENTS
R
To design a loop filter, one designs for a fixed VCO value,
although it is understood that the VCO will tune around. This
typical value is usually chosen as the average VCO
frequency
Average VCO
frequency
fVCOavg = (fVCOmax + fVCOmin) / 2
1510 MHz
This parameter has nothing to do with LMX2491, but is
rather set by the external VCO choice. In this case, it was
the CVCO55BE-1400-1624 VCO.
VCO gain
KVCO
65 MHz/V
VCO input
capacitance
This parameter has nothing to do with LMX2491, but is
rather set by the external VCO choice.
CVCO
LBW
CPG
120 pF
380 kHz
3.1 mA
PLL loop
bandwidth
This bandwidth is very wide to allow the VCO frequency to
be modulated.
Charge pump
gain
Using the larger gain allows a wider loop bandwidth and
gives good phase performance.
R-divider
N-divider
PLL_R = fOSCin / fPD
PLL_N = fVCO / fPD
C1_LF
2
96
68 pF
3.9 nF
150 pF
390 Ω
150 Ω
C2_LF
Loop filter
components
C3_LF
These were calculated by TI PLLatinum Simulator Tool.
R2_LF
R3_LF
Once a loop filter bandwidth is chosen, the external loop filter component values can be calculated with a tool
such as PLLatinum Simulator Tool. It is also highly recommended to look at the EVM User's Guide. TICS Pro
software is an excellent starting point and example to see how to program this device.
8.2.3 TICS Pro Basic Setup
In the following application examples, TICS Pro is used to program the device to implement different ramp
profiles. The following procedure shows how to setup TICS Pro to put the device to lock to 1500 MHz without
modulation or ramp.
28
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Figure 15. TICS Pro
1. In the Menu bar, click Select Device and then select LMX2491.
2. In the Menu bar, click Default Configuration and then select Default Mode.
3. In the Page window, click PLL.
4. In the Main window, change R Divider value to 2 and VCO value to 1500.
5. In the Menu bar, click USB Communications and then click Write All Registers. The device is now locked to
1500 MHz.
Other TICS Pro fundamentals:
•
When a particular content in the Main window is moused-over, the Context window will show a brief
description of that content.
•
•
An alternative method to write all registers is press the Ctrl key and L key from the keyboard.
Whenever a value is updated in the Main window, the Message window will show which register is being
updated
8.2.4 Frequency Shift Keying Example
FSK operation requires an external input trigger signal at either MOD, TRIG1 or TRIG2 pin. In this example,
MOD pin is selected as the Trigger A source. A 20 kHz square-wave clock will be applied to MOD pin to toggle
the RF output to switch between 1500 MHz and 1502 MHz. That is, FSK frequency deviation is 2 MHz. The
following register bits are required to set in order to initiate FSK operation.
Table 20. FSK Register Settings
PARAMETER
REGISTER BIT
FSK_DEV
SETTING
COMMENTS
Frequency deviation = (fPD x FSK_DEV) / 224
Frequency deviation
671089 = 2 MHz
MOD pin
characteristic
MOD_PIN
7 = Input
Set MOD pin as an input pin
Use Trigger A to trigger FSK
FSK trigger source
FSK_DEV_TRIG
RAMP_TRIGA
RAMP_EN
1 = Trigger A
3 = MOD Rising Edge
1 = Enabled
Trigger source
definition
When there is a L-to-H transition at MOD pin, the set amount of
frequency deviation will be added to the unmodulated carrier
Enable ramp
Activate FSK operation
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Figure 16. TICS Pro FSK Configuration
Figure 17. Frequency Shift Keying Example
8.2.5 Single Sawtooth Ramp Example
In this example, Trigger B is used to trigger the ramp generator of LMX2491 to general a single frequency ramp
between 1500 MHz and 1520 MHz. Ramp duration is 50 µs. The ramp will finish and return back to 1500 MHz
immediately when the output frequency reaches 1520 MHz. Trigger 1 pin is assigned as Trigger B source.
Two ramp segments are setup to create this one-time single ramp. RAMP0 is used to establish a trigger for the
second ramp segment - RAMP1. When a trigger signal is received, RAMP1 will execute and bring the output
frequency to 1520 MHz in 50 µs.
30
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Table 21. Single Sawtooth Ramp Register Settings
PARAMETER
REGISTER BIT
SETTING
COMMENTS
This threshold frequency can be anything above 1520 MHz.
The fractional numerator is equal to 0 at 1550 MHz. The N-Divider
difference between 1500 MHz and 1550 MHz is 1. From Equation 1,
this threshold is equal to 0 + (1 x 224) = 16777216.
Set maximum ramp
frequency threshold
16777216 = 1550
MHz
RAMP_LIMIT_HIGH
This threshold frequency can be anything below 1500 MHz.
This threshold is equal to –16777216. This is a 33-bit long register,
2's complement is therefore equal to 8573157376.
Set minimum ramp
frequency threshold
8573157376 = 1450
MHz
RAMP_LIMIT_LOW
The duration of RAMP0 is not matter, for demonstration
convenience, it has the same ramp duration as RAMP1.
During ramp, LMX2491 ramp generator will increment its output
Number of ramp in
each ramp segment
RAMP0_LEN,
RAMP1_LEN
2500 = for ramp
duration equals 50 µs frequency once per phase detector cycle. For ramp duration of 50
µs and fPD = 50 MHz, there are 2500 ramps [= 50 µs / (1 / 50
MHz)].
Frequency change
per ramp in RAMP0
Since the output frequency would not change in RAMP0, there is no
frequency increment.
RAMP0_INC
0
Set next ramp
segment
RAMP0_NEXT
1 = RAMP1
Set RAMP1 as the next ramp segment following RAMP0.
Use Trigger B to trigger the execution of RAMP1.
Set next ramp
segment trigger
source
RAMP0_NEXT_TRIG 2 = Trigger B
RAMP0 will execute again after RAMP1 is finished but RAMP1 does
not end at 1500 MHz, a reset to the fractional numerator is required
before RAMP0 is executed.
Rest fractional
numerator
RAMP0_RST
1 = Reset
Between 1500 MHz and 1520 MHz, there are 2500 ramps. For each
ramp, the output frequency will increment by 20 MHz / 2500 = 8
kHz. For fPD = 50 MHz and fractional denominator = 224, fractional
numerator is incremented by a value of (8 kHz x 224) / 50 MHz ≈
2684.
Frequency change
per ramp in RAMP1
RAMP1_INC
2684 = 8 kHz
0 = RAMP0
Set next ramp
segment
RAMP1_NEXT
Set RAMP0 as the next ramp segment following RAMP1.
Set next ramp
segment trigger
source
After RAMP1 is finished, the next ramp segment will execute
immediately.
RAMP1_NEXT_TRIG 0 = TOC Timeout
Trigger source
definition
1 = TRIG1 Rising
RAMP_TRIGB
Edge
When there is a L-to-H transition at TRIG1 pin, RAMP1 will execute.
Set TRIG1 pin as an input pin.
TRIG1 pin
characteristic
TRIG1_PIN
7 = Input
Copyright © 2016–2017, Texas Instruments Incorporated
31
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
It is recommended to use the Ramp Calculator in TICS Pro to create the ramp profile. TICS Pro will calculate the
ramp-related register values automatically.
Figure 18. TICS Pro Ramp Calculator
Figure 19. Single Sawtooth Ramp Example
8.2.6 Continuous Sawtooth Ramp Example
This example shows how to generate a continuous sawtooth ramp. Only one ramp segment is necessary as it
will loop back to itself.
32
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
Figure 20. Continuous Sawtooth Ramp Configuration
Figure 21. Continuous Sawtooth Ramp Example
8.2.7 Continuous Sawtooth Ramp with FSK Example
A ramp and FSK can coexist at the same time. Since the amount of FSK is added to the instantaneous carrier,
the FSK will appear at the envelope of the ramp. Furthermore, a ramp and FSK are two independent operations,
their register settings can be combined in a single configuration setting. That is, when RAMP_EN is enabled,
both frequency ramp and FSK will be activated together.
Copyright © 2016–2017, Texas Instruments Incorporated
33
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
Figure 22. Continuous Sawtooth Ramp with FSK Configuration
Figure 23. Continuous Sawtooth Ramp with FSK Example
8.2.8 Continuous Triangular Ramp Example
Two ramp segments are used to create this ramp pattern. RAMP0 ramps from 1500 MHz to 1520 MHz. RAMP1
brings the frequency back to 1500 MHz and then RAMP0 starts over again. Since RAMP1 already brought the
frequency back to 1500 MHz, which is also the start frequency of RAMP0, a reset to fractional numerator is not
required.
34
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
Figure 24. Continuous Triangular Ramp Configuration
Ramp comparators are enabled so as to output flag signals when the threshold frequencies are hit. MOD pin is
assigned for CMP0 while TRIG1 pin is assigned for CMP1. RAMP_CMP0_EN is equal to 3 because ramp
segment 0 and 1 are monitored.
Figure 25. Ramp Comparators Configuration
Copyright © 2016–2017, Texas Instruments Incorporated
35
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
Figure 26. Continuous Triangular Ramp Example
Figure 27. Ramp Comparators Output Flags
8.2.9 Continuous Trapezoid Ramp Example
This is a long-ramp example, the ramp duration is 2 ms. Since fPD = 50 MHz, 100000 ramps are required for
each ramp segment. However, LMX2491 supports up to a maximum ramp length (RAMPx_LEN) of 65536 only.
There are two solutions to resolve this problem:
1. Reduce phase detector frequency. For example, reduce fPD to 25 MHz, then the required RAMPx_LEN
becomes 50000.
2. Enable RAMPx_DLY. When this register bit is set, the ramp generator will ramp every 2 phase detector
cycles instead of the normal 1 fPD cycle. In this example, this bit is set and as a result, RAMPx_LEN is
50000.
Four ramp segments are used to construct the ramp pattern. Again there is no need to reset the fractional
numerator because the last ramp end frequency is equal to the first ramp start frequency.
36
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
Figure 28. Continuous Trapezoid Ramp Configuration
Figure 29. Continuous Trapezoid Ramp Example
8.2.10 Arbitrary Waveform Ramp Example
An arbitrary ramp waveform can be easily constructed with the 8 ramp segments provided in LMX2491.
LMX2491 also provides flag signals output to indicate the start of a ramp. This example used the MOD pin to
initiate the ramp and used TRIG1 and TRIG2 as the output flags to indicate the status of the ramp.
Copyright © 2016–2017, Texas Instruments Incorporated
37
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
Figure 30. Arbitrary Waveform Ramp Configuration
Figure 31. Arbitrary Waveform Ramp Example
38
Copyright © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
Figure 32. Arbitrary Waveform Ramp Timing
9 Power Supply Recommendations
For power supplies, TI recommends placing 100 nF close to each of the power supply pins. If fractional spurs are
a large concern, using a ferrite bead to each of these power supply pins can reduce spurs to a small degree.
10 Layout
10.1 Layout Guidelines
For layout examples, the EVM instructions are the most comprehensive document. In general, the layout
guidelines are similar to most other PLL devices. For the high frequency Fin pin, it is recommended to use 0402
components and match the trace width to these pad sizes. Also the same needs to be done on the Fin* pin. If
layout is easier to route the signal to Fin* instead of Fin, then this is acceptable as well.
Copyright © 2016–2017, Texas Instruments Incorporated
39
LMX2491
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
www.ti.com.cn
10.2 Layout Example
Figure 33. Layout Recommendation
40
版权 © 2016–2017, Texas Instruments Incorporated
LMX2491
www.ti.com.cn
ZHCSFL5A –OCTOBER 2016–REVISED JANUARY 2017
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
德州仪器 (TI) 提供多款开发辅助软件工具，包括 TICS Pro 编程辅助工具、PLLatinum Simulator Tool 回路滤波器
设计辅助工具以及相位噪声/毛刺仿真辅助工具。所有这些工具均可从以下网址获得：www.ti.com。
11.2 文档支持
11.2.1 相关文档
相关文档如下：
•
•
《AN-1879 分数 N 频率合成》（文献编号：SNAA062）
《PLL 性能仿真和设计》
11.3 接收文档更新通知
要接收文档更新通知，请导航至德州仪器 TI.com.cn 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可
收到任意产品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航栏。
版权 © 2016–2017, Texas Instruments Incorporated
41
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMX2491RTWR
LMX2491RTWT
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
X2491
X2491
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMX2491RTWR
LMX2491RTWT
WQFN
WQFN
RTW
RTW
24
24
1000
250
178.0
178.0
12.4
12.4
4.3
4.3
4.3
4.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMX2491RTWR
LMX2491RTWT
WQFN
WQFN
RTW
RTW
24
24
1000
250
208.0
208.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RTW0024A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.1) TYP
EXPOSED
THERMAL PAD
7
12
20X 0.5
6
13
2X
25
2.5
2.6 0.1
1
18
0.3
24X
0.2
24
19
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
24X
4222815/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(1.05)
SYMM
25
(3.8)
20X (0.5)
(R0.05)
TYP
6
13
(
0.2) TYP
VIA
7
12
(1.05)
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222815/A 03/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
(0.675) TYP
19
(R0.05) TYP
24
24X (0.6)
1
18
24X (0.25)
(0.675)
TYP
SYMM
20X (0.5)
25
(3.8)
6
13
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222815/A 03/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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