LMX2492QRTWTQ1_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

LMX2492/LMX2492-Q1 14GHz 低噪声分数 N 分频锁相环 (PLL)，具有斜

坡/超宽带信号源发生功能

1 特性

3 说明

1

•

-227dBc/Hz 标称 PLL 噪声

LMX2492/92-Q1 是一款具有斜坡和超宽带信号源发生

功能的 14GHz 宽频带三角积分分数 N 分频 PLL。它

由一个相位频率检测器、可编程电荷泵以及用于外部

VCO 的高频输入组成。 LMX2492/92-Q1 支持宽范围

且灵活的斜升功能类 (class of ramping capabilities)，

其中包括 FSK，PSK 和高达 8 个段的可配置分段线性

FM 调制系统配置。它还支持精细的 PLL 分辨率以及

相位检测器速率高达 200MHz 的快速斜坡。

500MHz - 14GHz 宽频带 PLL

3.15 -5.25V 电荷泵 PLL 电源

多用途斜坡/超宽带信号源发生

最大相位检测器频率 200MHz

频移键控/相移键控 (FSK/PSK) 调制引脚

数字锁检测

单个 3.3V 电源

LMX2492/92-Q1 的任何一个寄存器均可被回读。

LMX2492/92-Q1 可由单个 3.3V 电源供电运行。而

且，对于电压高达 5.25V 的电荷泵的支持能够免除对

于外部放大器的需要，从而获得一个具有更佳相位噪声

性能的更简单解决方案。

汽车用 125°C Q100 1 级认证

非汽车用 (LMX2492) 选项

2

应用范围

•

汽车用调频连续波 (FMCW) 雷达

军用雷达

器件信息

微波回程

订货编号

封装

封装尺寸

测试和测量

LMX2492-Q1RTW

超薄四方扁平无

引线 (WQFN)

(24)

卫星通信

4mm x 4mm

LMX2492RTW

无线基础设施

针对高速模数转换器 (ADC) / 数模转换器 (DAC) 的

采样时钟

4 简化电路原理图

OSCin

2X

R Divider

(16 bit)

CPout

Phase

Comp

Charge

Pump

51 :

GND/OSCin*

C2_LF

R2_LF

51 :

C1_LF

Vcp

GND (x3)

18 :

Vcc (x5)

Fin

CE

CLK

MICROWIRE

Interface

36 :

18 :

DATA

To Circuit

N Divider

(18 bit)

LE

Fin*

68 :

TRIG1

TRIG2

51 :

6'

Modulation

Generator

Compensation

(24 bit)

MUX

MOD

MUXout

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNAS624

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.6 Register Map........................................................... 14

8.7 Register Field Descriptions ..................................... 18

8.8 Lock Detect and Charge Pump Monitoring............. 21

8.9 TRIG1,TRIG2,MOD, and MUXout Pins .................. 22

8.10 Ramping Functions ............................................... 24

8.11 Individual Ramp Controls...................................... 26

Applications and Implementation ...................... 27

9.1 Application Information............................................ 27

9.2 Typical Applications ................................................ 27

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Terminal Configuration and Functions................ 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings................................... 4

7.2 Handling Ratings ...................................................... 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information ................................................. 4

7.5 Electrical Characteristics .......................................... 5

9

10 Power Supply Recommendations ..................... 33

11 Layout................................................................... 34

11.1 Layout Guidelines ................................................. 34

11.2 Layout Example .................................................... 34

12 Device and Documentation Support ................. 35

12.1 Device Support .................................................... 35

12.2 Documentation Support ....................................... 35

12.3 Related Links ........................................................ 35

12.4 Trademarks........................................................... 35

12.5 Electrostatic Discharge Caution............................ 35

12.6 Glossary................................................................ 35

13 机械封装和可订购信息 .......................................... 35

7.6 Timing Requirements, Programming Interface (CLK,

DATA, LE).................................................................. 6

7.7 Serial Data Input Timing ........................................... 6

7.8 Typical Characteristics ............................................. 7

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ......................................... 9

8.3 Feature Description................................................... 9

8.4 Device Functional Modes........................................ 13

8.5 Programming........................................................... 14

8

5 修订历史记录

日期

修订版本

注释

2014 年 3 月

*

最初发布版本。

2

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

6 Terminal Configuration and Functions

WQFN (RTW)

24 Terminal

(Top View)

24 23 22 21 20 19

GND

18 Vcc

1

2

3

4

5

6

17 MUXout

LE

16

15

Pin 0

(Ground Substrate)

Fin

Fin*

Vcc

DATA

14 CLK

CE

13

7

8

9

10 11 12

Terminal Functions

TERMINAL

TYPE

DESCRIPTION

NUMBER

NAME

DAP

0

1

GND

Die Attach Pad. Connect to PCB ground plane.

Ground for charge pump.

GND

2,3

Ground for Fin Buffer

Complimentary high frequency input pins. Should be AC coupled. If driving single-ended,

impedance as seen from Fin and Fin* pins looking outwards from the part should be roughly the

same.

Fin

Fin*

4,5

Input

6

7

8

9

Vcc

Supply

Input

Power Supply for Fin Buffer

Supply for On-chip LDOs

Supply for OSCin Buffer

Vcc

OSCin

Reference Frequency Input

Complimentary input for OSCin.

GND/

OSCin*

10

GND/Input If not used, it is recommended to match the termination as seen from the OSCin terminal looking

outwards. However, this may also be grounded as well.

11

12

13

14

15

16

17

18

19

20

21

22

23

24

GND

MOD

CE

GND

Ground for OSCin Buffer

Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics

Input

GND

Input

Chip Enable

CLK

DATA

LE

Serial Programming Clock.

Serial Programming Data

Serial Programming Latch Enable

MUXout Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics

Vcc

Supply

Supply for delta sigma engine.

Supply for general circuitry.

TRIG1

TRIG2

Vcp

Input/Output Multiplexed Input/Output Pins for Ramp Triggers, FSK/PSK Modulation, FastLock, and Diagnostics

Supply

NC

Power Supply for the charge pump.

No connect.

Rset

CPout

Output

Charge Pump Output

3

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

Vcc

-0.3

MAX

5.5

UNIT

V

Vcp

Supply Voltage for Charge Pump

Charge Pump Output Pin

All Vcc Pins

CPout

Vcc

Vcp

V

3.6

V

Others

T_Solder

T_Junction

All Other I/O Pins

Vcc + 0.3

260

V

Lead Temperature (solder 4 seconds)

Junction Temperature

°C

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN

MAX

150

3

UNIT

°C

T_STG

MSL

Storage Temperature Range

-65

Moisture Sensitivity Level

n/a

V

Human body model (HBM) ESD stress voltage⁽²⁾

Charged device model (CDM) ESD stress voltage⁽³⁾

2500

1500

(1)

V_ESD

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows

safe manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe

manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SYMBOL

Vcc

PARAMETER

PLL Supply Voltage

DEVICE

MIN

3.15

Vcc

-40

TYP

MAX

3.45

5.25

85

UNIT

V

3.3

Vcp

Charge Pump Supply Voltage

V

LMX2492

LMX2492-Q1

LMX2492

T_A

T_J

Ambient Temperature

°C

-40

125

135

-40

Junction Temperature

LMX2492-Q1

-40

7.4 Thermal Information

THERMAL METRIC⁽¹⁾

Temperature

UNIT

R_θJA

R_θJC

ψ_JB

Junction-to-ambient thermal resistance

Junction-to-case thermal resistance

Junction-to-board characterization parameter

39.4

7.1

20

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

4

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

7.5 Electrical Characteristics

(3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C.

-40°C ≤ T_A≤ 85 °C for the LMX2492 and -40°C ≤ T_A≤ 125 °C for the LMX2492-Q1 ; except as specified.)

SYMBOL

PARAMETER

Current Consumption

Current

CONDITIONS

Fpd = 10 MHz

MIN

TYP

45

50

55

2

MAX

UNIT

All Vcc Pins

Fpd = 100 MHz

Fpd = 200 MHz

Kpd = 0.1 mA

Kpd = 1.6 mA

Kpd = 3.1 mA

Icc

mA

Vcp Pin

10

19

3

IccPD

f_OSCin

POWERDOWN

OSC_DIFFR=0, Doubler Disabled

OSC_DIFFR=0, Doubler Enabled

OSC_DIFFR=1, Doubler Disabled

OSC_DIFFR=1, Doubler Enabled

10

600

300

Frequency for OSCin

terminal

MHz

10

1200

600

10

v_OSCin

f_Fin

Voltage for OSCin Pin⁽¹⁾

Frequency for FinPin⁽²⁾

Power for Fin Pin

0.5

500

-5

Vcc-0.5

14000

5

Vpp

MHz

p_Fin

Single-Ended Operation

dBm

f_PD

Phase Detector Frequency

PLL Figure of Merit⁽³⁾

200

MHz

PN1Hz

-227

-120

dBc/Hz

Normalized PLL 1/f

Noise⁽³⁾

Normalized to 10 kHz offset for a 1 GHz

carrier.

PN10kHz

dBc/Hz

nA

Charge Pump Leakage Tri-

state Leakage

Charge Pump Mismatch⁽⁴⁾V_CPout= Vcp / 2

I_CPoutTRI

I_CPoutMM

10

5 %

0.1

CPG=1X

…

I_CPout

Charge Pump Current

V_CPout= Vcp / 2

mA

CPG=31X

3.1

(1) For optimal phase noise performance, higher input voltage and a slew rate of at least 3 V/ns is recommended

(2) Tested to 13.5 GHz, Guaranteed to 14 GHz by characterization

(3) PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model

the PLL noise for an infinite loop bandwidth as:

PLL_Total = 10×log( 10^PLL_Flat/10+ 10^{PLL_Flicker(Offset)/10}

PLL_Flat = PN1Hz + 20×log(N) + 10×log(Fpd/1Hz)

)

PLL_Flicker = PN10kHz - 10×log(Offset/10kHz) + 20×log(Fvco/1GHz)

(4) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation.

5

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

Electrical Characteristics (continued)

(3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C.

-40°C ≤ T_A≤ 85 °C for the LMX2492 and -40°C ≤ T_A≤ 125 °C for the LMX2492-Q1 ; except as specified.)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC OUTPUT TERMINALS (MUXout,TRIG1,TRIG2,MOD)

0.8 x

Vcc

V_OH

V_OL

Output High Voltage

Output Low Voltage

Vcc

0

V

0.2 x Vcc

LOGIC INPUT TERMINALS (CE,CLK,DATA,LE,MUXout,TRIG1,TRIG2,MOD)

V_IH

Input High Voltage

Input Low Voltage

Input Leakage

1.4

0

Vcc

0.6

5

V

V_IL

I_IH

-5

5

1

uA

us

T_CELOW

T_CEHIGH

Chip enable Low Time

Chip enable High Time

5

7.6 Timing Requirements, Programming Interface (CLK, DATA, LE)

SYMBOL

PARAMETER

MIN

35

10

25

10

TYP

MAX

UNIT

ns

T_CE

Clock To LE Low Time

T_CS

Data to Clock Setup Time

Data to Clock Hold Time

Clock Pulse Width High

Clock Pulse Width Low

Enable to Clock Setup Time

Enable Pulse Width High

ns

T_CH

ns

T_CWH

T_CWL

T_CES

T_EWH

ns

7.7 Serial Data Input Timing

MSB

LSB

D0

DATA

CLK

LE

R/W

A15

t

CWH

CS

t

CE

t

CH

CES

t

CWL

t

EWH

There are several other considerations for programming:

•

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE

signal, the data is sent from the shift register to an actual counter.

•

If no LE signal is given after the last data bit and the clock is kept toggling, then these bits will be read into

the next lower register. This eliminates the need to send the address each time.

•

A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals

Timing specs also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD

terminals.

6

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

7.8 Typical Characteristics

5

4

5

4

3

2

1

0

±1

±2

±3

±4

±5

±1

±2

±3

±4

±5

Kpd = 8x

Kpd = 16x

Kpd = 31x

Kpd = 8x

Kpd = 16x

Kpd = 31x

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Charge Pump Voltage (V)

C001

C002

For a charge pump supply of 3.3 V, optimal performance is for a

typical charge pump output voltage between 0.5 and 2.8 volts.

Figure 1. Charge Pump Current for Vcp = 3.3 V

For a charge pump supply voltage of 5 volts or higher, optimal

performance is typically for a charge pump output voltage between

0.5 and 4.5 volts.

Figure 2. Charge Pump Current for Vcp = 5.5 V

0

±5

±10

±15

±20

±25

±30

±35

±40

0

2

4

6

8

10

12

14

16

Frequency (GHz)

C001

Typical value of lowest power level as a function of frequency. Design to electrical specifications for input sensitivity, not typical performance

graphs.

Figure 3. Fin Input Sensitivity

7

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

Typical Characteristics (continued)

±90

Theoretical 1/f

Theoretical Flat

Theoretical Model

Measurement

±95

±100

±105

±110

±115

±120

1k

10k

100k

1M

Offset (Hz)

C001

This plot is for a phase detector of 100 MHz, 2 MHz loop bandwidth, and VCO at 9600 MHz. However, the plot shown is the divide by 2 port

at 4800 MHz. The input was a 100 MHz Wenzel Oscillator. The model shows this phase noise has a figure of merit of -227 dBc/Hz and a

normalized 1/f noise of -120.5 dBc/Hz. The charge pump supply was 5 V and the charge pump output voltage was 1.34 V.

Figure 4. LMX2492/92-Q1 Phase Noise for Fpd =100 MHz, Fvco = 9600 MHz/2

8

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

8 Detailed Description

8.1 Overview

The LMX2492/92-Q1 is a microwave PLL, consisting of a reference input and divider, high frequency input and

divider, charge pump, ramp generator, and other digital logic. The Vcc power supply pins run at a nominal 3.3

volts, while the charge pump supply pin, Vcp, operates anywhere from Vcc to 5 volts. The device is designed to

operate with an external loop filter and VCO. Modulation is achieved by manipulating the MASH engine.

8.2 Functional Block Diagram

GND (x3)

Vcc (x5)

Vcp

2X

OSCin

R Divider

(16 bit)

Charge

Pump

Phase

Comp

CPout

GND/OSCin*

Lock

Detect

Fin

Fin*

CE

N Divider

(18 bit)

4/5

Prescaler

TRIG1

TRIG2

MOD

CLK

6'

Modulation

Generator

MUX

MICROWIRE

Interface

Compensation

(24 bit)

DATA

LE

MUXout

8.3 Feature Description

8.3.1 OSCin Input

The reference can be applied in several ways. If using a differential input, this should be terminated differentially

with a 100 ohm resistance and AC coupled to the OSCin and GND/OSCin* terminals. If driving this single-ended,

then the GND/OSCin* terminal may be grounded, although better performance is attained by connecting the

GND/OSCin* terminal through a series resistance and capacitance to ground to match the OSCin terminal

impedance.

8.3.2 OSCin Doubler

The OSCin doubler allows the input signal to the OSCin to be doubled in order to have higher phase detector

frequencies. This works by clocking on both the rising and falling edges of the input signal, so it therefore

requires a 50% input duty cycle.

8.3.3 R Divider

The R counter is 16 bits divides the OSCin signal from 1 to 65535. If DIFF_R = 0, then any value can be chosen

in this range. If DIFF_R=1, then the divide is restricted to 2,4,8, and 16, but allows for higher OSCin frequencies.

8.3.4 PLL N Divider

The 16 bit N divider divides the signal at the Fin terminal down to the phase detector frequency. It contains a 4/5

prescaler that creates minimum divide restrictions, but allows the N value to increment in values of one.

Minimum N

Modulator Order

Divide

Integer Mode, 1st

16

Order Modulator

2nd Order Modulator

3rd Order Modulator

4th Order Modulator

17

19

25

9

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.3.5 Fractional Circuitry

The fractional circuitry controls the N divider with delta sigma modulation that supports a programmable first,

second, third, and fourth order modulator. The fractional denominator is a fully programmable 24-bit denominator

that can support any value from 1,2,..., 2²⁴, with the exception when the device is running one of the ramps, and

in this case it is a fixed size of 2²⁴.

8.3.6 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the R and N dividers and generates a correction voltage

corresponding to the phase error. This voltage is converted to a correction current by the charge pump. The

phase detector frequency, f_PD, can be calculated as follows: f_PD= f_OSCin× OSC_2X / R.

The charge pump supply voltage on this device, Vcp, can be either run at the Vcc voltage, or up to 5.25 volts in

order to get higher tuning voltages to present to the VCO.

8.3.7 External Loop Filter

The loop filter is external to the device and is application specific. Texas Instruments website has details on this

at www.ti.com.

8.3.8 Fastlock and Cycle Slip Reduction

The Fastlock™ and Cycle Slip Reduction features can be used to improved lock time. When the frequency is

changed, a timeout counter can be used to engage these features for a prescribed number of phase detector

cycles. During this time that the timeout counter is counting down, the device can be used to pull a terminal from

high impedance to ground switch in an extra resistor (R2pLF), change the charge pump current (FL_CPG), or

change the phase detector frequency. TRIG2 is recommended for switching the resistor with a setting of

TRIG2_MUX = Fastlock (2) and TRIG2_PIN = Inverted/Open Drain (5).

Charge

CPout

Pump

C2_LF

TRIG2

C1_LF

R2pLF

R2_LF

Fastlock

Control

Parameter

Normal Operation

Fastlock Operation

Charge Pump Gain

CPG

FL_CPG

Device Pin

(TRIG1, TRIG2, MOD, or MUXout)

High Impedance

Grounded

The resistor and the charge pump current are changed simultaneously so that the phase margin remains the

same while the loop bandwidth is by a factor of K as shown in the following table:

Parameter

Symbol

FL_CPG

K

Calculation

Typically use the highest value.

K=sqrt(FL_CPG/CPG)

R2 / (K-1)

Charge Pump Gain in Fastlock

Loop Bandwidth Multiplier

External Resistor

R2pLF

10

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

Cycle slip reduction is another method that can also be used to speed up lock time by reducing cycle slipping.

Cycle slipping typically occurs when the phase detector frequency exceeds about 100x the loop bandwidth of the

PLL. Cycle slip reduction works in a different way than fastlock. To use this, the phase detector frequency is

decreased while the charge pump current is simultaneously increased by the same factor. Although the loop

bandwidth is unchanged, the ratio of the phase detector frequency to the loop bandwidth is, and this is helpful for

cases when the phase detector frequency is high. Because cycle slip reduction changes the phase detector rate,

it also impacts other things that are based on the phase detector rate, such as the fastlock timeout-counter and

ramping controls.

8.3.9 Lock Detect and Charge Pump Voltage Monitor

The LMX2492/92-Q1 offers two methods to determine if the PLL is in lock, charge pump voltage monitoring and

digital lock detect. These features can be used individually or in conjunction to give a reliable indication of when

the PLL is in lock. The output of this detection can be routed to the TRIG1, TRIG2, MOD, or MUXout terminals.

8.3.9.1 Charge Pump Voltage Monitor

The charge pump voltage monitor allows the user to set low (CMP_THR_LOW) and high (CMP_THR_HIGH)

thresholds for a comparator that monitors the charge pump output voltage.

Vcp

Threshold

Suggested Level

CPM_THR_LOW

= (Vthresh + 0.08) / 0.085

6 for 0.5V limit

3.3 V

CPM_THR_HIGH

42 for 2.8V limit

4 for 0.5V limit

46 for 4.5V limit

= (Vthresh - 0.96) / 0.044

CPM_THR_LOW

= (Vthresh + 0.056) / 0.137

5.0 V

CPM_THR_HIGH

= (Vthresh -1.23) / 0.071

8.3.9.2 Digital Lock Detect

Digital lock detect works by comparing the phase error as presented to the phase detector. If the phase error

plus the delay as specified by the PFD_DLY bit is outside the tolerance as specified by DLD_TOL, then this

comparison would be considered to be an error, otherwise passing. The DLD_ERR_CNT specifies how may

errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT specifies

how many passing comparisons are necessary to cause the PLL to be considered to be locked and also resets

the count for the errors. The DLD_TOL value should be set to no more than half of a phase detector period plus

the PFD_DLY value. The DLD_ERR_CNT and DLD_PASS_CNT values can be decreased to make the circuit

more sensitive. If the circuit is too sensitive, then chattering can occur and the DLD_ERR_CNT,

DLD_PASS_CNT, or DLD_TOL values should be increased.

Note that if the OSCin signal goes away and there is no noise or self-oscillation at the OSCin pin, then it is

possible for the digital lock detect to indicate a locked state when the PLL really is not in lock. If this is a concern,

then digital lock detect can be combined with charge pump voltage monitor to detect this situation..

8.3.10 FSK/PSK Modulation

Two level FSK or PSK modulation can be created whenever a trigger event, as defined by the FSK_TRIG field is

detected. This trigger can be defined as a transition on a terminal (TRIG1, TRIG2, MOD, or MUXout) or done

purely in software. The RAMP_PM_EN bit defines the modulation to be either FSK or PSK and the FSK_DEV

register determines the amount of the deviation. Remember that the FSK_DEV[32:0] field is programmed as the

2's complement of the actual desired FSK_DEV value. This modulation can be added to the modulation created

from the ramping functions as well.

RAMP_PM_EN

Modulation Type

2 Level FSK

Deviation

0

1

Fpd × FSK_DEV / 2²⁴

360° × FSK_DEV / 2²⁴

2 Level PSK

11

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.3.11 Ramping Functions

The LMX2492/92-Q1 supports a broad and flexible class of FMCW modulation formed by up to 8 linear ramps.

When the ramping function is running, the denominator is fixed to a forced value of 2²⁴= 16777216. The

waveform always starts at RAMP0 when the LSB of the PLL_N (R16) is written to. After it is set up, it will start at

the initial frequency and have piecewise linear frequency modulation that deviates from this initial frequency as

specified by the modulation. Each of the eight ramps can be individually programmed. Various settings are as

follows

Ramp Characteristic

Programming Field Name

Description

The user programs the length of the ramp in phase detector cycles. If

RAMPx_DLY=1, then each count of RAMPx_LEN is actually two phase detector

cycles.

RAMPx_LEN

RAMPx_DLY

Ramp Length

The user does not directly program slope of the line, but rather this is done by

defining how long the ramp is and how much the fractional numerator is

increased per phase detector cycle. The value for RAMPx_INC is calculated by

taking the total expected increase in the frequency, expressed in terms of how

much the fractional numerator increases, and dividing it by RAMPx_LEN. The

value programmed into RAMPx_INC is actually the two's complement of the

desired mathematical value.

RAMPx_LEN

RAMPx_DLY

RAMPx_INC

Ramp Slope

The event that triggers the next ramp can be defined to be the ramp finishing or

can wait for a trigger as defined by TRIG A, TRIG B, or TRIG C.

Trigger for Next Ramp

Next Ramp

RAMPx_NEXT_TRIG

RAMPx_NEXT

This sets the ramp that follows. Waveforms are constructed by defining a chain

ramp segments. To make the waveform repeat, make RAMPx_NEXT point to

the first ramp in the pattern.

Ramp Fastlock

Ramp Flags

RAMPx_FL

This allows the ramp to use a different charge pump current or use Fastlock

This allows the ramp to set a flag that can be routed to external terminals to

trigger other devices.

RAMPx_FLAG

8.3.11.1 Ramp Count

If it is desired that the ramping waveform keep repeating, then all that is needed is to make the RAMPx_NEXT of

the final ramp equal to the first ramp. This will run until the RAMP_EN bit is set to zero. If this is not desired, then

one can use the RAMP_COUNT to specify how may times the specified pattern is to repeat.

8.3.11.2 Ramp Comparators and Ramp Limits

The ramp comparators and ramp limits use programable thresholds to allow the device to detect whenever the

modulated waveform frequency crosses a limit as set by the user. The difference between these is that

comparators set a flag to alert the user while a ramp limits prevent the frequency from going beyond the

prescribed threshold. In either case, these thresholds are expressed by programming the

Extended_Fractional_Numerator.

Extended_Fractional_Numerator

=

Fractional_Numerator

+

(N-N*)

×

2²⁴

In the above, N is the PLL feedback value without ramping and N* is the instantaneous value during ramping.

The actual value programmed is the 2's complement of Extended_Fractional_Numerator.

Type

Programming Bit

RAMP_LIMIT_LOW

RAMP_LIMIT_HIGH

Threshold

Lower Limit

Upper Limit

Ramp Limits

For the ramp comparators, if the ramp is increasing and exceeds the value as specified

by RAMP_CMPx, then the flag will go high, otherwise it is low. If the ramp is decreasing

and goes below the value as specified by RAMP_CMPx, then the flag will go high,

otherwise it will be low.

Ramp

Comparators

RAMP_CMP0

RAMP_CMP1

8.3.12 Power on Reset (POR)

The power on reset circuitry sets all the registers to a default state when the device is powered up. This same

reset can be done by programming SWRST=1. In the programming section, the power on reset state is given for

all the programmable fields.

12

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

8.4 Device Functional Modes

The two primary ways to use the LMX2492/92-Q1 are to run it to generate a set of frequencies

8.4.1 Continuous Frequency Generator

In this mode, the LMX2492/92-Q1 generates a single frequency that only changes when the N divider is

programmed to a new value. In this mode, the RAMP_EN bit is set to 0 and the ramping controls are not used.

The fractional denominator can be programmed to any value from 1 to 16777216. In this kind of application, the

PLL is tuned to different channels, but at each channel, the goal is to generate a stable fixed frequency.

8.4.1.1 Integer Mode Operation

In integer mode operation, the VCO frequency needs to be an integer multiple of the phase detector frequency.

This can be the case when the output frequency or frequencies are nicely related to the input frequency. As a

rule of thumb, if this an be done with a phase detector of as high as the lesser of 10 MHz or the OSCin

frequency, then this makes sense. To operate the device in integer mode, disable the fractional circuitry by

programming the fractional order (FRAC_ORDER) , dithering (FRAC_DITH), and numerator (FRAC_NUM) to

zero.

8.4.1.2 Fractional Mode Operation

In fractional mode, the output frequency does not need to be an integer multiple of the phase detector frequency.

This makes sense when the channel spacing is more narrow or the input and output frequencies are not nicely

related. There are several programmable controls for this such as the modulator order, fractional dithering,

fractional numerator, and fractional denominator. There are many trade-offs with choosing these, but here are

some guidelines

Parameter

Field Name

How to Choose

The first step is to find the fractional denominator. To do this, find the frequency that

divides the phase detector frequency by the channel spacing. For instance, if the

output ranges from 5000 to 5050 in 5 MHz steps and the phase detector is 100

MHz, then the fractional denominator is 100 MHz/5 = 20. So for a an output of 5015

MHz, the N divider would be 50 + 3/20. In this case, the fractional numerator is 3

and the fractional denominator is 20. Sometimes when dithering is used, it makes

Fractional Numerator and

Denominator

FRAC_NUM

FRAC_DEN

sense

to

express

this

as

a

larger

equivalent

fraction.

Note that if ramping is active, the fractional denominator is forced to 2²⁴

.

There are many trade-offs, but in general try either the 2nd or 3rd order modulator

Fractional Order

Dithering

FRAC_ORDER as starting points. The 3rd order modulator may give lower main spurs, but may

generate others. Also if dithering is involved, it can generate phase noise.

Dithering can reduce some fractional spurs, but add noise. Consult application note

FRAC_DITH

AN-1879 for more details on this.

8.4.2 Modulated Waveform Generator

In this mode, the device can generate a broad class of frequency sweeping waveforms. The user can specify up

to 8 linear segments in order to generate these waveforms. When the ramping function is running, the

denominator is fixed to a forced value of 2²⁴= 16777216

In addition to the ramping functions, there is also the capability to use a terminal to add phase or frequency

modulation that can be done by itself or added on top of the waveforms created by the ramp generation

functions.

13

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.5 Programming

8.5.1 Loading Registers

The device is programmed using several 24 bit registers. The first 16 bits of the register are the address,

followed by the next 8 bits of data. The user has the option to pull the LE terminal high after this data, or keep

sending data and it will apply this data to the next lower register. So instead of sending three registers of 24 bits

each, one could send a single 40 bit register with the 16 bits of address and 24 bits of data. For that matter, the

entire device could be programmed as a single register if desired.

8.6 Register Map

Registers are programmed in REVERSE order from highest to lowest. Registers NOT shown in this table or

marked as reserved can be written as all 0's unless otherwise stated. The POR value is the power on reset value

that is assigned when the device is powered up or the SWRST bit is asserted.

Table 1. Register Map

Register

D7

D6

D5

D4

D3

D2

D1

D0

POR

0x18

0x00

-

0

1

2

0

0x1

0

1

0

Reserved

0x2

0

SWRST

POWERDOWN[1:0]

PLL_N[17:16]

3-15

16

17

18

19

20

21

22

23

24

25

26

0x3 - 0xF

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

PLL_N[7:0]

0x64

0x00

0x04

0x00

PLL_N[15:8]

FRAC_ORDER[2:0]

FRAC_DITHER[1:0]

FRAC_NUM[7:0]

FRAC_NUM[15:8]

FRAC_NUM[23:16]

FRAC_DEN[7:0]

FRAC_DEN[15:8]

FRAC_DEN[23:16]

PLL_R[7:0]

PLL_R[15:8]

PLL_R_

DIFF

27

0x1B

0

FL_CSR[1:0]

PFD_DLY[1:0]

0

OSC_2X

0x08

28

29

0x1C

0x1D

0

CPPOL

CPG[4:0]

0x00

FL_TOC[10:8]

FL_CPG[4:0]

CPM_

FLAGL

30

31

0x1E

0x1F

0

CPM_THR_LOW[5:0]

CPM_THR_HIGH[5:0]

0x0a

0x32

CPM_

FLAGH

32

33

34

0x20

0x21

0x22

FL_TOC[7:0]

DLD_PASS_CNT[7:0]

DLD_ERR_CNTR[4:0]

TRIG1

_MUX[5]

0x00

0x0f

0x00

DLD_TOL[2:0]

1

MOD_

MUX[5]

MUXout

_MUX[5]

TRIG2

_MUX[5]

35

0x23

0

1

0x41

36

37

0x24

0x25

TRIG1_MUX[4:0]

TRIG2_MUX[4:0]

MOD_MUX[4:0]

TRIG1_PIN[2:0]

TRIG2_PIN[2:0]

MOD_PIN[2:0]

0x08

0x10

0x18

0x38

-

38

0x26

39

0x27

MUXout_MUX[4:0]

MUXout_PIN[2:0]

40-57

0x28-0x39

Reserved

14

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

Register Map (continued)

Table 1. Register Map (continued)

Register

0x3A

D7

D6

D5

D4

D3

D2

D1

D0

POR

RAMP_

PM_EN

RAMP_

CLK

58

RAMP_TRIG_A[3:0]

RAMP_TRIG_C[3:0]

0

RAMP_EN

0x00

59

60

61

62

63

64

65

66

67

68

69

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

RAMP_TRIG_B[3:0]

0x00

RAMP_CMP0[7:0]

RAMP_CMP0[15:8]

RAMP_CMP0[23:16]

RAMP_CMP0[31:24]

RAMP_CMP0_EN[7:0]

RAMP_CMP1[7:0]

RAMP_CMP1[15:8]

RAMP_CMP1[23:16]

RAMP_CMP1[31:24]

RAMP_CMP1_EN[7:0]

RAMP_

LIMH[32]

RAMP_

LIML[32]

FSK_

DEV[32]

RAMP_

CMP1[32] CMP0[32]

RAMP_

70

0x46

0

FSK_TRIG[1:0]

0x08

71

72

73

74

75

76

77

78

79

80

81

82

83

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

FSK_DEV[7:0]

0x00

0xff

FSK_DEV[15:8]

FSK_DEV[23:16]

FSK_DEV[31:24]

RAMP_LIMIT_LOW[7:0]

RAMP_LIMIT_LOW[15:8]

RAMP_LIMIT_LOW[23:16]

RAMP_LIMIT_LOW[31:24]

RAMP_LIMIT_HIGH[7:0]

RAMP_LIMIT_HIGH[15:8]

RAMP_LIMIT_HIGH[23:16]

RAMP_LIMIT_HIGH[31:24]

RAMP_COUNT[7:0]

0xff

0x00

RAMP_

AUTO

84

85

0x54

0x55

RAMP_TRIG_INC[1:0]

RAMP_COUNT[12:8]

0x00

Reserved

15

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

Register Map (continued)

Table 1. Register Map (continued)

Register

0x56

D7

D6

D5

D4

D3

D2

D1

D0

POR

0x00

86

87

88

RAMP0_INC[7:0]

RAMP0_INC[15:8]

RAMP0_INC[23:16]

0x57

0x58

RAMP0_

DLY

RAMP0_

FL

89

0x59

RAMP0_INC[29:24]

RAMP0_LEN[7:0]

0x00

90

91

0x5A

0x5B

0x00

RAMP0_LEN[15:8]

RAMP0_

NEXT_TRIG[1:0]

RAMP0_

RST

92

0x5C

RAMP0_NEXT[2:0]

RAMP0_FLAG[1:0]

RAMP1_FLAG[1:0]

RAMP2_FLAG[1:0]

RAMP3_FLAG[1:0]

0x00

93

94

95

0x5D

0x5E

0x5F

RAMP1_INC[7:0]

RAMP1_INC[15:8]

RAMP1_INC[23:16]

0x00

RAMP1_

DLY

RAMP1_

FL

96

0x60

RAMP1_INC[29:24]

0x00

97

98

0x61

0x62

RAMP1_LEN[7:0]

0x00

RAMP1_LEN[15:8]

RAMP1_

NEXT_TRIG[1:0]

RAMP1_

RST

99

0x63

RAMP1_NEXT[2:0]

0x00

100

101

102

0x64

0x65

0x66

RAMP2_INC[7:0]

RAMP2_INC[15:8]

RAMP2_INC[23:16]

0x00

RAMP2

DLY

RAMP2_

FL

103

0x67

RAMP2_INC[29:24]

0x00

104

105

0x68

0x69

RAMP2_LEN[7:0]

0x00

RAMP2_LEN[15:8]

RAMP2_

NEXT_TRIG[1:0]

RAMP2_

RST

106

0x6A

RAMP2_NEXT[2:0]

0x00

107

108

109

0x6B

0x6C

0x6D

RAMP3_INC[7:0]

RAMP3_INC[15:8]

RAMP3_INC[23:16]

0x00

RAMP3_

DLY

RAMP3_

FL

110

0x6E

RAMP3_INC[29:24]

RAMP3_LEN[7:0]

0x00

111

112

0x6F

0x70

0x00

RAMP3_LEN[15:8]

RAMP3_

NEXT_TRIG[1:0]

RAMP3_

RST

113

0x71

RAMP3_NEXT[2:0]

0x00

16

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

Register Map (continued)

Table 1. Register Map (continued)

Register

0x72

D7

D6

D5

D4

D3

D2

D1

D0

POR

0x00

114

115

116

RAMP4_INC[7:0]

RAMP4_INC[15:8]

RAMP4_INC[23:16]

0x73

0x74

RAMP4_

DLY

RAMP4_

FL

117

0x75

RAMP4_INC[29:24]

RAMP4_LEN[7:0]

0x00

118

119

0x76

0x77

0x00

RAMP4_LEN[15:8]

RAMP4_

NEXT_TRIG[1:0]

RAMP4_

RST

120

0x78

RAMP4_NEXT[2:0]

RAMP4_FLAG[1:0]

RAMP5_FLAG[1:0]

RAMP6_FLAG[1:0]

RAMP7_FLAG[1:0]

0x00

121

122

123

0x79

0x7A

0x7B

RAMP5_INC[7:0]

RAMP5_INC[15:8]

RAMP5_INC[23:16]

0x00

RAMP5_

DLY

RAMP5_

FL

124

0x7C

RAMP5_INC[29:24]

0x00

125

126

0x7D

0x7E

RAMP5_LEN[7:0]

0x00

RAMP5_LEN[15:8]

RAMP5_

NEXT_TRIG[1:0]

RAMP5_

RST

127

0x7F

RAMP5_NEXT[2:0]

0x00

128

129

130

0x80

0x81

0x82

RAMP6_INC[7:0]

RAMP6_INC[15:8]

RAMP6_INC[23:16]

0x00

RAMP6_

DLY

RAMP6_

FL

131

0x83

RAMP6_INC[29:24]

0x00

132

133

0x84

0x85

RAMP6_LEN[7:0]

0x00

RAMP6_LEN[15:8]

RAMP6_

NEXT_TRIG[1:0]

RAMP6_

RST

134

0x86

RAMP6_NEXT[2:0]

0x00

135

136

137

0x87

0x88

0x89

RAMP7_INC[7:0]

RAMP7_INC[15:8]

RAMP7_INC[23:16]

0x00

RAMP7_

DLY

RAMP7_

FL

138

0x8A

RAMP7_INC[29:24]

RAMP7_LEN[7:0]

0x00

139

140

0x8B

0x8C

0x00

RAMP7_LEN[15:8]

RAMP7_

NEXT_TRIG[1:0]

RAMP7_

RST

141

0x8D

RAMP7_NEXT[2:0]

0x00

0x8E-

0x7fff

142-32767

Reserved

17

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.7 Register Field Descriptions

The following sections go through all the programmable fields and their states. Additional information is also

available in the applications and feature descriptions sections as well. The POR column is the power on reset

state that this field assumes if not programmed.

8.7.1 POWERDOWN and Reset Fields

Table 2. POWERDOWN and Reset Fields

Field

Location

POR

Description and States

Value

POWERDOWN State

POWERDOWN, ignore CE

Power Up, ignore CE

0

1

POWERDOWN

[1:0]

R2[1:0]

0

POWERDOWN Control

Power State Defined by CE

terminal state

2

3

Reserved

Reset State

Value

Software Reset. Setting this bit sets all

registers to their POR default values.

SWRST

R2[2]

0

1

Normal Operation

Register Reset

18

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

8.7.2 Dividers and Fractional Controls

Table 3. Dividers and Fractional Controls

Field

Location

POR

Description and States

PLL_N

[17:0]

R18[1] to

R16[0]

Feedback N counter Divide value. Minimum count is 16. Maximum is 262132. Writing of

the register R16 begins any ramp execution when RAMP_EN=1.

16

Value

Dither

Weak

0

FRAC_ DITHER

[1:0]

R18[3:2]

R18[6:4]

0

Dither used by the fractional modulator

1

Medium

2

Strong

3

Disabled

Value

Modulator Order

Integer Mode

1st Order Modulator

2nd Order Modulator

3rd Order Modulator

4th Order Modulator

Reserved

0

1

FRAC_ ORDER

[2:0]

Fractional Modulator order

2

3

4

5-7

FRAC_NUM

[23:0]

R21[7] to

R19[0]

Fractional Numerator. This value should be less than or equal to the fractional

denominator.

0

1

FRAC_DEN

[23:0]

R24[7] to

R22[0]

Fractional Denominator. If the RAMP_EN=1, this field is ignored and the denominator is

fixed to 2²⁴

.

PLL_R

[15:0]

R26[7] to

R25[0]

Reference Divider value. Selecting 1 will bypass counter.

Value

Doubler

Disabled

Enables the Doubler before the Reference

divider

OSC_2X

R27[0]

R27[2]

0

1

Enabled

Enables the Differential

R

counter.

Value

R Divider

Single-Ended

Differential

Pulse Width

Reserved

860 ps

This allows for higher OSCin frequencies,

but restricts PLL_R to divides of 2,4,8 or

16.

0

PLL_R _DIFF

1

Value

Sets the charge pump minimum pulse

width. This could potentially be a trade-off

between fractional spurs and phase noise.

Setting 1 is recommended for general use.

0

PFD_DLY

[1:0]

R27[4:3]

1

2

1200 ps

3

1500 ps

Value

Charge Pump State

Tri-State

0

1

100 uA

CPG

[4:0]

R28[4:0]

R28[5]

0

Charge pump gain

2

200 uA

…

31

Value

0

…

3100 uA

Charge Pump Polarity

Negative

Charge

Pump

Polarity

CPPOL

Positive is for a positive slope VCO

characteristic, negative otherwise.

1

Positive

19

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.7.2.1 Speed Up Controls (Cycle Slip Reduction and Fastlock)

Table 4. FastLock and Cycle Slip Reduction

Field

Location

POR

Description and States

Cycle Slip Reduction (CSR) reduces the

phase detector frequency by multiplying

both the R and N counters by the CSR

value while either the FastLock Timer is

counting or the RAMPx_FL=1 and the part

is ramping. Care must be taken that the R

and N divides remain inside the range of

the counters. Cycle slip reduction is

Value

CSR Value

0

1

2

Disabled

x 2

FL_ CSR

[1:0]

x 4.

R27[6:5]

0

3

Reserved

generally

ramping.

not

recommended

during

Value

Fastlock Charge Pump Gain

0

1

Tri-State

100 uA

Charge pump gain only when Fast Lock

FL_ CPG

[4:0]

R29[4:0]

0

Timer is counting down or

running with RAMPx_FL=1

a ramp is

2

200 uA

…

31

Value

0

…

3100 uA

Fast Lock Timer. This counter starts

counting when the user writes the

PLL_N(Register R16). During this time the

FL_CPG gain is sent to the charge pump,

Fastlock Timer Value

Disabled

1

1 x 32 = 32

R29[7:5]

and

R32[7:0]

FL_ TOC

[10:0]

0

and the FL_CSR shifts the R and N

...

counters if enabled. When the counter

terminates, the normal CPG is presented

and the CSR undo’s the shifts to give a

normal PFD frequency.

2047

2047 x 32 = 65504

20

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

8.8 Lock Detect and Charge Pump Monitoring

Table 5. Lock Detect and Charge Pump Monitor

Field

Location

POR

Description and States

Value

Threshold

Lowest

Charge pump voltage low threshold value.

0x0A When the charge pump voltage is below

this threshold, the LD goes low.

0

…

CPM_THR _LOW

[5:0]

R30[5:0]

…

63

Highest

Value

Flag Indication

This is a read only bit.

Low indicates the charge pump voltage is

below the minimum threshold.

Charge pump is below

CPM_THR_LOW threshold

0

1

CPM_FLAGL

R30[6]

R31[5:0]

R31[6]

-

Charge pump is above

CPM_THR_LOW threshold

Value

0

Threshold

Lowest

…

Charge pump voltage high threshold value.

CPM_THR _HIGH

[5:0]

0x32 When the charge pump voltage is above

this threshold, the LD goes low.

…

63

Highest

Threshold

Value

This

is

a

read

only

bit.

Charge pump is below

CPM_THR_HIGH threshold

Charge pump voltage high comparator

reading. High indicates the charge pump

voltage is above the maximum threshold.

0

1

CPM_FLAGH

-

Charge pump is above

CPM_THR_HIGH threshold

Digital Lock Detect Filter amount. There must be at least DLD_PASS_CNT good edges

0xff and less than DLD_ERR edges before the DLD is considered in lock. Making this number

smaller will speed the detection of lock, but also will allow a higher chance of DLD chatter.

DLD_ PASS_CNT

[7:0]

R33[7:0]

R34[4:0]

Digital Lock Detect error count. This is the maximum number of errors greater than

DLD_TOL that are allowed before DLD is de-asserted. Although the default is 0, the

recommended value is 4.

DLD_ ERR_CNT

[4:0]

0

Value

Window and Fpd Frequency

0

1 ns (Fpd > 130 MHz)

Digital Lock detect edge window. If both N

and R edges are within this window, it is

considered a “good” edge. Edges that are

farther apart in time are considered “error”

edges. Window choice depends on phase

detector frequency, charge pump minimum

pulse width, fractional modulator order and

the users desired margin.

1.7 ns (80 MHz , Fpd ≤ 130

1

MHz)

2

3

3 ns (60 MHz , Fpd ≤ 80 MHz)

6 ns (45 MHz , Fpd ≤ 60 MHz)

DLD _TOL

[2:0]

R34[7:5]

10 ns (30 MHz < Fpd ≤ 45

4

MHz)

5

18 ns ( Fpd ≤ 30 MHz)

6 and 7

Reserved

21

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.9 TRIG1,TRIG2,MOD, and MUXout Pins

Table 6. TRIG1, TRIG2, MOD, and MUXout Terminal States

Field

Location

POR

Description and States

Value

Pin Drive State

0

1

2

TRISTATE (default)

Open Drain Output

TRIG1 _PIN

[2:0]

R36[2:0]

0

Pullup / Pulldown Output

TRIG2 _PIN

[2:0]

R37[2:0]

R38[2:0]

0

3

Reserved

This is the terminal drive state for the

TRIG1, TRIG2, MOD, and MUXout Pins

MOD_ _PIN

[2:0]

4

5

6

7

GND

Inverted Open Drain Output

MUXout_ _PIN

[2:0]

Inverted Pullup / Pulldown

Output

R39[2:0]

0

Input

22

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

Table 7. TRIG1, TRIG2, MOD, and MUXout Selections

Field

Location

POR

Description and States

Value

MUX State

GND

0

1

2

3

Input TRIG1

Input TRIG2

Input MOD

Output TRIG1 after

synchronizer

4

5

6

Output TRIG2 after

synchronizer

Output MOD after

synchronizer

7

8

9

Output Read back

Output CMP0

Output CMP1

Output LD (DLD good AND

CPM good)

10

11

12

13

14

Output DLD

Output CPMON good

Output CPMON too High

Output CPMON too low

These fields control what signal is muxed

to or from the TRIG1,TRIG2, MOD, and

MUXout pins.

Some of the abbreviations used are:

COMP0, COMP1: Comparators 0 and 1

LD, DLD: Lock Detect, Digital Lock Detect

Output RAMP LIMIT

EXCEEDED

15

TRIG1_MUX

R36[7:3],

R37.3

R36[7:3],

R35.3

R37[7:3],

R35.4

R38[7:3],

R35.7

[5:0]

TRIG2_MUX

[5:0]

MOD_MUX

[5:0]

16

17

Output R Divide/2

Output R Divide/4

Output N Divide/2

Output N Divide/4

Reserved

1

2

3

7

18

CPM:

CPG:

CPUP:

Charge

Pump

Pump Up

Monitor

Gain

Pulse

MUXout_MUX

[5:0]

19

20

CPDN: Charge Pump Down Pulse

21

Reserved

22

Output CMP0RAMP

Output CMP1RAMP

Reserved

23

24

25

Reserved

26

Reserved

27

Reserved

28

Output Faslock

Output CPG from RAMP

Output Flag0 from RAMP

Output Flag1 from RAMP

Output TRIGA

29

30

31

32

33

Output TRIGB

34

Output TRIGC

35

Output R Divide

Output CPUP

36

37

Output CPDN

38

Output RAMP_CNT Finished

Reserved

39 to 63

23

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.10 Ramping Functions

Table 8. Ramping Functions

Field

Location

POR

Description and States

Enables the RAMP functions. When this bit

is set, the Fractional Denominator is fixed

to 2²⁴. RAMP execution begins at RAMP0

upon the PLL_N[7:0] write. The Ramp

should be set up before RAMP_EN is set.

Value

Ramp

0

Disabled

RAMP_EN

R58[0]

0

1

Enabled

RAMP clock input source. The ramp can

be clocked by either the phase detector

clock or the MOD terminal based on this

selection.

Value

Source

0

Phase Detector

RAMP_CLK

R58[1]

R58[2]

0

1

MOD Terminal

Value

Modulation Type

RAMP_PM_EN

Phase modulation enable.

0

1

Frequency Modulation

Phase Modulation

Value

0

Source

Never Triggers (default)

TRIG1 terminal rising edge

TRIG2 terminal rising edge

MOD terminal rising edge

DLD Rising Edge

1

2

3

4

5

CMP0 detected (level)

RAMPx_CPG Rising edge

RAMPx_FLAG0 Rising edge

Always Triggered (level)

TRIG1 terminal falling edge

TRIG2 terminal falling edge

MOD terminal falling edge

DLD Falling Edge

RAMP_TRIGA

[3:0]

RAMP_TRIGB

[3:0]

RAMP_TRIGC

[3:0]

6

R58[7:4]

R59[3:0]

R59[7:4]

0

Trigger A,B, and C Sources

7

8

9

10

11

12

13

14

15

CMP1 detected (level)

RAMPx_CPG Falling edge

RAMPx_FLAG0 Falling edge

R70[0],

R63[7] to

R60[0]

RAMP_CMP0

[32:0]

Twos compliment of Ramp Comparator 0 value. Be aware of that the MSB is in Register

R70.

0

Comparator 0 is active during each RAMP corresponding to the bit. Place a 1 for ramps it

is active in and 0 for ramps it should be ignored. RAMP0 corresponds to R64[0], RAMP7

corresponds to R64[7]

RAMP_CMP0_EN

[7:0]

R64[7:0]

R70[1],

R68[7] to

R65[0]

RAMP_CMP1

[32:0]

Twos compliment of Ramp Comparator 1 value. Be aware of that the MSB is in Register

R70.

Comparator 1 is active during each RAMP corresponding to the bit. Place a 1 for ramps it

is active in and 0 for ramps it should be ignored. RAMP0 corresponds to R64[0], RAMP7

corresponds to R64[7].

RAMP_CMP1_EN

[7:0]

R69[7:0]

Value

Trigger

Always Triggered

Trigger A

0

1

2

3

Deviation trigger source. When this trigger

source specified is active, the FSK_DEV

value is applied.

FSK_TRIG

[1:0]

R76[4] to

R75[3]

0

Trigger B

Trigger C

R70[2],

R74[7] to

R71[0]

Twos compliment of the deviation value for frequency modulation and phase modulation.

This value should be written with 0 when not used. Be aware that the MSB is in Register

R70.

FSK_DEV

[32:0]

24

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

Ramping Functions (continued)

Table 8. Ramping Functions (continued)

Field

Location

POR

Description and States

Twos compliment of the ramp lower limit that the ramp can not go below . The ramp limit

0x000 occurs before any deviation values are included. Care must be taken if the deviation is

00000 used and the ramp limit must be set appropriately. Be aware that the MSB is in Register

R70.

R70[3],

R78[7] to

75[0]

RAMP_LIMIT_LOW

[32:0]

Twos compliment of the ramp higher limit that the ramp can not go above. The ramp limit

0xfffffff occurs before any deviation values are included. Care must be taken if the deviation is

R70[4],

R82[7] to

79.0[0]

RAMP_LIMIT_HIGH

[32:0]

f

used and the ramp limit must be set appropriately. Be aware that the MSB is in Register

R70.

Number of RAMPs that will be executed before a trigger or ramp enable is brought down.

Load zero if this feature is not used. Counter is automatically reset when RAMP_EN goes

from 0 to 1.

RAMP_COUNT

[12:0]

R84[4] to

R83[0]

0

Value

Ramp

RAMP_EN unaffected by ramp

counter (default)

0

Automatically clear RAMP_EN when

RAMP Count hits terminal count.

RAMP_AUTO

R84[5]

0

RAMP_EN automatically

brought low when ramp

counter terminal counts

1

Value

Source

Increments occur on each

ramp transition

0

Increment Trigger source for RAMP

Counter. To disable ramp counter, load a

count value of 0.

RAMP_TRIG_INC

[1:0]

R84[7:6]

1

2

3

Increment occurs on trigA

Increment occurs on trigB

Increment occurs on trigC

25

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

8.11 Individual Ramp Controls

These bits apply for all eight ramps. For the field names, x can be 0,1,2,3,4,5,6, or 7.

Table 9. Individual Ramp Controls

Field

Location POR

Description and States

RAMPx

_INC[29:0]

Varies

0

Signed ramp increment.

Value

0

CPG

RAMPx _FL

Varies

0

This enables fastlock and cycle slip reduction for ramp x.

Disabled

Enabled

Clocks

1

Value

During this ramp, each increment takes 2 PFD cycles per

LEN clock instead of the normal 1 PFD cycle. Slows the

ramp by a factor of 2.

1 PFD clock per RAMP

tick.(default)

RAMPx

_DLY

0

1

Varies

0

2 PFD clocks per RAMP

tick.

RAMPx

_LEN

Number of PFD clocks (if DLY is 0) to continue to increment RAMP. 1=>1 cycle, 2=>2 etc. Maximum of

65536 cycles.

Value

Flag

Both FLAG1 and FLAG0

are zero. (default)

0

FLAG0 is set, FLAG1 is

clear

RAMPx

_FLAG[1:0]

1

2

3

Varies

0

General purpose FLAGS sent out of RAMP.

FLAG0 is clear, FLAG1 is

set

Both FLAG0 and FLAG1

are set.

Forces a clear of the ramp accumulator. This is used to

erase any accumulator creep that can occur depending on

how the ramps are defined. Should be done at the start of a

ramp pattern.

Value

Reset

Disabled

Enabled

RAMP0

_RST

0

1

Value

Operation

RAMPx_LEN

TRIG_A

RAMPx_

[1:0]

Determines what event is necessary to cause the state

machine to go to the next ramp. It can be set to when the

RAMPx_LEN counter reaches zero or one of the events for

Triggers A,B, or C.

0

1

2

3

Varies

0

TRIG_B

TRIG_C

RAMP0

_NEXT[2:0]

The next RAMP to execute when the length counter times out

26

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

9 Applications and Implementation

9.1 Application Information

The LMX2492/92-Q1 can be used in a broad class of applications such as generating a single frequency for a

high frequency clock, generating a tunable range of frequencies, or generating swept waveforms that can be

used in applications such as radar.

9.2 Typical Applications

The following schematic is an example of hat could be used in a typical application.

3.3 or 5 V

R3_LF

100 nF

C2_LF

C1_LF

3.3 V

C3_LF

R2_LF

100 nF

24 23 22 21 20 19

3.3 V

Vcc

GND

18

17

16

15

14

13

1

2

3

4

5

6

MUXOUT

100 nF

18 :

LE

10 pF

36 :

To

DATA

Fin

Circuit

Fin*

CLK

CE

68 :

3.3 V

10 pF

Vcc

51 :

100 nF

3.3 V

7

8

9

10 11 12

3.3 V

18 :

100 nF

68 :

18 :

9.2.1 Design Requirements

For these examples, it will be assumed that there is a 100 MHz input signal and the output frequency is between

9400 and 9800 MHz with various modulated waveforms.

Parameter

Symbol

Value

Comments

Input Frequency

OSCin

100 MHz

There are many possibilities, but this choice gives

good performance and saves a little current (as

shown in the electrical specifications).

Phase Detector

Frequency

Fpd

100 MHz

27

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

Typical Applications (continued)

Parameter

Symbol

Value

Comments

9400 - 9800 MHz (Simple Chirp)

9400 - 9800 (Flattened Ramp)

In the different examples, the VCO frequency is

actually changing. However, the same loop filter

design can be used for all three.

VCO Frequency

Fvco

9500 - 9625 MHz (Complex Triggered

Ramp

This parameter has nothing to do with the

LMX2492/92-Q1, but is rather set by the external

VCO choice.

VCO Gain

Kvco

200 MHz/V

9.2.2 Detailed Design Procedure

The first step is to calculate the reference divider (PLL_R) and feedback divider (PLL_N) values as shown in the

table that follows.

Parameter

Symbol and Calculations

Value

Comments

To design a loop filter, one designs for a fixed VCO

value, although it is understood that the VCO will

tune around. This typical value is usually chosen as

the average VCO frequency.

Average

VCO Frequency

Fvco_Avg

= (Fvco_Max+ Fvco_Min)/2

9600 MHz

This parameter has nothing to do with the

LMX2492/92-Q1, but is rather set by the external

VCO choice. In this case, it was the RFMD1843

VCO.

VCO Gain

Kvco

200 MHz/V

This bandwidth is very wide to allow the VCO

frequency to be modulated.

PLL Loop Bandwidth

Charge Pump Gain

R Divider

BW

380 kHz

3.1 mA

1

Using the larger gain allows a wider loop bandwidth

and gives good phase performance.

CPG

PLL_R

= OSCin / Fpd

This value is calculated from previous values.

PLL_N

= Fvco / Fpd

N Divider

96

C1_LF

C2_LF

C3_LF

R2_LF

R3_LF

68 pF

3.9 nF

Loop Filter

Components

150 pF

390 ohm

These were calculated by TI design tools.

Once a loop filter bandwidth is chosen, the external loop filter components of C1_LF, C2_LF, C3_LF, R2_LF, and

R3_LF can be calculated with a tool such as the Clock Architect tool available at www.ti.com. It is also highly

recommended to look at the EVM instructions. The CodeLoader software is an excellent starting point and

example to see how to program this device.

28

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

9.2.3 Application Performance Plot - Sawtooth Waveform Example

Using the above design, it can be programmed to generate a sawtooth waveform with the following paramters.

Parameter

Ramp Duration

VCO Frequency

Range

Symbol

ΔT

Value

100 uS

Fvco

ΔF

9400 - 9800 MHz

9400 - 9800 MHz = 400 MHz Change

tRAMP0t

Because we want the ramp length to be 100 us, this works out to 10,000 phase detector cycles which means

that RAMP0_LEN=10000. To change 400 MHz, we know that each one of the 10000 steps is 40 kHz. Given the

fractional denominator is 2²⁴= 16777216 and the phase detector frequency is 100 MHz, this implies that the

fractional numerator at the end of the ramp will be 6711. However, since this 6711 number is not exact (closer to

6718.8864), the ramp will creep if we do not reset it. Therefore, we set reset the ramp. After the ramp finishes,

we want to start with the same ramp, so RAMP0_NEXT is RAMP0. The results of this analysis are in the table

below:

RAMP

RAMP0_LEN

RAMP0_INC

RAMP0_NEXT

RAMP0_RST

ΔT × Fpd = 100 us / 100 MHz

(ΔF / Fpd) /RAMP0_LEN × 2²⁴

= (400/100)/10000 ×16777216 = 6711

RAMP0

0

1

= 10000

The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually

measured was from the divide by two output of the VCO and therefore the measured frequency was half of the

actual frequency presented to the PLL. This ramping waveform does show some undershoot as the frequency

rapidly returns from 9800 MHz ( 4900 MHz on the plot) to 9400 MHz (4700 MHz on the plot). This undershoot

can be mitigated by adding additional ramps.

29

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

9.2.4 Application Performance Plot - Flat Top Triangle Waveform

Now consider pattern as shown below. The ramp is sometimes used because it can better account for Doppler

Shift. The purpose for making the top and bottom portions flat is to help reduce the impact of the PLL

overshooting and undershooting in order to make the sloped ramped portions more linear.

Parameter

Symbol

ΔT0

Value

10 uS

90 uS

10 uS

90 uS

0

ΔT1

Ramp Duration

ΔT2

ΔT3

ΔF0

ΔF1

400 MHz

0

Range

ΔF2

ΔF3

-400 MHz

tRAMP1t

RAMP0

RAMP2

RAMP0

RAMP2

RAMP

RAMPx_LEN

RAMPx_INC

RAMPx_NEXT

RAMPx_RST

10 us/ 100 MHz

=1000

RAMP0

0

1

0

(ΔF / Fpd) /RAMP1_LEN × 2²⁴

= (400/100)/9000 ×16777216 =

7457

90 us / 100 MHz

=9000

RAMP1

RAMP2

2

3

10 us/ 100 MHz

=1000

0

(ΔF / Fpd) /RAMP1_LEN × 2²⁴

= (-400/100)/9000 ×16777216 =

-7457

90 us / 100 MHz

=9000

RAMP3

0

Program in 2's complement of -

7457

= 2³⁰-7457 = 1073734367

30

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually

measured was from the divide by two output of the VCO and therefore the measured frequency was half of the

actual frequency presented to the PLL. The flattened top and bottom of this triangle wave help mitigate the

overshoot and undersoot in the frequency.

The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually

measured was from the divide by two output of the VCO and therefore the measured frequency was half of the

actual frequency presented to the PLL. The flattened top and bottom of this triangle wave help mitigate the

overshoot and undersoot in the frequency.

31

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

9.2.5 Applications Performance Plot -- Complex Triggered Ramp

In this example, the modulation is not started until a trigger pulse from the MOD terminal goes high. Assume a

phase detector frequency of 100 MHz and we RAMP1 to be 60 us and ramps 2,3,and 4 to be 12 us each. We

set the next trigger for RAMP0 to be trigger A and define trigger A to be the MOD terminal. Then we configure as

follows:

MOD

Frequency

9.800 GHz

Increased Charge Pump Gain

9.800 GHz

9.400 GHz

9.725 GHz

9.600 GHz

FLAG0

TRIG1 Output as Loop Filter Switch 1

FLAG1

TRIG2 Output as Loop Filter Switch 2

'T2

'T3

'T4

'T2

'T3

'T4

'T0

'T1

Figure 5. Complex Triggered Ramp Example

RAMPx

_LEN

RAMPx_

INC

RAMPx

_NEXT

RAMPx_

NEXT_TRIG

RAMPx_RS

T

RAMP

RAMP0

RAMP1

RAMPx_FL

RAMPx_FLAG

FLAG0 and

FLAG1

1

0

1

2

TRIG A

1

FLAG0 and

FLAG1

6000

1073730639

TOC Timeout

RAMP2

RAMP3

1200

27963

17476

1

0

3

4

Disabled

FLAG1

TOC Timeout

0

FLAG0 and

FLAG1

RAMP4

1200

10486

0

1

TOC Timeout

0

32

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually

measured was from the divide by two output of the VCO and therefore the measured frequency was half of the

actual frequency presented to the PLL. The flattened top and bottom of this triangle wave help mitigate the

overshoot and undersoot in the frequency.

Figure 6. Actual Measurement for Complex Triggered Ramp

10 Power Supply Recommendations

For power supplies, it is recommended to place 100 nF close to each of the power supply pins. If fractional spurs

are a large concern, using a ferrite bead to each of these power supply pins can reduce spurs to a small degree.

33

LMX2492, LMX2492-Q1

ZHCSCB6 –MARCH 2014

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

For layout examples, the EVM instructions are the most comprehensive document. In general, the layout

guidelines are similar to most other PLL devices. For the high frequency Fin pin, it is recommended to use 0402

components and match the trace width to these pad sizes. Also the same needs to be done on the Fin* pin. If

layout is easier to route the signal to Fin* instead of Fin, then this is acceptable as well.

11.2 Layout Example

34

LMX2492, LMX2492-Q1

www.ti.com.cn

ZHCSCB6 –MARCH 2014

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

Texas Instruments has several software tools to aid in the development process including CodeLoder for

programming, Clock Design Tool for Loop filter design and phase noise/spur simulation, and the Clock Architect.

All these tools are available at www.ti.com.

12.2 Documentation Support

12.2.1 Related Documentation

For the avid reader, the following resources are available at www.ti.com.

Application Note 1879 -- Fractional N Frequency Synthesis

PLL Performance, Simulation, and Design -- by Dean Banerjee

12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 10. Related Links

TECHNICAL

DOCUMENTS

TOOLS and

SOFTWARE

SUPPORT and

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE and BUY

LMX2492

Click here

LMX2492-Q1

12.4 Trademarks

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧导航栏。

35

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

4.1

3.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

7

12

20X 0.5

6

13

2X

25

2.5

2.6 0.1

1

18

0.3

24X

0.2

24

19

PIN 1 ID

(OPTIONAL)

0.1

C A B

C

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(1.05)

SYMM

25

(3.8)

20X (0.5)

(R0.05)

TYP

6

13

(

0.2) TYP

VIA

7

12

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

19

(R0.05) TYP

24

24X (0.6)

1

18

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

25

(3.8)

6

13

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMX2492QRTWTQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有斜坡/线性调频脉冲生成功能的汽车级 500MHz 至 14GHz 宽带、低噪声分数 N PLL \| RTW \| 24 \| -40 to 125 脉冲
文件：	总41页 (文件大小：1910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMX2492QRTWTQ1 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E