LMX2571SRHHTEP_技术文档

LMX2571-EP

ZHCSP40B –OCTOBER 2021 –REVISED JUNE 2022

具有FSK 调制功能的LMX2571-EP 低功耗、高性能PLLatinum^™射频合成器

1 特性

3 说明

• VID#：V62/21613-01XE

• -55 °C 至+125 °C 工作温度

• 10MHz 至1344MHz 范围内的任何频率

• 低相位噪声和毛刺

LMX2571-EP 器件是一款低功耗、高性能的宽带

PLLatinum^™射频合成器，该器件集成了 Δ-Σ 分数 N

PLL、多核电压控制振荡器(VCO)、可编程输出分频器

和两个输出缓冲器。VCO 内核的工作频率高达

5.376GHz ，持续输出频率范围为 10MHz

1344MHz。

至

– -123dBc/Hz（在480MHz 且偏移为12.5kHz

时）

– -145dBc/Hz（在480MHz 且偏移为1MHz 时）

– 标准PLL 本底噪声为–231dBc/Hz

– 杂散优于–75dBc/Hz

该合成器还可搭配外部 VCO 使用。在此配置下，需使

用专用的5V 电荷泵和输出分频器。

该合成器还包含一个独特的可编程乘法器，有助于去除

毛刺，即使毛刺落在整数边界，系统也仍能够使用任一

通道。

• 新型FastLock 技术，缩短了锁定时间

• 新型整数边界毛刺去除技术

• 集成5V 电荷泵和输出分频器，用于外部VCO 操作

• 2、4 和8 电平或者任意电平数直接数字FSK 调制

• 一个TX/RX 输出或两个扇出输出

• 低电流消耗

输出具有集成式 SPDT 开关，可用作 FDD 无线电应用

中的发送和接收开关。并且可同时导通两个开关，以便

同时提供双输出。

– 39mA 典型合成器模式（内部VCO）

– 9mA 典型PLL 模式（外部VCO）

• 24 位分数N Δ-Σ调制器

通过编程或引脚，LMX2571-EP 可支持直接数字 FSK

调制。此外，还支持离散电平 FSK、脉冲成形 FSK 以

及模拟FM 调制。

• LMX2571 与LMX2571-EP 之间的功能差异

– LMX2571-EP 没有TrCtl 引脚

– LMX2571-EP 没有OSCin* 引脚、差分模式和晶

振模式

该合成器采用了全新的 FastLock 技术，即使在外部

VCO 与窄带回路滤波器搭配使用时，用户也能够在不

到1.5ms 的时间内从一个频率切换至另一频率。

器件信息⁽¹⁾

2 应用

封装尺寸（标称值）

器件型号

封装

• 导引头前端

• 国防无线电

• 飞行器驾驶舱显示屏

• 飞行控制单元

• 无线基础设施

LMX2571-EP

V62/21613-01XE

VQFN (36)

6.00mm × 6.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

Vcc3p3VccIO

VcpExt

CPout

Power

supply

5-V CP

supply

CP

MUX

Int. charge

pump

Output

divider

OP

MUX

RFoutTx

Phase

detector

OSCin

R-divider

Prescaler

N-divider

Fast

lock

5-V charge

pump

VCO

MUX

Output

divider

Lock

dect

µWIRE

SPI

Enable

CE

RFoutRx

modulator

FSK

FLout

CPoutExt

Fin

MUXout

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS824

LMX2571-EP

ZHCSP40B –OCTOBER 2021 –REVISED JUNE 2022

www.ti.com.cn

Table of Contents

7.6 Register Maps...........................................................20

8 Application and Implementation..................................39

8.1 Application Information............................................. 39

8.2 Typical Applications.................................................. 46

8.3 Do's and Don'ts.........................................................55

9 Power Supply Recommendations................................56

10 Layout...........................................................................57

10.1 Layout Guidelines................................................... 57

10.2 Layout Example...................................................... 57

11 Device and Documentation Support..........................58

11.1 Device Support........................................................58

11.2 Documentation Support.......................................... 58

11.3 接收文档更新通知................................................... 58

11.4 支持资源..................................................................58

11.5 Trademarks............................................................. 58

11.6 Electrostatic Discharge Caution..............................58

11.7 术语表..................................................................... 58

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements..................................................8

6.7 Timing Diagrams.........................................................8

6.8 Typical Characteristics................................................9

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................13

7.4 Device Functional Modes..........................................18

7.5 Programming............................................................ 18

Information.................................................................... 58

4 Revision History

Changes from Revision A (December 2021) to Revision B (June 2022)

Page

• 删除了对TrCtl 引脚的所有引用...........................................................................................................................1

• 删除了“差分模式”........................................................................................................................................... 1

• 删除了“晶振模式”........................................................................................................................................... 1

• Redefined the OSCin* pin to NC........................................................................................................................ 3

• Added the Differences Between the LMX2571 and LMX2571-EP section.......................................................13

Changes from Revision * (October 2021) to Revision A (December 2021)

Page

• 将数据表状态从“预告信息”更改为：量产数据................................................................................................ 1

2

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5 Pin Configuration and Functions

图5-1. RHH Package 36-Pin VQFN Top View

表5-1. Pin Functions

TYPE

DESCRIPTION

NAME

Bypass1

Bypass2

CE

NO.

2

Bypass Place a 100-nF capacitor to GND.

3

19

11

25

30

Input

Chip Enable input. Active HIGH powers on the device.

MICROWIRE clock input.

CLK

Input

CPout

Output Internal VCO charge pump access point to connect to a 2^ndorder loop filter.

CPoutExt

Output 5-V charge pump output used in PLL mode (external VCO).

DAP

GND

12

GND

Input

The DAP should be grounded.

MICROWIRE serial data input.

DATA

High-frequency, AC-coupled input pin for an external VCO. Leave it open or AC-coupled to GND if not

being used.

Fin

24

Input

FSK_D0

FSK_D1

FSK_D2

FSK_DV

FLout1

FLout2

GND

7

Input

FSK data bit 0 (FSK PIN mode) / I2S FS input (FSK I2S mode).

FSK data bit 1 (FSK PIN mode) / I2S DATA input (FSK I2S mode).

FSK data bit 2 (FSK PIN mode).

6

5

4

FSK data valid input (FSK PIN mode) / I2S CLK input (FSK I2S mode).

29

28

23

31

35

13

10

Output FastLock output control 1 for external switch. Output is HIGH when F1 is selected.

Output FastLock output control 2 for external switch. Output is HIGH when F2 is selected.

GND

Input

VCO ground.

GND

Charge pump ground.

OSCin ground.

GND

LE

MICROWIRE latch enable input.

MUXout

Output Multiplexed output that can be assigned to lock detect or readback serial data output.

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NC

NO.

14, 26

34

NC

Input

NC

Leave floating, do not connect to GND or power supply.

Reference clock input.

OSCin

NC

8,18, 36

16

These pins may be left floating or connected to GND.

RFoutRx

RFoutTx

Output RF output used to drive receive mixer. Selectable open-drain or push-pull output.

Output RF output used to drive transmit signal. Selectable open-drain or push-pull output.

17

1, 9, 20,

27

Vcc3p3

VccIO

Supply Connect to 3.3-V supply.

15, 33

32

Supply Supply for digital logic interface. Connect to 3.3-V supply.

Supply for 5-V charge pump. Connect to 5-V supply in PLL mode. Connect to either 3.3-V or 5-V

supply in synthesizer mode.

VcpExt

Supply

VrefVCO

VregVCO

22

21

Bypass LDO output. Place a 100-nF capacitor to GND.

Bypass Bias circuitry for the VCO. Place a 2.2-µF capacitor to GND.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

3.6

UNIT

V

V_CC

V_IO

V_CP

V_IN

T_J

Power supply voltage

IO supply voltage

3.6

V

Charge pump supply voltage

IO input voltage

5.25

V

V_CC+ 0.3

150

V

Junction temperature

Storage temperature

°C

–55

–65

T_stg

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC

JS-001, all pins⁽¹⁾

±1500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

3.45

V_CC

5

UNIT

V_CC

V_IO

Power supply voltage

IO supply voltage

3.15

3.3

V

PLL mode (external VCO)

V_CP

T_A

Charge pump supply voltage

Ambient temperature

V

Synthesizer mode (internal VCO)

V_CC

5

125

°C

–55

4

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6.4 Thermal Information

LMX2571-EP

THERMAL METRIC⁽¹⁾

NJK (WQFN)

36 PINS

32.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

14.5

6.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JT

6.3

Ψ_JB

R_θJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

3.15 V ≤V_CC≤3.45 V, V_IO= V_CC, –55 °C ≤T_A≤125 °C, except as specified. Typical values are at V_CC= V_IO= 3.3 V,

V_CP= 3.3 V or 5 V in synthesizer mode, V_CP= 5 V in PLL mode, T_A= 25 °C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT CONSUMPTION

Configuration A⁽¹⁾

39

44

46

51

9

Configuration B⁽²⁾

Configuration C⁽³⁾

Configuration D⁽⁴⁾

Configuration E⁽⁵⁾

Configuration F⁽⁶⁾

Configuration G⁽⁷⁾

I_CC

Synthesizer mode

f_OUT= 480 MHz, SE

OSCIN

mA

I_PLL

PLL mode

15

21

CE = 0 V or POWERDOWN = 1, V_CC= 3.3

V, Push-pull output

I_PD

Powerdown

0.9

OSCIN REFERENCE INPUT

f_OSCIN

Input frequency

Input voltage⁽⁸⁾

10

150

3.3

MHz

V

V_OSCIN

0.8

REFERENCE INPUT PROGRAMMABLE MULTIPLIER

f_MULTin

f_MULTout

PLL

MULT input frequency

MULT output frequency

10

60

30

MULT > Pre-divider

MHz

130

f_PD

Phase detector frequency

Charge pump current⁽⁹⁾

10

130

Internal charge

pump

312.5

625

Programmable

minimum value

5-V charge pump

Internal charge

pump

312.5

625

Per programmable

step

K_PD

µA

5-V charge pump

Internal charge

pump

7187.5

6875

Programmable

maximum value

5-V charge pump

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3.15 V ≤V_CC≤3.45 V, V_IO= V_CC, –55 °C ≤T_A≤125 °C, except as specified. Typical values are at V_CC= V_IO= 3.3 V,

V_CP= 3.3 V or 5 V in synthesizer mode, V_CP= 5 V in PLL mode, T_A= 25 °C.

PARAMETER

TEST CONDITIONS

MIN

TYP

–124

–120

–231

–226

MAX

UNIT

Internal charge

pump

PN_{PLL_1/f}

Normalized PLL 1/f noise⁽¹⁰⁾

5-V charge pump

At maximum charge

pump current

dBc/Hz

Internal charge

pump

PN_{PLL_FLAT}Normalized PLL noise floor⁽¹⁰⁾

5-V charge pump

EXTVCO_CHDIV = 1

100

–10

–5

0

2000

1900

1400

f_RFIN

External VCO input frequency⁽¹¹⁾

External VCO input power

EXTVCO_CHDIV = 8, 10

MHz

dBm

EXTVCO_CHDIV = 2, 3, 4, 5, 6, 7, 9

0.1 GHz ≤f_RFIN< 1 GHz

1 GHz ≤f_RFIN≤1.4 GHz

1.4 GHz < f_RFIN≤2 GHz

P_RFIN

VCO

f_VCO

VCO frequency

VCO gain⁽¹²⁾

4300

5376

165

MHz

K_VCO

f_VCO= 4800 MHz

56

MHz/V

VCO not being recalibrated, –40 °C ≤T_A

≤125 °C

Allowable temperature drift⁽¹³⁾

VCO calibration time

°C

µs

|ΔT_CL

|

f_OSCIN= f_PD= 100

MHz

t_VCOCAL

140

100 Hz offset

1 kHz offset

–32.4

–62.3

10 kHz offset

f_OUT= 480 MHz

–92.1

PNVCO

Open loop VCO phase noise

dBc/Hz

100 kHz offset

–121.1

–144.5

–156.8

1 MHz offset

10 MHz offset

Outputs

Synthesizer mode

10

1344

1400

f_OUT

RF output frequency

MHz

PLL mode, RF output from buffer

P_TX, P_RX

H2_RFout

RF output power

Second harmonic

0

dBm

dBc

Power control bit =

f_OUT= 480 MHz

6

–25

DIGITAL FSK MODULATION

FSK_Level

FSK_Baud

FSK_Dev

FSK level⁽¹⁴⁾

FSK PIN mode

2

8

FSK baud rate⁽¹⁵⁾

Loop bandwidth = 200 kHz

Configuration H⁽¹⁶⁾

100

±39

kSPs

kHz

FSK deviation

DIGITAL INTERFACE

V_IH

V_IL

I_IH

High-level input voltage

1.4

V_CC

0.4

25

V

Low-Level input voltage

High-level input current

Low-Level input current

High-level output voltage

Low-level input voltage

V_IH= 1.75 V

V_IL= 0 V

µA

V

–25

2

I_IL

25

V_OH

V_OL

I_OH= 500 μA

I_OL= –500 μA

0

0.4

V

(1) f_OSCIN= 19.44 MHz, MULT = 1, Prescaler = 4, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(2) f_OSCIN= 19.44 MHz, MULT = 1, Prescaler = 2, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(3) f_OSCIN= 19.44 MHz, MULT = 5, Prescaler = 2, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(4) f_OSCIN= 19.44 MHz, MULT = 5, Prescaler = 2, f_PD= 97.2 MHz, one RF output, output type = push pull, output power = –3 dBm

(5) f_OSCIN= 19.44 MHz, MULT = 1, f_PD= 19.44 MHz, output from VCO

6

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(6) f_OSCIN= 19.44 MHz, MULT = 1, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(7) f_OSCIN= 19.44 MHz, MULT = 1, f_PD= 19.44 MHz, two RF outputs, output type = push pull, output power = –3 dBm

(8) See OSCIN Configuration for definition of OSCIN input voltage.

(9) This is referring to the total base charge pump current. In PLL mode, this is equal to EXTVCO_CP_IDN + EXTVCO_CP_IUP. In

synthesizer mode, this is equal to CP_IDN + CP_IUP.

(10) Measured with a clean OSCIN signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for

an infinite loop bandwidth as:

PLL_Total = 10 * log[10^{(PLL_Flat / 10)}+ 10^{(PLL_Flicker / 10)}

PLL_Flat = PN1Hz + 20 * log(N) + 10 * log(f_PD

]

)

PLL_Flicker = PN10kHz –10 * log(Offset / 10 kHz) + 20 * log(f_OUT/ 1 GHz)

(11) For external VCO frequencies above 1.4 GHz, there are restrictions on the output divider and register R70 needs to be programmed

to 0x046110.

(12) The VCO gain changes as a function of the VCO core and frequency. See Integrated VCO for details.

(13) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an

initial temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay in lock.

This change could be up or down in temperature and the specification does not apply to temperatures that go outside the

recommended operating temperatures of the device.

(14) The data showed here simply specifies the range of discrete FSK level that is supported in PIN mode. PIN mode supports 2-, 4- and 8-

level of FSK modulation. If arbitrary level of FSK modulation is desired, use FSK SPI™ FAST mode or FSK I2S mode. See Direct

Digital FSK Modulation for details.

(15) The baud rate is limited by the loop bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth

at least twice the baud rate.

(16) f_PD= 100 MHz, DEN = 224, CHDIV1 = 5, CHDIV2 = 2, Prescaler = 2, FSK step value = 32716, 32819. The maximum

achievable frequency deviation depends on the configuration, see Direct Digital FSK Modulation for details.

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6.6 Timing Requirements

3.15 V ≤V_CC≤3.45 V, V_IO= V_CC, –55 °C ≤T_A≤125 °C, except as specified. Typical values are at V_CC= V_IO= 3.3 V, T_A

= 25 °C.

MIN

NOM

MAX

UNIT

Timing Requirements

t_ES

CLK to LE low time

5

2

ns

t_CS

DATA to CLK setup time

DATA to CLK hold time

CLK pulse width high

CLK pulse width low

t_CH

2

t_CWH

t_CWL

t_CES

t_EWH

t_OD

10

5

See Figure 6-1

LE to CLK setup time

LE pulse width high

2

CLK to MUXOUT delay time

8

6.7 Timing Diagrams

There are several other considerations for programming:

• A slew rate of at least 30 V/µs is recommended for the CLK, DATA and LE. The same apply for other digital

control signals such as FSK_D[0:2] and FSK_DV signals.

• The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the 24^th

CLK, the data is transferred from the data field to the selected register bank.

• The LE pin may be held high after programming, causing the LMX2571-EP to ignore clock pulses.

• When CLK or DATA lines are shared between devices, it is recommended to divide down the voltage to the

CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.

• If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines

are shared with other parts, the phase noise may be degraded during the time of this programming.

MSB

t_CSt_CH

LSB

DATA

CLK

LE

t_CWL

t_CWH

t_ES

t_CES

t_EWH

图6-1. MICROWIRE Timing Diagram

8

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6.8 Typical Characteristics

at T_A= 25°C (unless otherwise noted)

OSCin = 19.44 MHz

f_OUT= 200 MHz Synthesizer mode

OSCin = 19.44 MHz

f_OUT= 500 MHz Synthesizer mode

图6-2. Typical Closed-Loop Phase Noise

图6-3. Typical Closed-Loop Phase Noise

OSCin = 19.44 MHz

f_OUT= 900 MHz Synthesizer mode

OSCin = 19.44 MHz

f_OUT= 1200 MHz Synthesizer mode

图6-4. Typical Closed-Loop Phase Noise

图6-5. Typical Closed-Loop Phase Noise

FSK_Baud= 4.8 kSPS

FSK PIN mode

Reference clock is a FM modulated signal with f_MOD= 2.4 kHz

图6-6. 4FSK Direct Digital Modulation

图6-7. FM Modulation Through Reference Clock

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6.8 Typical Characteristics (continued)

at T_A= 25°C (unless otherwise noted)

Switching between int. and ext. VCO as well as Tx and Rx

port

Freq. jump = 50 MHz

.

LBW = 4 kHz

PLL mode

图6-8. Output Port and VCO Switching

图6-9. FastLock With SPST Switch

Start: 100 MHz

图6-10. Fin Input Impedance

Stop: 2000 MHz

Start: 10 MHz

Stop: 300 MHz

图6-11. OSCin Input Impedance

-80

-90

Modeled flicker noise

Modeled flat noise

OSCin noise

Modeled flicker noise

Modeled flat noise

OSCin noise

-90

Model total noise

Actual measurement

Modeled total noise

Actual measurement

-100

-110

-120

-130

-140

-150

-160

-100

-110

-120

-130

-140

-150

-160

10²

10³

10⁴

10⁵

10⁶

10⁷

10²

10³

10⁴

10⁵

10⁶

10⁷

Offset /Hz

f_OUT= 1228.8 MHz

f_PD= 122.88 MHz

Synthesizer mode

f_OUT= 430.08 MHz

f_PD= 61.44 MHz

PLL mode

图6-12. Normalized PLL 1/f Noise and Noise Floor

图6-13. Normalized PLL 1/f Noise and Noise Floor

10

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6.8 Typical Characteristics (continued)

at T_A= 25°C (unless otherwise noted)

100

50

single-ended input

30

20

10

5

3

2

1

0.5

0.3

0.2

0.1

85

90

95

100

105

110

115

120

125

Continuous Junction TempertureTj (^oC)

图6-14. Lifetime vs. Temperature

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7 Detailed Description

7.1 Overview

The LMX2571-EP is a frequency synthesizer with low-noise, high-performance integrated VCOs. The 5-GHz

VCO cores, together with the output channel dividers, can produce frequencies from 10 MHz to 1344 MHz. The

LMX2571-EP supports two operation modes, synthesizer mode and PLL mode. In synthesizer mode, the entire

device is used; in PLL mode the internal VCO is bypassed, and an external VCO is required to implement a

complete synthesizer.

The PLL is a fractional-N PLL with programmable Delta Sigma modulator (first order to fourth order). The

fractional denominator is of variable length and up to 24-bits long, providing a frequency step with very fine

resolution.

The internal VCO can be bypassed, allowing the use of an external VCO. A separate 5-V charge pump is

dedicated for the external VCO, eliminating the need for an op-amp to support 5-V VCOs. A new advanced

FastLock technique is developed to shorten the lock time to less than 1.5 ms, even there is a very narrow loop

bandwidth.

A unique programmable multiplier is incorporated in the R-divider. The multiplier is used to avoid and reduce

integer boundary spurs or to increase the phase detector frequency for higher performance.

The LMX2571-EP supports direct digital FSK modulation, thus allowing a change in the output frequency by

changing the N-divider value. The N-divider value can be programmed through MICROWIRE interface or

through pins. Discrete 2-, 4- and 8-level FSK, as well as arbitrary-level FSK, are supported. Arbitrary-level FSK

can be used to construct pulse-shaping FSK or analog-FM modulation.

The output has an integrated T/R switch, and the divided-down internal or external VCO signal can be output to

either the TX port or the RX port. The switch can also be configured as a 1:2 fanout buffer, providing the signal

on both outputs at the same time. In addition to port switching, the output frequency can be switched between

two pre-defined frequencies, F1 and F2, simultaneously. This feature is ideal for use in FDD duplex system

where the TX frequency is different from RX (LO) frequency.

The LMX2571-EP requires only a single 3.3-V power supply. Digital logic interface is 1.8-V input compatible. The

analog blocks power supplies use integrated LDOs, eliminating the need for high performance external LDOs.

Programming of the device is achieved through the MICROWIRE interface. The device can be powered down

through a register programming or toggling the Chip Enable (CE) pin.

7.2 Functional Block Diagram

Vcc3p3VccIO

VcpExt

CPout

Power

supply

5-V CP

supply

CP

MUX

Int. charge

pump

Output

divider

OP

MUX

RFoutTx

Phase

detector

OSCin

R-divider

Prescaler

N-divider

Fast

lock

5-V charge

pump

VCO

MUX

Output

divider

Lock

dect

µWIRE

SPI

Enable

CE

RFoutRx

modulator

FSK

FLout

CPoutExt

Fin

MUXout

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7.3 Feature Description

7.3.1 Differences Between the LMX2571 and LMX2571-EP

For both devices, pin 8 is not connected to the die and pins 14 and 26 are. However, tor the LMX2571-EP, both

Pin 36 and Pin 18 are different and are true no connect pins, meaning that this pin is not connected to the die.

This impacts some of the functionality of the device.

表7-1. Differences Between LMX2571 and LMX2571-EP

Aspect

Details

LMX2571

LMX2571-EP

Pin 36

OSCin*

NC. There is no connection to the die.

Not Supported

R34[14]=0

One may drive OSCin and pin 36 with a

differential signal, but pin 36 is high

impedance (open) and the signal is ignored

at this pin.

Supported

R34[14]=IPBUF_SE_DIFF_SEL

Differential Input

Reference Input

Supported

R34[10]=XTAL_EN

Not Supported

R34[10]=0

Crystal Mode

Pin 18

R34[11]=XTAL_PWRCTRL

R34[11]=2

TrCtl

NC. There is no connection to the die.

Supported

R0[8]=F1F2_CTRL

Software Only

R0[8]=0

Rx/Tx Switching

Pin Switching

R0[10]=RXTX_POL

R0[11]=RXTX_CTL

R0[10]=0

R0[11]=0

7.3.2 Reference Oscillator Input

The OSCin pin is used as frequency reference input to the device. The OSCin pin can be driven single-ended

with a CMOS clock.

The OSCin signal is used as a clock for VCO calibration, therefore a proper signal must be applied at the OSCin

pin at the time of programming the R0 register. A higher slew rate tends to yield the best fractional spurs and

phase noise, so a square wave signal is best for the OSCin pin. If using a sine wave, higher frequencies tend to

yield better phase noise and fractional spurs due to their higher slew rates.

7.3.3 R-Dividers and Multiplier

The R-divider consists of a Pre-divider, a Multiplier (MULT), and a Post-divider.

Pre-

divider

Post-

divider

MULT

OSCin

Phase detector

图7-1. R-Divider

Both the Pre- and Post-dividers divide frequency down while the MULT multiplies frequency up. The purpose of

adding a multiplier is to avoid and reduce integer boundary spurs or to increase the phase-detector frequency for

higher performance. See MULT Multiplier for details. The phase detector frequency, f_PD, is therefore equal to

f_PD= (f_OSCin/ Pre-divider) × (MULT / Post-divider)

(1)

When using the Multiplier (MULT > 1), there are some points to remember:

• The Multiplier must be greater than the Pre-divider.

• Using the multiplier may add noise, especially for multiplier values greater than 6.

7.3.4 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-divider and N-divider and generates a correction current

corresponding to the phase error. This charge pump current is programmable to different strengths. The pump

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up and pump down currents are individually programmable, but should always programmed to the same value.

The effective charge pump current is the sum of the up and down currents and multiplied by a gain multiplier. In

other words, Effective Charge Pump Current = (Base Charge Pump Current) × (Gain Multiplier)

7.3.4.1 CPout Pin Charge Pump Current

When using internal VCO mode, the charge pump output is the CPout pin and the base charge pump current is

programmable in 156.25 µA increments set by the CP_IUP and CP_IDN fields (see 表 7-2). This value is

doubled and then multiplied by the charge pump gain value specified in 表7-3.

表7-2. Base Charge Pump Current When Using Internal VCO

CP_IUP, CP_IDN

BASE CHARGE PUMP CURRENT (µA)

0

Tri-State

156.25

312.5

1

2

3

...

468.75.

...

7

1093.75

1250

8 or 16

9 or 17

...

1406.25

15 or 23

24

2343.75

2500

25

2656.25

...

31

3593.75

表7-3. Charge Pump Gain Multiplier When Using Internal VCO

CP_GAIN

GAIN MULTIPLIER

0

1

2

3

1X

2X

1.5X

2.5X

7.3.4.2 Charge Pump Current When Using External VCO

When using external VCO mode, the charge pump output is the CPoutExt pin and the base charge pump current

is programmable in 312.5 µA increments set by the EXTVCO_CP_IUP and EXTVCO_CP_IDN fields as shown

in 表 7-4. Odd values for EXTVCO_CP_IUP and EXTVCO_CP_IDN are not valued. This value is doubled and

then multiplied by the charge pump gain value specified in 表7-5.

表7-4. Base Charge Pump Current in External VCO Mode

EXTVCO_CP_IUP, EXTVCO_CP_IDN

BASE CHARGE PUMP CURRENT (µA)

0

2

Tri-state

312.5

625

4

6

937.5

1250

8 or 16

10 or 18

12 or 20

14 or 22

24

1562.5

1875

2187.5

2500

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表7-4. Base Charge Pump Current in External VCO Mode (continued)

EXTVCO_CP_IUP, EXTVCO_CP_IDN

BASE CHARGE PUMP CURRENT (µA)

26

28

30

2812.5

3125

3437.5

表7-5. Charge Pump Gain Multiplier in External VCO Mode

EXTVCO_CP_GAIN

CHARGE PUMP GAIN MULTIPLIER

0

1

2

3

1X

2X

1.5X

2.5X

7.3.5 PLL N-Divider and Fractional Circuitry

The total N-divider value is determined by N_integer+ NUM / DEN. The N-divider includes fractional compensation

and can achieve any fractional denominator (DEN) from 1 to 16,777,215 (2²⁴– 1). The integer portion, N_integer

,

is the whole part of the N-divider value and the fractional portion, N_frac= NUM / DEN, is the remaining fraction.

N_integer, NUM and DEN are programmable.

The order of the delta sigma modulator is also programmable from integer mode to fourth order. There are

several dithering modes that are also programmable. Dithering is used to reduce fractional spurs. In order to

make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

7.3.6 Partially Integrated Loop Filter

The LMX2571-EP integrates the third and fourth pole of the loop filter. The values for the resistors can be

programmed independently through the MICROWIRE interface. The larger the values of the resistors, the

stronger the attenuation of the internal loop filter. This partially integrated loop filter can only be used in

synthesizer mode.

CPout

Int. charge

pump

100pF

50pF

图7-2. Integrated Loop Filter

7.3.7 Low-Noise, Fully Integrated VCO

The LMX2571-EP includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning

voltage from the loop filter. Output of the VCO is fed to a prescaler before going to the N-divider. The prescaler

value is selectable between 2 and 4. In general, prescaler equals 2 will result in better phase noise especially

when the PLL is operated in fractional-N mode. If the prescaler equals 4, however, the device will consume less

current. The VCO frequency is related to the other frequencies and Prescaler as follows:

f_VCO= f_PD× N-divider × Prescaler

(2)

To reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency range is

divided into several different frequency bands. This creates the need for frequency calibration to determine the

correct frequency band given a desired output frequency. The VCO is also calibrated for amplitude to optimize

phase noise. These calibration routines are activated any time that the R0 register is programmed with the

FCAL_EN bit equals one. It is important that a valid OSCin signal must present before VCO calibration begins.

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This device will support a full sweep of the valid temperature range of 125°C (–40°C to 85°C) without having to

recalibrate the VCO. This is important for continuous operation of the synthesizer under the most extreme

temperature variation.

7.3.8 External VCO Support

The LMX2571-EP supports an external VCO in PLL mode. In PLL mode, the internal VCO and its associated

charge pump are powered down, and a 5-V charge pump is switched in to support external VCO. No extra

external low noise op-amp is required to support 5-V tuning range VCO. The external VCO output can be

obtained directly from the VCO or from the RF output buffer of the device.

7.3.9 Programmable RF Output Divider

The internal VCO RF output divider consists of two sub-dividers; the total division value is equal to the

multiplication of them. As a result, the minimum division is 4 while the maximum division is 448.

Int.

VCO

Ext.

VCO

CHDIV1

4,5,6,7

CHDIV2

1,2,4,8,16,32,64

CHDIV3

1,2,3,Y,9,10

OP MUX

图7-3. VCO Output Divider

There is only one output divider when external VCO is being used. This divider supports even and odd division,

and its values are programmable between 1 and 10.

7.3.10 Programmable RF Output Buffer

The RF output buffer type is selectable between push-pull and open-drain. If the open-drain buffer is selected,

external pullup to VccIO is required. Regardless of output type, output power can be programmed to various

levels. The RF output buffer can be disabled while still keeping the PLL in lock. See RF Output Buffer Type for

details.

7.3.11 Integrated TX, RX Switch

The LMX2571-EP integrates a T/R switch. The output from the internal VCO or external VCO divider will be

routed to either the RFoutTx or RFoutRx ports, depending on the state of the F1F2_SEL bit.

The T/R switch could also be configured as a fanout buffer to output the same signal at both RFoutTx and

RFoutRx ports at the same time. All of these features are also programmable, see Programming for details.

7.3.12 Power Down

The LMX2571-EP can be powered up and down using the CE pin or the POWERDOWN bit. All registers are

preserved in memory and the device may still be programmed when the device is in a powered down state.

When the device comes out of the powered down state, do the following:

1. If it was powered-down by CE pin, pull CE pin HIGH

2. If it was powered-down by POWERDOWN bit, set POWERDOWN = 0 and FCAL_EN = 0

3. Wait for 100-µs to have the internal LDOs settled down

4. Program register R0 with FCAL_EN=1

7.3.13 Lock Detect

The MUXout pin of the LMX2571-EP can be configured to output a signal that indicates when the PLL is being

locked. If lock detect is enabled while the MUXout pin is configured as a lock-detect output, when the device is

locked the MUXout pin output is a logic HIGH voltage. When the device is unlocked, MUXout output is a logic

LOW voltage.

7.3.14 FSK Modulation

Direct digital FSK modulation is supported in LMX2571-EP. FSK modulation is achieved by changing the output

frequency by changing the N-divider value. The LMX2571-EP supports four different types of FSK operation.

1. FSK PIN mode. LMX2571-EP supports 2-, 4-, and 8-level FSK modulation in PIN mode. In this mode,

symbols are directly fed to the FSK_D0, FSK_D1, and FSK_D2 pins. Symbol clock is fed to the FSK_DV pin.

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Symbols are latched into the device on the rising edge of the symbol clock. The maximum supported symbol

clock rate is 1 MHz. The device has eight dedicated registers to prestore the desired FSK frequency

deviations, with each register corresponding to one of the FSK symbols. The LMX2571-EP will change its

output frequency according to the states on the FSK pins; no extra register programming is required.

2. FSK SPI mode. This mode is identical to the FSK PIN mode with the exception that the control for the

selected FSK level is not performed with external pins but with register R34. Each time when register R34 is

programmed, change only the FSK_DEV_SEL field to select the desired FSK frequency deviation as stored

in the dedicated registers.

3. FSK SPI FAST mode. In this mode, instead of selecting one of the prestored FSK level, change the FSK

deviation directly by writing to the register R33, FSK_DEV_SPI_FAST field. As a result, this mode supports

arbitrary-FSK level, which is useful to construct pulse-shaping or analog-FM modulation.

4. FSK I2S mode. This mode is similar to the FSK SPI FAST mode, but the programming format is an I2S

format on dedicated pins instead of SPI. The benefit of using I2S is that this interface could be shared and

synchronous to other digital audio interfaces. The same FSK data input pins that are used in FSK PIN mode

are reused to support I2S programming. In this mode only the 16 bits of DATA field is required to program.

The data is transmitted on the high or low side of the frame sync (programmable in register R34,

FSK_I2S_FS_POL). The unused side of the frame sync needs to be at least one clock cycle. In other words,

17 (16 + 1) CLK cycles are required at a minimum for one I2S frame. Maximum I2S clock rate is 100 MHz.

I2S DATA

(FSK_D1)

MSB

Bit 15

LSB

Bit 0

FSK_D[0:2]

I2S CLK

(FSK_DV)

FSK_DV

I2S FS

(FSK_D0)

图7-4. FSK PIN Mode Timing

图7-5. FSK I2S Mode Timing

See Direct Digital FSK Modulation for FSK operation details.

7.3.15 FastLock

The LMX2571-EP includes a FastLock feature that can be used to improve the lock times in PLL mode when the

loop bandwidth is small. In general, the lock time is approximately equal to 4 divided by the loop bandwidth. If

the loop bandwidth is 1 kHz, then the lock time would be 4 ms. However, if the f_PDis much higher than the loop

bandwidth, cycle slipping may occur, and the actual lock time will be much longer. Traditional fastlock usually

reduces lock time by increasing loop bandwidth during frequency switching. However, there is a limitation on the

achievable maximum loop bandwidth due to limitation on charge-pump current and loop filter component values.

In some cases, this kind of fastlock technique will make cycle slip even worse.

The LMX2571-EP adopts a new FastLock approach that eliminates the cycle slip problem. With an external

analog SPST switch in conjunction with FastLock control of the LMX2571-EP, the lock time for a 100-MHz

frequency switch could be settled in less than 1.5 ms. See FastLock With External VCO for details.

7.3.16 Register Readback

The LMX2571-EP allows any of its registers to be read back. The MUXout pin can be programmed to support

either lock-detect output or register-readback serial-data output. To read back a certain register value, follow the

following steps:

1. Set the R/W bit to 1; the data field contents are ignored.

2. Send the register to the device; readback serial data outputs starting at the falling edge of the 8^thclock cycle.

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R/W

= 1

Address

7-bit

Data

= Ignored

DATA

CLK

1^st

2^nd-8^th

9^th-24^th

Read back register value

16-bit

MUXout

LE

图7-6. Register Readback Timing Diagram

7.4 Device Functional Modes

7.4.1 Operation Mode

The device can be operated in synthesizer mode or PLL mode.

1. Synthesizer mode. The internal VCO is adopted.

2. PLL mode. The device is operated as a standalone PLL; an external VCO is required to complete the loop.

7.4.2 Duplex Mode

LMX2571-EP supports fast frequency switching between two predefined register sets, F1 and F2. This feature is

good for duplex operation. The device supports three duplex modes:

1. Synthesizer duplex mode. Both F1 and F2 are operated in synthesizer mode.

2. PLL duplex mode. Both F1 and F2 are operated in PLL mode.

3. Synthesizer/PLL duplex mode. In this mode, F1 and F2 will be operated in different operation mode.

7.4.3 FSK Mode

LMX2571-EP supports four direct digital FSK modulation modes.

1. FSK PIN mode. 2-, 4-, and 8-level FSK modulation. Modulation data is fed to the device through dedicated

pins.

2. FSK SPI mode. 2-, 4-, and 8-level FSK modulation. Pre-defined FSK deviation is selected through SPI

programming.

3. FSK SPI FAST mode. This mode supports arbitrary-level FSK modulation. Desired FSK deviation is written

to the device through SPI programming.

4. FSK I2S mode. Arbitrary-level FSK modulation is supported. Desired FSK deviation is fed to the device

through dedicated pins.

7.5 Programming

The LMX2571-EP is programmed using several 24-bit registers. A 24-bit shift register is used as a temporary

register to indirectly program the on-chip registers. The shift register consists of a data field, an address field,

and a R/W bit. The MSB is the R/W bit. 0 means register write while 1 means register read. The following 7 bits,

ADDR[6:0], form the address field which is used to decode the internal register address. The remaining 16 bits

form the data field DATA[15:0]. While LE is low, serial data is clocked into the shift register upon the rising edge

of clock. Serial data is shifted MSB first into the shift register when programming. When LE goes high, data is

transferred from the data field into the selected active register bank. See 图6-1 for timing diagram details.

7.5.1 Recommended Initial Power on Programming Sequence

When the device is first powered up, it must to be initialized, and the ordering of this programming is important.

The sequence is listed below. After this sequence is completed, the device should be running and locked to the

proper frequency.

1. Apply power to the device and ensure the Vcc pins are at the proper levels.

2. If CE is LOW, pull it HIGH.

3. Wait 100 µs for the internal LDOs to become stable.

4. Ensure that a valid reference is applied to the OSCin pin.

5. Program register R0 with RESET=1. This will ensure all the registers are reset to their default values.

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6. Program in sequence registers R60, R58, R53, …, R1 and then R0.

7.5.2 Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies in different scenarios is as follows:

1. If the N-divider is changing, program the relevant registers, then program R0 with FCAL_EN = 1.

2. In FSK SPI mode, FSK SPI FAST mode, and FSK I2S mode, the fractional numerator is changing; program

the relevant registers only.

3. If switching frequency between F1 and F2, program the relevant control registers only toggle the F1F2_SEL

bit.

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7.6.1 R60 Register (offset = 3Ch) [reset = 4000h]

图7-7. R60 Register

15

1

14

0

13

1

12

0

11

0

10

0

9

8

7

6

5

0

4

0

3

0

2

0

1

0

R/W-4000h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-6. R60 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

R/W

4000h

Program A000h to this field.

7.6.2 R58 Register (offset = 3Ah) [reset = C00h]

图7-8. R58 Register

15

14

13

12

11

10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

1

0

1

0

R/W-C00h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-7. R58 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

R/W

C00h

Program 8C00h to this field.

7.6.3 R53 Register (offset = 35h) [reset = 2802h]

图7-9. R53 Register

15

14

13

12

11

10

9

8

7

6

5

0

4

0

3

0

2

1

0

1

0

R/W-2802h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-8. R53 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

R/W

2802h

Program 7806h to this field.

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7.6.4 R47 Register (offset = 2Fh) [reset = 0h]

图7-10. R47 Register

15

0

14

13

12

0

11

0

10

0

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DITHERING

R/W-0h

0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-9. R47 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

R/W

0h

Program 0h to this field.

14-13

DITHERING

R/W

0h

Set the level of dithering. This feature is used to mitigate spurs

level in certain use case by increasing the level of randomness

in the Delta Sigma modulator, typically done at the expense of

noise at certain offset.

0 = Disabled

1 = Weak

2 = Medium

3 = Strong

12-0

R/W

0h

Program 0h to this field.

7.6.5 R46 Register (offset = 2Eh) [reset = 1Ah]

图7-11. R46 Register

15

14

13

12

11

10

9

8

7

6

5

0

4

1

3

1

2

1

0

VCO_

SEL_S

TRT

VCO_SEL

R/W-1Ah

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-10. R46 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-3

R/W

3h

Program 3h to this field.

2

VCO_SEL_STRT

R/W

0h

Enables VCO calibration to start with the VCO core being

selected in VCO_SEL. Please note that programming to this

register is optional. That is, you do not need to program this

register, the default POR value of this register will ensure that

the right VCO core will be picked up automatically.

0 = Disabled

1 = Enabled

1-0

VCO_SEL

R/W

2h

Set the VCO core to start calibration with. Please note that

programming to this register is optional. That is, you do not need

to program this register, the default POR value of this register

will ensure that the right VCO core will be picked up

automatically.

0 = VCOL

1 = VCOM

2 = VCOH

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7.6.6 R42 Register (offset = 2Ah) [reset = 210h]

图7-12. R42 Register

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

1

0

EXTVC

O_CP_

POL

EXTVCO_CP_IDN

R/W-8h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W-0h

R/W-10h

表7-11. R42 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-6

R/W

8h

Program 8h to this field.

5

EXTVCO_CP_POL

R/W

0h

Sets the phase detector polarity for external VCO in PLL mode

operation. Positive means VCO frequency increases directly

proportional to Vtune voltage.

0 = Positive

1 = Negative

4-0

EXTVCO_CP_IDN

R/W

10h

Set the base charge pump current for external VCO in PLL

mode operation. The total base charge pump current is equal to

EXTVCO_CP_IDN + EXTVCO_CP_IUP. EXTVCO_CP_IDN

must be equal to EXTVCO_CP_IUP. Only even number values

are supported.

0 = Tri-state

2 = 312.5 µA

4 = 625 µA

...

30 = 3437.5 µA

7.6.7 R41 Register (offset = 29h) [reset = 810h]

图7-13. R41 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

EXTVCO_CP_IUP

EXTVCO_CP_

GAIN

CP_IDN

R/W-0h

R/W-10h

R/W-0h

R/W-10h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-12. R41 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-12

R/W

0h

Program 0h to this field.

11-7

EXTVCO_CP_IUP

R/W

10h

Set the base charge pump current for external VCO in PLL

mode operation. The total base charge pump current is equal to

EXTVCO_CP_IDN + EXTVCO_CP_IUP. EXTVCO_CP_IDN

must be equal to EXTVCO_CP_IUP. Only even number values

are supported.

0 = Tri-state

2 = 312.5 µA

4 = 625 µA

...

30 = 3437.5 µA

24

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表7-12. R41 Register Field Descriptions (continued)

BIT

FIELD

EXTVCO_CP_GAIN

TYPE

RESET

DESCRIPTION

6-5

R/W

0h

Set the multiplication factor to the base charge pump current for

external VCO in PLL mode operation. For example, if the gain

here is 2x and if the total base charge pump current

(EXTVCO_CP_IDN + EXTVCO_CP_IUP) is 2.5 mA, then the

final charge pump current applied to the loop filter is 5 mA. The

gain values are not precise. They are provided as a quick way to

boost the total charge pump current for debug purposes or

specific applications.

0 = 1x

1 = 2x

2 = 1.5x

3 = 2.5x

4-0

CP_IDN

R/W

10h

Set the base charge pump current for internal VCO in

synthesizer mode operation. The total base charge pump

current is equal to CP_IDN + CP_IUP. CP_IDN must be equal to

CP_IUP.

0 = Tri-state

1 = 156.25 µA

2 = 312.5 µA

3 = 468.75 µA

...

31 = 3593.75 µA

7.6.8 R40 Register (offset = 28h) [reset = 101Ch]

图7-14. R40 Register

15

14

13

12

11

10

9

8

7

6

5

0

4

1

3

1

2

1

0

CP_IUP

R/W-10h

CP_GAIN

R/W-0h

R/W-1Ch

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-13. R40 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-13

R/W

0h

Program 0h to this field.

12-8

CP_IUP

R/W

10h

Set the base charge pump current for internal VCO in

synthesizer mode operation. The total base charge pump

current is equal to CP_IDN + CP_IUP. CP_IDN must be equal to

CP_IUP.

0 = Tri-state

1 = 156.25 µA

2 = 312.5 µA

3 = 468.75 µA

...

31 = 3593.75 µA

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表7-13. R40 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

7-6

CP_GAIN

R/W

0h

Set the multiplication factor to the base charge pump current for

internal VCO in synthesizer mode operation. For example, if the

gain here is 2x and if the total base charge pump current

(CP_IDN + CP_IUP) is 2.5 mA, then the final charge pump

current applied to the loop filter is 5 mA. The gain values are not

precise. They are provided as a quick way to boost the total

charge pump current for debug purposes or specific

applications.

0 = 1x

1 = 2x

2 = 1.5x

3 = 2.5x

5-0

R/W

1Ch

Program 1Ch to this field.

7.6.9 R39 Register (offset = 27h) [reset = 11F0h]

图7-15. R39 Register

15

14

13

12

11

10

9

8

7

6

5

1

4

1

3

2

0

1

0

1

0

1

SDO_L

D_SEL

LD_EN

R/W-11Fh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W-0h

表7-14. R39 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-4

R/W

11Fh

Program 11Fh to this field.

3

SDO_LD_SEL

R/W

0h

Defines the MUXout pin function.

0 = Register readback serial data output

1 = Lock detect output

2-1

0

R/W

0h

Program 1h to this field.

LD_EN

Enables lock detect function.

0 = Disabled

1 = Enabled

7.6.10 R35 Register (offset = 23h) [reset = 647h]

图7-16. R35 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MULT_WAIT

OUTB OUTB OUTB

UF_AU UF_TX UF_RX

TOMU _TYPE _TYPE

TE

R/W-0h

R/W-C8h

R/W-1h R/W-1h R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-15. R35 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

R/W

0h

Program 0h to this field.

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表7-15. R35 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

13-3

MULT_WAIT

R/W

C8h

A 20-µs settling time is required for MULT, if it is enabled. These

bits set the correct settling time according to the OSCin

frequency. For example, if OSCin frequency is 100 MHz, set

these bits to 2000. No matter if MULT is enabled or not, the

configured MULT settling time forms part of the total frequency

switching time.

0 = Do not use this setting

1 = 1 OSCin clock cycle

...

2047 = 2047 OSCin clock cycles

2

OUTBUF_AUTOMUTE

R/W

1h

If this bit is set, the output buffers will be muted until PLL is

locked. This bit applies to the following events: (a) device

initialization (b) manually change VCO frequency, and (c) F1F2

switching. However, if the PLL is unlocked afterward (for

example, OSCin is removed), the output buffers will not be

muted and will remain active.

0 = Disabled

1 = Enabled

1

0

OUTBUF_TX_TYPE

OUTBUF_RX_TYPE

R/W

1h

Sets the output buffer type of RFoutTx. If the buffer is open drain

output, a pullup to VccIO is required. See RF Output Buffer Type

for details.

0 = Open drain

1 = Push pull

Sets the output buffer type of RFoutRx. If the buffer is open

drain output, a pullup to VccIO is required. See RF Output Buffer

Type for details.

0 = Open drain

1 = Push pull

7.6.11 R34 Register (offset = 22h) [reset = 1000h]

图7-17. R34 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

IPBUF

DIFF_

TERM

0

1

0

FSK_I2 FSK_I2 FSK_LEVEL

S_FS_ S_CLK

FSK_DEV_SEL

FSK_M FSK_M

ODE_ ODE_

SEL0 SEL1

POL

_POL

R/W-0h R/W-0h

R/W-2h

R/W-0h R/W-0h R/W-0h R/W-0h

R/W-0h

R/W-0h R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-16. R34 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

IPBUFDIFF_TERM

R/W

0h

Enables independent 50 Ωinput termination on the OSCin Pin.

0 = Disabled

1 = Enabled

14

13-11

10

R/W

0h

2h

0h

Program 0h to this field.

Program 2h to this field.

Program 0h to this field.

9

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表7-16. R34 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

8

FSK_I2S_FS_POL

R/W

0h

Sets the polarity of the I2S Frame Sync input in FSK I2S mode.

0 = Active HIGH

1 = Active LOW

7

FSK_I2S_CLK_POL

FSK_LEVEL

R/W

0h

Sets the polarity of the I2S CLK input in FSK I2S mode.

0 = Rising edge strobe

1 = Falling edge strobe

6-5

Define the desired FSK level in FSK PIN mode and FSK SPI

mode. When this bit is zero, FSK operation in these modes is

disabled even if FSK_EN_Fx = 1.

0 = Disabled

1 = 2FSK

2 = 4FSK

3 = 8FSK

4-2

FSK_DEV_SEL

R/W

0h

In FSK SPI mode, these bits select one of the FSK deviations as

defined in registers R25-32 or R9-16.

0 = FSK_DEV0_Fx

1 = FSK_DEV1_Fx

...

7 = FSK_DEV7_Fx

1

FSK_MODE_SEL0

FSK_MODE_SEL1

FSK_MODE_SEL0 and FSK_MODE_SEL1 define the FSK

operation mode. FSK_MODE_SEL[1:0] =

00 = FSK PIN mode

01 = FSK SPI mode

10 = FSK I2S mode

11 = FSK SPI FAST mode

0

Same as above.

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7.6.12 R33 Register (offset = 21h) [reset = 0h]

图7-18. R33 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV_SPI_FAST

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-17. R33 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

FSK_DEV_SPI_FAST

R/W

0h

Define the desired frequency deviation in FSK SPI FAST mode.

See Direct Digital FSK Modulation for details.

7.6.13 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]

图7-19. R25 to R32 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV0_F2 to FSK_DEV7_F2

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-18. R25 to R32 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

FSK_DEV0_F2 to FSK_DEV7_F2

R/W

0h

Define the desired frequency deviation in FSK PIN mode and

FSK SPI mode. See Direct Digital FSK Modulation for details.

7.6.14 R24 Register (offset = 18h) [reset = 10h]

图7-20. R24 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_E

N_F2

EXTVCO_CHDIV_F2

EXTVC

O_SEL

_F2

OUTBUF_TX_PWR_F2

R/W-0h

R/W-10h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-19. R24 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

R/W

0h

Program 0h to this field.

10

FSK_EN_F2

R/W

0h

Enables FSK operation in all FSK operation modes. When this

bit is set, fractional denominator DEN should be zero. See Direct

Digital FSK Modulation for details.

0 = Disabled

1 = Enabled

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表7-19. R24 Register Field Descriptions (continued)

BIT

FIELD

TYPE

RESET

DESCRIPTION

9-6

EXTVCO_CHDIV_F2

R/W

0h

Set the value of the output channel divider, CHDIV3, when using

external VCO in PLL mode.

0 = Divide by 1

1 = Reserved

2 = Divide by 2

3 = Divide by 3

...

10 = Divide by 10

11-15 = Reserved

5

EXTVCO_SEL_F2

R/W

0h

Selects synthesizer mode (internal VCO) or PLL mode (external

VCO) operation.

0 = Synthesizer mode

1 = PLL mode

4-0

OUTBUF_TX_PWR_F2

10h

Set the output power at RFoutTx port. See RF Output Buffer

Power Control for details.

7.6.15 R23 Register (offset = 17h) [reset = 10A4h]

图7-21. R23 Register

15

14

13

12

11

10

9

8

7

6

5

0

4

0

3

0

2

1

0

OUTBUF_RX_PWR_F2

OUTB OUTB

UF_TX UF_RX

_EN_F _EN_F

LF_R4_F2

2

R/W-0h

R/W-10h

R/W-1h R/W-0h

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-20. R23 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-13

R/W

0h

Program 0h to this field.

12-8

OUTBUF_RX_PWR_F2

OUTBUF_TX_EN_F2

R/W

10h

Set the output power at RFoutRx port. See RF Output Buffer

Power Control for details.

7

R/W

1h

Enables RFoutTx port.

0 = Disabled

1 = Enabled

6

OUTBUF_RX_EN_F2

R/W

0h

4h

Enables RFoutRx port.

0 = Disabled

1 = Enabled

5-3

Program 0h to this field.

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表7-20. R23 Register Field Descriptions (continued)

BIT

FIELD

LF_R4_F2

TYPE

RESET

DESCRIPTION

Set the resistor value for the 4^thpole of the internal loop filter.

2-0

R/W

4h

The shunt capacitor of that pole is 100 pF.

0 = Bypass

1 = 3.2 kΩ

2 = 1.6 kΩ

3 = 1.1 kΩ

4 = 800 Ω

5 = 640 Ω

6 = 533 Ω

7 = 457 Ω

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7.6.16 R22 Register (offset = 16h) [reset = 8584h]

图7-22. R22 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LF_R3_F2

R/W-4h

CHDIV2_F2

R/W-1h

CHDIV1_F2

R/W-1h

PFD_DELAY_F2

R/W-4h

MULT_F2

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-21. R22 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

Set the resistor value for the 3^rdpole of the internal loop filter.

15-13

LF_R3_F2

R/W

4h

The shunt capacitor of that pole is 50 pF.

0 = Bypass

1 = 3.2 kΩ

2 = 1.6 kΩ

3 = 1.1 kΩ

4 = 800 Ω

5 = 640 Ω

6 = 533 Ω

7 = 457 Ω

12-10

CHDIV2_F2

R/W

1h

Set the value of the output channel divider, CHDIV2, when using

internal VCO in synthesizer mode.

0 = Divide by 1

1 = Divide by 2

2 = Divide by 4

3 = Divide by 8

4 = Divide by 16

5 = Divide by 32

6 = Divide by 64

9-8

CHDIV1_F2

R/W

1h

Set the value of the output channel divider, CHDIV1, when using

internal VCO in synthesizer mode.

0 = Divide by 4

1 = Divide by 5

2 = Divide by 6

3 = Divide by 7

7-5

4-0

PFD_DELAY_F2

MULT_F2

R/W

4h

Used to optimize spurs and phase noise. Suggested values are:

Integer mode (NUM = 0): use PFD_DELAY ≤5

Fractional mode with N-divider < 22: use PFD_DELAY ≤4

Fractional mode with N-divider ≥22: use PFD_DELAY ≥3

Set the MULT multiplier value. MULT value must be greater than

Pre-divider value. See MULT Multiplier for details.

0 = Reserved

1 = Bypass

2 = 2x

...

13 = 13x

14-31 = Reserved

7.6.17 R21 Register (offset = 15h) [reset = 101h]

图7-23. R21 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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图7-23. R21 Register (continued)

PLL_R_F2

R/W-1h

PLL_R_PRE_F2

R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-22. R21 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

PLL_R_F2

R/W

1h

Set the OSCin buffer Post-divider value.

7-0

PLL_R_PRE_F2

R/W

1h

Set the OSCin buffer Pre-divider value. This value must be

smaller than MULT value.

7.6.18 R20 Register (offset = 14h) [reset = 28h]

图7-24. R20 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_N

_PRE_

F2

FRAC_ORDER_F2

PLL_N_F2

R/W-0h

R/W-28h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-23. R20 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15

PLL_N_PRE_F2

R/W

0h

Sets the Prescaler value.

0 = Divide by 2

1 = Divide by 4

14-12

FRAC_ORDER_F2

R/W

0h

Select the order of the Delta Sigma modulator.

0 = Integer mode

1 = 1^storder

2 = 2^ndorder

3 = 3^rdorder

4-7 = 4^thorder

11-0

PLL_N_F2

R/W

28h

Set the integer portion of the N-divider value. Maximum value is

1023.

7.6.19 R19 Register (offset = 13h) [reset = 0h]

图7-25. R19 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F2[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-24. R19 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

PLL_DEN_F2[15:0]

R/W

0h

Set the LSB bits of the fractional denominator of the N-divider.

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7.6.20 R18 Register (offset = 12h) [reset = 0h]

图7-26. R18 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM_F2[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-25. R18 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

PLL_NUM_F2[15:0]

R/W

0h

Set the LSB bits of the fractional numerator of the N-divider.

7.6.21 R17 Register (offset = 11h) [reset = 0h]

图7-27. R17 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F2[23:16]

R/W-0h

PLL_NUM_F2[23:16]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-26. R17 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-8

PLL_DEN_F2[23:16]

R/W

0h

Set the MSB bits of the fractional denominator of the N-divider.

Set the MSB bits of the fractional numerator of the N-divider.

7-0

PLL_NUM_F2[23:16]

R/W

0h

7.6.22 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]

图7-28. R9 to R16 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV0_F1 to FSK_DEV7_F1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-27. R9 to R16 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

FSK_DEV0_F1 to FSK_DEV7_F1

R/W

0h

See 表7-18.

7.6.23 R8 Register (offset = 8h) [reset = 10h]

图7-29. R8 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_E

N_F1

EXTVCO_CHDIV_F1

EXTVC

O_SEL

_F1

OUTBUF_TX_PWR_F1

R/W-0h

R/W-10h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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表7-28. R8 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-11

R/W

0h

Program 0h to this field.

See 表7-19.

10

9-6

5

FSK_EN_F1

R/W

0h

EXTVCO_CHDIV_F1

EXTVCO_SEL_F1

OUTBUF_TX_PWR_F1

0h

See 表7-19.

0h

See 表7-19.

4-0

10h

See 表7-19.

7.6.24 R7 Register (offset = 7h) [reset = 10A4h]

图7-30. R7 Register

15

14

13

12

11

10

9

8

7

6

5

0

4

0

3

0

2

1

0

OUTBUF_RX_PWR_F1

OUTB OUTB

UF_TX UF_RX

_EN_F _EN_F

LF_R4_F1

1

R/W-0h

R/W-10h

R/W-1h R/W-0h

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-29. R7 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-13

R/W

0h

Program 0h to this field.

See 表7-20.

12-8

7

OUTBUF_RX_PWR_F1

OUTBUF_TX_EN_F1

OUTBUF_RX_EN_F1

R/W

10h

1h

0h

4h

See 表7-20.

6

See 表7-20.

5-3

2-0

Program 0h to this field.

See 表7-20.

LF_R4_F1

7.6.25 R6 Register (offset = 6h) [reset = 8584h]

图7-31. R6 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LF_R3_F1

R/W-4h

CHDIV2_F1

R/W-1h

CHDIV1_F1

R/W-1h

PFD_DELAY_F1

R/W-4h

MULT_F1

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-30. R6 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

See 表7-21.

15-13

LF_R3_F1

R/W

4h

12-10

9-8

CHDIV2_F1

CHDIV1_F1

PFD_DELAY_F1

MULT_F1

R/W

1h

4h

7-5

4-0

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7.6.26 R5 Register (offset = 5h) [reset = 101h]

图7-32. R5 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_R_F1

R/W-1h

PLL_R_PRE_F1

R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-31. R5 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

See 表7-22.

15-8

PLL_R_F1

R/W

1h

7-0

PLL_R_PRE_F1

R/W

1h

7.6.27 R4 Register (offset = 4h) [reset = 28h]

图7-33. R4 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_N

_PRE_

F1

FRAC_ORDER_F1

PLL_N_F1

R/W-0h

R/W-28h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-32. R4 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

See 表7-23.

15

PLL_N_PRE_F1

R/W

0h

14-12

11-0

FRAC_ORDER_F1

PLL_N_F1

R/W

0h

28h

See 表7-23.

7.6.28 R3 Register (offset = 3h) [reset = 0h]

图7-34. R3 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F1[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-33. R3 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

PLL_DEN_F1[15:0]

R/W

0h

See 表7-24.

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7.6.29 R2 Register (offset = 2h) [reset = 0h]

图7-35. R2 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM_F1[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-34. R2 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-0

PLL_NUM_F1[15:0]

R/W

0h

See 表7-25.

7.6.30 R1 Register (offset = 1h) [reset = 0h]

图7-36. R1 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F1[23:16]

R/W-0h

PLL_NUM_F1[23:16]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-35. R1 Register Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

See 表7-26.

15-8

PLL_DEN_F1[23:16]

R/W

0h

7-0

PLL_NUM_F1[23:16]

R/W

0h

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7.6.31 R0 Register (offset = 0h) [reset = 3h]

图7-37. R0 Register

15

0

14

0

13

12

11

0

10

0

9

8

7

6

5

0

4

0

3

0

2

0

1

0

RESET POWE

F1F2_I

NIT

0

F1F2_ F1F2_

MODE SEL

FCAL_

EN

RDOW

N

R/W-0h

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-36. R0 Register Field Descriptions

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-14

R/W

0h

Program 0h to this field.

13

RESET

R/W

0h

Resets all the registers to the default values. This bit is self-clearing.

0 = Normal operation

1 = Reset

12

POWERDOWN

R/W

Powers down the device. When the device comes out of the powered down state,

either by resuming this bit to zero or by pulling back CE pin HIGH (if it was powered

down by CE pin), it is required that register R0 with FCAL_EN = 1 be programmed

again to re-calibrate the device. A 100-µs wait-time is recommended before

programming R0.

0 = Normal operation

1 = Power down

11

10

9

R/W

0h

Program this field to 0h.

F1F2_INIT

Toggling this bit re-calibrates F1F2 if F1, F2 are modified after calibration. This bit is

not self-clear, so it is required to clear the bit value after use. See Register R0

F1F2_INIT, F1F2_MODE Usage for details.

0 = Clear bit value

1 = Re-calibrate

8

7

R/W

0h

Program this field to 0h.

F1F2_MODE

Calibrates F1 and F2 during device initialization (initial power on programming).

Even if this bit is not set, F1-F2 switching is still possible but the first switching time

will not be optimized because either F1 or F2 will only be calibrated. If F1-F2

switching is not required, set this bit to zero. See Register R0 F1F2_INIT,

F1F2_MODE Usage for details.

0 = Disable F1F2 calibration

1 = Enable F1F2 calibration

6

F1F2_SEL

FCAL_EN

R/W

0h

Selects F1 or F2 configuration registers.

0 = F1 registers

1 = F2 registers

5-1

0

R/W

1h

Program 1h to this field.

Activates all kinds of calibrations, suggest keep it enabled all the time. If it is

desired that the R0 register be programmed without activating this calibration, then

this bit can be set to zero.

0 = Disabled

1 = Enabled

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Direct Digital FSK Modulation

In fractional mode, the finest delta frequency difference between two programmable output frequencies is equal

to:

f₁–f₂= Δf_min= f_PD× {[(N + 1) / DEN] –(N / DEN)} = f_PD/ DEN

(3)

In other words, when the fractional numerator is incremented by 1 (one step), the output frequency will change

by Δf_min. A two steps increment will therefore change the frequency by 2 × Δf_min

.

In FSK operation, the instantaneous carrier frequency is kept changing among some pre-defined frequencies. In

general, the instantaneous carrier frequency is defined as a certain frequency deviation from the nominal carrier

frequency. The frequency deviation could be positive and negative.

Nominal

carrier

frequency

4FSK symbol: 11 10 00 01

Instantaneous

carrier

frequency

Frequency

Negative

swing

Positive

swing

f_DEV0

图8-2. Typical 4FSK Definition

f_DEV

1

图8-1. General FSK Definition

The following equations define the number of steps required for the desired frequency deviation with respect to

the nominal carrier frequency output at the RFoutTx or RFoutRx port.

表8-1. FSK Step Equations

POLARITY

SYNTHESIZER MODE

PLL MODE

f_DEV* DEN CHDIV1 * CHDIV2

*

f_DEV* DEN

Round

CHDIV3

*

POSITIVE SWING

f_PD

Prescaler

f_PD

(4)

(5)

(7)

NEGATIVE SWING

2's complement of Equation 4

(6) 2's complement of Equation 5

In FSK PIN mode and FSK SPI mode, register R25-32 and R9-16 are used to store the desired FSK frequency

deviations in term of the number of step as defined in the above equations. The order of the registers, 0 to 7,

depends on the application system. 图 8-2 shows a typical 4FSK definition. In this case, FSK_DEV0_Fx and

FSK_DEV1_Fx shall be calculated using 方程式4 or 方程式5 while FSK_DEV2_Fx and FSK_DEV3_Fx shall be

calculated using 方程式6 or 方程式7.

For example, if FSK PIN mode is enabled in F1 to support 4FSK modulation, set

FSK_MODE_SEL1 = 0

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FSK_MODE_SEL0 = 0

FSK_LEVEL = 2

FSK_EN_F1 = 1

表8-2. FSK PIN Mode Example

RAW FSK DATA STREAM INPUT

EQUIVALENT SYMBOL INPUT

REGISTER SELECTED

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV1_F1

FSK_DEV0_F1

...

RF OUTPUT

10

11

10

11

01

00

...

Freq.

FSK_D0

FSK_D1

FSK_DV

Time

FSK SPI mode assumes the user knows which symbol to send; user can directly write to register R34,

FSK_DEV_SEL to select the desired frequency deviation.

For example, to enable the device to support 4FSK modulation at F1 using FSK SPI mode, set

FSK_MODE_SEL1 = 0

FSK_MODE_SEL0 = 1

FSK_LEVEL = 2

FSK_EN_F1 = 1

表8-3. FSK SPI Mode Example

DESIRED SYMBOL

WRITE REGISTER FSK_DEV_SEL

REGISTER SELECTED

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV1_F1

FSK_DEV0_F1

…

10

11

10

11

01

00

...

2

3

2

3

1

0

...

Both the FSK PIN mode and FSK SPI mode support up to 8 levels of FSK. To support an arbitrary-level FSK,

use FSK SPI FAST mode or FSK I2S mode. Constructing pulse-shaping FSK modulation by over-sampling the

FSK modulation waveform is one of the use cases of these modes.

Analog-FM modulation can also be produced in these modes. For example, with a 1-kHz sine wave modulation

signal with peak frequency deviation of ±2 kHz, the signal can be over-sampled, say 10 times. Each sample

point corresponding to a scaled frequency deviation.

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Freq. dev.

+2kHz

t₅t₆t₇t₈t₉

Time

t₀t₁t₂t₃t₄

-2kHz

图8-3. Over-Sampling Modulation Signal

In FSK SPI FAST mode, write the desired FSK steps directly to register R33, FSK_DEV_SPI_FAST. To enable

this mode, set

FSK_MODE_SEL1 = 1

FSK_MODE_SEL0 = 1

FSK_EN_F1 = 1

表8-4. FSK SPI FAST Mode Example

TIME

FREQUENCY

DEVIATION

CORRESPONDING FSK

STEPS⁽¹⁾

BINARY EQUIVALENT

WRITE TO

FSK_DEV_SPI_FAST

t₀

t₁

t₂

618.034 Hz

1618.034 Hz

2000 Hz

518

1357

1678

0000 0010 0000 0110

0000 0101 0100 1101

0000 0110 1000 1110

518

1357

1678

…

t₆

64178

1111 1010 1011 0010

64178

–1618.034 Hz

–2000 Hz

…

t₇

63857

1111 1001 0111 0001

63857

…

(1) Synthesizer mode, f_VCO= 4800 MHz, f_OUT= 480 MHz, f_PD= 100 MHz, Prescaler = 2, DEN = 2²⁴, Use 方程式4 and 方程式6 to

calculate the step value.

In FSK I2S mode, clock in the desired binary format FSK steps in the FSK_D1 pin.

FSK_D1

FSK_DV

FSK_D0

t₀

t₁

图8-4. FSK I2S Mode Example

To enable FSK I2S mode, set

FSK_MODE_SEL1 = 1

FSK_MODE_SEL0 = 0

FSK_EN_F1 =1

8.1.2 Frequency and Output Port Switching

The F1F2_SEL bit controls the output switching.

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8.1.3 OSCin Configuration

The OSCin only supports a single-ended clock. The impedance can be programmed as high impedance or 50 Ω.

图8-5. OSCin Configuration

8.1.4 Register R0 F1F2_INIT, F1F2_MODE Usage

These register bits are used to define the calibration behavior. Correct setting is important to ensure that every

F1-F2 switching time is optimized. 图8-6 illustrates the usage of these register bits.

Freq

F2'

F2

FCAL_EN=1

Change F1, F2

F1F2_INIT=1

F1F2_MODE=1

F1F2_INIT=0

F1

F1'

Time

t₀

t₁

t₂

t₃

t₄

t₅

t₆t₇

t₈t₉

t₁₀

t₁₁

图8-6. F1F2_INIT, F1F2_MODE Usage

Before t₀: Device initialization

• Power up the device.

• Write all registers to the device.

– Ensure FCAL_EN = 1 to enable calibration.

– Only the output frequency (F1 in this example) will be calibrated, F2 will not be calibrated.

– Set F1F2_INIT = 0. Although the setting of this bit is irrelevant and not important here but if F1F2_INIT =

1, change it back to zero before attempting to change the frequency from F1 to F2.

At t₀: Locked to F1

After initialization, both F1 and F2 are calibrated. The calibration data is stored in the internal memory.

At t₁: Switch to F2.

Because FCAL_EN = 1, calibration will start over again when the output is switching from F1 to F2. F2

calibration begins based on the last calibration data, which is the calibration data obtained at t₀. If the

environment (for example, temperature) does not change much, the new calibration data will be similar to the old

data. As a result, the calibration time is minimal and therefore, the switching time will be short.

At t₂: Switch back to F1

Again, F1 calibration starts over and begins with the last calibration data as obtained at t₀. Calibration time is

again very short, as is the switching time.

At t₃: Switch again to F2

This time, the calibration begins with the calibration data obtained at t₁, which is the last calibration data.

At t₄: Switch back to F1

Calibration begins with the calibration data obtained at t₂, which is the last calibration data.

At t₅: Set new F1, F2 frequency

• Write to the relevant registers to set the new F1 and F2 frequency (for example, change the N-divider values)

• Initiate calibration by rewriting register R0

– Set F1F2_INIT=1. Both F1' and F2' will be calibrated

At t₆: Locked to F1'

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F1' and F2' calibration completed and their calibration data are ready.

At t₇: Release F1F2_INIT bit

This bit has to be reset to zero or otherwise both F1' and F2' will be calibrated every time they are toggling.

At t₈: F1' calibration data is updated

Since F1F2_INIT is located in register R0, when writing F1F2_INIT = 0 to the device, calibration is once again

triggered. However, only F1' will be recalibrated, the calibration data of F2' remains unchanged.

At t₉: Switch to F2'

F2' calibration begins with the calibration data obtained at t₆, which is the last calibration data. Calibration time is

again very short, as is the switching time.

At t₁₀: Switch back to F1'

F1' calibration starts over and begins with the last calibration data as obtained at t₈.

At t₁₁: Switch again to F2'

The calibration begins with the calibration data obtained at t₉, which is the last calibration data.

As illustrated above, register F1F2_INIT must be used properly in order to ensure that every F1-F2 switching

time is optimized.

8.1.5 FastLock With External VCO

Fastlock may be required in PLL mode where an external VCO with a narrow loop bandwidth is desired. The

LMX2571-EP adopts a new FastLock approach to support the very fast switching time requirement in PLL mode.

There are two control pins in the chip, FLout1 and FLout2. Each pin is used to control a SPST analog switch, S1

and S2. The loop filter value with or without FastLock is the same, except that with FastLock, one more C2 and

two SPST switches are needed.

Ordinary 2^nd

order loop filter

With FastLock

control switches

R2

C2

R2

C2a=C2b=C2

S1 S2

C2b

C2a

图8-7. FastLock With SPST Switches

When LMX2571-EP is locked to F1, FLout1 will close the switch S1. When the LMX2571-EP is locked to F2, the

user can program the F1F2_SEL bit in the R0 register to release the switch S1 while the FLout2 closes the S2.

Although S1 is released, the charge stored in C2a remains unchanged. Thus, when the output is switched back

to F1, the Vtune voltage is almost correct, no (or little) charging or discharging to C2a is required which speeds

up the switching time. For example, if Vtune for F1 and F2 are 1 V and 2 V, respectively, without FastLock, when

the switching frequency shifts from F1 to F2, C2 will have to be re-charged from 1 V to 2 V — this is a big

voltage jump. With FastLock, when S2 is closed, Vtune is almost equal to 2 V because C2b maintains the

charge. Only a tiny voltage jump (re-charge) is required to make it reach the final Vtune voltage.

图 8-8 and 图 8-9 compare the frequency switching time using different switching methods. In both cases, the

loop bandwidth is 4 kHz while f_PDis 28 MHz. 图 8-8 shows the switching time for a frequency jump from 430

MHz to 480 MHz with SPST switches. Frequency switching is toggled by the F1F2_SEL bit. Switching time is

approximately 1 ms. Frequency switching in 图 8-9 is done in the traditional way. That is, change the output

frequency by writing to the relevant registers such as N-divider values. In this case, because f_PDis very much

bigger than the loop bandwidth, cycle slipping jeopardizes the switching time to more than 20 ms.

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图8-8. F1F2 Switching With SPST Switches

图8-9. Change F1 Frequency Through SPI

Programming

8.1.6 OSCin Slew Rate

A phase-lock loop consists of a clean reference clock, a PLL, and a VCO. Each of these contributes to the total

phase noise. The LMX2571-EP is a high-performance PLL with integrated VCO. Both PLL noise and VCO noise

are very good. Typical PLL 1/f noise and noise floor are –124 dBc/Hz and –231 dBc/Hz, respectively. To get

the best possible phase-noise performance from the device the quality of the reference clock is very important

because it may add noise to the loop. First of all, the phase noise of the reference clock must be good so that

the final performance of the system is not degraded. Furthermore, using reference clock with a rather high slew

rate (such as a square wave) is highly preferred. Driving the device input with a lower slew rate clock will

degrade the device phase noise.

For a given frequency, a sine wave clock has the slowest slew rate, especially when the frequency is low. A

CMOS clock or differential clock have much faster slew rates and are recommended. 图 8-10 shows a phase-

noise comparison with different types of reference clocks. Output frequency is 480 MHz while the input clock

frequency is 26 MHz. As one can see, there is a 5-dB difference in phase noise when using a clipped sine wave

TCXO compared to a differential LVPECL clock. Note that the crystal option is not available in the LMX2571-EP,

but is included in the LMX2571 for comparison purposes.

-80

Crystal

TCXO

LVPECL

-90

-100

-110

-120

-130

-140

-150

-160

10³

10⁴

10⁵

10⁶

10⁷

Offset /Hz

图8-10. Phase Noise vs. Input Clock

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8.1.7 RF Output Buffer Power Control

Registers OUTBUF_TX_PWR_Fx and OUTBUF_RX_PWR_Fx are used to set the output power at the RFoutTx

and RFoutRx ports. 图 8-11 shows a typical output power vs. power control bit plot in synthesizer mode. VCO

frequency was 4800 MHz, and channel dividers were set to produce the shown output frequencies.

6

60

58

56

54

52

50

48

46

44

fout=1200MHz

fout=480MHz

fout=150MHz

3

Current, fout=480MHz

0

-3

-6

-9

-12

-15

-18

0

3

6

9

12

15

18

21

24

27

30

33

Power control bit

图8-11. Configurable RF Output Power

8.1.8 RF Output Buffer Type

Registers R35, OUTBUF_TX_TYPE, OUTBUF_RX_TYPE are used to configure the RF output buffer type

between open drain and push-pull. Push-pull is easy to use; all that is required is a DC-blocking capacitor at the

output. The output waveform is square wave and therefore, harmonics rich. Open-drain output provides an

option to reduce the harmonics using an LC resonant pullup network at its output. 表 8-5 summarizes an

example an open-drain vs. push-pull application.

表8-5. RF Output Buffer Type

BUFFER TYPE

OPEN-DRAIN

PUSH-PULL

Connection

Diagram

VccIO

39nH

100pF

2.7pF

RFoutTx

100pF

Output Power

470 MHz

480 MHz

2.8 dBm

490 MHz

2.8 dBm

470 MHz

–0.1 dBm

–30.4 dBc

–11.9 dBc

–28.5 dBc

–15.6 dBc

–29.5 dBc

480 MHz

0 dBm

490 MHz

0.1 dBm

f_o

2.7 dBm

–31 dBc

2f_o

3f_o

4f_o

5f_o

6f_o

–30.7 dBc

–17.9 dBc

–40.4 dBc

–17.8 dBc

–27.2 dBc

–30.5 dBc

–18.1 dBc

–41.6 dBc

–17.6 dBc

–28.5 dBc

–30.2 dBc

–12.1 dBc

–28.4 dBc

–15.6 dBc

–29.8 dBc

–30 dBc

–12.4 dBc

–28.1 dBc

–15.7 dBc

–29.3 dBc

–17.3 dBc

–39 dBc

–18.1 dBc

–27.6 dBc

Clearly, with a proper LC pull up in open-drain architecture, the 3^rdto 5^thharmonics could be reduced.

8.1.9 MULT Multiplier

The main purpose of the multiplier, MULT, in the R–divider is to push the in-band fractional spurs far away from

the carrier such that the spurs could be filtered out by the loop filter. In a fractional engine, the fractional spurs

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appear at a multiple of f_PD× N_frac. In cases where both f_PDand N_fracare small, the fractional spurs will appear

very close to the carrier. These kinds of spurs are called in-band spurs.

表8-6. MULT Application Example

USE CASE OSCin /M

Hz

PRE-DIVIDER

MULT

POST-DIVIDER f_PD/MHz VCO /MH N_integer

z

N_frac

SPURS /

MHz

I

19.2

1

5

1

4

19.2

24

460.8

461

24

19

0

0.2

5

II

0.0104167

0.2083333

III

461

In Case I, the VCO frequency is an integer multiple of the f_PD, so N_fracis zero and there are no spurs. However,

in Case II, the spur appears at an offset of 200 kHz. If this spur cannot be reduced by other typical spur-

reduction techniques such as dithering, user can enable the MULT to overcome this problem. If the MULT is

enabled as depicted in Case III, the spurs can be pushed to an offset of 5 MHz. In this case, the MULT together

with the Post-divider changes the phase detector to a little bit higher frequency. As a consequence, the spurs are

pushed further away from the carrier and are reduced more by the loop filter.

Another use case of MULT is to make higher phase-detector frequency. For example, if OSCin is 20 MHz, user

can set MULT to 5 to make f_PDgo to 100 MHz. As a result, the N-divider value will be reduced by 5 times;

therefore, the PLL phase noise is reduced. A wide loop bandwidth can then be used to reduce the VCO noise.

Consequently, the synthesizer close-in phase noise would be very good.

The MULT multiplier is an active device in nature, whenever it is enabled, it will add noise to the loop. For best

phase noise performance, TI recommends setting the MULT not greater than 6.

To use the MULT, beware of the restriction as indicated in the Electrical Characteristics table and 表7-21.

8.1.10 Integrated VCO

The integrated VCO is composed of 3 VCO cores. The approximate frequency ranges for the three VCO cores

with their gains is as follows:

表8-7. Approximate VCO Ranges and VCO Gain

VCO CORE

TYPICAL FREQUENCY RANGE (MHz)

TYPICAL VCO GAIN (MHz/V)

LOW

4200

4560

4920

HIGH

4700

5100

5520

LOW

46

MID

52

HIGH

61

VCOL

VCOM

VCOH

50

56

65

55

63

73

8.2 Typical Applications

8.2.1 Synthesizer Duplex Mode

In this example, the internal VCO is being used. The PLL will be put in fractional mode to support 4FSK direct

digital modulation using FSK PIN mode. Both frequency (F1, F2) switching as well as RF output port switching is

toggled by the F1F2_SEL bit. MULT multiplier in the R-divider will be used to reduce spurs.

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3.3V

0.1µF

XO

26MHz

Vcc3p3

OSCin

VccIO

VcpExt

Bypass

100pF

RFoutTx

100pF

RFoutRx

CPout

LMX2571-EP

VrefVCO

VregVCO

2.2µF

680

0.1µF

390pF

4.7nF

图8-12. Typical Synthesizer Duplex Mode Application Schematic

8.2.1.1 Design Requirements

OSCin frequency = 26 MHz, LVCMOS

RFoutTx frequency = 902 MHz

RFoutRx frequency = 928 MHz

Frequency switching time ≤500 µs

4FSK modulation on TX, baud rate = 20 kSPs

Frequency deviation = ±10 kHz and ±30 kHz

FSK error ≤1 %

Spurs ≤–72 dBc

Lock detect is required to indicate lock status

Output power < 1 dBm

8.2.1.2 Detailed Design Procedure

First of all, calculate all the frequencies in each functional block.

OSCin

26MHz

Pre-div

1

MULT

4

Post-div

1

PDF

104MHz

VCO

4510MHz

CHDIV1

5

CHDIV2

1

Output

902MHz

N

21.68269231

Prescaler

2

图8-13. F1 Frequency Plan

Assign F1 frequency to be 902 MHz. With CHDIV1 = 5 and CHDIV2 = 1, the total division is 5. As a result, the

VCO frequency will be 902 × 5 = 4510 MHz, which is within the VCO tuning range.

OSCin is 26 MHz, put Pre-divider = 1 to meet the MULT input frequency range requirement.

To meet the maximum MULT output frequency requirement, possible MULT values are 3 to 5. Play around the

allowable MULT values and Post-divider values to get the optimum phase noise and spurs performance.

Assuming MULT = 4 and Post-divider = 1 returns the best performance, then f_PD= 104 MHz.

N-divider = 21.68269231, that means N_integer= 21 while N_frac= 0.68269231. To use the direct digital modulation

feature, put fractional denominator, DEN = 0. The actual DEN value is, in fact, equal to 2²⁴= 16777216. So the

fractional numerator, NUM, is equal to N_frac× DEN = 11453676.

Use 方程式 4 and 方程式 6 to calculate the required FSK steps. For +10-kHz frequency deviation, the FSK step

value is equal to [10000 × 16777216 / (104 × 10⁶)] × (5 × 1 / 2) = 4033. For –10-kHz frequency deviation, the

FSK step value is equal to 2's complement of 4033 = 61502. Similarly, the FSK step values for ±30-kHz

frequency deviation are 12099 and 53436.

All the required configuration values for F2, 928 MHz can be calculated in the similar fashion and are

summarized as follows:

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表8-8. Frequency Plan Summary

CONFIGURATION PARAMETER

F1 (902 MHz)

F2 (928 MHz)

Pre-divider

MULT

1

4

Post-divider

PDF

1

104 MHz

4510 MHz

21.68269231

21

1

104 MHz

VCO

4640 MHz

N-divider

N_integer

22.30769231

22

DEN

0

NUM

11453676

5

5162220

CHDIV1

CHDIV2

FSK_DEV0

FSK_DEV1

FSK_DEV2

FSK_DEV3

5

1

4033

12099

61502

53436

Assume here that the base charge pump current = 1250 µA, CP Gain = 1x and 3^rdorder Delta Sigma Modulator

without dithering is adopted in both frequency sets. The register settings are summarized as follows:

表8-9. Register Settings Summary

CONFIGURATION

PARAMETERS

REGISTER BIT

COMMON SETTING

F1 SPECIFIC SETTING

F2 SPECIFIC SETTING

VCO calibration

FCAL_EN

1 = Enabled

Lock detect

SDO_LE_SEL

LD_EN

1 = Lock detect output

1 = Enabled

0 = Disabled

1 = 1x

Dithering

DITHERING

Charge pump gain

Base charge pump current

CP_GAIN

CP_IUP

8 = 1250 µA

520 = 20 µs

1 = Push pull

0 = Disabled

1 = Enabled

CP_IDN

MULT settling time

Output buffer type

MULT_WAIT

OUTBUF_RX_TYPE

OUTBUF_TX_TYPE

OUTBUF_AUTOMUTE

F1F2_MODE

PLL_R_PRE_F1

PLL_R_PRE_F2

MULT_F1

Output buffer auto mute

Enable F1 F2 initialization

Pre-divider

1

4

1

4

1

MULT multiplier

Post-divider

MULT_F2

PLL_R_F1

PLL_R_F2

FRAC_ORDER_F1

FRAC_ORDER_F2

PFD_DELAY_F1

PFD_DELAY_F2

CHDIV1_F1

3 = 3^rdorder

ΔΣmodulator order

PFD delay

3 = 3^rdorder

5 = 8 clock cycles

1 = Divide by 5

0 = Divide by 1

5 = 8 clock cycles

1 = Divide by 5

0 = Divide by 1

CHDIV1 divider

CHDIV2 divider

CHDIV1_F2

CHDIV2_F1

CHDIV2_F2

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表8-9. Register Settings Summary (continued)

CONFIGURATION

PARAMETERS

REGISTER BIT

COMMON SETTING

F1 SPECIFIC SETTING

F2 SPECIFIC SETTING

Internal 3^rdpole loop filter

LF_R3_F1

4 = 800 Ω

LF_R3_F2

4 = 800 Ω

Internal 4^thpole loop filter

LF_R4_F1

4 = 800 Ω

LF_R4_F2

4 = 800 Ω

Output port selection

Output power control

FSK mode

OUTBUF_TX_EN_F1

OUTBUF_RX_EN_F2

OUTBUF_TX_PWR_F1

OUTBUF_RX_PWR_F2

1 = TX port enabled

6

1 = RX port enabled

6

FSK_MODE_SEL1

FSK_MODE_SEL0

00 = FSK PIN mode

2 = 4FSK

FSK level

FSK_LEVEL

Enable FSK modulation

FSK deviation at 00

FSK deviation at 01

FSK deviation at 10

FSK deviation at 11

Fractional denominator

FSK_EN_F1

1 = Enabled

4033 = +10 kHz

12099 = +30 kHz

61502 = -10 kHz

53436 = -30 kHz

0

FSK_DEV0_F1

FSK_DEV1_F1

FSK_DEV2_F1

FSK_DEV3_F1

PLL_DEN_F1[23:16]

PLL_DEN_F1[15:0]

PLL_DEN_F2[23:16]

PLL_DEN_F2[15:0]

PLL_NUM_F1[23:16]

PLL_NUM_F1[15:0]

PLL_NUM_F2[23:16]

PLL_NUM_F2[15:0]

PLL_N_F1

0

Fractional numerator

174

50412

78

50412

N_integer

21

PLL_N_F2

22

Prescaler

PLL_N_PRE_F1

PLL_N_PRE_F2

0 = Divide by 2

8.2.1.3 Synthesizer Duplex Mode Application Curves

图8-14. F1 (TX) Phase Noise and Spurs

图8-15. F2 (RX) Phase Noise and Spurs

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图8-16. F1 (TX) to F2 (RX) Switching

图8-17. F2 (RX) to F1 (TX) Switching

图8-18. F1 to F2 Switching Time

图8-19. F2 to F1 Switching Time

.

图8-20. 4FSK Modulation

图8-21. 4FSK Modulation Quality

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8.2.2 PLL Duplex Mode

In this example, the internal VCO is bypassed, and the device is used to lock to an external VCO. TI’s dual

SPST analog switch, TS5A21366 is used to facilitate FastLock between two frequencies.

3.3V

5V

0.1µF

XO

16.8MHz

Vcc3p3

OSCin

VccIO

VcpExt

Bypass

100pF

RFoutTx

VCO

100pF

430-480MHz

Fin

LMX2571-EP

10

CPoutExt

100pF

50

VrefVCO

VregVCO

2.2µF

10

470nF 39nF 39nF

0.1µF

FLout1

FLout2

TS5A21366

4.7µF

图8-22. Typical PLL Duplex Mode Application Schematic

8.2.2.1 Design Requirements

OSCin frequency = 16.8 MHz, LVCMOS

F1 frequency = 430 MHz

F2 frequency = 480 MHz

Frequency switching time ≤1.5 ms within 100-Hz frequency tolerance

8.2.2.2 Detailed Design Procedure

Again, we need to figure out all the frequencies in each functional block first.

OSCin

16.8MHz

Pre-div

1

MULT

5

Post-div

3

PDF

28MHz

VCO

430MHz

CHDIV3

1

Output

430MHz

N

15.35714286

图8-23. Frequency Plan in PLL Duplex Mode

Follow the previous example to determine all the necessary configurations. 表 8-10 is the summary in this

example.

表8-10. PLL Duplex Mode Frequency Plan Summary

CONFIGURATION PARAMETER

F1 (430 MHz)

F2 (480 MHz)

Pre-divider

MULT

1

5

1

5

Post-divider

PDF

3

28 MHz

430 MHz

15.35714286

15

28 MHz

480 MHz

17.14285714

17

VCO

N-divider

N_integer

DEN

1234567

440917

1234567

176367

NUM

To enable external VCO operation, set the following bits:

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表8-11. PLL Duplex Mode Register Settings Summary

CONFIGURATION PARAMETER

REGISTER BITS

SETTING

Charge pump polarity

EXTVCO_CP_POL

0 = Positive

1 = 1x

External VCO charge pump gain

Base charge pump current

EXTVCO_CP_GAIN

EXTVCO_CP_IUP

8 = 1250 µA

1 = External VCO

EXTVCO_CP_IDN

Select PLL mode operation

CHDIV3 divider

EXTVCO_SEL_F1, EXTVCO_SEL_F2

EXTVCO_CHDIV_F1, EXTVCO_CHDIV_F2 0 = Bypass

Make sure that register R0, FCAL_EN is set so that FastLock is enabled.

The loop bandwidth had been design to be around 4 kHz, while phase margin is about 40 degrees.

8.2.2.3 PLL Duplex Mode Application Curves

图8-24. F1 to F2 Switching

图8-25. F2 to F1 Switching

图8-26. F1 to F2 Switching Time

图8-27. F2 to F1 Switching Time

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8.2.3 Synthesizer/PLL Duplex Mode

This example will demonstrate the device's capability in switching two frequencies using internal and external

VCO. VCO switching is toggled by F1F2_SEL bit. Direct digital FSK modulation is enabled in TX using FSK I2S

mode.

3.3V

5V

0.1µF

XO

19.2MHz

Vcc3p3

OSCin

VccIO

VcpExt

Bypass

100pF

RFoutRx

100pF

RFoutTx

VCO

430-480MHz

LMX2571-EP

Fin

VrefVCO

VregVCO

10

100pF

50

2.2µF

CPoutExt

0.1µF

10

470nF 39nF 39nF

4.7µF

图8-28. Typical Synthesizer/PLL Duplex Mode Application Schematic

8.2.3.1 Design Requirements

OSCin frequency = 19.2 MHz, LVCMOS

RFoutRX frequency = 440 MHz, external VCO = F1

RFoutTx frequency = 540 MHz, internal VCO = F2

Frequency switching time ≤1.5 ms within 100-Hz frequency tolerance

Arbitrary FSK modulation to simulate analog FM modulation (10 times and 20 times over-sampling rate)

FM modulation frequency = 1 kHz

Frequency deviation = ±2000 Hz

Spurs ≤–72 dBc

8.2.3.2 Detailed Design Procedure

Frequency plans in TX and RX paths are as follows:

OSCin

19.2MHz

Pre-div

1

MULT

1

Post-div

1

PDF

19.2MHz

VCO

440MHz

CHDIV3

1

Output

440MHz

N

22.91666687

OSCin

19.2MHz

Pre-div

1

MULT

5

Post-div

1

PDF

96MHz

VCO

5400MHz

CHDIV1

5

CHDIV2

2

Output

540MHz

N

28.125

Prescaler

2

图8-29. TX and RX Frequency Plans

Follow the previous examples to determine all the necessary configurations. To enable FSK I2S mode, set

FSK_MODE_SEL1=1

FSK_MODE_SEL=0

FSK_EN_F2=1

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8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves

图8-30. External VCO to Internal VCO Switching

图8-31. Internal VCO to External VCO Switching

图8-32. External VCO to Internal VCO Switching

图8-33. Internal VCO to External VCO Switching

Time

图8-34. Simulated FM Modulation (10 Times Over- 图8-35. Simulated FM Modulation (20 Times Over-

Sampling)

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8.3 Do's and Don'ts

INCORRECT

CORRECT

VregVCO

100nF

2.2µF

VregVCO DECOUPLING

VcpExt SUPPLY

DAP PIN

3.3V or 5V: Synthesizer mode

5V: PLL mode

VcpExt

DAP

VcpExt

DAP

图8-36. Do's and Don'ts

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9 Power Supply Recommendations

TI recommends placing a 100-nF capacitor close to each of the power supply pins. If fractional spurs are a large

concern, using a ferrite bead to each of these power supply pins may reduce spurs to a small degree.

VcpExt is the power supply pin for the 5-V charge pump. In PLL mode, the 5-V charge pump is active and a 5 V

is required at VcpExt pin. In synthesizer mode, although the 5-V charge pump is not active, either a 3.3-V

or 5-V supply is still needed at this pin.

Because LMX2571-EP has integrated LDOs, the requirement to external power supply is relaxed. In addition to

LDO, LMX2571-EP is able to operate with DC-DC converter. The switching noise from the DC-DC converter

would not affect performance of the LMX2571-EP. 表9-1 lists some of the suggested DC-DC converters.

表9-1. Recommended DC-DC Converters

PART NUMBER

TPS560200

TPS62050

TOPOLOGY

Buck

V_IN

V_OUT

I_OUT

SWITCHING FREQUENCY

600 kHz

4.5 V to 17 V

2.7 V to 10 V

3 V to 17 V

4.5 V to 17 V

2.5 V to 5.5 V

0.8 V to 6.5 V

0.7 V to 6 V

0.9 V to 6 V

0.76 V to 7 V

2.5 V to 5.5 V

500 mA

Buck

800 mA

1 MHz

TPS62160

Buck

1000 mA

2000 mA

500 mA to 1 A

2.25 MHz

TPS562200

TPS63050

Buck

650 kHz

Buck Boost

2.5 MHz

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10 Layout

10.1 Layout Guidelines

See EVM instructions (SNAU182) for details. In general, the layout guidelines are similar to most other PLL

devices. The followings are some guidelines specific to the device.

• It may be beneficial to separate main ground and OSCin ground, crosstalk spurs might be reduced.

• Don't route any traces that carry switching signal close to the charge pump traces and external VCO.

• When using FSK I2S mode on this device, take care to avoid coupling between the I2S clock and any of the

PLL circuit.

10.2 Layout Example

图10-1. Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

Texas Instruments has three main tools to assist with this product. The Clock Tree Architect assists as a solution

finder, the PLLatinum Sim tool is used to design and simulate the loop filter (including filter design, bode plot,

phase noise, spurs, and lock time), and the TICS Pro software is used to program the device. All these tools are

available at www.ti.com.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, TS5A21366 0.75-ΩDual SPST Analog Switch With 1.8-V Compatible Input Logic data

sheet

• Texas Instruments, TPS560200 4.5-V to 17-V Input, 500-mA Synchronous Step-Down SWIFT™ Converter

data sheet

• Texas Instruments, TPS62050 800-mA Synchronous Step-Down Converter data sheet

• Texas Instruments, TPS62160 3-V to 17-V, 1-A Step-Down Converters With DCS-Control data sheet

• Texas Instruments, TPS562200 4.5-V to 17-V Input, 2-A Synchronous Step-Down Voltage Regulator in

SOT-23 data sheet

• Texas Instruments, TPS63050 Tiny Single Inductor Buck Boost Converter data sheet

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

PLLatinum^™is a trademark of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

RHH 36

6 x 6, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225440/A

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PACKAGE OUTLINE

VQFN - 1 mm max height

RHH0036G

PLASTIC QUAD FLATPACK-NO LEAD

6.1

5.9

A

B

PIN 1 INDEX AREA

6.1

5.9

C

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

4.7

4.5

SQ

2X 4

(0.1) TYP

10

18

32X 0.5

9

19

37

SYMM

2X

4

27

1

0.34

0.14

0.1

0.05

36X

PIN 1 ID

(OPTIONAL)

C A B

36

28

SYMM

C

0.5

0.3

36X

4226455/A 12/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RHH0036G

PLASTIC QUAD FLATPACK-NO LEAD

(5.8)

(SQ 4.6)

28

36

36X (0.6)

36X (0.24)

1

27

32X (0.5)

SYMM

37

(5.8)

(1.16)

(0.89)

9

19

(R0.05) TYP

18

10

(Ø 0.2)VIA

TYP

(1.16)

(0.89)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 14X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

SOLDERMASK

OPENING

EXPOSED METAL

NON- SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226455/A 12/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271)

.

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RHH0036G

PLASTIC QUAD FLATPACK-NO LEAD

(5.8)

16X (SQ 0.96)

28

36

36X (0.6)

36X (0.24)

1

27

32X (0.5)

37

(0.58)

(5.8)

SYMM

(1.16)

19

9

(R0.05) TYP

METAL TYP

18

10

(0.58)

SYMM

(1.16)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

70% PRINTED COVERAGE BY AREA

SCALE: 14X

4226455/A 12/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	LMX2571SRHHTEP
厂家：	TEXAS INSTRUMENTS
描述：	具有 FSK 调制功能的增强型 1.34GHz、低功耗、极端温度 RF 合成器 \| RHH \| 36 \| -55 to 125
文件：	总67页 (文件大小：3807K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMX2571SRHHTEP [TI]

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