LMX2615-SP [TI]
具有相位同步功能且 JESD204B 支持的航天级 40MHz 至 15GHz 宽带合成器;型号: | LMX2615-SP |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有相位同步功能且 JESD204B 支持的航天级 40MHz 至 15GHz 宽带合成器 |
文件: | 总71页 (文件大小:1448K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
具有相位同步功能且支持 JESD204B 的 LMX2615-SP 航空级 40MHz 至
15GHz 宽带合成器
1 特性
2 应用
1
•
辐射规范
•
•
•
•
航空通信
单粒子闩锁 > 120MeV-cm2/mg
天基雷达系统
–
–
相控阵天线和波束形成
电离辐射总剂量达 100 krad(Si)
高速数据转换器时钟(支持 JESD204B)
•
•
40MHz 至 15GHz 输出频率
在 100KHz 偏频和 15GHz 载波的情况下具有
-110dBc/Hz 的相位噪声
3 说明
LMX2615-SP 是一款集成有电压控制振荡器 (VCO) 和
稳压器的高性能宽带锁相环 (PLL),在无倍频器的情
况,可输出 40MHz 至 15GHz 范围内的任意频率,从
而无需使用 ½ 谐波滤波器。此器件上的 VCO 涵盖了
整个倍频区间,因而频率覆盖度可完全低至 40MHz。
品质因数为 -236dBc/Hz 的高性能 PLL 和高相位检测
器频率可实现非常低的带内噪声和集成抖动。
•
45在 8 GHz 时,具有 45fs RMS 抖动(100Hz 至
100MHz)
•
•
可编程输出功率
PLL 主要规格
–
–
–
品质因数:–236dBc/Hz
标称 1/f 噪声:–129dBc/Hz
相位检测器频率高达 200MHz
•
•
•
•
•
•
•
跨多个设备实现输出相位同步
支持具有 9ps 分辨率可编程延迟的 SYSREF
3.3V 单电源运行
LMX2615-SP 允许用户同步多个器件实例的输出。这
意味着我们可从任意应用情形下的器件中获得确定性相
位,包括采用分数引擎或启用输出分频器的情形。该器
件还可支持生成或重复 SYSREF(符合 JESD204B 标
准),使其成为高速数据转换器的理想低噪声时钟源。
71 种预选引脚模式
11 x 11 mm² 64 引线 CQFP 陶瓷封装
工作温度范围为 -55°C 至 +125°C
由 PLLatinum Sim 设计工具提供支持
该器件采用德州仪器 (TI) 先进的 BiCMOS 工艺制造,
可提供 64 引线 CQFP 陶瓷封装。
器件信息
器件编号
等级
封装
LMX2615W-MPR 非飞行用工程样片
LMX2615W-MLS 飞行用生产器件
64 引线 CQFP
64 引线 CQFP
简化原理图
External loop filter
Vtune
CPout
OSCin
OSCinP
Phase
Detector
RFoutAP
Vcc
Buffer
MUX
MUX
Input
signal
OSCin
Douber
Pre-R
Divider
Post-R
Divider
Charge
Pump
RFoutAM
Channel
Divider
f
OSCinM
RFoutBM
Vcc
Sigma-Delta
Modulator
RFoutBP
SYSREF
Synchronization
and Delay
Output
Buffer
CSB)
SCK
SDI
Serial Interface
Control
N Divider
MUXout
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNAS739
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
目录
7.6 Register Maps......................................................... 38
Application and Implementation ........................ 56
8.1 Application Information............................................ 56
8.2 Typical Application .................................................. 60
Power Supply Recommendations...................... 62
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Timing Requirements.............................................. 10
6.7 Typical Characteristics............................................ 12
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 36
7.5 Programming........................................................... 37
8
9
10 Layout................................................................... 62
10.1 Layout Guidelines ................................................. 62
10.2 Layout Example .................................................... 63
10.3 Footprint Example on PCB Layout........................ 64
10.4 Radiation Environments ....................................... 64
11 器件和文档支持 ..................................................... 65
11.1 器件支持................................................................ 65
11.2 文档支持................................................................ 65
11.3 商标....................................................................... 65
11.4 静电放电警告......................................................... 65
11.5 术语表 ................................................................... 65
12 机械、封装和可订购信息....................................... 65
12.1 工程样片 ............................................................... 65
12.2 封装机械信息......................................................... 66
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision B (June 2018) to Revision C
Page
•
•
•
•
•
•
•
•
将器件状态从“预告信息”更改成了“生产数据” ......................................................................................................................... 1
已更改 output power, VCO Calibration time, and harmonics. ............................................................................................... 7
已添加 Typical Performance Characteristics ....................................................................................................................... 12
已更改 Updated Max Frequencies for higher divides to be based on 11.5 GHz, not 15.2 GHz ......................................... 24
已添加 FS7 Pin description .................................................................................................................................................. 34
已添加 Typical Application.................................................................................................................................................... 60
已添加 more details including capacitor requirements for Vtune pin.................................................................................... 62
已添加 Layout Example ........................................................................................................................................................ 63
Changes from Revision A (June 2018) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
已更改 将典型抖动更改为 45 fs .............................................................................................................................................. 1
Added Max Digital pin and OSCin Voltage............................................................................................................................. 7
Changed Typical VCO Gain ................................................................................................................................................... 9
已更改 readback timing diagram and added tCD. ............................................................................................................... 11
已更改 VCO Frequency range to 7600 to 15200 MHz ........................................................................................................ 17
已更改 VCO calibration updated to new VCO range of 7600 to 15200 MHz ...................................................................... 21
已更改 Ordering of VCOs in calibration time table .............................................................................................................. 22
已添加 Watchdog feature description................................................................................................................................... 22
已更改 RECAL feature description ...................................................................................................................................... 23
已更改 VCO Gain table ........................................................................................................................................................ 23
已更改 Channel divider description and picture .................................................................................................................. 23
已更改 Channel Divider usage for VCO frequency ............................................................................................................. 23
已更改 5 GHz, not 5 MHz .................................................................................................................................................... 24
2
版权 © 2018, Texas Instruments Incorporated
LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
•
•
•
•
•
•
•
已添加 information on what to do with unused pins ............................................................................................................ 25
已更改 Case of Fosc%Fout=0 is now category 2 ................................................................................................................ 28
已更改 Recommendation for CAL and RECAL_EN ............................................................................................................ 34
已更改 RECAL_EN to CAL pin ............................................................................................................................................ 34
已更改 pin mode 17 to not be used...................................................................................................................................... 34
已添加 10 ms delay to recommended initial power up sequence and more details on what registers to program. ............ 37
已添加 Register Map Table ................................................................................................................................................. 38
Changes from Original (May 2017) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed the //ESD Ratings// table ....................................................................................................................................... 7
Changed ambient temperature parameter to case temperature in the //Recommended Operating Conditions// table......... 7
Deleted the junction temperature parameter from the //Recommended Operating Conditions// table .................................. 7
Changed the supply voltage minimum value from: 3.15 V to: 3.2 V ...................................................................................... 8
Changed the test conditions to the supply current parameter................................................................................................ 8
Changed the power on reset current typical value for the RESET=1 test condition from: 270 mA to: 289 mA..................... 8
Changed the power on reset current typical value for the POWERDOWN=1 test condition from: 5 mA to: 6 mA................ 8
Changed the test conditions and added minimum values to the reference input voltage parameter .................................... 8
Added phase detector frequency test conditions ................................................................................................................... 8
Changed the text toclarify that output power assumes that load is matched and losses are de-embedded......................... 8
Changed VCO phase noise test conditions and typical values.............................................................................................. 9
Changed the Assisting the VCO Calibration Speed and the MINIMUM VCO_SEL for Partial Assist tables....................... 22
已添加 Typical Calibration times for fOSC = fPD = 100 MHz based on VCO_SEL table ....................................................... 22
Changed the MASH_SEED considerations in the Phase Adjust section............................................................................. 29
Copyright © 2018, Texas Instruments Incorporated
3
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
5 Pin Configuration and Functions
64-Pin CQFP
Top View
1
2
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
NC
3
FS0
NC
RECAL_EN
VrefVCO2
SysRefReq
VbiasVCO2
VccVCO2
GND
4
FS1
5
CAL
6
GND
VbiasVCO
GND
SYNC
GND
VccDIG
OSCinP
OSCinM
VregIN
FS2
7
8
DAP
(Die Attach Pad)
9
10
11
12
13
14
15
16
CSB
GND
RFoutAP
RFoutAM
GND
VccBUF
NC
FS3
4
Copyright © 2018, Texas Instruments Incorporated
LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
Pin Functions
CQFP Package (QFN) Pin Functions
PIN
I/O
TYPE
DESCRIPTION
NO.
1
NAME
NC
—
—
I
—
—
—
—
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
Parallel pin control. This is the LSB.
2
NC
3
FS0
FS1
4
I
Parallel pin control
Chip enable. In Pin Mode (not SPI Mode), rising edges presented to this pin activate
the VCO calibration.
5
CAL
I
—
6
GND
VbiasVCO
GND
—
—
—
I
—
—
—
—
—
—
Ground
7
VCO bias. Requires connecting 10uF capacitor to ground. Place close to pin.
8
Ground
9
SYNC
Phase synchronization input pin.
10
11
GND
—
—
Ground
VccDIG
Digital supply. Recommend connecting 0.1uF capacitor to ground.
Complimentary Reference input clock pins. High input impedance. Requires connecting
series capacitor (0.1 uF recommended).
12
13
14
OSCinP
OSCinM
VregIN
I
I
—
—
—
Complimentary pin to OSCinP.
Input reference path regulator decoupling. Requires connecting 1uF capacitor to
ground. Place close to pin.
—
15
16
17
18
19
FS2
FS3
FS4
FS5
FS6
I
I
I
I
I
—
—
—
—
—
Parallel pin control
Parallel pin control
Parallel pin control
Parallel pin control
Parallel pin control
Parallel pin control. This is the MSB. Controls output state in pin mode. When this pin
is low, only RFoutA is active, otherwise both outputs are active.
20
21
22
FS7
I
—
—
—
VccCP
CPout
—
O
Charge pump supply. Recommend connecting 0.1uF capacitor to ground.
Charge pump output. Recommend connecting C1 of loop filter close to charge pump
pin.
23
24
25
26
27
28
29
GND
GND
—
—
—
I
Ground
Ground
—
Ground
Ground
VccMASH
SCK
Digital supply. Recommend connecting 0.1uF and 10uF capacitor to ground.
SPI input clock. High impedance CMOS input. 1.8 – 3.3V logic.
SPI input data. High impedance CMOS input. 1.8 – 3.3V logic.
Ground
—
SDI
I
—
GND
—
O
Ground
—
RFoutBM
Complementary pin for RFoutBP
Differential output B Pair. Requires connecting a 50-Ω resistor pull-up to Vcc as close
as possible to pin. Can be used as a synthesizer output or SYSREF output.
30
RFoutBP
O
—
31
32
33
34
35
36
GND
MUXout
NC
—
O
Ground
—
Ground
Multiplexed output pin. Can output: lock detect, SPI readback and diagnostics.
No connection. Leave Unconnected
—
—
—
O
—
VccBUF
GND
—
Output buffer supply. Requires connecting 0.1uF capacitor to ground.
Ground
Ground
—
RFoutAM
Complementary pin for RFoutAP
Differential output B Pair. Requires connecting a 50-Ω resistor pull-up to Vcc as close
as possible to pin.
37
RFoutAP
O
—
38
39
40
GND
CSB
GND
—
I
Ground
—
Ground
SPI chip select bar. High impedance CMOS input. 1.8 – 3.3V logic.
Ground
—
Ground
Copyright © 2018, Texas Instruments Incorporated
5
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
CQFP Package (QFN) Pin Functions (continued)
PIN
NAME
I/O
TYPE
DESCRIPTION
NO.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VccVCO2
VbiasVCO2
SysRefReq
VrefVCO2
RECAL_EN
NC
—
—
I
—
—
VCO supply. Recommend connecting 0.1uF and 10uF capacitor to ground.
VCO bias. Requires connecting 1uF capacitor to ground.
SYSREF request input for JESD204B support.
VCO supply reference. Requires connecting 10uF capacitor to ground.
Enables the automatic recalibration feature.
—
—
I
—
—
—
—
—
—
—
—
—
—
—
I
—
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
Ground
NC
—
NC
—
NC
—
NC
—
GND
Ground
—
NC
No connection. Pin may be grounded or left unconnected.
VCO Varactor bias. Requires connecting 10uF capacitor to ground.
Ground
VbiasVARAC
GND
—
Ground
—
Vtune
VCO tuning voltage input.
VrefVCO
VccVCO
NC
—
—
—
—
—
—
—
—
—
—
VCO supply reference. Requires connecting 10uF capacitor to ground.
VCO supply. Recommend connecting 0.1uF and 10uF capacitor to ground.
No connection. Leave Unconnected
—
—
VregVCO
GND
—
VCO regulator node. Requires connecting 1uF capacitor to ground.
Ground
Ground
Ground
—
GND
Ground
NC
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
No connection. Pin may be grounded or left unconnected.
NC
—
NC
—
6
版权 © 2018, Texas Instruments Incorporated
LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
-0.3
MAX
3.6
UNIT
V
VCC
VDIG
|VOSCin
TJ
Power supply voltage(1)
Digital pin voltage (FS0-FS7,SYNC, SysRefReq,RECAL_EN,CAL)
Differential AC voltage between OSCinP and OSCinN
Junction temperature
VCC+0.3
2.1
V
|
Vpp
°C
–55
–65
150
Tstg
Storage temperature
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V
(1) JEDEC document JEP155 states that 500 V HBM allows safemanufacturing with a standard ESD control process. Manufacturing with
less than 500 V HBM ispossible with the necessary precautions. Pins listed as ±XXX V may actually have higherperformance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.2
NOM
3.3
MAX
3.45
125
UNIT
V
VCC
Tc
Power supply voltage
Case temperature
–55
25
°C
6.4 Thermal Information
CQFP
THERMAL METRIC(1)
UNIT
64 PINS
22.7
7.3
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(2)
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
7.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.2
ψJB
7.4
RθJC(bot)
1.0
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
(2) DAP
Copyright © 2018, Texas Instruments Incorporated
7
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
6.5 Electrical Characteristics
3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤+125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
Supply voltage
3.2
3.3
3.45
V
OUTA_PD = 0, OUTB_PD = 1
OUTA_MUX = OUTB_MUX = 1
OUTA_PWR = 31, CPG=7
fOSC= fPD = 100 MHz, fVCO = fOUT = 14.5 GHz
Supply current
360
ICC
mA
Power on reset current
Power down current
RESET=1
289
6
POWERDOWN=1
OUTPUT CHARACTERISTICS
fOUT = 8 GHz
fOUT = 15 GHz
6
4
50-Ω resistor pullup
OUTx_PWR = 31
pOUT
Single-ended output power(1) (2)
dBm
MHz
INPUT SIGNAL PATH
OSC_2X = 0
OSC_2X = 1
5
5
1000
200
2
fOSCin
Reference input frequency
fOSCin≥ 20 MHz
0.4
Single-ended AC
coupled sine wave input 10 MHz ≤ fOSCin <20
with complementary side MHz
AC coupled to ground
5 MHz ≤ fOSCin <10
with 50 Ω resistor
MHz
0.8
1.6
2
2
vOSCin
Reference input voltage
Vpp
PHASE DETECTOR AND CHARGE PUMP
MASH_ORDER=0
MASH_ORDER>0
CPG = 0
0.125
5
250
200
15
fPD
Phase detector frequency(3)
Charge-pump leakage current
MHz
nA
CPG = 4
3
6
CPG = 1
Effective charge pump current.
This is the sum of the up and
down currents
ICPout
CPG = 5
9
mA
CPG = 3
12
CPG = 7
15
PNPLL_1/f Normalized PLL 1/f noise
–129
dBc/Hz
dBc/Hz
fPD = 100 MHz, fVCO = 12 GHz(4)
PNPLL_FO
Normalized PLL noise floor
–236
M
(1) Single ended output power obtained after de-embeddingmicrostrip trace losses and matching with a manual tuner. Unused port
terminated to 50-Ωload.
(2) Output power, spurs, and harmonics can vary based on boardlayout and components.
(3) For lower VCO frequencies, the N divider minimum value canlimit the phase-detector frequency.
(4) The PLL noise contribution is measured using a clean referenceand a wide loop bandwidth and is composed into flicker and flat
components. PLL_flat = PLL_FOM + 20× log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_1/f + 20 × log(Fvco / 1GHz) –
10× log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculatedas PLL_Noise = 10 × log(10
PLL_Flat / 10 + 10 PLL_flicker /10
)
8
Copyright © 2018, Texas Instruments Incorporated
LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
Electrical Characteristics (continued)
3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤+125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCO CHARACTERISTICS
100 kHz
1 MHz
-105
-127
-148
-155
-103
-125
-146
-153
-103
-125
-147
-158
-101
-124
-146
-158
-102
-126
-147
-156
-101
-124
-146
-160
-101
-124
-146
-157
VCO1
fVCO = 8.1 GHz
10 MHz
100 MHz
100 kHz
1 MHz
VCO2
fVCO = 9.3 GHz
10 MHz
100 MHz
100 kHz
1 MHz
VCO3
fVCO = 10.4 GHz
10 MHz
100 MHz
100 kHz
1 MHz
VCO4
fVCO = 11.4 GHz
PNVCO
VCO phase noise
dBc/Hz
10 MHz
100 MHz
100 kHz
1 MHz
VCO5
fVCO = 12.5 GHz
10 MHz
100 MHz
100 kHz
1 MHz
VCO6
fVCO = 13.6 GHz
10 MHz
100 MHz
100 kHz
1 MHz
VCO7
fVCO = 14.7 GHz
10 MHz
100 MHz
VCO calibration speed, switch
across the entire frequency
tVCOCAL
band, fOSC = 100 MHz, fPD
100 MHz, fVCO = 7.9
GHz,VCO_SEL=7
=
Partial assist
650
µs
8.1 GHz
94
106
122
148
185
202
233
9.3 GHz
10.4 GHz
11.4 GHz
12.5 GHz
13.6 GHz
14.7 GHz
KVCO
VCO Gain
MHz/V
Allowable temperature drift
|ΔTCL
|
125
°C
when VCO is not re-calibrated
VCO second harmonic
VCO third haromonic
H2
H3
fVCO = 8 GHz, divider disabled
fVCO = 8 GHz, divider disabled
–30
-25
dBc
DIGITAL INTERFACE
Applies to SCLK, SDI, CSB, CAL, RECAL_EN, MUXout, SYNC, SysRefReq
VIH High-level input voltage
1.6
V
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Electrical Characteristics (continued)
3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TC ≤+125°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
0.4
TYP
MAX
UNIT
V
VIL
IIH
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
High-level output current
–100
100
100
µA
µA
V
IIL
–100
VOH
VOL
Load current = –5 mA
Load current = 5 mA
VCC – 0.6
MUXout pin
0.6
V
6.6 Timing Requirements
(3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TA ≤+125°C, except as specified. Nominal values are at VCC = 3.3 V,TA = 25°C)
MIN
NOM
MAX
UNIT
DIGITAL INTERFACE WRITE SPECIFICATIONS
fSPIWrite
tCE
SPI write speed
2
MHz
ns
Clock to enable low time
Data to clock setup time
Data to clock hold time
Clock pulse width high
Clock pulse width low
Enable to clock setup time
Enable pulse width high
50
50
tCS
ns
tCH
50
ns
tCWH
tCWL
tCES
tEWH
See 图 1
200
200
100
100
ns
ns
ns
ns
10
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Timing Requirements (continued)
(3.2 V ≤ VCC ≤ 3.45 V, –55°C ≤ TA ≤+125°C, except as specified. Nominal values are at VCC = 3.3 V,TA = 25°C)
MIN
NOM
MAX
UNIT
DIGITAL INTERFACE READBACK SPECIFICATIONS
fSPIReadb
SPI readback speed
ack
See 图 2
2
MHz
tCE
Clock to enable low time
Clock to data wait time
See 图 2
See 图 2
See 图 2
See 图 2
See 图 2
See 图 2
See 图 2
50
50
ns
ns
ns
ns
ns
ns
ns
tCS
tCWH
tCWL
tCES
tEWH
tCD
Clock pulse width high
200
200
50
Clock pulse width low
Enable to clock setup time
Enable pulse width high
Falling clock edge to data wait time
100
200
MSB
LSB
D0
SDI
R/W
A5
A0
D15
D14
SDK
CSB
t
t
CWH
CS
t
CE
t
CH
t
CES
t
CWL
t
EWH
图 1. Serial Data Input Timing Diagram
There are several other considerations for writing on the SPI:
•
•
•
•
•
The R/W bit must be set to 0.
The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.
The CSB transition from high to low must occur when SCK is low.
When SCK and SDI lines are shared between devices, TI recommends hold the CSB line high on the device
that is not to be clocked.
LSB
MUXout
RB15
RB14
RB0
MSB
R/W
SDI
A6
A5
A0
SCK
CSB
t
CE
t
CES
t
EWH
图 2. Serial Data Readback Timing Diagram
There are several other considerations for SPI readback:
•
•
•
The R/W bit must be set to 1.
The MUXout pin will always be low for the address portion of the transaction.
The data on MUXout becomes available momentarily after the falling edge of SCK and therefore should be
read back on the rising edge of SCK.
•
The data portion of the transition on the SDI line is always ignored.
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6.7 Typical Characteristics
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-60
-60
-70
100 Hz -90.0 dBc/Hz 1 MHz -123.5 dBc/Hz
100 Hz -88.8 dBc/Hz 1 MHz -121.9 dBc/Hz
-70
-80
1 kHz -96.5 dBc/Hz 10 MHz -147.6 dBc/Hz
10 kHz -106.8 dBc/Hz 20 MHz -151.9 dBc/Hz
100 kHz -113.6 dBc/Hz 95 MHz -154.1 dBc/Hz
1 kHz -95.1 dBc/Hz 10 MHz -146.0 dBc/Hz
10 kHz -104.9 dBc/Hz 20 MHz -150.9 dBc/Hz
100 kHz -111.4 dBc/Hz 95 MHz -154.0 dBc/Hz
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
8.1 GHz
1 kHz
4.9 dBm
9.3 GHz
1 kHz
3.6 dBm
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Offset (Hz)
Offset (Hz)
tc_P
tc_P
fOSC = 100 MHz
fPD = 200 MHz
Jitter = 53.0 fs (100 Hz - 100 MHz)
fOSC = 100 MHz
fPD = 200 MHz
Jitter = 56.7 fs (100 Hz - 100 MHz)
图 3. Closed Loop Phase Noise at 8.1 GHz
图 4. Closed Loop Phase Noise at 9.3 GHz
-60
-70
-60
-70
100 Hz -87.7 dBc/Hz 1 MHz -120.8 dBc/Hz
1 kHz -94.2 dBc/Hz 10 MHz -145.1 dBc/Hz
10 kHz -103.3 dBc/Hz 20 MHz -146.0 dBc/Hz
100 kHz -110.4 dBc/Hz 95 MHz -154.8 dBc/Hz
100 Hz -86.9 dBc/Hz 1 MHz -119.7 dBc/Hz
1 kHz -93.2 dBc/Hz 10 MHz -144.4 dBc/Hz
10 kHz -102.8 dBc/Hz 20 MHz -149.9 dBc/Hz
100 kHz -109.7 dBc/Hz 95 MHz -157.0 dBc/Hz
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
10.4 GHz
1 kHz
4.9 dBm
10.4 GHz
1 kHz
2.1 dBm
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Offset (Hz)
Offset (Hz)
tc_P
gtcr_aPp
fOSC = 100 MHz
fPD = 200 MHz
Jitter = 57.6 fs (100 Hz - 100 MHz)
fOSC = 100 MHz
fPD = 200 MHz
Jitter = 57.8 fs (100 Hz - 100 MHz)
图 5. Closed Loop Phase Noise at 10.4 GHz
图 6. Closed Loop Phase Noise at 11.4 GHz
-60
-70
-60
-70
100 Hz -86.5 dBc/Hz 1 MHz -115.9 dBc/Hz
1 kHz -93.2 dBc/Hz 10 MHz -142.6 dBc/Hz
10 kHz -102.4 dBc/Hz 20 MHz -148.7 dBc/Hz
100 kHz -109.3 dBc/Hz 95 MHz -155.2 dBc/Hz
100 Hz -85.5 dBc/Hz 1 MHz -115.4 dBc/Hz
1 kHz -92.3 dBc/Hz 10 MHz -141.6 dBc/Hz
10 kHz -100.9 dBc/Hz 20 MHz -147.7 dBc/Hz
100 kHz -108.0 dBc/Hz 95 MHz -154.3 dBc/Hz
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-160
-100
-110
-120
-130
-140
-150
-160
12.5 GHz
1 kHz
0.0 dBm
13.6 GHz
1 kHz
-1.2 dBm
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Offset (Hz)
Offset (Hz)
tc_P
tc_P
fOSC = 100 MHz
fPD = 200 MHz
Jitter = 62.4 fs (100 Hz - 100 MHz)
fOSC = 100 MHz
fPD = 200 MHz
fVCO = 14 GHz
fOUT = 14 GHz/2 = 3.5 GHz
Jitter = 64.2 fs (100 Hz - 100 MHz)
图 7. Closed Loop Phase Noise at 12.5 GHz
图 8. Closed Loop Phase Noise at 13.6 GHz
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Typical Characteristics (接下页)
-60
100 Hz -84.9 dBc/Hz 1 MHz -114.3 dBc/Hz
-70
1 kHz -91.6 dBc/Hz 10 MHz -140.4 dBc/Hz
10 kHz -100.8 dBc/Hz 20 MHz -146.7 dBc/Hz
100 kHz -107.2 dBc/Hz 95 MHz -154.2 dBc/Hz
-80
-90
-100
-110
-120
-130
-140
-150
-160
14.7 GHz
1 kHz
-3.6 dBm
100 Hz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Offset (Hz)
tc_P
fOSC = 100 MHz
fPD = 200 MHz
Jitter = 65.5 fs (100 Hz - 100 MHz)
图 9. Closed Loop Phase Noise at 14.7 GHz
-90
-95
8
Flicker Degrade
FOM Degrade
Measurement
Flicker Noise
Flat Noise
Modeled Phase Noise
7
6
-100
-105
-110
-115
-120
-125
-130
-135
5
4
3
2
1
0
-1
100
fOSC = 200 MHz
图 11. PLL Phase Noise Metrics vs. Fosc Slew Rate
200
300
400
500
600
700
800
100 Hz
1 kHz
10 kHz
Offset (Hz)
100 kHz
1 MHz
Slew Rate (v/ms)
tc_P
tc_P
fVCO = 14.8 GHz
fVCO = 10 GHz
FOM = -237.5
fPD = 200 MHz
Flicker = -130.5
图 10. Calculation of PLL Noise Metrics
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Typical Characteristics (接下页)
7.5
6
12
10.5
9
Ta=-55C
Ta=25C
Ta=85C
Ta=125C
TA=-55C, TLock=25C
TA=-55C, TLock=-55C
TA=125C, TLock=25C
TA=125C, TLock=125C
4.5
3
7.5
6
4.5
3
1.5
0
1.5
0
-1.5
-3
-1.5
-3
-4.5
-6
-4.5
-6
-7.5
-7.5
-9
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
Offset (Hz)
Offset (Hz)
tc_d
tc_d
fVCO = 10 GHz, Narrow Loop
Bandwidth (<100 Hz)
VCO Re-Calibrated at Final
Frequency
fVCO = 10 GHz,
Narrow Loop
Bandwidth (<100
Hz)
VCO Calibrated at
25C and
Temperature Drifted
图 12. CHANGE in VCO Phase Noise Over Temperature
图 13. CHANGE in 8 GHz VCO Phase Noise Over
Temperature
-70
-152
-154
-156
-158
-160
-162
-164
-166
-168
-170
FOUT=8 GHz
FOUT=4 GHz
FOUT=2 GHz
FOUT= 1GHz
FOUT=500 MHx
FOUT=250 MHz
FOUT=125 MHz
FOUT=62.5 MHz
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
Raw Noise Floor
Additive Divider Noise
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
0
1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)
Offset (Hz)
tc_P
tc_P
This noise adds to the scaled VCO Noise when the channel
divider is used.
图 15. Additive VCO Divider Noise Floor
图 14. Divided Output Frequency
14
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Typical Characteristics (接下页)
4
3.2
2.4
1.6
0.8
0
15
12.5
10
Ta=-55
Ta=-40
Ta=25
Ta=85
Ta=125
7.5
5
2.5
0
-0.8
-1.6
-2.4
-3.2
-4
-2.5
-5
1 nH Pull-Up
50 ohm Pull-Up
-7.5
-10
0
2000 4000 6000 8000 10000 12000 14000 16000
0
2000 4000 6000 8000 10000 12000 14000 16000
Frequency (MHz)
tc_P
Frequency (MHz)
tc_P
Single-ended output OUTx_PWR=31
Single-Ended
Output
OUTx_PWR = 31
图 17. CHANGE in Output Power vs Temperature
图 16. Output Power vs Pull-up
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
1 nH Pull-Up
50 ohm Pull-Up
0
5
10 15 20 25 30 35 40 45 50 55 60 65
OUTx_PWR
tc_P
Single-Ended Output
OUTx_PWR=31
图 18. Impact of OUTx_PWR on Output Power
15200
14400
13600
12800
12000
11200
10400
9600
15000
CAL_CLK_DIV=3
CAL_CLK_DIV=2
CAL_CLK_DIV=1
VCO7
VCO6
VCO5
VCO4
VCO3
VCO2
VCO1
14500
14000
13500
13000
12500
12000
11500
11000
10500
10000
9500
9000
8500
8800
8000
7500
8000
7200
7000
0
0.5
1
1.5
2
2.5
3
3.5
0
80 160 240 320 400 480 560 640 720 800
Time (ms)
Time (ms)
tc_V
tc_V
fOSC = 100 MHz
fPD = 200 MHz
VCO_SEL = VCO7
fOSC = 100 MHz
fPD = 200 MHz
FCAL_HPFD_ADJ=
2
FCAL_HPFD_ADJ=
3
CAL_CLK_DIV=2
图 19. Impact of CAL_CLK_DIV on VCO Calibration Time
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图 20. Impact of VCO_SEL on VCO Calibration Time
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Typical Characteristics (接下页)
15200
14400
13600
12800
12000
11200
10400
9600
FCAL_HPFD_ADJ=0
FCAL_HPFD_ADJ=1
FCAL_HPFD_ADJ=2
FCAL_HPFD_ADJ=3
8800
8000
7200
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
tc_V
fOSC = 100 MHz
fPD = 500 MHz
VCO_SEL=VCO7
CAL_CLK_DIV=2
图 21. Impact of FCAL_HPFD_ADJ on VCO Calibration Time
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7 Detailed Description
7.1 Overview
The LMX2615 is a high-performance, wideband frequency synthesizer with integrated VCO and output divider.
The VCO operates from 7600 to 15200 MHz and this can be combined with the output divider to produce any
frequency in the range of 40 MHz to 15.2 GHz. Within the input path there are two dividers .
The PLL is fractional-N PLL with programmable delta-sigma modulator up to 4th order. The fractional
denominator is a programmable 32-bit long, which can provide fine frequency steps easily below 1-Hz resolution
as well as be used to do exact fractions like 1/3, 7/1000, and many others.
For applications where deterministic or adjustable phase is desired, the SYNC pin can be used to get the phase
relationship between the OSCin and RFout pins deterministic. Once this is done, the phase can be adjusted in
very fine steps of the VCO period divided by the fractional denominator.
The ultra-fast VCO calibration is ideal for applications where the frequency must be swept or abruptly changed.
The frequency can be manually programmed.
The JESD204B support includes using the RFoutB output to create a differential SYSREF output that can be
either a single pulse or a series of pulses that occur at a programmable distance away from the rising edges of
the output signal.
The LMX2615 device requires only a single 3.3 V power supply. The internal power supplies are provided by
integrated LDOs, eliminating the need for high performance external LDOs.
表 1 shows the range of several of the doubler, dividers, and fractional settings.
表 1. Range of Doubler, Divider, and Fractional Settings
PARAMETER
MIN
MAX
COMMENTS
Outputs enabled
0
2
The low noise doubler can be used to increase the
phase detector frequency to improve phase noise and
avoid spurs. This is in reference to the OSC_2X bit.
OSCin doubler
0 (1X)
1 (2X)
Only use the Pre R divider if the input frequency is too
high for the Post R divider.
Pre-R divider
Post-R divider
1 (bypass)
1 (bypass)
128
255
The maximum input frequency for the post-R divider is
250 MHz. Use the Pre R divider if necessary.
The minimum divide depends on modulator order and
VCO frequency. See N Divider and Fractional Circuitry
for more details.
N divider
≥ 28
524287
The fractional denominator is programmable and can
assume any value between 1 and 232–1; it is not a
fixed denominator.
Fractional numerator/
denominator
1 (Integer mode)
0
232 – 1 = 4294967295
Order 0 is integer mode and the order can be
programmed
Fractional order
Channel divider
Output frequency
4
This is the series of several dividers. Also, be aware
that above 10 GHz, the maximum allowable channel
divider value is 6.
1 (bypass)
40 MHz
192
This is implied by the minimum VCO frequency divided
by the maximum channel divider value.
15 GHz
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7.2 Functional Block Diagram
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CPout
Vtune
OSCin
OSCinP
Phase
Detector
RFoutAP
Buffer
MUX
MUX
Vcc
Input
signal
OSCin
Douber
Pre-R
Divider
Post-R
Divider
Charge
Pump
RFoutAM
f
Channel
Divider
OSCinM
RFoutBM
Vcc
Sigma-Delta
Modulator
RFoutBP
SYSREF
Synchronization
and Delay
Output
Buffers
CSB
SCK)
SDI
Serial Interface
Control
N Divider
MUXout
7.3 Feature Description
7.3.1 Reference Oscillator Input
The OSCin pins are used as a frequency reference input to the device. The input is high impedance and requires
AC-coupling caps at the pin. The OSCin pins can be driven single-ended with a CMOS clock or XO. Differential
clock input is also supported, making it easier to interface with high-performance system clock devices such as
TI’s LMK series clock devices. As the OSCin signal is used as a clock for the VCO calibration, a proper
reference signal must be applied at the OSCin pin at the time of programming FCAL_EN.
7.3.2 Reference Path
The reference path consists of an OSCin doubler (OSC_2X), Pre-R divider, and a Post-R divider.
OSCin
OSCinP
Buffer
Input
signal
OSCin
Douber
Pre-R
Divider
Post-R
Divider
OSCinM
图 22. Reference Path Diagram
The OSCin doubler (OSC_2X) can double up low OSCin frequencies. Pre-R (PLL_R_PRE) and Post-R (PLL_R)
dividers both divide frequency down. The phase detector frequency, fPD, is calculated as follows:
fPD = fOSC × OSC_2X / (PLL_R_PRE × PLL_R)
(1)
•
•
If the OSCin doubler is used, the OSCin signal should have a 50% duty cycle as both the rising and falling
edges are used.
If the OSCin doubler is not used, only rising edges of the OSCin signal are used and duty cycle is not critical.
18
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Feature Description (接下页)
7.3.2.1 OSCin Doubler (OSC_2X)
The OSCin doubler allows one to double the input reference frequency up to 400 MHz while adding minimal
noise. In some situations it may be advantageous to use the doubler to go to a higher frequency than the
maximum phase detector frequency because the Pre-R divider may be able to divide down this frequency to
phase detector frequency that is advantageous for fractional spurs.
7.3.2.2 Pre-R Divider (PLL_R_PRE)
The pre-R divider is useful for reducing the input frequency to help meet the maximum 250 MHz input frequency
limitation to the PLL-R divider. Otherwise, it does not have to be used.
7.3.2.3 Post-R Divider (PLL_R)
The post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is
used (PLL_R > 1), the input frequency to this divider is limited to 250 MHz.
7.3.3 State Machine Clock
The state machine clock is a divided down version of the OSCin signal that is used internally in the device. This
divide value 1,2,4, 8, or 16 and is determined by CAL_CLK_DIV programming word (described in the
programming section). This state machine clock impacts various features like the VCO calibration and ramping.
The state machine clock is calculated as fsmclk = fOSC / 2CAL_CLK_DIV
.
7.3.4 PLL Phase Detector and Charge Pump
The phase detector compares the outputs of the Post-R divider and N divider and generates a correction current
corresponding to the phase error until the two signals are aligned in phase. This charge-pump current is software
programmable to many different levels, allowing modification of the closed loop bandwidth of the PLL. See
application section on phase noise due to the charge pump.
7.3.5 N Divider and Fractional Circuitry
The N divider includes fractional compensation and can achieve any fractional denominator from 1 to (232 – 1).
The integer portion of N is the whole part of the N divider value, and the fractional portion, Nfrac = NUM / DEN, is
the remaining fraction. In general, the total N divider value is determined by N + NUM / DEN. The N, NUM and
DEN are software programmable. The higher the denominator, the finer the resolution step of the output. For
example, even when using fPD = 200 MHz, the output can increment in steps of 200 MHz /( 232- 1) = 0.047 Hz. 公
式 2 shows the relationship between the phase detector and VCO frequencies. Note that in SYNC mode, there is
an extra divider that is not shown in 公式 2.
NUM
DEN
≈
’
fVCO = fpd ì N +
∆
÷
◊
«
(2)
The sigma-delta modulator that controls this fractional division is also programmable from integer mode to fourth
order. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is
programmed.
The N divider has minimum value restrictions based on the modulator order and VCO frequency. Furthermore,
the PFD_DLY_SEL bit must be programmed in accordance to the 表 2. In SYNC mode, IncludedDivide may be
larger than one, otherwise it is just one.
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Feature Description (接下页)
表 2. Minimum N Divider Restrictions
FRAC_ORDER
fVCO / IncludedDivide (MHz)
MINIMUM N
PFD_DLY_SEL
0
≤ 12500
> 12500
29
33
30
34
38
31
31
32
36
33
37
41
45
45
49
53
57
1
2
1
2
3
1
2
2
3
1
2
3
4
3
4
5
6
1
2
≤ 10000
10000-12500
>12250
≤ 4000 (SYNC Mode)
4000-7500 (SYNC Mode)
7500 - 10000
>10000
3
4
≤ 4000 (SYNC Mode)
4000-7500 (SYNC Mode)
7500 - 10000
>10000
≤ 4000 (SYNC Mode)
4000-7500 (SYNC Mode)
7500-10000
>10000
7.3.6 MUXout Pin
The MUXout pin can be configured as lock detect indicator for the PLL or as an serial data output (SDO) for the
SPI interface to readback registers. Field MUXOUT_LD_SEL (register R0[2]) configures this output
表 3. MUXout Pin Configurations
MUXOUT_LD_SEL
FUNCTION
0
1
Serial data output for readback
Lock detect indicator
When lock detect indicator is selected, there are two types of indicator and they can be selected with the field
LD_TYPE (register R59[0]). The first indicator is called “VCOCal” (LD_TYPE=0) and the second indicator is
called “Vtune and VCOCal” (LD_TYPE=1).
7.3.6.1 Serial data output for readback
In this mode, the MUXout pin become the serial data output of the SPI interface. This output cannot be tri-stated
so no line sharing is possible. Details of this pin operation are described with the serial interface description.
Readback is very useful when a device is used is full assist mode and VCO calibration data are retrieve and
saved for future use. It can also be used to read back the lock detect status using the field
rb_LD_VTUNE(register R110[10:9]).
7.3.6.2 Lock detect indicator set as type “VCOCal”
In this mode the MUXout pin is will be low when the VCO is being calibrated or the lock detect delay timer is
running, otherwise it will be high. The programmable timer (LD_DLY, register R60[15:0]) adds an additional delay
after the VCO calibration finishes before the lock detect indicator is asserted high. LD_DLY is a 16 bit unsigned
quantity that corresponds to the number of phase detector cycles in absolute delay. For example, a phase
detector frequency of 100 MHz and the LD_DLY=10000 will add a delay of 100 usec before the indicator is
asserted. This indicator will remain in its current state (high or low) until register R0 is programmed with
FCAL_EN=1 with a valid input reference. In other words, if the PLL goes out of lock or the input reference goes
away when the current state is high, then the current state will remain high.
20
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7.3.6.3 Lock detect indicator set as type “Vtune and VCOCal”
In this mode the MUXout pin is will be high when the VCO calibration has finished, the lock detect delay timer is
finished running, and the PLL is locked. This indicator may remain in its current state (high or low) if the OSCin
signal is lost. The true status of the indicator will be updated and resume its operation only when a valid input
reference to the OSCin pin is returned. An alternative method to monitor the OSCin of the PLL is recommended.
This indicator is reliable as long as the reference to OSCin is present.
The output of the device can be automatically muted when lock detect indicator “Vtune and VCOCal” is low. This
feature is enabled with the field OUT_MUTE (register R0[9]) asserted.
7.3.7 VCO (Voltage Controlled Oscillator)
The LMX2615 includes a fully integrated VCO. The VCO takes the voltage from the loop filter and converts this
into a frequency. The VCO frequency is related to the other frequencies and as follows:
fVCO = fPD × N divider × N Included Divide
(3)
7.3.7.1 VCO Calibration
To reduce the VCO tuning gain and therefore improve the VCO phase-noise performance, the VCO frequency
range is divided into several different frequency bands. The entire range, 7600 to 15200 MHz, covers an octave
that allows the divider to take care of frequencies below the lower bound. This creates the need for frequency
calibration to determine the correct frequency band given a desired output frequency. The frequency calibration
routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. It is important that a
valid OSCin signal must present before VCO calibration begins.
The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated
any time the R0 register is programmed.
The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much
without being re-calibrated, some minor phase noise degradation could result. The maximum allowable drift for
continuous lock, ΔTCL, is stated in the electrical specifications. For this device, a number of 125°C means the
device never loses lock if the device is operated under recommended operating conditions.
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The LMX2615 allows the user to assist the VCO calibration. In general, there are three kinds of assistance, as
shown in 表 4:
表 4. Assisting the VCO Calibration Speed
VCO_SEL_FORCE
ASSIST
ANCE
LEVEL
VCO_CAPCTRL_FO
RCE
VCO_DACISET_FOR
CE
VCO_CAPCTRL
VCO_DACISET
DESCRIPTION
VCO_SEL
No
assist
User does nothing to improve VCO calibration speed.
7
0
0
Dont Care
Don't Care
Partial Upon every frequency change, before the FCAL_EN bit is
assist checked, the user provides the initial starting VCO_SEL
Choose by table
The user forces the VCO core (VCO_SEL), amplitude
settings (VCO_DACISET), and frequency band
(VCO_CAPCTRL) and manually sets the value.
Full
assist
Choose by
readback
1
Choose by readback
For the no assist method, just set VCO_SEL=7 and this is done. For partial assist, the VCO calibration speed
can be improved by changing the VCO_SEL bit according to the frequency. Note that the frequency is not the
actual VCO core range, but actually favors choosing the VCO. This is not only optimal for VCO calibration speed,
but required for reliable locking.
表 5. Minimum VCO_SEL for Partial Assist
fVCO
VCO Core (min)
VCO1
7600 - 8740 MHz
8740 - 10000 MHz
10000 - 10980 MHz
10980 -12100 MHz
12100 - 13080 MHz
13080 - 14180 MHz
14180 - 15200 MHz
VCO2
VCO3
VCO4
VCO5
VCO6
VCO7
For fastest calibration time, it is ideal to use the minimum VCO core as recommended in the previous table. The
following table shows typical VCO calibration times for this choice in bold as well as showing how long the
calibration time is increased if a higher than necessary VCO core is chosen. Realize that these calibration times
are specific to these fOSC and fPD conditions specified and at the boundary of two cores, sometimes the
calibration time can be increased.
表 6. Typical Calibration times for fOSC = fPD = 100 MHz based on VCO_SEL
VCO_SEL
fVCO
VCO7
650
610
590
340
270
240
160
VCO6
540
530
520
290
170
130
VCO5
550
VCO4
440
VCO3
360
VCO2
230
VCO1
110
8.1 GHz
9.3 GHz
540
430
320
220
Invalid
10.4 GHz
11.4 GHz
12.5 GHz
13.6 GHz
14.7 GHz
530
430
240
Invalid
Invalid
280
180
120
Invalid
Invalid
Invalid
7.3.7.2 Watchdog Feature
The watchdog feature is used to the scenario when radiation during VCO calibration from causes the VCO
calibration to fail. When this feature is enabled, the watchdog timer will run during VCO calibration. If this timer
runs out before the VCO calibration is finished, then the VCO calibration will be re-started. The WD_DLY word
sets how many times this calibration may be restarted by the watchdog feature.
22
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7.3.7.3 RECAL Feature
The RECAL feature is used to mitigate the scenario when the VCO is in lock, but then radiation causes it to go
out of lock. When the RECAL_EN pin is high, if the PLL loses lock and stays out of lock for a time specified by
the LD_DLY word, then it will trigger a VCO re-calibration.
7.3.7.4 Determining the VCO Gain
The VCO gain varies between the seven cores and is the lowest at the lowest end of the band and highest at the
highest end of each band. For a more accurate estimation, use 表 7:
表 7. VCO Gain
f1
f2
Kvco1
78
Kvco2
114
125
136
168
206
218
248
7600
8740
8740
10000
10980
12100
13080
14180
15200
91
10000
10980
12100
13080
14180
112
136
171
188
218
Based in this table, the VCO gain can be estimated for an arbitrary VCO frequency of fVCO as:
Kvco = Kvco1 + (Kvco2-Kvco1) × (fVCO – f1) / (f2 – f1)
(4)
7.3.8 Channel Divider
To go below the VCO lower bound of 7600 MHz, the channel divider can be used. The channel divider consists
of four segments, and the total division value is equal to the multiplication of them. Therefore, not all values are
valid.
MUX
RFoutA
Divide by
2 or 3
Divide by
2 or 4
Divide by
2,4, or 8
1/2
MUX
VCO
MUX
RFoutB
图 23. Channel Divider
When the channel divider is used, there are limitations on the values. 表 8 shows how these values are
implemented and which segments are used.
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表 8. Channel Divider Segments
EQUIVALENT
FREQUENCY
DIVISION
VALUE
OutMin (MHz)
OutMax (MHz)
CHDIV[4:0]
SEG0
SEG1
SEG2
SEG3
LIMITATION
2
4
3800
1900
7600
3800
0
1
2
2
1
2
1
1
1
1
None
6
1266.667
950
2533.333
1437.5
958.333
718.75
469.167
359.375
239.583
179.688
159.722
119.792
89.844
59.896
n/a
2
2
3
1
1
8
3
2
2
2
1
12
633.333
475
4
2
3
2
1
16
5
2
2
4
1
24
316.667
237.5
6
2
3
4
1
32
7
2
2
8
1
48
fVCO ≤ 11.5 GHz
158.333
118.75
105.556
79.167
59.375
39.583
n/a
8
2
3
8
1
64
9
2
2
8
2
72
10
11
12
13
14-31
2
3
6
2
96
2
3
8
2
128
192
Invalid
2
2
8
4
2
3
8
4
n/a
n/a
n/a
n/a
n/a
The channel divider is powered up whenever an output (OUTx_MUX) is selected to the channel divider or
SysRef, regardless of whether it is powered down or not. When an output is not used, TI recommends selecting
the VCO output to ensure that the channel divider is not unnecessarily powered up.
表 9. Channel Divider
OUTA MUX
Channel Divider
X
OUTB MUX
CHANNEL DIVIDER
Powered up
X
Channel Divider or SYSREF
Powered up
All Other Cases
Powered down
7.3.9 Output Buffer
The RF output buffer type is open collector and requires an external pull-up to Vcc. This component may be a
50-Ω resistor or an inductor. The inductor has less controlled impedance, but higher power. For the inductor
case, it is often helpful to follow this with a resistive pad. The output power can be programmed to various levels
or disabled while still keeping the PLL in lock. If using a resistor, limit OUTx_PWR setting to 31; higher than this
tends to actually reduce power. Note that states 32 through 47 are redundant and should be ignored. In other
words, after state 31, the next higher power setting is 48.
表 10. OUTx_PWR Recommendations
fOUT
Restrictions
Comments
At lower frequencies, the output buffer impedance is high, so the 50-Ω pull-up will
make the output impedance look somewhat like 50-Ω. Typically, maximum output
power is near a setting of OUTx_PWR=50.
10 MHz ≤ fOUT ≤ 5 GHz None
In this range, parasitic inductances have some impact, so the output setting is
restricted.
5 GHz < fOUT ≤ 10 GHz
OUTx_PWR ≤ 31
OUTx_PWR ≤ 20
At these higher frequency ranges, it is best to keep below 20 for highest power and
optimal noise floor.
10 GHz < fOUT
7.3.10 Powerdown Modes
The LMX2615 can be powered up and down using the CAL Pin or the POWERDOWN bit. When the device
comes out of the powered down state, either by resuming the POWERDOWN bit to zero or by pulling back CAL
Pin HIGH (if it was powered down by CAL Pin), register R0 must be programmed with FCAL_EN high again to
re-calibrate the device.
24
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7.3.11 Treatment of Unused Pins
This device has several pins for many features and there is a preferred way to treat these pins if not needed. For
the input pins, a series resistor is recommend, but they can be directly shorted.
表 11. Recommended Treatment of Pins
Pins
SPI Mode
Pin Mode
Recommended Treatment if NOT Used
FS0,FS1,FS2,FS3,F Never Used Always Used GND with 1 kΩ.
S4,FS5,FS6,FS7
CAL
Never Used Sometimes
Used
VCC with 1 kΩ
GND with 1 kΩ
SYNC, SysRefReq
OSCinP,OSCinM
Sometimes Never Used
Used
Always
Used
Always Used GND with 50 Ω to ground after AC coupling Cap. If one side of complimentary side is
used and other side is not, impedance looking out should be similar for both of these
pins.
SCK, SDI
CSB
Always
Used
Never Used
Never Used
GND with 1 kΩ
Always
Used
VCC with 1 kΩ
RECAL_EN
RFoutXX
MUXOUT
Sometimes Sometimes
Used Used
Internally pulled to VCC with 200 kΩ
Sometimes Sometimes
Used Used
VCC with 50 Ω. If one side of complimentary side is used and the other side is not,
impedance looking out should be similar for both of these pins.
Sometimes Sometimes
Used Used
GND with 10 kΩ
7.3.12 Phase Synchronization
7.3.12.1 General Concept
The SYNC pin allows one to synchronize the LMX2615 such that the delay from the rising edge of the OSCin
signal to the output signal is deterministic. Initially, the devices are locked to the input, but are not synchronized.
The user sends a synchronization pulse that is reclocked to the next rising edge of the OSCin pulse. After a
given time, t1, the phase relationship from OSCin to fOUT will be deterministic. This time is dominated by the sum
of the VCO calibration time, the analog setting time of the PLL loop, and the MASH_RST_CNT if used in
fractional mode.
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...
Device 1
SYNC
...
Device 2
...
...
fOSC
t2
t1
图 24. Devices Are Now Synchronized to OSCin Signal
When the SYNC feature is enabled, part of the channel divide may be included in the feedback path.
表 12. IncludedDivide with VCO_PHASE_SYNC = 1
OUTx_MUX
CHANNEL DIVIDER
Don't Care
IncludedDivide
1
OUTA_MUX = OUTB_MUX = 1 ("VCO")
Divisible by 3, but NOT 24 or 192
All other values
SEG0 × SEG1 = 6
SEG0 × SEG1 = 4
All Other Valid Conditions
External loop filter
RFoutA
RFoutB
MUX
MUX
Pre-R
Divider
R
OSCin
Doubler
X M
Divider
Charge
Pump
SEG0
f
SEG2
SEG1
SEG3
N Divider
图 25. Phase SYNC Diagram
7.3.12.2 Categories of Applications for SYNC
The requirements for SYNC depend on certain setup conditions. In cases that the SYNC is not timing critical, it
can be done through software by toggling the VCO_PHASE_SYNC bit from 0 to 1. The 图 26 gives the different
categories. When it is timing critical, then it must be done through the pin and the setup and hold times for the
OSCin pin are critical. For timing critical sync (Category 3) ONLY, adhere to the following guidelines.
26
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表 13. SYNC Pin Timing Characteristics for Category 3 SYNC
Parameter
fOSC
Description
Min
Max
Unit
MHz
ns
Input reference Frequency
40
tSETUP
tHOLD
Setup time between SYNC and OSCin rising edges
Hold time between SYNC and OSCin rising edges
2.5
2.5
ns
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Start
NO
/I5Lë G 128
?
CHDIV = 1,2,4,6
This means the channel divider after the
VCO is either bypassed,2,4, or 6. In this
case, SYNC mode will put it in the loop.
NO
Category 4
Device can NOT be reliably
used in SYNC mode
NO
OSC_2X=0
?
CHDIV = 1,2,4,6
?
fOUT and fOSC related by integer multiple?
This means that the output (fOUT) and
input frequencies (fOSC) are related.
In other words:
NO
(fOUT % fOSC=0) OR (fOSC % fOUT=0)
fOUT%(2| (OSC)=0
fOUT and fOSC
related by integer
NO
fOSC G 50 MHz
?
multiple
?
Category 3
ñ SYNC Required
ñ SYNC Timing Critical
ñ Limitations on fOSC
CHDIV = 1,2,4,6
This means the channel
divider after the VCO is either
bypassed,2,4, or 6. In this
case, SYNC mode will put it in
the loop.
Category 2
ñ SYNC Required
ñ SYNC Timing NOT critical
ñ No limitations on fOSC
NO
CHDIV = 1,2,4, 6
?
Integer Mode
This is asking if the device is
in integer mode, which
would mean the fractional
numerator is zero.
YES
NO
Integer Mode
?
Category 1
ñ SYNC Mode Required
NO
CHDIV=1?
ñ No Software/Pin SYNC Pulse required
Category 1
ñ SYNC Mode Not required at all
ñ No limitations on fOSC
图 26. Determining the SYNC Category
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7.3.12.3 Procedure for Using SYNC
This procedure must be used to put the device in SYNC mode.
1. Use the flowchart to determine the SYNC category.
2. Make determinations for OSCin and using SYNC based on the category
1. If Category 4, SYNC cannot be performed in this setup.
2. If category 3, ensure that the maximum fOSC frequency for SYNC is not violated and there are hardware
accommodations to use the SYNC pin.
3. If the channel divide is used, determine the included channel divide value which will be 2 × SEG1 of the
channel divide:
1. If OUTA_MUX is not channel divider and OUTB_MUX is not channel divider or SysRef, then
IncludedDivide = 1.
2. Otherwise, IncludedDivide = 2 × SEG1. In the case that the channel divider is 2, then IncludedDivide=4.
4. If not done already, divide the N divider and fractional values by the included channel divide to account for
the included channel divide.
5. Program the device with the VCO_PHASE_SYNC = 1. Note that this does not count as applying a SYNC to
device (for category 2).
6. Apply the SYNC, if required
1. If category 2, VCO_PHASE_SYNC can be toggled from 0 to 1. Alternatively, a rising edge can be sent to
the SYNC pin and the timing of this is not critical.
2. If category 3, the SYNC pin must be used, and the timing must be away from the rising edge of the
OSCin signal.
7.3.12.4 SYNC Input Pin
The SYNC input pin can be driven either in CMOS. However, if not using SYNC mode (VCO_PHASE_SYNC =
0), then the INPIN_IGNORE bit must be set to one, otherwise it causes issues with lock detect. If the pin is
desired for to be used and VCO_PHASE_SYNC=1, then set INPIN_IGNORE = 0.
7.3.13 Phase Adjust
The MASH_SEED word can use the sigma-delta modulator to shift output signal phase with respect to the input
reference. If a SYNC pulse is sent (software or pin) or the MASH is reset with MASH_RST_N, then this phase
shift is from the initial phase of zero. If the MASH_SEED word is written to, then this phase is added. The phase
shift is calculated as below.
Phase shift in degrees = 360 × ( MASH_SEED / PLL_DEN) × ( IncludedDivide/CHDIV )
(5)
Example:
Mash seed = 1
Denominator = 12
Channel divider = 16
Phase shift ( VCO_PHASE_SYNC=0) = 360 × (1/12) × (1/16) = 1.875 degrees
Phase Shift (VCO_PHASE_SYNC=1) = 360 × (1/12) × (4/16) = 7.5 degrees
There are several considerations when using MASH_SEED
•
Phase shift can be done with a FRAC_NUM=0, but FRAC_ORDER must be greater than zero. For
FRAC_ORDER=1, the phase shifting only occurs when MASH_SEED is a multiple of PLL_DEN.
•
For the 2nd order modulator, PLL_N≥45, for the 3rd order modulator, PLL_N≥49, and for the fourth order
modulator, PLL_N≥54.
When using MASH_SEED in the case where IncludedDivide>1, there are several additional considerations in
order to get the phase shift to be monotonically increasing with MASH_SEED.
•
•
It is recommended to use MASH_ORDER <=2.
When using the 2nd order modulator for VCO frequencies below 10 GHz (when IncludedDivide=6) or 9 GHz
(when IncludedDivide=4), it may be necessary to increase the PLL_N value much higher or change to first
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order modulator. When this is necessary depends on the VCO frequency, IncludedDivide, and PLL_N value.
7.3.14 Fine Adjustments for Phase Adjust and Phase SYNC
Phase SYNC refers to the process of getting the same phase relationship for every power up cycle and each
time assuming that a given programming procedure is followed. However, there are some adjustments that can
be made to get the most accurate results. As for the consistency of the phase SYNC, the only source of variation
could be if the VCO calibration chooses a different VCO core and capacitor, which can introduce a bimodal
distribution with about 10 ps of variation. If this 10 ps is not desirable, then it can be eliminated by reading back
the VCO core, capcode, and DACISET values and forcing these values to ensure the same calibration settings
every time. The delay through the device varies from part to part and can be on the order of 60 ps. This part to
part variation can be calibrated out with the MASH_SEED. The variation in delay through the device also
changes on the order of +2.5 ps/°C, but devices on the same board likely have similar temperatures, so this will
somewhat track. In summary, the device can be made to have consistent delay through the part and there are
means to adjust out any remaining errors with the MASH_SEED. This tends only to be an issue at higher output
frequencies when the period is shorter.
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7.3.15 SYSREF
The LMX2615 can generate a SYSREF output signal that is synchronized to fOUT with a programmable delay.
This output can be a single pulse, series of pulses, or a continuous stream of pulses. To use the SYSREF
capability, the PLL must first be placed in SYNC mode with VCO_PHASE_SYNC = 1.
fOUT
RFoutA
MUX
Rest of Channel
Divider
fVCO
IncludedDivide
N Divider
To Phase
Detector
Divider
(SYSREF_DIV_PRE)
Divider
(SYSREF_DIV)
1/2
fSYSREF
Delay Circuit
RFoutB
Re-clocking
Circuit
SysRefReq Pin
图 27. SYSREF Setup
As 图 27 shows, the SYSREF feature uses IncludedDivide and SYSREF_DIV_PRE divider to generate
fINTERPOLATOR. This frequency is used for re-clocking of the rising and falling edges at the SysRefReq pin. In
master mode, the fINTERPOLATOR is further divided by 2×SYSREF_DIV to generate finite series or continuous
stream of pulses.
表 14. SYSREF Setup
PARAMETER
fVCO
MIN
7600
0.8
TYP
MAX
15200
1.5
UNIT
MHz
GHz
fINTERPOLATOR
IncludedDivide
SYSREF_DIV_PRE
SYSREF_DIV
4 or 6
1, 2, or 4
4,6,8, ..., 4098
fPRESYSREF = fVCO /(IncludedDivide ×
SYSREF_DIV_PRE)
fINTERPOLATOR
fSYSREF
Delay step size
fSYSREF = fINTERPOLATOR / (2 × SYSREF_DIV)
9
ps
Pulses for pulsed mode (SYSREF_PULSE_CNT)
0
15
n/a
The delay can be programmed using the JESD_DAC1_CTRL, JESD_DAC2_CTRL, JESD_DAC3_CTRL, and
JESD_DAC4_CTRL words. By concatenating these words into a larger word called "SYSREFPHASESHIFT", the
relative delay can be found. The sum of these words must always be 63.
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表 15. SysRef Delay
SYSREFPHASESHIFT
DELAY
JESD_DAC1
JESD_DAC2
JESD_DAC3
JESD_DAC4
0
...
Minimum
36
27
0
0
0
0
0
0
0
0
36
0
63
1
37
62
...
99
0
0
0
0
63
62
0
1
100
...
161
162
163
225
226
247
> 247
0
0
0
1
62
0
0
63
1
0
0
0
62
63
0
0
62
1
0
0
0
0
Maximum
Invalid
41
22
Invalid
Invalid
Invalid
Invalid
7.3.15.1 Programmable Fields
表 16 has the programmable fields for the SYSREF functionality.
表 16. SYSREF Programming Fields
FIELD
PROGRAMMING
DEFAULT
DESCRIPTION
Enables the SYSREF mode. SYSREF_EN
must be 1 if and only if OUTB_MUX=2
(SysRef)
0 = Disabled
1 = enabled
SYSREF_EN
0
1: DIV1
2: DIV2
4: DIV4
Other states: invalid
The output of this divider is the
fINTERPOLATOR.
SYSREF_DIV_PRE
SYSREF_REPEAT
In master mode, the device creates a series
of SYSREF pulses. In repeater mode,
SYSREF pulses are generated with the
SysRefReq pin.
0 = Master mode
1 = Repeater mode
0
Continuous mode continuously makes
SYSREF pulses, where pulsed mode makes
a series of SYSREF_PULSE_CNT pulses
0 = Continuous mode
1 = Pulsed mode
SYSREF_PULSE
0
4
In the case of using pulsed mode, this is the
number of pulses. Setting this to zero is an
allowable, but not practical state.
SYSREF_PULSE_CNT
0 to 15
0: Divide by 4
1: Divide by 6
2: Divide by 8
...
The SYSREF frequency is at the VCO
frequency divided by this value.
SYSREF_DIV
0
2047: Divide by 4098
32
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7.3.15.2 Input and Output Pin Formats
7.3.15.2.1 SYSREF Output Format
The SYSREF output comes in differential format through RFoutB. This will have a minimum voltage of about 2.3
V and a maximum of 3.3 V. If DC coupling cannot be used, there are two strategies for AC coupling.
3.3 V
SysRefOutP
Data
Converter
SysRefOutN
LMX2594
3.3 V
Copyright © 2017, Texas Instruments Incorporated
图 28. SYSREF Output
1. Send a series of pulses to establish a DC-bias level across the AC-coupling capacitor.
2. Establish a bias voltage at the data converter that is below the threshold voltage by using a resistive divider.
7.3.15.3 Examples
The SysRef can be used in a repeater mode, which just echos the input, after being re-clocked to the
fINTERPOLATOR frequency and then RFout, or it can be used in a repeater. In repeater mode, it can repeat 1,2,4,8,
or infinite (continuous) pulses. The frequency for repeater mode is equal to the RFout frequency divided by the
SYSREF divider.
RFoutAM
OSCinM
OSCinP
RFoutAP
RFoutBP
RFoutBM
SysRefReq
t2
t1
t2
f
t1
f
图 29. SYSREF Out In Repeater Mode
In master mode, the SysRefReq pin is pulled high to allow the SysRef output.
RFoutAM
OSCinM
OSCinP
RFoutAP
RFoutBP
RFoutBM
SysRefReq
f
f
图 30. Figure 1. SYSREF Out In Pulsed/Continuous Mode
版权 © 2018, Texas Instruments Incorporated
33
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
7.3.15.4 SYSREF Procedure
To use SYSREF, do the these steps:
1. Put the device in SYNC mode using the procedure already outlined.
2. Figure out IncludedDivide the same way it is done for SYNC mode.
3. Calculate the SYSREF_DIV_PRE value such that the interpolator frequency (fINTERPOLATOR) is in the range of
800 to 1500 MHz. fINTERPOLATOR = fVCO/IncludedDivide/SYSREF_DIV_PRE. Make this frequency a multiple of
fOSC if possible.
4. If using master mode (SYSREF_REPEAT = 0), ensure SysRefReq pin is high, ensure the SysRefReq pin is
high.
5. If using repeater mode (SYSREF_REPEAT = 1), set up the pulse count if desired. Pulses are created by
toggling the SysRefReq pin.
6. Adjust the delay between the RFoutA and RFoutB signal using the JESD_DACx_CTL fields.
7.3.16 Pin Modes
The LMX2615-SP has 8 pins that can be used to program pre-selected modes. A few rules of operation for these
pin modes are as folows:
•
•
Set the pin mode as desired. Pin Mode 0 is SPI mode
If a single frequency is desired, tie CAL should be tied to supply through 1 kohm resistance and and
RECAL_EN shoudl be left open.
•
•
•
The rise time for the supply needs to be <50 ms.
Fractional denominator for all pin modes is 4250000
Some words can be overwritten in pin mode including OUTx_PWR, OUTx_EN, RESET, and POWERDOWN
When changing between pin modes, after the pins are changed, the CAL pin needs to be toggled
•
If the FS7 pin is low, then only the RFoutA output is active. If the FS7 pin is high, then both the RFoutA and
RFoutB outputs are active.
The following table shows all the pin modes
表 17. Pin Modes
fOSC
(MHz)
fPD
(MHz)
CPG
(mA)
fOUT
(MHz)
fVCO
CHDIV
Mode
N
Fraction
(MHz)
0
1
SPI Mode
10
10
20
10
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
160
395
48
24
12
6
7680
9480
384
948
432
384
48
0/4250000000
0/4250000000
2
3
10
20
720
8640
0/4250000000
4
10
20
1280
7680
0/4250000000
5
100
100
100
20
200
200
200
40
300
32
8
9600
0/4250000000
6
1000
8000
40
0/4250000000
7
1200
8
9600
48
0/4250000000
8
6199.855
2000
2
12399.71
8000
309
40
4219187500/4250000000
0/4250000000
9
100
50
200
100
100
100
40
4
10
11
12
13
14
15
16
17
18
19
250
32
16
12
2
8000
80
0/4250000000
50
500
8000
80
0/4250000000
50
850
10200
102
282
455
512
100
0/4250000000
20
5654.912
1517.867839
1708.670653
2500
11309.824
9107.207034
10252.02392
10000
3168800000/4250000000
1531494725/4250000000
2555082575/4250000000
0/4250000000
10
20
6
10
20
6
50
100
4
Reserved. Do not use this pin mode.
10
50
20
15
15
3035.735678
3200
4
4
12142.94271
12800
607
128
625326300/4250000000
0/4250000000
100
34
版权 © 2018, Texas Instruments Incorporated
LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
表 17. Pin Modes (接下页)
fOSC
(MHz)
fPD
(MHz)
CPG
(mA)
fOUT
(MHz)
fVCO
CHDIV
Mode
N
Fraction
(MHz)
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
10
20
100
100
100
100
20
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
3417.341306
4500
4
2
13669.36522
9000
683
90
1990110100/4250000000
0/4250000000
50
50
4800
2
9600
96
0/4250000000
50
5350
2
10700
107
136
683
683
683
683
96
0/4250000000
50
6800
2
13600
0/4250000000
10
6834
2
13668
1700000000/4250000000
1990109675/4250000000
1992187500/4250000000
2018750000/4250000000
0/4250000000
10
20
6834.682611
6834.6875
6834.75
9600
2
13669.36522
13669.375
13669.5
9600
10
20
2
10
20
2
50
100
100
100
100
37.5
37.5
75
1
50
9650
1
9650
96
2125000000/4250000000
0/4250000000
50
13500
1
13500
135
89
100
18.75
18.75
37.5
20
70
128
24
24
24
2
8960
2550000000/4250000000
0/4250000000
393.75
422.4990441
422.4990441
6785.552
2088.38
2210
9450
252
270
135
339
208
88
10139.97706
10139.97706
13571.104
8353.52
8840
1697399952/4250000000
848699976/4250000000
1179800000/4250000000
3561500000/4250000000
1700000000/4250000000
2210000000/4250000000
1848750000/4250000000
0/4250000000
40
20
40
4
100
100
20
100
100
40
4
2238
4
8952
89
2254.35
2270
4
9017.4
9080
225
227
228
360
180
203
204
205
205
205
206
207
210
211
211
212
212
205
643
650
651
656
661
305
669
670
317
20
40
4
20
40
2280
4
9120
0/4250000000
18.75
37.5
20
37.5
75
6759.984705
6759.984705
8125
2
13519.96941
13519.96941
8125
2263199800/4250000000
1131599900/4250000000
531250000/4250000000
1593750000/4250000000
0/4250000000
2
40
1
20
40
8175
1
8175
20
40
8200
1
8200
20
40
8210
1
8210
1062500000/4250000000
1328125000/4250000000
3718750000/4250000000
2125000000/4250000000
0/4250000000
20
40
8212.5
8275
1
8212.5
8275
20
40
1
20
40
8300
1
8300
20
40
8400
1
8400
20
40
8450
1
8450
1062500000/4250000000
2125000000/4250000000
425000000/4250000000
1700000000/4250000000
1275000000/4250000000
0/4250000000
20
40
8460
1
8460
20
40
8484
1
8484
20
40
8496
1
8496
20
40
8212
1
8212
10
20
12860
1
12860
10
20
13000
1
13000
0/4250000000
10
20
13022.5
13125
1
13022.5
13125
531250000/4250000000
1062500000/4250000000
531250000/4250000000
1030306250/4250000000
2125000000/4250000000
3718750000/4250000000
1030412500/4250000000
10
20
1
10
20
13222.5
12209.697
13390
1
13222.5
12209.697
13390
20
40
1
10
20
1
10
20
13417.5
12689.697
1
13417.5
12689.697
20
40
1
版权 © 2018, Texas Instruments Incorporated
35
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
表 17. Pin Modes (接下页)
fOSC
(MHz)
fPD
(MHz)
CPG
(mA)
fOUT
(MHz)
fVCO
CHDIV
Mode
N
Fraction
(MHz)
67
68
69
70
71
72
20
20
40
40
15
15
15
15
15
15
13906.667
14192.727
8212.5
1250
1
1
1
8
8
6
13906.667
14192.727
8212.5
347
354
410
200
100
300
2833368750/4250000000
3477243750/4250000000
2656250000/4250000000
0/4250000000
10
20
100
50
50
10000
100
37.5
1250
10000
0/4250000000
18.75
1875
11250
0/4250000000
7.4 Device Functional Modes
表 18. Device Functional Modes
MODE
DESCRIPTION
SOFTWARE SETTINGS
Registers are held in their reset state. This device does have a
power on reset, but it is good practice to also do a software reset if
there is any possibility of noise on the programming lines, especially
if there is sharing with other devices. Also realize that there are
registers not disclosed in the data sheet that are reset as well.
RESET = 1
POWERDOWN = 0
RESET
POWERDOWN = 1
or
POWERDOWN
Device is powered down.
CAL Pin = Low
One of FS0, FS1, ... FS7 pins is
NOT low
Pin Mode
Normal operating mode
SYNC mode
Device settings are determined by pin states.
This is used with at least one output on as a frequency synthesizer
and the device can be controlled through the SPI interface
ALL of FS0, FS1, ... FS7 pins are
low
This is used where part of the channel divider is in the feedback path
to ensure deterministic phase.
VCO_PHASE_SYNC = 1
VCO_PHASE_SYNC =1,
SYSREF_EN = 1
SYSREF mode
In this mode, RFoutB is used to generate pulses for SYSREF.
36
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LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
7.5 Programming
When not in pin mode, the LMX2615 is programmed using 24-bit shift registers. The shift register consists of a
R/W bit (MSB), followed by a 7-bit address field and a 16-bit data field. For the R/W bit, 0 is for write, and 1 is for
read. The address field ADDRESS[6:0] is used to decode the internal register address. The remaining 16 bits
form the data field DATA[15:0]. While CSB is low, serial data is clocked into the shift register upon the rising
edge of clock (data is programmed MSB first). When CSB goes high, data is transferred from the data field into
the selected register bank. See 图 1 for timing details.
7.5.1 Recommended Initial Power-Up Sequence
For the most reliable programming, TI recommends this procedure:
1. Apply power to device.
2. Program RESET = 1 to reset registers.
3. Program RESET = 0 to remove reset.
4. Program registers as shown in the register map in REVERSE order from highest to lowest.
–
–
–
Programming of register R114 is only needed one wants to change the default states for WD_CNTRL or
WD_DLY.
Programming of registers R113 down to R76 is not required, but if they are programmed, they should be
done so as the register map shows.
Programming of registers R75 down to R0 is required. Registers in this range that only 1's and 0's should
also be programmed in accordance to the register map. Do NOT assume that the power on reset state
and the recommended value are the same. Also, in the register descriptions, it lists a "Reset" value. This
is actually the recommended value that should match the main register map table; it is not necessarily the
power on reset value.
5. Wait 10 ms
6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a
stable state.
7.5.2 Recommended Sequence for Changing Frequencies
The recommended sequence for changing frequencies is as follows:
1. Change the N divider value.
2. Program the PLL numerator and denominator.
3. Program FCAL_EN (R0[3]) = 1.
版权 © 2018, Texas Instruments Incorporated
37
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
7.6 Register Maps
7.6.1 Register Map
www.ti.com.cn
表 19. Complete Register Map Table
REG
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCO_
PHAS
E_
MUX
POW
ERDO
WN
OUT_
MUTE
FCAL_
HPFD_ADJ
FCAL OUT_ RESE
_EN LD_S
EL
R0
0
1
0
0
0
0
0
1
T
SYNC
R1
R2
R3
R4
R5
R6
R7
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
CAL_CLK_DIV
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
VCO_
DACI
SET_
FORC
E
VCO_
CAPC
TRL_
FORC
E
R8
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
OSC_
2X
R9
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
0
0
1
0
0
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
PLL_R
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
1
0
0
0
0
PLL_R_PRE
0
0
0
0
1
0
CPG
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
VCO_DACISET
1
0
1
0
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
VCO_CAPCTRL
VCO_
SEL_
FORC
E
R20
1
1
VCO_SEL
0
0
0
1
0
1
0
0
0
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
SEG1
_EN
R31
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
R32
R33
R34
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
0
PLL_N[18:16]
38
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LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
Register Maps (接下页)
表 19. Complete Register Map Table (接下页)
R35
R36
R37
R38
R39
R40
R41
R42
R43
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
PLL_N[15:0]
0
PFD_DLY_SEL
0
0
PLL_DEN[31:16]
PLL_DEN[15:0]
MASH_SEED[31:16]
MASH_SEED[15:0]
PLL_NUM[31:16]
PLL_NUM[15:0]
MASH
_RES
ET_N
OUTB OUTA
R44
0
0
OUTA_PWR
0
0
MASH_ORDER
_PD
_PD
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUTA_MUX
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
OUTB_PWR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
OUTB_MUX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INPIN
_
IGNO
RE
R58
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
LD_
TYPE
R59
0
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
LD_DLY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MASH_RST_COUNT[31:16]
MASH_RST_COUNT[15:0]
SYSR
EF_R
EPEA
T
SYSR SYSR
EF_P EF
ULSE _EN
R71
0
0
0
0
0
0
0
0
0
SYSREF_DIV_PRE
0
0
0
0
R72
R73
R74
R75
0
0
0
0
0
0
0
0
SYSREF_DIV
JESD_DAC2_CTRL
JESD_DAC4_CTRL
CHDIV
JESD_DAC1_CTRL
JESD_DAC3_CTRL
SYSREF_PULSE_CNT
0
0
0
0
1
0
0
0
0
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Register Maps (接下页)
表 19. Complete Register Map Table (接下页)
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
R100
R101
R102
R103
R104
R105
R106
R107
R108
R109
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
rb_LD
_VTUNE
R110
0
0
0
0
0
0
0
rb_VCO_SEL
0
0
0
0
0
R111
R112
R113
R114
0
0
0
0
0
0
0
0
0
0
0
0
0
rb_VCO_CAPCTRL
rb_VCO_DACISET
0
0
rb_IO_STATUS
WD_DLY
0
0
0
0
0
WD_CNTRL
Table 20 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in
Table 20 should be considered as reserved locations and the register contents should not be modified.
Table 20. Device Registers
Address
0x0
Acronym
R0
Register Name
Section
Go
0x1
R1
Go
40
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Table 20. Device Registers (continued)
Address
0x8
Acronym
R8
Register Name
Section
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
0x9
R9
0xB
R11
R12
R14
R16
R19
R20
R31
R34
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R58
R59
R60
R69
R70
R71
R72
R73
R74
R75
R110
R111
R112
R113
R114
0xC
0xE
0x10
0x13
0x14
0x1F
0x22
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x3A
0x3B
0x3C
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x6E
0x6F
0x70
0x71
0x72
Complex bit access types are encoded to fit into small table cells. Table 21 shows the codes that are used for
access types in this section.
Table 21. Device Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
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Table 21. Device Access Type Codes (continued)
Access Type
Code
Description
-n
Value after reset or the default
value
7.6.1.1 R0 Register (Address = 0x0) [reset = X]
R0 is shown in Figure 31 and described in Table 22.
Return to Summary Table.
Figure 31. R0 Register
7
6
5
4
3
2
1
0
FCAL_HPFD_A
DJ
RESERVED
FCAL_EN
MUXOUT_LD_
SEL
RESET
POWERDOWN
R/W-0x0
R-0x0
R/W-0x1
R/W-0x1
R/W-0x0
R/W-0x0
Table 22. R0 Register Field Descriptions
Bit
Field
Type
Reset
Description
14
VCO_PHASE_SYNC
R/W
X
Phase Sync Mode Enable. In this state, part of the channel divider is
put in the feedback path to ensure determinisic phase. The action of
toggling this bit from 0 to 1 also sends an asynchronous SYNC
pulse.
0x0 = Phase SYNC disabled
0x1 = Phase SYNC enabled
13-10
9
RESERVED
OUT_MUTE
R
X
X
R/W
0x1 = Mute output (RFOUTA/B) during FCAL
8-7
FCAL_HPFD_ADJ
R/W
0x0
Adjustment to decrease the state machine clock for the VCO
calibration speed based on phase detector frequency.
6-4
3
RESERVED
FCAL_EN
R
0x0
0x1
R/W
Writing register R0 with this bit set to a '1' enables and triggers the
VCO frequency calibration.
2
MUXOUT_LD_SEL
R/W
R/W
0x1
Selects the functionality of the MUXout Pin
0x0 = Readback
0x1 = Lock Detect
1
RESET
0x0
Register Reset. This resets all registers and state machines. After
writing a '1', you must write a '0' to remove the reset.It is
recommended to toggle the RESET bit before programming the part
to ensure consistent performance.
0x0 = Normal Operation
0x1 = Reset
0
POWERDOWN
R/W
0x0
Powers down device.
0x0 = Normal Operation
0x1 = Powered Down
7.6.1.2 R1 Register (Address = 0x1) [reset = 0x4]
R1 is shown in Figure 32 and described in Table 23.
Return to Summary Table.
Figure 32. R1 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
CAL_CLK_DIV
R/W-0x4
42
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ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
Table 23. R1 Register Field Descriptions
Bit
7-3
2-0
Field
Type
R
Reset
0x0
Description
RESERVED
CAL_CLK_DIV
R/W
0x4
Divides down the Fosc frequency to the state machine clock
(SM_CLK) frequency. SM_CLK = Fosc/(2CAL_CLK_DIV). Ensure that
the state machine clock frequency 50 MHz or less.
0x0 = Up to 50 MHz
0x1 = Up to 100 MHz
0x2 = Up to 200 MHz
0x3 = Up to 400 MHz
0x4 = Up to 800 MHz
0x5 = Greater than 800 MHz
7.6.1.3 R8 Register (Address = 0x8) [reset = X]
R8 is shown in Figure 33 and described in Table 24.
Return to Summary Table.
Figure 33. R8 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
Table 24. R8 Register Field Descriptions
Bit
Field
Type
Reset
Description
14
VCO_DACISET_FORCE R/W
X
Forces VCO_DACISET Value. Useful for fully assisted VCO
calibration and debugging purposes.
13-12
11
RESERVED
R
X
X
VCO_CAPCTRL_FORCE R/W
Forces VCO_CAPCTRL value. Useful for fully assisted VCO
calibration and debugging purposes.
10-0
RESERVED
R
0x0
7.6.1.4 R9 Register (Address = 0x9) [reset = X]
R9 is shown in Figure 34 and described in Table 25.
Return to Summary Table.
Figure 34. R9 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
Table 25. R9 Register Field Descriptions
Bit
Field
Type
Reset
Description
12
OSC_2X
R/W
X
Reference Path Doubler
0x0 = Disabled
0x1 = Enable
11-0
RESERVED
R
0x0
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7.6.1.5 R11 Register (Address = 0xB) [reset = 0x10]
R11 is shown in Figure 35 and described in Table 26.
Return to Summary Table.
Figure 35. R11 Register
7
6
5
4
3
2
1
0
PLL_R
RESERVED
R-0x0
R/W-0x1
Table 26. R11 Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
0x1
Description
11-4
3-0
PLL_R
PLL R divider Value
RESERVED
0x0
7.6.1.6 R12 Register (Address = 0xC) [reset = 0x1]
R12 is shown in Figure 36 and described in Table 27.
Return to Summary Table.
Figure 36. R12 Register
7
6
5
4
3
2
1
0
PLL_R_PRE
R/W-0x1
Table 27. R12 Register Field Descriptions
Bit
7-0
Field
PLL_R_PRE
Type
Reset
Description
R/W
0x1
PLL Pre-R divider value
7.6.1.7 R14 Register (Address = 0xE) [reset = 0x70]
R14 is shown in Figure 37 and described in Table 28.
Return to Summary Table.
Figure 37. R14 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
CPG
RESERVED
R-0x0
R/W-0x7
Table 28. R14 Register Field Descriptions
Bit
7
Field
Type
R
Reset
0x0
Description
RESERVED
CPG
6-4
R/W
0x7
Effective charge pump gain . This is the sum of the up and down
currents.
3-0
RESERVED
R
0x0
7.6.1.8 R16 Register (Address = 0x10) [reset = 0x80]
R16 is shown in Figure 38 and described in Table 29.
Return to Summary Table.
44
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Figure 38. R16 Register
7
6
5
4
3
2
1
0
VCO_DACISET
R/W-0x80
Table 29. R16 Register Field Descriptions
Bit
Field
VCO_DACISET
Type
Reset
Description
8-0
R/W
0x80
Programmable current setting for the VCO that is applied when
VCO_DACISET_FORCE=1.
7.6.1.9 R19 Register (Address = 0x13) [reset = 0xB7]
R19 is shown in Figure 39 and described in Table 30.
Return to Summary Table.
Figure 39. R19 Register
7
6
5
4
3
2
1
0
VCO_CAPCTRL
R/W-0xB7
Table 30. R19 Register Field Descriptions
Bit
7-0
Field
VCO_CAPCTRL
Type
Reset
Description
R/W
0xB7
Programmable band within VCO core that applies when
VCO_CAPCTRL_FORCE=1. Valid values are 183 to 0, where the
higher number is a lower frequency.
7.6.1.10 R20 Register (Address = 0x14) [reset = X]
R20 is shown in Figure 40 and described in Table 31.
Return to Summary Table.
Figure 40. R20 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
Table 31. R20 Register Field Descriptions
Bit
Field
Type
Reset
Description
13-11
VCO_SEL
R/W
X
User specified start VCO for calibration. Also is the VCO core that is
forced by VCO_SEL_FORCE
10
VCO_SEL_FORCE
RESERVED
R/W
R
X
Force the VCO_SEL Value
9-0
0x0
7.6.1.11 R31 Register (Address = 0x1F) [reset = X]
R31 is shown in Figure 41 and described in Table 32.
Return to Summary Table.
Figure 41. R31 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
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Table 32. R31 Register Field Descriptions
Bit
14
Field
Type
R/W
R
Reset
X
Description
SEG1_EN
RESERVED
Enables first divide by 2 in channel divider.
13-0
0x0
7.6.1.12 R34 Register (Address = 0x22) [reset = 0x0]
R34 is shown in Figure 42 and described in Table 33.
Return to Summary Table.
Figure 42. R34 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
PLL_N_18:16
R/W-0x0
Table 33. R34 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
7-3
2-0
RESERVED
PLL_N_18:16
R/W
0x0
Upper 3 bits of N mash, total 19 bits, split as 16 + 3
7.6.1.13 R36 Register (Address = 0x24) [reset = 0x46]
R36 is shown in Figure 43 and described in Table 34.
Return to Summary Table.
Figure 43. R36 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PLL_N
R/W-0x46
Table 34. R36 Register Field Descriptions
Bit
15-0
Field
PLL_N
Type
Reset
Description
R/W
0x46
PLL N divider value
7.6.1.14 R37 Register (Address = 0x25) [reset = 0x400]
R37 is shown in Figure 44 and described in Table 35.
Return to Summary Table.
Figure 44. R37 Register
15
7
14
6
13
5
12
4
11
PFD_DLY_SEL
R/W-0x4
10
9
1
8
0
RESERVED
R-0x0
3
2
RESERVED
R-0x0
46
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ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
Table 35. R37 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-14
13-8
RESERVED
PFD_DLY_SEL
R/W
0x4
Programmable phase detector delay. This should be programmed
based on VCO frequency, fractional order, and N divider value. DLY
= (PFD_DLY_SEL + 3)*4*VCO_cycle.
7-0
RESERVED
R
0x0
7.6.1.15 R38 Register (Address = 0x26) [reset = 0xFD51]
R38 is shown in Figure 45 and described in Table 36.
Return to Summary Table.
Figure 45. R38 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
3
3
2
2
2
1
1
1
0
0
0
PLL_DEN_31:16
R/W-0xFD51
Table 36. R38 Register Field Descriptions
Bit
15-0
Field
PLL_DEN_31:16
Type
Reset
Description
Fractional Denominator(MSB)
R/W
0xFD51
7.6.1.16 R39 Register (Address = 0x27) [reset = 0xDA80]
R39 is shown in Figure 46 and described in Table 37.
Return to Summary Table.
Figure 46. R39 Register
15
14
13
12
11
10
9
8
7
6
5
4
PLL_DEN
R/W-0xDA80
Table 37. R39 Register Field Descriptions
Bit
15-0
Field
PLL_DEN
Type
Reset
Description
R/W
0xDA80
Fractional Denominator
7.6.1.17 R40 Register (Address = 0x28) [reset = 0x0]
R40 is shown in Figure 47 and described in Table 38.
Return to Summary Table.
Figure 47. R40 Register
15
14
13
12
11
10
9
8
7
6
5
4
MASH_SEED_31:16
R/W-0x0
Table 38. R40 Register Field Descriptions
Bit
15-0
Field
MASH_SEED_31:16
Type
Reset
Description
R/W
0x0
MASH_SEED(MSB)
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7.6.1.18 R41 Register (Address = 0x29) [reset = 0x0]
R41 is shown in Figure 48 and described in Table 39.
Return to Summary Table.
Figure 48. R41 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MASH_SEED
R/W-0x0
Table 39. R41 Register Field Descriptions
Bit
15-0
Field
MASH_SEED
Type
Reset
Description
R/W
0x0
Sets the initial state of the fractional engine. Useful for producing a
phase shift and fractional spur optimization.
7.6.1.19 R42 Register (Address = 0x2A) [reset = 0x0]
R42 is shown in Figure 49 and described in Table 40.
Return to Summary Table.
Figure 49. R42 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PLL_NUM_31:16
R/W-0x0
Table 40. R42 Register Field Descriptions
Bit
15-0
Field
PLL_NUM_31:16
Type
Reset
Description
R/W
0x0
Fractional Numerator (MSB)
7.6.1.20 R43 Register (Address = 0x2B) [reset = 0x0]
R43 is shown in Figure 50 and described in Table 41.
Return to Summary Table.
Figure 50. R43 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PLL_NUM
R/W-0x0
Table 41. R43 Register Field Descriptions
Bit
15-0
Field
PLL_NUM
Type
Reset
Description
R/W
0x0
Fractional Numerator
7.6.1.21 R44 Register (Address = 0x2C) [reset = 0x1FA3]
R44 is shown in Figure 51 and described in Table 42.
Return to Summary Table.
Figure 51. R44 Register
15
7
14
6
13
5
12
4
11
10
2
9
1
8
0
RESERVED
R-0x0
OUTA_PWR
R/W-0x1F
3
48
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MASH_ORDER
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OUTB_PD
R/W-0x1
OUTA_PD
R/W-0x0
MASH_RESET
_N
RESERVED
R-0x0
R/W-0x1
R/W-0x3
Table 42. R44 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-14
13-8
RESERVED
OUTA_PWR
R/W
0x1F
Sets current that controls output power for output A. 0 is minimum
current, 63 is maximum current.
7
6
OUTB_PD
R/W
R/W
R/W
R
0x1
0x0
0x1
0x0
0x3
\nPowers down output B
Powers down output A
Active low reset for MASH
OUTA_PD
5
MASH_RESET_N
RESERVED
MASH_ORDER
4-3
2-0
R/W
MASH Order
7.6.1.22 R45 Register (Address = 0x2D) [reset = X]
R45 is shown in Figure 52 and described in Table 43.
Return to Summary Table.
Figure 52. R45 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
OUTB_PWR
R/W-0x1F
Table 43. R45 Register Field Descriptions
Bit
Field
Type
R/W
R
Reset
X
Description
12-11
10-6
5-0
OUTA_MUX
RESERVED
OUTB_PWR
\nSelects input to OUTA output
0x0
R/W
0x1F
Sets current that controls output power for output B. 0 is minimum
current, 63 is maximum current.
7.6.1.23 R46 Register (Address = 0x2E) [reset = 0x1]
R46 is shown in Figure 53 and described in Table 44.
Return to Summary Table.
Figure 53. R46 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
OUTB_MUX
R/W-0x1
Table 44. R46 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
7-2
1-0
RESERVED
OUTB_MUX
R/W
0x1
\nSelects input to the OUTB output
7.6.1.24 R58 Register (Address = 0x3A) [reset = X]
R58 is shown in Figure 54 and described in Table 45.
Return to Summary Table.
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Figure 54. R58 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
Table 45. R58 Register Field Descriptions
Bit
Field
Type
Reset
Description
15
INPIN_IGNORE
R/W
X
Ignore SYNC and SYSREF pins when VCO_PHASE_SYNC=0. This
bit should be set to 1 unless VCO_PHASE_SYNC=1
14-0
RESERVED
R
0x0
7.6.1.25 R59 Register (Address = 0x3B) [reset = 0x1]
R59 is shown in Figure 55 and described in Table 46.
Return to Summary Table.
Figure 55. R59 Register
7
6
5
4
3
2
1
0
RESERVED
R-0x0
LD_TYPE
R/W-0x1
Table 46. R59 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
7-1
0
RESERVED
LD_TYPE
R/W
0x1
Lock Detect Type. VCOCal lock detect asserts a high output after
the VCO has finished calibration and the LD_DLY timout counter is
finished. Vtune and VCOCal lock detect asserts a high output when
VCOCal lock detect would assert a signal and the tuning voltage to
the VCO is within acceptable limits.
0x0 = VCOCal Lock Detect
0x1 = VCOCal and Vtune Lock Detect
7.6.1.26 R60 Register (Address = 0x3C) [reset = 0x9C4]
R60 is shown in Figure 56 and described in Table 47.
Return to Summary Table.
Figure 56. R60 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LD_DLY
R/W-0x9C4
Table 47. R60 Register Field Descriptions
Bit
15-0
Field
LD_DLY
Type
Reset
Description
R/W
0x9C4
For the VCOCal lock detect, this is the delay in phase detector
cycles that is added after the calibration is finished before the
VCOCal lock detect is asserted high.
7.6.1.27 R69 Register (Address = 0x45) [reset = 0x0]
R69 is shown in Figure 57 and described in Table 48.
Return to Summary Table.
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Figure 57. R69 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MASH_RST_COUNT_31:16
R/W-0x0
Table 48. R69 Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
Upper 16 bits of MASH_RST_CNT.
MASH_RST_COUNT_31: R/W
16
0x0
7.6.1.28 R70 Register (Address = 0x46) [reset = 0xC350]
R70 is shown in Figure 58 and described in Table 49.
Return to Summary Table.
Figure 58. R70 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MASH_RST_COUNT
R/W-0xC350
Table 49. R70 Register Field Descriptions
Bit
15-0
Field
MASH_RST_COUNT
Type
Reset
Description
R/W
0xC350
MASH reset count is used to add a delay when using phase SYNC.
The delay should be set at least four times the PLL lock time. This
delay is expressed in state machine clock periods.\nOne of these
periods is equal to 2CAL_CLK_DIV/Fosc
7.6.1.29 R71 Register (Address = 0x47) [reset = 0x80]
R71 is shown in Figure 59 and described in Table 50.
Return to Summary Table.
Figure 59. R71 Register
15
7
14
13
5
12
11
10
2
9
1
8
0
RESERVED
R-0x0
6
4
3
SYSREF_DIV_PRE
SYSREF_PUL
SE
SYSREF_EN
SYSREF_REP
EAT
RESERVED
R-0x0
R/W-0x4
R/W-0x0
R/W-0x0
R/W-0x0
Table 50. R71 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-8
7-5
RESERVED
SYSREF_DIV_PRE
R/W
0x4
This divider is used to get the frequency input to the SYSREF
interpolater within accetable limits
4
3
SYSREF_PULSE
SYSREF_EN
R/W
R/W
0x0
0x0
When in master mode (SYSREF_REPEAT=0), this allows multiple
pulses (as determined by SYSREF_PULSE_CNT) to be sent out
whenever the SysRefReq pin goes high.
Enable SYREF mode.
0x0 = Disabled
0x1 = Enabled
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Table 50. R71 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
SYSREF_REPEAT
R/W
0x0
Defines the SYSREF mode.
0x0 = Master mode. In this mode, SYSREF pulses are generated
continuously at the output.
0x1 = Repeater Mode. In this mode, SYSREF pulses are generated
in respolse to the SysRefReq pin.
1-0
RESERVED
R
0x0
7.6.1.30 R72 Register (Address = 0x48) [reset = 0x1]
R72 is shown in Figure 60 and described in Table 51.
Return to Summary Table.
Figure 60. R72 Register
15
7
14
6
13
12
11
10
2
9
8
0
RESERVED
R-0x0
SYSREF_DIV
R/W-0x1
5
4
3
1
SYSREF_DIV
R/W-0x1
Table 51. R72 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-11
10-0
RESERVED
SYSREF_DIV
R/W
0x1
This divider further divides the output frequency for the SYSREF.
7.6.1.31 R73 Register (Address = 0x49) [reset = 0x3F]
R73 is shown in Figure 61 and described in Table 52.
Return to Summary Table.
Figure 61. R73 Register
15
14
13
5
12
11
10
9
8
0
RESERVED
R-0x0
JESD_DAC2_CTRL
R/W-0x0
7
6
4
3
2
1
JESD_DAC2_CTRL
R/W-0x0
JESD_DAC1_CTRL
R/W-0x3F
Table 52. R73 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-12
11-6
5-0
RESERVED
JESD_DAC2_CTRL
JESD_DAC1_CTRL
R/W
R/W
0x0
Programmable delay adjustment for SysRef mode
Programmable delay adjustment for SysRef mode
0x3F
7.6.1.32 R74 Register (Address = 0x4A) [reset = 0x0]
R74 is shown in Figure 62 and described in Table 53.
Return to Summary Table.
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Figure 62. R74 Register
15
7
14
13
12
11
10
9
8
0
SYSREF_PULSE_CNT
R/W-0x0
JESD_DAC4_CTRL
R/W-0x0
6
5
4
3
2
1
JESD_DAC4_CTRL
R/W-0x0
JESD_DAC3_CTRL
R/W-0x0
Table 53. R74 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
SYSREF_PULSE_CNT
R/W
0x0
Used in SYSREF_REPEAT mode to define how many pulses are
sent.
11-6
5-0
JESD_DAC4_CTRL
JESD_DAC3_CTRL
R/W
R/W
0x0
0x0
Programmable delay adjustment for SysRef mode
Programmable delay adjustment for SysRef mode
7.6.1.33 R75 Register (Address = 0x4B) [reset = 0x0]
R75 is shown in Figure 63 and described in Table 54.
Return to Summary Table.
Figure 63. R75 Register
15
7
14
6
13
12
11
10
2
9
8
0
RESERVED
R-0x0
CHDIV
R/W-0x0
5
4
3
1
CHDIV
RESERVED
R-0x0
R/W-0x0
Table 54. R75 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-11
10-6
RESERVED
CHDIV
R/W
0x0
Channel divider (Equivalent Division) controls divider value of each
segment of the channel divider
5-0
RESERVED
R
0x0
7.6.1.34 R110 Register (Address = 0x6E) [reset = 0x0]
R110 is shown in Figure 64 and described in Table 55.
Return to Summary Table.
Figure 64. R110 Register
15
7
14
13
12
11
10
2
9
1
8
RESERVED
R-0x0
rb_LD_VTUNE
R-0x0
RESERVED
R-0x0
6
5
4
3
0
rb_VCO_SEL
R-0x0
RESERVED
R-0x0
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Table 55. R110 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-11
10-9
RESERVED
rb_LD_VTUNE
R
0x0
Readback field for the lock detect.
0x0 = Unlocked (Fvco Low)
0x1 = Invalid
0x2 = Locked
0x3 = Unlocked (Fvco High)
8
RESERVED
rb_VCO_SEL
RESERVED
R
R
R
0x0
0x0
0x0
7-5
4-0
Readback
7.6.1.35 R111 Register (Address = 0x6F) [reset = 0x0]
R111 is shown in Figure 65 and described in Table 56.
Return to Summary Table.
Figure 65. R111 Register
7
6
5
4
3
2
1
0
rb_VCO_CAPCTRL
R-0x0
Table 56. R111 Register Field Descriptions
Bit
7-0
Field
rb_VCO_CAPCTRL
Type
Reset
Description
R
0x0
Readback field for the actual VCO_CAPCTRL value that is chosen
by the VCO calibration.
7.6.1.36 R112 Register (Address = 0x70) [reset = 0x0]
R112 is shown in Figure 66 and described in Table 57.
Return to Summary Table.
Figure 66. R112 Register
7
6
5
4
3
2
1
0
rb_VCO_DACISET
R-0x0
Table 57. R112 Register Field Descriptions
Bit
8-0
Field
rb_VCO_DACISET
Type
Reset
Description
R
0x0
Readback field for the actual VCO_DACISET value that is chosen by
the VCO calibration.
7.6.1.37 R113 Register (Address = 0x71) [reset = 0x0]
R113 is shown in Figure 67 and described in Table 58.
Return to Summary Table.
Figure 67. R113 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rb_IO_STATUS
R-0x0
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Table 58. R113 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reads back status of mode pins. <0> RECAL_EN, <1-8> Pin Modes
15-0
rb_IO_STATUS
R
0x0
7.6.1.38 R114 Register (Address = 0x72) [reset = 0x26F]
R114 is shown in Figure 68 and described in Table 59.
Return to Summary Table.
Figure 68. R114 Register
15
7
14
6
13
12
4
11
10
2
9
1
8
0
RESERVED
R-0x0
WD_DLY
R/W-0x4D
5
3
WD_DLY
WD_CNTRL
R/W-0x7
R/W-0x4D
Table 59. R114 Register Field Descriptions
Bit
Field
Type
R
Reset
0x0
Description
15-10
9-3
RESERVED
WD_DLY
R/W
0x4D
Delay for the internal watchdog timer. It is internally multiplied by 214
Default value is 25 ms with 50 MHz SM CLK.
.
2-0
WD_CNTRL
R/W
0x7
Watchdog Control
0x0 = Digital Watchdog disabled.
0x1 = Watchdog triggers 1 time
0x2 = Watchdog triggers up to 2 times
0x3 = Watchdog triggers up to 3 times
0x4 = Watchdog triggers up to 4 times
0x5 = Watchdog triggers up to 5 times
0x6 = Watchdog triggers up to 6 times
0x7 = Watchdog retriggers as many times as necessary with no limit.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 OSCin Configuration
OSCin supports single or differential-ended clock. There must be a AC -coupling capacitor in series before the
device pin. The OSCin inputs are high impedance CMOS with internal bias voltage. TI recommends putting
termination shunt resistors to terminate the differential traces (if there are 50-Ω characteristic traces, place 50-Ω
resistors). The OSCin and OSCin* side must be matched in layout. A series AC-coupling capacitors must
immediately follow OSCin pins in the board layout, then the shunt termination resistors to ground must be placed
after.
Input clock definitions are shown in 图 69:
VOSCin
VOSCin
VOSCin
CMOS
Sine wave
Differential
图 69. Input Clock Definitions
8.1.2 OSCin Slew Rate
The slew rate of the OSCin signal can have an impact on the spurs and phase noise of the LMX2615 if it is too
low. In general, the best performance is for a high slew rate, but lower amplitude signal, such as LVDS.
8.1.3 RF Output Buffer Power Control
The OUTA_PWR and OUTB_PWR registers control the amount of drive current for the output. This current
creates a voltage accross the pull-up component and load. It is generally recommended to keep the OUTx_PWR
setting at 31 or less as higher settings consume more current consumption and can also lead to higher output
power. Optimal noise floor is typically obtained by setting OUTx_PWR in the range of 15 to 25.
8.1.4 RF Output Buffer Pullup
The choice of output buffer components is very important and can have a profound impact on the output power.
The pull-up component can be a resistor or inductor or combination thereof. The signal swing is created is
created by a current this pull-up, so a higher impedance implies a higher signal swing. However, as this pull-up
component can be treated as if it is in parallel with the load impedance, there are diminishing returns as the
impedance gets much larger than the load impedance. The output impedance of the device varies as a function
of frequency and is a complex number, but typically has a magnitude on the order of 100 ohms, but this
decreases with frequency.
The output can be used differentially or single-ended. If using single-ended, the pullup is still needed, and user
needs to terminate the unused complimentary side such that the impedance as seen from the pin looking out is
similar to the pin that is being used. Following are some typical components that might be useful.
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Application Information (接下页)
表 60. Output Pullup Configuration
COMPONENT
VALUE
PART NUMBER
Toko LL1005-FH1N0S
Toko LL1005-FH3N3S
Toko LL1005-FH10NU
Vishay FC0402E50R0BST1
1 nH, 13.6 GHz SRF
3.3 nH, 6.8 GHz SRF
10 nH, 3.8 GHz SRF
50 Ω
Inductor
Resistor
ATC 520L103KT16T
ATC 504L50R0FTNCFT
Capacitor
Varies with frequency
8.1.4.1 Resistor Pullup
One strategy for the choice of the pull-up component is to a resistor (R). This is typically chosen to be 50-Ω and
under the assumption that the part output impedance is high, then the output impedance will theoretically be 50
ohms, regardless of output frequency. As the output impedance of the device is not infinite, the output
impedance when the pull-up resistor is used will be less than 50 ohms, but reasonably close. There will be some
drop across the resistor, but this does not seem to have a large impact on signal swing for a 50-Ω resistor
provided that OUTx_PWR≤31.
+vcc
R
C
RFoutAP
图 70. Resistor Pullup
8.1.4.2 Inductor Pullup
Another strategy is to choose an inductor pull-up (L). This allows a higher impedance without any concern of
creating any DC drop across the component. Ideally, the inductor should be chosen large enough so that the
impedance is high relative to the load impedance and also be operating away from its self-resonant frequency.
For instance, consider a 3.3 nH pull-up inductor with a self-resonant frequency of 7 GHz driving a 25-Ω spectrum
analyzer input. This inductor theoretically has j50-Ω input impedance around 2.4 GHz. At this frequency, this in
parallel with load is about j35-Ω, which is a 3 dB power reduction. At 1.4 GHz, this inductor has impedance of
about 29-Ω. This in parallel with the 50-Ω load has a magnitude of 25-Ω, which is the same as you would get
with the 50-Ω pull-up. The main issue with the inductor pull-up is the impedance does not look nicely matched to
the load.
+vcc
L
C
RFoutAP
图 71. Inductor Pullup
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As the output impedance is not so nicely matched, but there is higher output power, it makes sense to use a
resistive pad to get the best impedance control. A 6 dB pad (R1 =18-Ω, R2=68-Ω) is likely more attenuation than
necessary; 3 dB or even 1 dB might suffice. Two AC coupling capacitor is required before the pad. In the
configuration below, one of them is placed by the resistor to ground to minimize the number of components in the
high frequency path for lower loss.
+vcc
L
C
R1
R1
RFoutAP
R2
图 72. Inductor Pullup With Pad
For the resistive pad, here are some common values:
表 61. Resitive T-Pad Values
Attenuation
1 dB
R1
R2
2.7 Ω
5.6 Ω
6.8 Ω
12 Ω
15 Ω
18 Ω
420 Ω
220 Ω
150 Ω
100 Ω
82 Ω
2 dB
3 dB
4 dB
5 dB
6 dB
68 Ω
8.1.4.3 Combination Pullup
The resistor gives a good low frequency response, while the inductor gives a good high frequency response with
worse matching. It is desirable to have the impedance of the pull-up to be high, but if a resistor is used, then
there could be too much DC drop. If an inductor is used, it is hard to find one good at low frequencies and
around its self-resonant frequency. One approach to address this is to use a series resistor and inductor followed
by resistive pad.
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+vcc
R
L
R1
R1
RFoutAP
C
R2
图 73. Inductor and Resistor Pullup
8.1.5 RF Output Treatment for the Complimentary Side
Regardless of whether both sides of the differential outputs are used, both sides should see a similar load.
8.1.5.1 Single-Ended Termination of Unused Output
The unused output should see a roughly the same impedance as looking out of the pin to minimize harmonics
and get the best output power. As placement of the pull-up components is critical for the best output power, the
routing does not need to be perfectly symmetrical; it makes sense to give highest priority routing to the used
output (RFoutA in this case).
+vcc
R
L
R1
R1
RFoutAP
C
+vcc
R2
R
L
RFoutAP
RL
C
图 74. Termination of Unused Output
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8.1.5.2 Differential Termination
For differential termination this can be done by doing the same termination to both sides, or it is also possible to
connect the grounds together. This approach can also be accompanied by a differential to single-ended balun for
the highest possible output power.
R1
R1
RFoutAP
C
L
R
+vcc
2xR2
R
L
R1
R1
RFoutAM
C
图 75. Termination of Unused Output
8.2 Typical Application
C5
RFoutAP
Vcc
R37
50
Vcc
C30
U1
VCCBUF
L1
34
11
21
25
41
57
5
3
4
FS1
FS2
FS3
FS4
FS5
FS6
FS7
FS8
FS1
FS2
FS3
FS4
FS5
FS6
FS7
FS8
C27
1uF
18nH
C6
15
16
17
18
19
20
VCCDIG
VCCCP
C26
1uF
C29
1uF
0.01uF
VCCMASH
VCCVCO2
VCCVCO
CE
C18
1uF
R38
50
C23
1uF
37
36
RFOUTAP
RFOUTAM
C7
RFoutAM
RFoutBM
CE
39
27
26
C12
CSB
SDI
SCK
CSB
SDI
SCK
29
30
32
22
55
9
RFOUTBN/SYSREFOUTN
RFOUTBO/SYSREFOUTP
MUXOUT
C28
14
56
59
44
7
VREGIN
C22
1uF
C24
R40
50
MUXout
VREFVCO
VREGVCO
VREFVCO2
VBIASVCO
VBIASVCO2
VBIASVARAC
OSCINP
Vcc
CPOUT
L2
10uF
R4_LF
R3_LF
C20
1uF
C25
VTUNE
18nH
C11
C2_LF
R2_LF
SYNC
SYNC
10uF
C4_LF
C3_LF
C1_LF
43
C19
SYSREFREQ
SysRefReq
10uF
C21
0.01uF
C10
42
53
12
13
R39
50
45
52
RAMPCLK/TRIG1
RAMPDIR/TRIG2
RECAL_EN
RampDir
10uF
C14
RFoutBP
10uF
6
8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OSCINP
0.1uF
10
23
24
28
31
35
38
40
51
54
60
61
OSCINM
1
2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R32
100
33
46
47
48
49
50
58
62
63
64
C15
OSCINM
0.1uF
65
PAD
LMX2615W-MLS
图 76. Typical Application Schematic
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Typical Application (接下页)
8.2.1 Design Requirements
The design of the loop filter is complex and is typically done with software. The PLLatinum Sim software is an
excellent resource for doing this and the design is shown in图 77. For those interested in the equations involved,
the PLL Performance, Simulation, and Design Handbook (SNAA106) goes into great detail as to theory and
design of PLL loop filters.
图 77. PLLatinum Sim Tool
8.2.2 Detailed Design Procedure
The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to
signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise
outside the loop bandwidth is dominated by the VCO. Generally, jitter is lowest if loop bandwidth is designed to
the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop
bandwidth and thus lower jitter. The tradeoff with this is that longer lock times and spurs must be considered in
design as well.
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61
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www.ti.com.cn
Typical Application (接下页)
8.2.3 Application Curve
Using the settings described, the performance measured using a clean 100-MHz input reference is shown. Note
the loop bandwidth is about 350 kHz, as simulations predict.
-60
100 Hz -87.7 dBc/Hz 1 MHz -120.8 dBc/Hz
1 kHz -94.2 dBc/Hz 10 MHz -145.1 dBc/Hz
-70
10 kHz -103.3 dBc/Hz 20 MHz -146.0 dBc/Hz
100 kHz -110.4 dBc/Hz 95 MHz -154.8 dBc/Hz
-80
-90
-100
-110
-120
-130
-140
-150
10.4 GHz
4.9 dBm
-160
100 Hz
1 kHz
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Offset (Hz)
tc_P
图 78. Results for Loop Filter Design
9 Power Supply Recommendations
TI recommends placement of bypass capacitors close to the pins. Consult the EVM instructions for layout
examples. If fractional spurs are a large concern, using a ferrite bead to each of these power supply pins can
reduce spurs to a small degree. This device has integrated LDOs, which improves the resistance to power supply
noise. However, the pullup components on the RFoutA and RFoutB pins on the outputs have a direct connection
to the power supply, so extra care must be made to ensure that the voltage is clean for these pins.
10 Layout
10.1 Layout Guidelines
In general, the layout guidelines are similar to most other PLL devices. Here are some specific guidelines.
•
•
•
•
GND pins may be routed on the package back to the DAP.
The OSCin pins, these are internally biased and must be AC coupled.
If not used, the SysRefReq may be grounded to the DAP.
For optimal VCO phase noise in the 200kHz - 1 MHz range, it is ideal that the capacitor closest to the Vtune
pin be at least 3.3 nF. As requiring this larger capacitor may restrict the loop bandwidth, this value can be
reduced (to say 1.5 nF) at the expense of VCO phase noise.
•
•
For the outputs, keep the pullup component as close as possible to the pin and use the same component on
each side of the differential pair.
If a single-ended output is needed, the other side must have the same loading and pullup. However, the
routing for the used side can be optimized by routing the complementary side through a via to the other side
of the board. On this side, use the same pullup and make the load look equivalent to the side that is used.
•
•
Ensure DAP on device is well-grounded with many vias, preferably copper filled.
Have a thermal pad that is as large as the LMX2615 exposed pad. Add vias to the thermal pad to maximize
thermal performance.
•
Use a low loss dielectric material, such as Rogers 4350B, for optimal output power.
62
版权 © 2018, Texas Instruments Incorporated
LMX2615-SP
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ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
10.2 Layout Example
In addition to the layout guidelines already given, here are some additional comments for this specific layout
example
•
The most critical part of the layout that the placement of the pull-up components (R37, R38, R39, and R40) is
close to the pin for optimal output power.
•
For this layout, most of the loop filter (C1_LF, C2_LF, C3_LF, R2_LF, R3_LF, and R4_LF) are on the back
side of the board. However note that C4_LF is on the top side right next to the Vtune pin. In the event that
this C4_LF capacitor would be open, it is recommended to move one of loop capacitors in this spot. For
instance, if a 3rd order loop filter was used, technically C3_LF would be non-zero and C4_LF would be open.
However, for this layout example that is designed for a 4th order loop filter, it would be optimal to make
R3_LF = 0 ohm, C3_LF = open, and C4_LF to be whatever C3_LF would have been.
图 79. LMX2615 Layout Example
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63
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
www.ti.com.cn
10.3 Footprint Example on PCB Layout
64
49
8.00
1
48
0.5
8.00
0.30
7.175
Thermal pad
16
33
Device outline
2.15
17
32
1. All dimensions in millimeters.
2. Top view
图 80. LMX2615 PCB Layout
10.4 Radiation Environments
Careful consideration must be given to environmental conditions when using a product in a radiation
environment.
10.4.1 Total Ionizing Dose
Radiation Hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level
specified in the ordering information. Testing and qualification of these product is done on a wafer level according
to MIL-STD-883, test method 1019. Wafer level TID data are available with lot shipments.
10.4.2 Single Event Effect
One time single event effect (SEE), including single event latch-up (SEL), single event functional interrupt (SEFI)
and single event upset (SEU), testing was performed according to EIA/JEDEC Standard, EIA/JEDEC57. A test
report is available upon request.
64
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LMX2615-SP
www.ti.com.cn
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 开发支持
德州仪器 (TI) 在 www.ti.com.cn 提供了多种辅助开发的软件工具。其中包括:
•
•
•
EVM 软件,用于了解如何对器件和 EVM 板进行编程。
EVM 板说明,用于了解典型测量数据、详细测量条件以及完整设计的信息。
PLLatinum Sim 程序,用于设计回路滤波器以及对相位噪声和杂散进行仿真。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档:
•
•
《AN-1879 分数 N 频率合成》(SNAA062)
《PLL 性能、仿真和设计手册》(SNAA106)
11.3 商标
All trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
12.1 工程样片
工程样片 (LMX2615W-MPR) 具有与运行器件 (LMX2615W-MLS) 相同的封装、引脚、编程和典型性能。这些器件
在室温下经过测试,符合电气规范,但尚未经历或通过全面的生产流程或测试。工程样片可能被 QCI 拒绝,无法通
过全面的生产测试(如辐射或可靠性测试)。
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65
LMX2615-SP
ZHCSIC4C –JUNE 2018–REVISED NOVEMBER 2018
12.2 封装机械信息
www.ti.com.cn
图 81. 封装机械信息
66
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
14
1
(1)
(2)
(3)
(4/5)
(6)
5962R1723601VXC
LMX2615-MKT-MS
LMX2615W-MPR
ACTIVE
CFP
CFP
CFP
HBD
64
64
64
RoHS & Green
TBD
NIAU
Level-1-NA-UNLIM
Call TI
-55 to 125
25 to 25
25 to 25
5962R1723601VXC
LMX2615WRQMLV
Samples
Samples
Samples
ACTIVE
ACTIVE
HBD
Call TI
NIAU
LMX2615-MKT-MS
MECHANICAL
HBD
14
RoHS & Green
Level-1-NA-UNLIM
LMX2615W-MPR
ENG SAMPLE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962R1723601VXC
LMX2615W-MPR
HBD
HBD
CFP (HSL)
CFP (HSL)
64
64
14
14
495
495
33
33
11176
11176
16.51
16.51
Pack Materials-Page 1
PACKAGE OUTLINE
HBD0064A
CFP - 2.31 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
11.03
10.77
49
64
SEAL RING
4X
(R0.75)
0.27
0.17
64X
1
48
10.16
0.08
4X 7.5 0.13
16
33
60X 0.5 0.05
4X (45 X 0.3)
3.99 0.25
TYP
32
17
1.25 0.13
(0.3)
(0.2) TYP
2.31 MAX
(0.73) TYP
0.5 0.1
64X 0.15 0.05
(
8)
HEAT SINK
17
32
16
33
SYMM
8
0.13
HEAT SINK
1
48
PIN 1 ID
64
49
SYMM
BOTTOM VIEW
4223243/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid.
4. Ground pad to be electronic connected to heat sink and seal ring.
5. The leads are gold plated and can be solder dipped.
www.ti.com
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