LMZ21700 [TI]

采用 3.5mm × 3.5mm 封装的 3V 至 17V、0.65A 降压直流/直流电源模块;


型号：	LMZ21700
厂家：	TEXAS INSTRUMENTS
描述：	采用 3.5mm × 3.5mm 封装的 3V 至 17V、0.65A 降压直流/直流电源模块电源电路
文件：	总36页 (文件大小：1845K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

具有 17V 最大输入电压的 LMZ21700 650mA 微型模块

1 特性

2 应用

•

集成电感

•

3.3V、5V 或 12V 输入电压的

负载点转换

微型 3.5mm × 3.5mm × 1.75mm 封装

35 mm² Solution Size (Single Sided)

–40°C 至 125°C 结温范围

可调输出电压

•

空间受限型应用

低压降稳压器 (LDO) 替代产品

3 说明

集成补偿

LMZ21700 微型模块是易于使用的降压直流/直流解决

方案，可在空间受限的应用中驱动高达 650mA 的负

载。仅需一个输入电容器、一个输出电容器、一个软启

动电容器和两个电阻器即可完成基本操作。

可调软启动功能

启动至预偏置负载

电源正常状态和使能引脚

节能模式无缝转换

输出电流高达 650 mA

输入电压范围为 3V 至 17V

输出电压范围为 0.9V 到 6V

效率高达 95 %

典型应用快速链接：V_OUT= 1.2 V、V_OUT= 1.8 V、

V_OUT= 2.5 V、V_OUT= 3.3 V、V_OUT= 5.0 V

器件信息⁽¹⁾

器件型号

LMZ21700

封装

µSIP (8)

封装尺寸（标称值）

1.5µA 关断电流

3.50mm x 3.50mm

17µA 静态电流

使用 LMZ21700 并借助 WEBENCH^®电源设计器

创建定制设计

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

空白

简化原理图

V_IN= 12V 时的效率

V_IN

V_OUT

100

VIN

VOUT

LMZ21700

OUT

VOS

FBT

GND

FBB

VOUT = 1.2 V

VOUT = 1.8 V

VOUT = 2.5 V

VOUT = 3.3 V

VOUT = 5 V

0.0001

0.001

0.01

0.1

Output Current (A)

D023

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVS872

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

8.1 Application Information............................................ 11

8.2 Typical Application ................................................. 11

8.3 Do's and Don'ts ...................................................... 24

Power Supply Recommendations...................... 24

9.1 Voltage Range ........................................................ 24

9.2 Current Capability ................................................... 24

9.3 Input Connection .................................................... 24

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Handling Ratings....................................................... 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics.............................................. 6

Detailed Description .............................................. 8

7.1 Overview ................................................................... 8

7.2 Functional Block Diagram ......................................... 8

7.3 Package Construction............................................... 9

7.4 Feature Description................................................... 9

7.5 Device Functional Modes........................................ 11

Application and Implementation ........................ 11

10 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 25

10.2 Layout Example .................................................... 26

11 器件和文档支持 ..................................................... 29

11.1 器件支持 ............................................................... 29

11.2 开发支持 ............................................................... 29

11.3 接收文档更新通知 ................................................. 29

11.4 社区资源................................................................ 29

11.5 商标....................................................................... 29

11.6 静电放电警告......................................................... 29

11.7 术语表 ................................................................... 29

12 机械、封装和可订购信息....................................... 30

12.1 Tape and Reel Information ................................... 30

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (November 2014) to Revision D

Page

•

删除了 Simple Switcher 品牌；添加了 TI 参考设计顶部导航图标、Webench 链接和 T&R 内容........................................... 1

Changes from Revision B (October 2014) to Revision C

Page

•

已更改将“产品概述”更改成了“生产数据” ................................................................................................................................ 1

Changed to Final Limits ......................................................................................................................................................... 5

Changes from Revision A (October 2013) to Revision B

Page

•

已添加添加了“器件信息”表和“处理额定值”表、“特性说明”、“应用和实施”、“布局”、“器件和文档支持”以及“机械、封

装和可订购信息”，将一些曲线移到了“应用曲线”中................................................................................................................. 1

已将数据表更改为最新 TI 标准 ............................................................................................................................................... 1

Changes from Original (August 2012) to Revision A

Page

•

已更改说明............................................................................................................................................................................. 1

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

5 Pin Configuration and Functions

Figure 1. LMZ21700 in the SIL0008E Package

SIL0008E

8-Pin

Top View

TOP

VIN

PAD

(GND)

PAD

(GND)

VOS

GND

VOUT

Table 1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Soft-start pin. An external capacitor connected to this pin sets the internal voltage reference

ramp time. It can be used for tracking and sequencing.

Voltage feedback. Connect resistive voltage divider to this pin to set the output voltage.

Output power good (High = VOUT ready, Low = VOUT below nominal regulation); open drain

(requires pull-up resistor; goes low impedance when EN is low)

Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter

capacitor between VOUT and PGND.

VOUT

GND

VOS

Ground for the power MOSFETs and gate-drive circuitry.

Output voltage sense pin and connection for the control loop circuitry.

Enable input (High = enabled, Low = disabled). Internal pull down resistor keeps logic level

low if pin is left floating

VIN

PAD

Supply voltage for control circuitry and power stage.

Electrically connected to GND. Must be soldered to a ground copper plane to achieve

appropriate power dissipation and mechanical reliability.

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

MAX

UNIT

VIN

−0.3

VIN +0.3 V

w/ 20 V

max

EN, SS

−0.3

FB, PG, VOS

PG sink current

°C

Junction Temperature (T_J-MAX

)

−40

125

260

Maximum Lead Temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

6.2 Handling Ratings

MIN

−65

MAX

150

UNIT

T_stg

Storage temperature range

°C

Human body model (HBM),

−2000

2000

per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM),

−500

500

per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

Input Voltage Range

0.9

Output Voltage Range

6.0

Recommended Load Current

Junction Temperature (T_J)

650

125

°C

−40

(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits.

For guaranteed specifications, see the Electrical Characteristics section.

6.4 Thermal Information

LMZ21700

THERMAL METRIC⁽¹⁾

SIL0008E

8 PINS

42.6

20.8

9.4

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.5

ψ_JB

9.3

R_θJC(bot)

1.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) Junction-to-ambient thermal resistance (θ_JA) is based on 4 layer board thermal measurements, performed under the conditions and

guidelines set forth in the JEDEC standards JESD51-1 to JESD51-11. θ_JAvaries with PCB copper area, power dissipation, and airflow.

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

6.5 Electrical Characteristics⁽¹⁾

Limits apply over the recommended operating junction temperature (T_J) range of -40 °C to +125 °C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 12 V.

PARAMETER

SYSTEM PARAMETERS

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX⁽¹⁾

UNIT

I_Q

Operating quiescent current

EN = high, I_OUT= 0 mA, T_J= -40°C to

85°C

μA

device not switching

EN = high, I_OUT= 0 mA, T_J= -40°C to

125°C

device not switching

I_SD

Shutdown current

EN = low, T_J= -40 °C to 85 °C

EN = low, T_J= -40 °C to 125 °C

1.5

μA

VIN_UVLO

Input under voltage lock out

rising threshold

2.8

2.9

VIN_UVLO-HYS

Input under voltage lock out

hysteresis

0.125

0.180

0.260

T_SD

Thermal shutdown

Rising Threshold

160

°C

T_SD-HYST

CONTROL

V_{IH, ENABLE}

V_{IL, ENABLE}

I_LKG

Thermal shutdown hysteresis

Enable logic HIGH voltage

Enable logic LOW voltage

Input leakage current

0.9

0.3

EN = VIN or GND

0.01

95 %

90 %

0.07

μA

V_{TH_PG}

Power Good threshold voltage

Rising (% V_OUT

)

92 %

87 %

98 %

93 %

0.3

Falling (% V_OUT

)

V_{OL_PG}

Power Good output low voltage

Power Good leakage current

Softstart Pin source current

I_PG= -2 mA

I_{LKG_PG}

V_PG= 1.8 V

400

2.8

μA

I_SS

2.2

2.5

POWER STAGE

R_DS(ON)

High-Side MOSFET ON

Resistance

V_IN≥ 6 V

V_IN= 3 V

V_IN≥ 6 V

V_IN= 3 V

120

mΩ

Low-Side MOSFET ON

Resistance

Integrated power inductor value

2.2

μH

DCR

Integrated power inductor DC

resistance

mΩ

I_CL-HS

I_CL-LS

I_CL-DC

OUTPUT

V_REF

High-Side MOSFET Current Limit T_A= 25 °C

Low-Side MOSFET Current Limit T_A= 25 °C

1.2

1.5

0.9

1.9

Output (DC) current limit

V_OUT= 5.0 V, T_A= 85 °C

0.95

Internal reference voltage

0.7869

-2.3 %

0.803

0.8191

100

I_FB

Feedback pin leakage current

V_FB= 0.8V

V_OUT

Light load initial voltage accuracy Power save mode, C_OUT= 22 µF,

T_A= -40 °C to 85 °C, 1% FB

Resistors

2.8 %

V_OUT

Load regulation

V_OUT= 3.3 V

PWM mode operation

0.05 %

/ A

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely parametric norm.

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

Electrical Characteristics⁽¹⁾(continued)

Limits apply over the recommended operating junction temperature (T_J) range of -40 °C to +125 °C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at T_J= 25 °C, and are provided for reference purposes only. Unless otherwise stated the following

conditions apply: V_IN= 12 V.

PARAMETER

TEST CONDITIONS

MIN⁽¹⁾

TYP⁽²⁾

MAX⁽¹⁾

UNIT

V_OUT

Line regulation

3 V ≤ V_IN≤ 17 V, V_OUT= 3.3 V, I_OUT

= 650 mA

0.02 %

/ V

PWM mode operation

SYSTEM CHARACTERISTICS

Full Load Efficiency

Light Load Efficiency

V_OUT= 3.3 V, I_OUT= 650 mA

V_OUT= 3.3 V, I_OUT= 1 mA

88 %

72 %

6.6 Typical Characteristics

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25 °C

100

0.5

0.4

0.3

0.2

0.1

2-LAYER 70 µm (2 oz) Cu

4-LAYER 70 µm (2 oz) Cu

VIN = 3.3 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Copper Area (cm²)

Load Current (A)

D012

005

V_OUT= 1.2 V

T_A= 85 ºC

Figure 2. Package Thermal Resistance vs. Board Copper

Area, No Air Flow

Figure 3. Power Dissipation

0.5

0.4

0.3

0.2

0.1

VIN = 3.3 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 3.3 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Load Current (A)

D006

D007

V_OUT= 1.8 V

T_A= 85 ºC

V_OUT= 2.5 V

T_A= 85 ºC

Figure 4. Power Dissipation

Figure 5. Power Dissipation

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

Typical Characteristics (continued)

Unless otherwise specified the following conditions apply: V_IN= 12 V, T_A= 25 °C

0.5

0.4

0.3

0.2

0.1

0.5

0.4

0.3

0.2

0.1

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Load Current (A)

D008

D009

V_OUT= 3.3 V

T_A= 85 ºC

V_OUT= 5.0 V

T_A= 85 ºC

Figure 6. Power Dissipation

Figure 7. Power Dissipation

IOUT = 0.2 A

IOUT = 0.4 A

IOUT = 0.65 A

IOUT = 0.2 A

IOUT = 0.4 A

IOUT = 0.65 A

3.8

3.6

3.4

3.2

5.5

4.5

2.8

2.6

2.4

2.2

3.5

4.5

5.5

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

Input Voltage (V)

D011

D010

V_OUT= 5.0 V

T_A= 85 ºC

V_OUT= 3.3 V

T_A= 85 ºC

Figure 8. Dropout

Figure 9. Dropout

100

Peak Emissions

Quasi Peak Limit

Average Limit

Evaluation Board

EN 55022 Class B Limit

EN 55022 Class A Limit

200

400

600

800

1000

0.1

100

Frequency (MHz)

D002

D001

V_IN= 12 V

V_OUT= 3.3 V

I_OUT= 650 mA

V_IN= 12 V

Lf = 2.2 µH

V_OUT= 3.3 V

Cf = 1.0 µF

I_OUT= 650 mA

Figure 10. Radiated EMI on EVM

Figure 11. Conducted EMI on EVM

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

7 Detailed Description

7.1 Overview

The LMZ21700 SIMPLE SWITCHER^®Nano Module is an easy-to-use step-down DC-DC solution capable of

driving up to 650 mA load in space-constrained applications. Only an input capacitor, an output capacitor, a

softstart capacitor, and two resistors are required for basic operation. The Nano Module comes in 8-pin DFN

footprint package with an integrated inductor. The LMZ21700 architecture is based on DCS-Control™ (Direct

Control with Seamless Transition into Power Save Mode). This architecture combines the fast transient response

and stability of hysteretic type converters along with the accurate DC output regulation of voltage mode and

current mode regulators.

The LMZ21700 architecture uses Pulse Width Modulation (PWM) mode for medium and heavy load requirements

and Power Save Mode (PSM) at light loads for high efficiency. In PWM mode the switching frequency is

controlled over the input voltage range. The value depends on the output voltage setting and is typically reduced

at low output voltages to achieve higher efficiency. In PSM the switching frequency decreases linearly with the

load current. Since the architecture of the device supports both operation modes (PWM and PSM) in a single

circuit building block, the transition between the modes of operation is seamless with minimal effect on the output

voltage.

7.2 Functional Block Diagram

HIGH SIDE

INDUCTOR

SWITCH

VIN

VOUT

2.2µH

HIGH SIDE

CURRENT

LIMIT

LDO

BYPASS

5V LDO

UVLO

HIGH SIDE DRIVER

WITH INTERNAL BOOTSTRAP

LOW SIDE

DRIVER

LOW SIDE

SWITCH

400kΩ

CONTROL LOGIC

LOW SIDE

CURRENT

LIMIT

ZERO

CURRENT

DETECT

THERMAL

SHUTDOWN

SOFTSTART

CURRENT AND

TRACKING

VOS

DIRECT CONTROL

COMPENSATION

t_ONTIMER

6.6V

CLAMP

25pF

C_FF

GND

COMPARATOR

VREF

ERROR

AMPLIFIER

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

7.3 Package Construction

In order to achieve a small solution size the LMZ21700 Nano Module comes in an innovative MicroSiP™

package. The construction consists of a synchronous buck converter IC embedded inside an FR-4 laminate

substrate, with a power inductor mounted on top of the substrate material. See Figure 12 and Figure 13 below.

The bottom (landing pads) of the package resemble a typical 8-pin DFN package. See the Mechanical drawings

at the end of the datasheet for details on the recommended landing pattern and solder paste stencil information.

Figure 12. LMZ21700 in the SIL0008E Package

INDUCTOR

FR-4 LAMINATE

BOTTOM

SUBSTRATE

COPPER PATTERN

EMBEDDED BUCK IC

Figure 13. LMZ21700 Package Construction Cross Section

(Illustration Only, Not to Scale)

7.4 Feature Description

7.4.1 Input Under Voltage Lockout

The LMZ21700 features input under voltage lockout (UVLO) circuit. It monitors the input voltage level and

prevents the device from switching the power MOSFETs if V_INis not high enough. The typical V_INUVLO rising

threshold is 2.9 V with 180 mV of hysteresis.

LMZ21700

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www.ti.com.cn

Feature Description (continued)

7.4.2 Enable Input (EN)

The enable pin (EN) is weakly pulled down internally through a 400 kΩ resistor to keep EN logic low when the

pin is floating. The pull-down resistor is not connected when EN is set high. Once the voltage on the enable pin

(EN) is set high the Nano Module will start operation. If EN is set low ( < 0.3 V ) the LMZ21700 will enter

shutdown mode. The typical shutdown quiescent current is 1.5 μA.

7.4.3 Softstart and Tracking Function (SS)

When EN is set high for device operation the LMZ21700 will start switching after 50 μs delay and the output

voltage will start rising. The V_OUTrising slope is controlled by the external capacitor C_SSconnected to the

softstart (SS) pin. The nano module has a 2.5 μA constant current source internally connected to the SS pin to

program the softstart time T_SS

T_SS= C_SSx 1.25 V / 2.5 μA

(1)

The softstart capacitor voltage is reset to zero volts when EN is pulled low and when the thermal protection is

active.

If tracking function is desired, the SS pin can be used to track external voltage. If the applied external tracking

voltage is between 100 mV and 1.2 V, the FB voltage will follow SS according to the following relationship:

V_FB= 0.64 x V_SS

(2)

7.4.4 Power Good Function (PG)

The LMZ21700 features a Power Good (PG) function which can be used for sequencing of multiple rails. The PG

pin is an open-drain output and requires a pull-up resistor R_PGto V_OUT(or any other external voltage less than 7

V). When the Nano Module is enabled and UVLO is satisfied, the power good function starts monitoring the

output voltage. The PG pin is kept at logic low if the output has not reached the proper regulation voltage. Refer

to the Electrical Characteristics table for the PG voltage thresholds. The PG pin can sink 2 mA of current which

sets the minimum limit of the R_PGresistance value:

R_PG-MIN= V_PULL-UP/ 2 mA

(3)

The PG pin goes low impedance if the device is disabled or the thermal protection is active.

7.4.5 Output Voltage Setting

The output voltage of the LMZ21700 is set by a resistive divider from V_OUTto GND, connected to the feedback

(FB) pin. The output voltage can be set between 0.9 V and 6 V. The voltage at the FB pin is regulated to 0.8 V.

The recommended minimum divider current is 2 μA. This sets a maximum limit on the bottom feedback resistor

R_FBB. Its value should not exceed 400 kΩ. The top feedback resistor R_FBTcan be calculated using the following

formula:

R_FBT= R_FBBx (V_OUT/ 0.8 – 1)

(4)

7.4.6 Output Current Limit and Output Short Circuit Protection

The LMZ21700 has integrated protection against heavy loads and output short circuit events. Both, the high-side

FET and low-side FET have current monitoring circuitry. If the current limit threshold of the high-side FET is

reached , the high-side FET will be turned off and the low-side FET will be turned on to ramp down the inductor

current. Once the current through the low-side FET has decreased below a safe level, the high-side device will

be allowed to turn on again. The actual DC output current depends on the input voltage, output voltage, and

switching frequency. Refer to the Application Curves section for more information.

7.4.7 Thermal Protection

The nano module monitors its junction temperature (Tj) and shuts itself off if the it gets too hot. The thermal

shutdown threshold for the junction is typically 160 °C. Both, high-side and low-side FETs are turned off until the

junction temperature has decreased under the hysteresis level, typically 30 °C below the shutdown temperature.

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

7.5 Device Functional Modes

7.5.1 PWM Mode Operation

The LMZ21700 operates in PWM mode when the output current is greater than half the inductor ripple current.

The frequency variation in PWM mode is controlled and depends on the V_INand V_OUTsettings. Refer to the

Application Curves section for switching frequency graphs for several typical output voltage settings. As the load

current is decreased and the valley of the inductor current ripple reaches 0 A the device enters PSM operation to

maintain high efficiency.

7.5.2 PSM Operation

Once the load current decreases and the valley of the inductor current reaches 0 A, the LMZ21700 will transition

to Power Save Mode of operation. The device will remain in PSM as long as the inductor current is

discontinuous. The switching frequency will decrease linearly with the load current. If V_INdecreases to about

15 % above V_OUTthe device will not enter PSM and will maintain output regulation in PWM mode.

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMZ21700 is a step down DC-to-DC converter. It is used to convert higher DC voltage to a regulated lower

DC voltage with maximum load current of 650 mA. The following design procedure can be used to select

components for the LMZ21700. Alternatively, the WEBENCH^®software can be used to select from a large

database of components, run electrical simulations, and optimize the design for specific performance. Please go

to webench.ti.com to access the WEBENCH^®tool.

8.2 Typical Application

For a quick start, the following component values can be used as a design starting point for several typical output

voltage rails and 650 mA of output load current.

V_OUT

V_IN

COMPONENT VALUES FOR VOUT=1.2V

VIN

VOUT

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

LMZ21700

3300pF

41.2kꢀ

82.5kꢀ

10kꢀ

OUT

VOS

FBT

FBB

FBT

GND

FBB

Figure 14. Typical Applications Circuit

Figure 15. External Component Values

( V_OUT= 1.2 V )

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

Typical Application (continued)

COMPONENT VALUES FOR VOUT=1.8V

COMPONENT VALUES FOR VOUT=2.5V

22µF

≥ 25V

≥ 10V

X7R or X5R

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

OUT

22µF

3300pF

147kꢀ

118kꢀ

10kꢀ

3300pF

357kꢀ

169kꢀ

10kꢀ

FBT

FBB

FBT

FBB

Figure 16. External Component Values

( V_OUT= 1.8 V )

Figure 17. External Component Values

( V_OUT= 2.5 V )

COMPONENT VALUES FOR VOUT=3.3V

COMPONENT VALUES FOR VOUT=5.0V

22µF

≥ 25V

≥ 10V

X7R or X5R

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

OUT

22µF

3300pF

1.21Mꢀ

383kꢀ

10kꢀ

3300pF

232kꢀ

44.2kꢀ

10kꢀ

FBT

FBB

FBT

FBB

Figure 18. External Component Values

( V_OUT= 3.3 V )

Figure 19. External Component Values

( V_OUT= 5.0 V )

8.2.1 Design Requirements

The design procedure requires a few typical design parameters. See Table 2 below.

Table 2. Design Parameters

Design Parameter

Input Voltage (V_IN

Output Voltage (V_OUT

Output Current (I_OUT

Softstart time (T_SS

Value

)

Range from 3.0 V to 17 V

Range from 0.9 V to 6 V

Up to 650 mA

)

Minimum of 0.5 ms recommended

8.2.2 Detailed Design Procedure

8.2.2.1 Input Capacitor (C_IN)

Low ESR multi-layer ceramic capacitors (MLCC) are recommended for the input capacitor of the LMZ21700.

Using a ≥ 10 µF ceramic input capacitor in ≥ 0805 (2012 metric) case size with 25 V rating typically provides

sufficient VIN bypass. Use of multiple capacitors can also be considered. Ceramic capacitors with X5R and X7R

temperature characteristics are recommended. These provide an optimal balance between small size, cost,

reliability, and performance for applications with limited space. The DC voltage bias characteristics of the

capacitors must be considered when selecting the DC voltage rating and case size of these components. The

effective capacitance of an MLCC is typically reduced by the DC voltage bias applied across its terminals.

Selecting a part with larger capacitance, larger case size, or higher voltage rating can compensate for the

capacitance loss due to the DC voltage bias effect. For example, a 10 µF, X7R, 25 V rated capacitor used under

12 V DC bias may have approximately 8 µF effective capacitance in a 1210 (3225 metric) case size and about 6

µF in a 1206 (3216 metric) case size. As another example, a 10 µF, X7R, 16 V rated capacitor in a 1210 (3225

metric) case size used at 12 V DC bias may have approximately 5.5 µF effective capacitance. Check the

capacitor specifications published by the manufacturer.

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

8.2.2.2 Output Capacitor (C_OUT

)

Similarly to the input capacitor, it is recommended to use low ESR multi-layer ceramic capacitors for C_OUT

Ceramic capacitors with X5R and X7R temperature characteristics are recommended. Use 10 µF or larger value

and consider the DC voltage bias characteristics of the capacitor when choosing the case size and voltage

rating. For stability, the output capacitor should be in the 10 µF – 200 µF effective capacitance range.

8.2.2.3 Softstart Capacitor (C_SS

)

The softstart capacitor is chosen according to the desired softstart time. As described in the Softstart and

Tracking Function section the softstart time T_SS= C_SSx 1.25 V / 2.5 μA.

A minimum C_SSvalue of 1000 pF is required for monotonic V_OUTramp up.

8.2.2.4 Power Good Resistor (R_PG

)

If the Power Good function is used, a pull up resistor R_PGis necessary from the PG pin to an external pull-up

voltage.

The minimum R_PGvalue is restricted by the pull down current capability of the internal pull down device.

R_PG-MIN= V_PULL-UP/ 2 mA

(5)

The maximum R_PGvalue is based on the maximum PG leakage current and the minimum “logic high” level

system requirements:

R_PG-MAX= (V_PULL-UP– V_LOGIC-HIGH) / I_{LKG_PG}

(6)

8.2.2.5 Feedback Resistors (R_FBBand R_FBT

)

The feedback resistors R_FBBand R_FBTset the desired output voltage. Choose R_FBBless than 400 kΩ and

calculate the value for R_FBTusing the following formula:

R_FBT= R_FBBx (V_OUT/ 0.8 – 1)

(7)

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

8.2.3 Application Curves

8.2.3.1 V_OUT= 1.2 V

V_OUT

V_IN

COMPONENT VALUES FOR VOUT=1.2V

VIN

VOUT

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

LMZ21700

3300pF

41.2kꢀ

82.5kꢀ

10kꢀ

OUT

VOS

FBT

FBB

FBT

GND

FBB

Figure 20. Typical Applications Circuit

Figure 21. External Component Values

(V_OUT= 1.2V)

100

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0001

0.001

0.01

Load Current (A)

0.1

Load Current (A)

C001

D013

Figure 23. Power Dissipation V_OUT= 1.2V

Figure 22. Efficiency V_OUT= 1.2V

ILOAD 500mA/Div

PGOOD 1V/Div

ILOAD 500mA/Div

VOUT 20mV/Div AC

1ms/Div

VOUT 500mV/Div

ENABLE 500mV/Div

1ms/Div

20MHz BW

Figure 24. Load Transient V_OUT= 1.2V

Figure 25. Startup V_OUT= 1.2V

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

COUT1 = 22ꢀF 10V 0805 X5R

Taiyo Yuden MK212BJ226MG-T

VOUT RIPPLE

COUT = 22ꢀF 10V 0805 X5R

WITH 500MHz SCOPE BANDWIDTH

COUT2 = 3x1000pF 0805 NP0

Johanson Dielectrics 500R15N102JV4T

Taiyo Yuden MK212BJ226MG-T

50mV/Div

10mV/Div

1µs/Div

20MHz BW

500MHz BW

1µs/Div

Figure 26. 20MHz Oscilloscope Bandwidth

Output Voltage Ripple V_OUT= 1.2V

Figure 27. 500MHz Oscilloscope Bandwidth, 3x1000pF

additional output capacitance

Output Voltage Ripple and HF Noise V_OUT= 1.2V

2.5

2.0

1.5

1.0

0.5

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VOUT=1.2V

INPUT VOLTAGE (V)

C001

Figure 28. Typical Switching Frequency at 650mA Load

V_OUT= 1.2V

Figure 29. Typical Current Limit V_OUT= 1.2V, T_A= 85 °C

1.206

1.204

1.202

1.2

0.7

0.6

0.5

0.4

0.3

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

1.198

1.196

1.194

1.192

1.19

0.2

VIN = 3.3 V

VIN = 5 V

VIN = 12 V

VIN = 17 V

0.1

0.0

100

110

120

130

0.0001

0.001

0.01

Load Current (A)

0.1

Ambient Temperature (°C)

C001

D014

Figure 31. Thermal Derating for θ_JA= 47 ºC/W, V_OUT= 1.2V

Figure 30. Line and Load Regulation V_OUT= 1.2V

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

8.2.3.2 V_OUT= 1.8 V

V_OUT

V_IN

COMPONENT VALUES FOR VOUT=1.8V

VIN

VOUT

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

LMZ21700

3300pF

147kꢀ

118kꢀ

10kꢀ

OUT

VOS

FBT

FBB

FBT

GND

FBB

Figure 32. Typical Applications Circuit

Figure 33. External Component Values

(V_OUT=1.8V)

100

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0001

0.001

0.01

Load Current (A)

0.1

Load Current (A)

C001

D015

Figure 35. Power Dissipation V_OUT= 1.8 V

Figure 34. Efficiency V_OUT= 1.8 V

ILOAD 500mA/Div

PGOOD 1V/Div

ILOAD 500mA/Div

VOUT 1V/Div

VOUT 20mV/Div AC

ENABLE 500mV/Div

1ms/Div

20MHz BW

1ms/Div

20MHz BW

Figure 37. Startup V_OUT= 1.8 V

Figure 36. Load Transient V_OUT= 1.8 V

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

COUT1 = 22ꢀF 10V 0805 X5R

Taiyo Yuden MK212BJ226MG-T

VOUT RIPPLE

COUT = 22ꢀF 10V 0805 X5R

WITH 500MHz SCOPE BANDWIDTH

COUT2 = 3x1000pF 0805 NP0

Johanson Dielectrics 500R15N102JV4T

Taiyo Yuden MK212BJ226MG-T

10mV/Div

50mV/Div

1µs/Div

20MHz BW

500MHz BW

1µs/Div

Figure 38. 20MHz Oscilloscope Bandwidth

Output Voltage Ripple V_OUT= 1.8 V

Figure 39. 500MHz Oscilloscope Bandwidth, 3x1000pF

additional output capacitance

Output Voltage Ripple and HF Noise V_OUT= 1.8 V

2.5

2.0

1.5

1.0

0.5

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VOUT=1.8V

INPUT VOLTAGE (V)

C001

Figure 40. Typical Switching Frequency at 650mA Load

V_OUT= 1.8 V

Figure 41. Typical Current Limit V_OUT= 1.8 V, T_A= 85 °C

1.81

1.808

1.806

1.804

1.802

1.8

0.7

0.6

0.5

0.4

0.3

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

1.798

1.796

1.794

1.792

1.79

0.2

VIN = 3.3 V

VIN = 5 V

VIN = 12 V

VIN = 17 V

0.1

0.0

100

110

120

130

0.0001

0.001

0.01

Load Current (A)

0.1

Ambient Temperature (°C)

C001

D016

Figure 43. Thermal Derating for θ_JA=47ºC/W, V_OUT= 1.8 V

Figure 42. Line and Load Regulation V_OUT= 1.8 V

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

8.2.3.3 V_OUT= 2.5 V

V_OUT

V_IN

COMPONENT VALUES FOR VOUT=2.5V

VIN

VOUT

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

LMZ21700

3300pF

357kꢀ

169kꢀ

10kꢀ

OUT

VOS

FBT

FBB

FBT

GND

FBB

Figure 44. Typical Applications Circuit

Figure 45. External Component Values

(V_OUT= 2.5 V)

100

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0001

0.001

0.01

Load Current (A)

0.1

Load Current (A)

C001

D017

Figure 47. Power Dissipation V_OUT= 2.5 V

Figure 46. Efficiency V_OUT= 2.5 V

ILOAD 500mA/Div

PGOOD 2V/Div

ILOAD 500mA/Div

VOUT 1V/Div

VOUT 20mV/Div AC

ENABLE 500mV/Div

1ms/Div

20MHz BW

1ms/Div

20MHz BW

Figure 49. Startup V_OUT= 2.5 V

Figure 48. Load Transient V_OUT= 2.5 V

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

COUT1 = 22ꢀF 10V 0805 X5R

Taiyo Yuden MK212BJ226MG-T

VOUT RIPPLE

COUT = 22ꢀF 10V 0805 X5R

WITH 500MHz SCOPE BANDWIDTH

COUT2 = 3x1000pF 0805 NP0

Johanson Dielectrics 500R15N102JV4T

Taiyo Yuden MK212BJ226MG-T

10mV/Div

50mV/Div

1µs/Div

20MHz BW

500MHz BW

1µs/Div

Figure 50. 20MHz Oscilloscope Bandwidth

Output Voltage Ripple V_OUT= 2.5 V

Figure 51. 500MHz Oscilloscope Bandwidth, 3x1000pF

additional output capacitance

Output Voltage Ripple and HF Noise V_OUT= 2.5 V

2.5

2.0

1.5

1.0

0.5

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VOUT=2.5V

INPUT VOLTAGE (V)

C001

Figure 52. Typical Switching Frequency at 650mA Load

V_OUT= 2.5 V

Figure 53. Typical Current Limit V_OUT= 2.5 V, T_A= 85 °C

2.5

0.7

0.6

0.5

0.4

0.3

VIN = 3 V

VIN = 3.3 V

VIN = 4.5 V

VIN = 5 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

2.498

2.496

2.494

2.492

2.49

2.488

2.486

2.484

2.482

2.48

0.2

VIN = 5 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.1

0.0

100

110

120

130

0.0001

0.001

0.01

Load Current (A)

0.1

Ambient Temperature (°C)

C001

D018

Figure 55. Thermal Derating for θ_JA=47ºC/W, V_OUT= 2.5 V

Figure 54. Line and Load Regulation V_OUT= 2.5 V

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

8.2.3.4 V_OUT= 3.3 V

V_OUT

V_IN

COMPONENT VALUES FOR VOUT=3.3V

VIN

VOUT

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

LMZ21700

3300pF

1.21Mꢀ

383kꢀ

10kꢀ

OUT

VOS

FBT

FBB

FBT

GND

FBB

Figure 56. Typical Applications Circuit

Figure 57. External Component Values

(V_OUT= 3.3V)

100

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0001

0.001

0.01

Load Current (A)

0.1

Load Current (A)

C001

D019

Figure 59. Power Dissipation V_OUT= 3.3 V

Figure 58. Efficiency V_OUT= 3.3 V

ILOAD 500mA/Div

VOUT 1V/Div

ILOAD 500mA/Div

PGOOD 2V/Div

VOUT 20mV/Div AC

ENABLE 500mV/Div

1ms/Div

20MHz BW

1ms/Div

20MHz BW

Figure 61. Startup V_OUT= 3.3 V

Figure 60. Load Transient V_OUT= 3.3 V

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

COUT1 = 22ꢀF 10V 0805 X5R

Taiyo Yuden MK212BJ226MG-T

VOUT RIPPLE

COUT = 22ꢀF 10V 0805 X5R

WITH 500MHz SCOPE BANDWIDTH

COUT2 = 3x1000pF 0805 NP0

Johanson Dielectrics 500R15N102JV4T

Taiyo Yuden MK212BJ226MG-T

10mV/Div

50mV/Div

1µs/Div

20MHz BW

500MHz BW

1µs/Div

Figure 62. 20 MHz Oscilloscope Bandwidth

Output Voltage Ripple V_OUT= 3.3 V

Figure 63. 500MHz Oscilloscope Bandwidth, 3x1000 pF

additional output capacitance

Output Voltage Ripple and HF Noise V_OUT= 3.3 V

2.5

2.0

1.5

1.0

0.5

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VOUT=3.3V

INPUT VOLTAGE (V)

C001

Figure 64. Typical Switching Frequency at 650mA Load

V_OUT= 3.3 V

Figure 65. Typical Current Limit V_OUT= 3.3 V, T_A= 85 °C

3.316

3.314

3.312

3.31

0.7

0.6

0.5

0.4

0.3

VIN = 4.5 V

VIN = 5 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

3.308

3.306

3.304

3.302

3.3

0.2

VIN = 5 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.1

0.0

100

110

120

130

0.0001

0.001

0.01

Load Current (A)

0.1

Ambient Temperature (°C)

C001

D020

Figure 67. Thermal Derating for θ_JA= 47ºC/W, V_OUT= 3.3 V

Figure 66. Line and Load Regulation V_OUT= 3.3 V

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

8.2.3.5 V_OUT= 5.0 V

V_OUT

V_IN

COMPONENT VALUES FOR VOUT=5.0V

VIN

VOUT

22µF

≥ 25V

≥ 10V

X7R or X5R

OUT

22µF

LMZ21700

3300pF

232kꢀ

44.2kꢀ

10kꢀ

OUT

VOS

FBT

FBB

FBT

GND

FBB

Figure 68. Typical Applications Circuit

Figure 69. External Component Values

(V_OUT= 5.0V)

100

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.0001

0.001

0.01

Load Current (A)

0.1

Load Current (A)

C001

D021

Figure 71. Power Dissipation V_OUT= 5.0 V

Figure 70. Efficiency V_OUT= 5.0 V

ILOAD 500mA/Div

VOUT 2V/Div

ILOAD 500mA/Div

PGOOD 5V/Div

VOUT 20mV/Div AC

ENABLE 500mV/Div

1ms/Div

20MHz BW

1ms/Div

20MHz BW

Figure 73. Startup V_OUT= 5.0 V

Figure 72. Load Transient V_OUT= 5.0 V

LMZ21700

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ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

COUT1 = 22ꢀF 10V 0805 X5R

Taiyo Yuden MK212BJ226MG-T

VOUT RIPPLE

COUT = 22ꢀF 10V 0805 X5R

WITH 500MHz SCOPE BANDWIDTH

COUT2 = 3x1000pF 0805 NP0

Johanson Dielectrics 500R15N102JV4T

Taiyo Yuden MK212BJ226MG-T

10mV/Div

50mV/Div

1µs/Div

20MHz BW

500MHz BW

1µs/Div

Figure 74. 20 MHz Oscilloscope Bandwidth

Output Voltage Ripple V_OUT= 5.0 V

Figure 75. 500 MHz Oscilloscope Bandwidth, 3x1000 pF

additional output capacitance

Output Voltage Ripple and HF Noise V_OUT= 5.0 V

2.5

2.0

1.5

1.0

0.5

0.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

VOUT=5.0V

INPUT VOLTAGE (V)

C001

Figure 76. Typical Switching Frequency at 650 mA Load

V_OUT= 5.0 V

Figure 77. Typical Current Limit V_OUT= 5.0 V, T_A= 85 °C

5.04

0.7

0.6

0.5

0.4

0.3

VIN = 9 V

VIN = 12 V

VIN = 15 V

VIN = 17 V

5.035

5.03

5.025

5.02

5.015

5.01

5.005

0.2

VIN = 9 V

VIN = 12 V

0.1

VIN = 15 V

VIN = 17 V

4.995

4.99

0.0

100

110

120

130

0.0001

0.001

0.01

Load Current (A)

0.1

Ambient Temperature (°C)

C001

D022

Figure 79. Thermal Derating for θ_JA= 47ºC/W, V_OUT= 5.0 V

Figure 78. Line and Load Regulation V_OUT= 5.0 V

LMZ21700

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www.ti.com.cn

8.3 Do's and Don'ts

● DO NOT exceed the Absolute Maximum Ratings.

● DO NOT exceed the Recommended Operating Conditions.

● DO NOT exceed the Handling Ratings.

● DO follow the Detailed Design Procedure.

● DO follow the PCB Layout Guidelines and Layout Example.

● DO follow the Power Supply Recommendations.

● DO visit the TI E2E Community Support Forum to have your questions answered and designs reviewed.

9 Power Supply Recommendations

9.1 Voltage Range

The voltage of the input supply must not exceed the Absolute Maximum Ratings and the Recommended

Operating Conditions of the LMZ21700.

9.2 Current Capability

The input supply must be able to supply the required input current to the LMZ21700 converter. The required

input current depends on the application's minimum required input voltage (V_IN-MIN), the required output power

(V_OUTx I_OUT-MAX), and the converter efficiency (η).

I_IN= V_OUTx I_OUT-MAX/ (V_IN-MINx η)

For example, for a design with 10 V minimum input voltage, 5 V output, and 0.5 A maximum load, considering

90 % conversion efficiency, the required input current is 0.278 A.

9.3 Input Connection

Long input connection cables can cause issues with the normal operation of any buck converter.

9.3.1 Voltage Drops

Using long input wires to connect the supply to the input of any converter adds impedance in series with the

input supply. This impedance can cause a voltage drop at the VIN pin of the converter when the output of the

converter is loaded. If the input voltage is near the minimum operating voltage, this added voltage drop can

cause the converter to drop out or reset. If long wires are used during testing, it is recommended to add some

bulk (i.e. electrolytic) capacitance at the input of the converter.

9.3.2 Stability

The added inductance of long input cables together with the ceramic (and low ESR) input capacitor can result in

an under damped RLC network at the input of the Buck converter. This can cause oscillations on the input and

instability. If long wires are used, it is recommended to add some electrolytic capacitance in parallel with the

ceramic input capacitor. The electrolytic capacitor's ESR will improve the damping.

Use an electrolytic capacitor with C_ELECTROLYTIC≥ 4 x C_CERAMICand ESR_ELECTROLYTIC≈ √ (L_CABLE/ C_CERAMIC

)

For example, two cables (one for V_INand one for GND), each 1 meter (~ 3 ft) long with ~1.0 mm diameter (18

AWG), placed 1 cm (~0.4 in) apart will form a rectangular loop resulting in about 1.2 µH of inductance. The

inductance in this example can be decreased to almost half if the input wires are twisted. Based on a 22 µF

ceramic input capacitor, the recommended parallel C_ELECTROLYTICis ≥ 88 µF. Using a 100 µF capacitor will be

sufficient. The recommended ESR_ELECTROLYTIC≈ 0.23 Ω or larger, based on about 1.2 µH of inductance and 22

µF of ceramic input capacitance.

See application note SNVA489C for more details on input filter design.

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

10 Layout

10.1 Layout Guidelines

The PCB layout is critical for the proper operation of any DC-DC switching converter. Although using modules

can simplify the PCB layout process, care should still be taken to minimize the inductance in the high di/dt loops

and to protect sensitive nodes. The following guidelines should be followed when designing a board layout with

the LMZ21700:

10.1.1 Minimize the High di/dt Loop Area

The input capacitor, the V_INterminal, and the GND terminal of the LMZ21700 form a high di/dt loop. Place the

input capacitor as close as possible to the V_INand GND terminals of the module IC. This minimizes the area of

the high di/dt loop and results in lower inductance in the switching current path. Lower inductance in the

switching current path translates to lower voltage spikes on the internal switch node and lower noise on the

output voltage. Make the copper traces between the input capacitor and the V_INand GND terminals wide and

short for better current handling and minimized parasitic inductance.

10.1.2 Protect the Sensitive Nodes in the Circuit

The feedback node is a sensitive circuit which can pick up noise. Make the feedback node as small as possible.

This can be achieved by placing the feedback divider as close as possible to the IC. Use thin traces to the

feedback pin in order to minimize the parasitic capacitance to other nodes. The feedback network carries very

small current and thick traces are not necessary. Another sensitive node to protect is the VOS pin. Use a thin

and short trace from the V_OUTterminal of the output capacitor to the VOS pin. The VOS pin is right next to the

GND terminal. For very noisy systems, a small (0402 or 0201) 0.1 µF capacitor can be placed from VOS to GND

to filter high frequency noise on the VOS line.

10.1.3 Provide Thermal Path and Shielding

Using the available layers in the PCB can help provide additional shielding and improved thermal performance.

Large unbroken GND copper areas provide good thermal and return current paths. Flood unused PCB area with

GND copper. Use thermal vias to connect the GND copper between layers.

The required board area for proper thermal dissipation can be estimated using the power dissipation curves for

the desired output voltage and the package thermal resistance vs. board area curve. Refer to the power

dissipation graphs in the Typical Characteristics section. Using the power dissipation (P_DISS) for the designed

input and output voltage and the max operating ambient temperature T_Afor the application, estimate the required

thermal resistance R_θJAwith the following expression.

R_{θJA - REQUIRED}≤ (125 ºC - T_A) / P_DISS

(8)

Then use Figure 80 to estimate the board copper area required to achieve the calculated thermal resistance.

100

2-LAYER 70 µm (2 oz) Cu

4-LAYER 70 µm (2 oz) Cu

Copper Area (cm²)

D012

Figure 80. Package Thermal Resistance vs. Board Copper Area, No Air Flow

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

Layout Guidelines (continued)

For example, for a design with 17 V input and 5 V output and 0.65 A load the power dissipation according to

Figure 7 is 0.43 W.

For 85 °C ambient temperature, the R_{θJA-REQUIRED}is ≤ (125 °C - 85 °C) / 0.43 W, or ≤ 93 °C/W. Looking at

Figure 80 the minimum copper area required to achieve this thermal resistance with a 4-layer board and 70 µm

(2 oz) copper is approximately 1 cm².

10.2 Layout Example

The following example is for a 4-layer board. Layers 2 and 4 provide additional shielding and thermal path. If a 2-

layer board is used, apply the Layer 1 and Layer 3 copper patterns for the top and bottom layers, respectively.

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

Layout Example (continued)

PLACE THE INPUT CAPACITOR AS CLOSE

AS POSSIBLE TO THE MODULE VIN AND

GND PINS

GND VIAS TO MINIMIZE INDUCTANCE IN

THE di/dt LOOP

VIN EN VOS GND

GND

^VOUTVOUT

LAYER 1

SS FB PG

PLACE THE FEEDBACK DIVIDER AS CLOSE

AS POSSIBLE TO THE MODULE TO KEEP

THE FB NODE SMALL

LAYER 2

LAYER 3

UNBROKEN GND PLANE FOR THERMAL

PERFORMANCE AND SHIELDING

ENABLE CONNECTION

VOS CONNECTION t KEEP AWAY FROM

NOISE SOURCES

CONNECTION TO THE SOFTSTART

CAPACITOR

POWER GOOD FLAG CONNECTION

UNBROKEN GND PLANE FOR THERMAL

PERFORMANCE AND SHIELDING

LAYER 4

Figure 81. Layout example

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

Layout Example (continued)

10.2.1 High Density Layout Example for Space Constrained Applications

10.2.1.1 35 mm² Solution Size (Single Sided)

The following layout example uses 0805 case size components for the input and output capacitors and 0402

case size components for the rest of the passives.

LAYER 1

LAYER 2

VIN

VOS

GND

VOUT

GND

VOUT GND

LAYER 3

LAYER 4

VOS

VOUT

Figure 82. 35mm² Solution Size (Single Sided)

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

11 器件和文档支持

11.1 器件支持

如需问题解答和设计检查，请访问德州仪器 (TI) E2E 社区支持论坛。

11.2 开发支持

11.2.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 LMZ21700 器件并借助 WEBENCH® 电源设计器创建定制设计。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

DCS-Control, MicroSiP, E2E are trademarks of Texas Instruments.

WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

LMZ21700

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

www.ti.com.cn

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

12.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

LMZ21700SILR

LMZ21700SILT

uSiP

SIL

3000

250

330.0

178.0

12.4

13.2

3.75

2.2

8.0

12.0

LMZ21700

www.ti.com.cn

ZHCSD73D –AUGUST 2012–REVISED AUGUST 2018

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

Package Drawing Pins

SPQ

3000

250

Length (mm) Width (mm)

Height (mm)

58.0

LMZ21700SILR

LMZ21700SILT

uSiP

SIL

383.0

223.0

353.0

194.0

35.0

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMZ21700SILR

LMZ21700SILT

ACTIVE

uSiP

SIL

3000 RoHS & Green

250 RoHS & Green

NIAU

Level-3-260C-168 HR

-40 to 125

7485

1700 7485 D9

Samples

ACTIVE

SIL

NIAU

7485

1700 7485 D9

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Mar-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMZ21700SILR

uSiP

SIL

3000

330.0

12.4

3.75

2.2

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

uSiP SIL

SPQ

Length (mm) Width (mm) Height (mm)

383.0 353.0 58.0

LMZ21700SILR

3000

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMZ21700 [TI]

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