LP2950ACZ-5.0/LFT7 [TI]

LP2950-N/LP2951-N Series of Adjustable Micropower Voltage Regulators; LP2950 -N / LP2951 -N系列的可调微功耗电压调节器


型号：	LP2950ACZ-5.0/LFT7
厂家：	TEXAS INSTRUMENTS
描述：	LP2950-N/LP2951-N Series of Adjustable Micropower Voltage Regulators LP2950 -N / LP2951 -N系列的可调微功耗电压调节器调节器
文件：	总43页 (文件大小：1949K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP2950-N, LP2951-N

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SNVS764N –JANUARY 2000–REVISED MAY 2013

LP2950-N/LP2951-N Series of Adjustable Micropower Voltage Regulators

Check for Samples: LP2950-N, LP2951-N

FEATURES

DESCRIPTION

The LP2950-N and LP2951-N are micropower

•

5V, 3V, and 3.3V Versions Available

High Accuracy Output Voltage

Ensured 100 mA Output Current

Extremely Low Quiescent Current

Low Dropout Voltage

voltage regulators with very low quiescent current (75

μA typ.) and very low dropout voltage (typ. 40 mV at

light loads and 380 mV at 100 mA). They are ideally

suited for use in battery-powered systems.

Furthermore, the quiescent current of the LP2950-

N/LP2951-N increases only slightly in dropout,

prolonging battery life.

Extremely Tight Load and Line Regulation

Very Low Temperature Coefficient

Use as Regulator or Reference

Needs Minimum Capacitance for Stability

Current and Thermal Limiting

The LP2950-N-5.0 is available in the surface-mount

PFM package, and in the popular 3-pin TO-92

package for pin-compatibility with older 5V regulators.

The 8-lead LP2951-N is available in plastic, ceramic

dual-in-line, WSON, or metal can packages and

offers additional system functions.

Stable With Low-ESR Output Capacitors (10

mΩ to 6Ω)

One such feature is an error flag output which warns

of a low output voltage, often due to falling batteries

on the input. It may be used for a power-on reset. A

second feature is the logic-compatible shutdown input

which enables the regulator to be switched on and

off. Also, the part may be pin-strapped for a 5V, 3V,

or 3.3V output (depending on the version), or

programmed from 1.24V to 29V with an external pair

of resistors.

LP2951-N VERSIONS ONLY

•

Error Flag Warns of Output Dropout

Logic-Controlled Electronic Shutdown

Output Programmable From 1.24 to 29V

Careful design of the LP2950-N/LP2951-N has

minimized all contributions to the error budget. This

includes a tight initial tolerance (.5% typ.), extremely

good load and line regulation (.05% typ.) and a very

low output voltage temperature coefficient, making

the part useful as a low-power voltage reference.

Block Diagram and Typical Applications

Figure 1. LP2950-N

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP2950-N, LP2951-N

SNVS764N –JANUARY 2000–REVISED MAY 2013

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Figure 2. LP2951-N

Connection Diagrams

Figure 3. TO-92 Plastic Package (LP) Bottom

View

Figure 6. 10-Lead Ceramic Surface-Mount

Package (NAC) Top View

Figure 4. Dual-In-Line Packages (P, NAB)

Surface-Mount Package (D, DGK) Top View

Figure 7. PFM (NDP) Front View

INPUT

OUTPUT

SENSE

FEEDBACK

DAP

TAP

SHUTDOWN

GND

ERROR

Figure 5. Metal Can Package (LMC) Top View

Connect DAP to GND at device pin 4.

Figure 8. 8-Lead WSON (NGT) Top View

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SNVS764N –JANUARY 2000–REVISED MAY 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

Input Supply Voltage - SHUTDOWN Input Voltage Error Comparator Output Voltage⁽³⁾

FEEDBACK Input Voltage⁽³⁾⁽⁴⁾

−0.3 to +30V

−1.5 to +30V

Power Dissipation

Internally Limited

+150°C

Junction Temperature (T_J)

Ambient Storage Temperature

−65° to +150°C

4 seconds, 260°C

10 seconds, 240°C

75 seconds, 219°C

2500V

Soldering Dwell Time, Temperature

Wave

Infrared

Vapor Phase

Human Body Model⁽⁵⁾

ESD Rating

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is specified. Operating Ratings do not imply ensured performance limits. For ensured performance limits and

associated test conditions, see the Electrical Characteristics tables.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) May exceed input supply voltage.

(4) When used in dual-supply systems where the output terminal sees loads returned to a negative supply, the output voltage should be

diode-clamped to ground.

(5) Human Body Model (HBM) is 1.5 kΩ in series with 100 pF; LP2950-N passes 2.5 kV (HBM) ESD; LP2951-N passes 2.5 kV (HBM)

except: Feedback pin passes 1kV (HBM) and Shutdown pin passes 2kV (HBM).

OPERATING RATINGS⁽¹⁾

Maximum Input Supply Voltage

30V

LP2950AC-XX, LP2950C-XX

LP2951

−40° to +125°C

−55° to +150°C

−40° to +125°C

Junction Temperature Range (T_J)⁽²⁾

LP2951AC-XX, LP2951C-XX

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is specified. Operating Ratings do not imply ensured performance limits. For ensured performance limits and

associated test conditions, see the Electrical Characteristics tables.

(2) The junction-to-ambient thermal resistances are as follows: 180°C/W and 160°C/W for the TO-92 package with 0.40 inch and 0.25 inch

leads to the printed circuit board (PCB) respectively, 105°C/W for the molded PDIP (P), 130°C/W for the ceramic DIP (NAB), 160°C/W

for the molded plastic SOIC (D), 200°C/W for the molded plastic VSSOP (DGK), and 160°C/W for the metal can package (LMC). The

above thermal resistances for the P, NAB, D, and DGK packages apply when the package is soldered directly to the PCB. Junction-to-

case thermal resistance for the LMC package is 20°C/W. Junction-to-case thermal resistance for the PFM package is 5.4°C/W. The

value of θ_JAfor the WSON package is typically 51°C/W but is dependent on the PCB trace area, trace material, and the number of

layers and thermal vias. For details of thermal resistance and power dissipation for the WSON package, refer to Application Note AN-

1187 (literature number SNOA401).

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ELECTRICAL CHARACTERISTICS⁽¹⁾

LP2950AC-XX

LP2951AC-XX

LP2950C-XX

LP2951C-XX

LP2951

Parameter

Conditions⁽¹⁾

Units

Typ

Tested

Typ

Tested Design Typ

Limit⁽²⁾Limit⁽⁴⁾

Tested Design

Limit⁽²⁾Limit⁽⁴⁾

Limit⁽²⁾⁽³⁾

3V Versions⁽⁵⁾

Output Voltage

T_J= 25°C

3.0

3.015

2.985

3.0

3.015

2.985

3.0

3.030

2.970

3.045

2.955

3.060

2.940

3.072

2.928

V max

V min

V max

V min

V max

V min

V max

V min

−25°C ≤ T_J≤ 85°C

3.030

2.970

3.036

2.964

3.042

2.958

Full Operating Temperature 3.0

Range

3.036

2.964

3.045

2.955

Output Voltage

100 μA ≤ I_L≤ 100 mA

T_J≤ T_JMAX

3.0

3.3V Versions⁽⁵⁾

Output Voltage

T_J= 25°C

3.3

3.317

3.284

3.3

3.317

3.284

3.3

3.333

3.267

3.350

3.251

3.366

3.234

3.379

3.221

V max

V min

V max

V min

V max

V min

V max

V min

−25°C ≤ T_J≤ 85°C

3.333

3.267

3.340

3.260

3.346

3.254

Full Operating Temperature 3.3

Range

3.340

3.260

3.350

3.251

Output Voltage

100 μA ≤ I_L≤ 100 mA

T_J≤ T_JMAX

3.3

5V Versions⁽⁵⁾

Output Voltage

T_J= 25°C

5.0

5.025

4.975

5.0

5.025

4.975

5.0

5.05

4.95

5.075

4.925

5.1

V max

V min

V max

V min

V max

V min

V max

V min

−25°C ≤ T_J≤ 85°C

5.05

4.95

Full Operating Temperature 5.0

Range

5.06

4.94

5.06

4.94

4.9

Output Voltage

100 μA ≤ I_L≤ 100 mA

T_J≤ T_JMAX

5.0

5.075

4.925

5.075

4.925

5.12

4.88

All Voltage Options

Output Voltage

Temperature

Coefficient

See⁽⁶⁾

120

100

150

ppm/°C

Line Regulation⁽⁷⁾

(V_ONOM + 1)V ≤ V_in

≤

0.03

0.1

0.03

0.1

0.04

0.2

% max

30V⁽⁸⁾

0.5

0.2

0.4

(1) Unless otherwise noted, all limits specified for V_IN= (V_ONOM+ 1)V, I_L= 100 μA and C_L= 1μF for 5V versions and 2.2 μF for 3V and

3.3V versions. Limits appearing in boldface type apply over the entire junction temperature range for operation. Limits appearing in

normal type apply for T_A= T_J= 25°C. Additional conditions for the 8-pin versions are FEEDBACK tied to V_TAP, OUTPUT tied to SENSE,

and V_SHUTDOWN≤ 0.8V.

(2) Ensured and 100% production tested.

(3) A Military RETS specification is available on request. At time of printing, the LP2951-N RETS specification complied with the boldface

limits in this column. The LP2951-N LMC, NAC, or NAB may also be procured as Standard Military Drawing Spec #5962-3870501MGA,

MXA, or MPA.

(4) Ensured but not 100% production tested. These limits are not used to calculate outgoing AQL levels.

(5) All LP2950 devices have the nominal output voltage coded as the last two digits of the part number. In the LP2951 products, the 3.0V

and 3.3V versions are designated by the last two digits, but the 5V version is denoted with no code at this location of the part number

(refer to ordering information table).

(6) Output or reference voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.

(7) Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to

heating effects are covered under the specification for thermal regulation.

(8) Line regulation for the LP2951-N is tested at 150°C for I_L= 1mA. For I_L= 100 μA and T_J= 125°C, line regulation is specified by design

to 0.2%. See TYPICAL PERFORMANCE CHARACTERISTICS for line regulation versus temperature and load current.

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SNVS764N –JANUARY 2000–REVISED MAY 2013

ELECTRICAL CHARACTERISTICS⁽¹⁾(continued)

LP2950AC-XX

LP2951AC-XX

LP2950C-XX

LP2951C-XX

LP2951

Parameter

Conditions⁽¹⁾

Units

Typ

Tested

Typ

Tested Design Typ

Limit⁽²⁾Limit⁽⁴⁾

Tested Design

Limit⁽²⁾Limit⁽⁴⁾

Limit⁽²⁾⁽³⁾

Load Regulation⁽⁷⁾

Dropout Voltage⁽⁹⁾

100 μA ≤ I_L≤ 100 mA

I_L= 100 μA

0.04

0.1

0.3

0.04

0.1

0.2

0.3

% max

0.2

max

150

450

600

150

max

I_L= 100 mA

450

max

380

600

140

380

600

max

Ground Current

I_L= 100 μA

120

140

120

140

μA max

I_L= 100 mA

max

Dropout Ground

Current

V_in= (V_ONOM − 0.5)V

I_L= 100 μA

110

160

170

200

110

160

170

200

110

160

170

200

μA max

200

220

Current Limit

V_out= 0

max

220

max

Thermal Regulation

See⁽¹⁰⁾

0.05

0.2

0.05

0.2

0.05

0.2

%/W

max

Output Noise, 10 Hz to C_L= 1μF (5V Only)

430

160

100

430

160

100

430

160

100

μV rms

100 kHz

C_L= 200 μF

C_L= 3.3 μF

(Bypass = 0.01 μF

Pins 7 to 1 (LP2951-N)

8-pin Versions Only

LP2951

LP2951AC-XX

LP2951C-XX

Reference Voltage

1.23

1.25

1.23

1.25

1.23

1.26

V max

1.26

1.22

1.2

1.26

1.27

V max

V min

1.22

1.21

1.2

V min

Reference Voltage

See⁽¹¹⁾

1.27

1.19

1.27

1.19

1.285

1.185

V max

V min

Feedback Pin Bias

Current

nA max

ppm/°C

Reference Voltage

Temperature

Coefficient

See⁽¹²⁾

Feedback Pin Bias

Current Temperature

Coefficient

0.1

nA/°C

(9) Dropout Voltage is defined as the input to output differential at which the output voltage drops 100 mV below its nominal value

measured at 1V differential. At very low values of programmed output voltage, the minimum input supply voltage of 2V (2.3V over

temperature) must be taken into account.

(10) Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load

or line regulation effects. Specifications are for a 50 mA load pulse at V_IN= 30V (1.25W pulse) for T = 10ms.

(11) V_REF≤ V_OUT≤ (V_IN− 1V), 2.3V ≤ V_IN≤ 30V, 100 μA ≤ I_L≤ 100 mA, T_J≤ T_JMAX

(12) Output or reference voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range.

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ELECTRICAL CHARACTERISTICS⁽¹⁾(continued)

LP2950AC-XX

LP2951AC-XX

LP2950C-XX

LP2951C-XX

LP2951

Parameter

Conditions⁽¹⁾

Units

Typ

Tested

Typ

Tested Design Typ

Limit⁽²⁾Limit⁽⁴⁾

Tested Design

Limit⁽²⁾Limit⁽⁴⁾

Limit⁽²⁾⁽³⁾

Error Comparator

Output Leakage

Current

V_OH= 30V

0.01

150

0.01

150

0.01

150

μA max

Output Low Voltage

V_in= (V_ONOM − 0.5)V

I_OL= 400μA

250

max

400

max

Upper Threshold

Voltage

See⁽¹³⁾

mV min

Lower Threshold

Voltage

max

140

max

Hysteresis

Shutdown Input

Input

See⁽¹³⁾

1.3

Logic

Low (Regulator ON)

High (Regulator OFF)

V_shutdown= 2.4V

0.6

2.0

0.7

2.0

0.7

V max

V min

Voltage

2.0

Shutdown Pin Input

Current

450

600

450

100

600

750

μA max

100

600

750

100

750

V_shutdown= 30V

See⁽¹⁴⁾

Regulator Output

Current in Shutdown

(13) Comparator thresholds are expressed in terms of a voltage differential at the Feedback terminal below the nominal reference voltage

measured at V_in= (V_ONOM + 1)V. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain =

V_OUT/V_REF= (R1 + R2)/R2.For example, at a programmed output voltage of 5V, the Error output is specified to go low when the output

drops by 95 mV × 5V/1.235V = 384 mV. Thresholds remain constant as a percent of V_outas V_outis varied, with the dropout warning

occurring at typically 5% below nominal, 7.5% ensured.

(14) V_SHUTDOWN≥ 2V, V_IN≤ 30V, V_OUT= 0, Feedback pin tied to V_TAP

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SNVS764N –JANUARY 2000–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS

Quiescent Current

Dropout Characteristics

Figure 9.

Figure 10.

Input Current

Figure 11.

Figure 12.

Output Voltage vs. Temperature of 3 Representative Units

Quiescent Current

Figure 13.

Figure 14.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Quiescent Current

Figure 15.

Figure 16.

Quiescent Current

Short Circuit Current

Figure 17.

Figure 18.

Dropout Voltage

Figure 19.

Figure 20.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

LP2951-N Minimum Operating Voltage

LP2951-N Feedback Bias Current

Figure 21.

Figure 22.

LP2951-N Feedback Pin Current

LP2951-N Error Comparator Output

Figure 23.

Figure 24.

LP2951-N Comparator Sink Current

Line Transient Response

Figure 25.

Figure 26.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Load Transient Response

Figure 27.

Figure 28.

LP2951-N Enable Transient

Output Impedance

Figure 29.

Figure 30.

Ripple Rejection

Figure 31.

Figure 32.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Ripple Rejection

LP2951-N Output Noise

Figure 33.

Figure 34.

LP2951-N Divider Resistance

Shutdown Threshold Voltage

Figure 35.

Figure 36.

Line Regulation

LP2951-N Maximum Rated Output Current

Figure 37.

Figure 38.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

LP2950-N Maximum Rated Output Current

Thermal Response

Figure 39.

Figure 40.

Output Capacitor ESR Range

LP2951-N Input Pin Current vs Input Voltage

120

= 2.0V

Output Load = Open

100

Ta= -50°C

Ta= -40°C

Ta= +25°C

Ta= +125°C

INPUT PIN VOLTAGE, V (V)

Figure 41.

Figure 42.

LP2951-N Input Pin Current vs Input Voltage

120

= 2.0V

Output Load = Short to Ground

100

Ta= -50°C

Ta= -40°C

Ta= +25°C

Ta= +125°C

INPUT PIN VOLTAGE, V (V)

Figure 43.

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APPLICATION HINTS

Output Capacitor Requirements

A 1.0 μF (or greater) capacitor is required between the output and ground for stability at output voltages of 5V or

higher. At lower output voltages, more capacitance is required (2.2 μF or more is recommended for 3.0V and

3.3V versions). Without this capacitor the part will oscillate. Most types of tantalum or aluminum electrolytic work

fine here; even film types work but are not recommended for reasons of cost. Many aluminum electrolytics have

electrolytes that freeze at about −30°C, so solid tantalums are recommended for operation below −25°C. The

important parameters of the capacitor are an ESR of about 5Ω or less and a resonant frequency above 500 kHz.

The value of this capacitor may be increased without limit.

Figure 44. Output Capacitor ESR Range

The reason for the lower ESR limit is that the loop compensation of the feedback loop relies on the capacitance

value and the ESR value of the output capacitor to provide the zero that gives added phase lead (See

Figure 44).

f_Z= (1 / (2 x π x C_OUTx ESR) )

(1)

Using the 2.2 µF value from the Output Capacitor ESR Range curve (Figure 44), a useful range for f_Zcan be

estimated:

f_Z(MIN)= (1 / (2 x π x 2.2 µF x 5Ω) ) = 14.5 kHz

f_Z(MAX)= (1 / (2 x π x 2.2 µF x 0.05Ω) ) = 318 kHz

(2)

(3)

For ceramic capacitors, the low ESR produces a zero at a frequency that is too high to be useful, so meaningful

phase lead does not occur. A ceramic output capacitor can be used if a series resistance is added

(recommended value of resistance about 0.1Ω to 2Ω) to simulate the needed ESR. Only X5R, X7R, or better,

MLCC types should be used, and should have a DC voltage rating at least twice the V_OUT(NOM)value.

At lower values of output current, less output capacitance is required for stability. The capacitor can be reduced

to 0.33 μF for currents below 10 mA or 0.1 μF for currents below 1 mA. Using the adjustable versions at voltages

below 5V runs the error amplifier at lower gains so that more output capacitance is needed. For the worst-case

situation of a 100 mA load at 1.23V output (Output shorted to Feedback) a 3.3 μF (or greater) capacitor should

be used.

Unlike many other regulators, the LP2950-N will remain stable and in regulation with no load in addition to the

internal voltage divider. This is especially important in CMOS RAM keep-alive applications. When setting the

output voltage of the LP2951-N versions with external resistors, a minimum load of 1 μA is recommended.

Applications having conditions that may drive the LP2950-N/51 into nonlinear operation require special

consideration. Nonlinear operation will occur when the output voltage is held low enough to force the output

stage into output current limiting while trying to pull the output voltage up to the regulated value. The internal loop

response time will control how long it takes for the device to regain linear operation when the output has returned

to the normal operating range. There are three significant nonlinear conditions that need to be considered, all can

force the output stage into output current limiting mode, all can cause the output voltage to over-shoot with low

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value output capacitors when the condition is removed, and the recommended generic solution is to set the

output capacitor to a value not less than 10 μF. Although the 10 μF value for C_OUTmay not eliminate the output

voltage over-shoot in all cases, it should lower it to acceptable levels (<10% of V_OUT(NOM)) in the majority of

cases. In all three of these conditions, applications with lighter load currents are more susceptible to output

voltage over-shoot than applications with higher load currents.

1) At power-up, with the input voltage rising faster than output stage can charge the output capacitor.

V_INt_RISE(MIN)> ((C_OUT/ 100 mA) x ΔV_IN)

where

•

ΔV_IN= V_OUT(NOM)+ 1.0V

(4)

(5)

(6)

2) Recovery from an output short circuit to ground condition.

_OUT(MIN)≈ (160 mA - I_LOAD(NOM))/((V_OUT(NOM)/10)/25 μs))

3) Toggling the LP2951-N SHUTDOWN pin from high (i.e. OFF) to low (i.e. ON).

_OUT(MIN)≈ (160 mA - I_LOAD(NOM))/((V_OUT(NOM)/10)/25 μs))

Figure 45. LP2951-N Enable Transient

Input Capacitor Requirements

A minimum 1 μF tantalum, ceramic or aluminum electrolytic capacitor should be placed from the LP2950-

N/LP2951-N input pin to ground if there is more than 10 inches of wire between the input and the AC filter

capacitor or if a battery is used as the input.

Error Detection Comparator Output

The comparator produces a logic low output whenever the LP2951-N output falls out of regulation by more than

approximately 5%. This figure is the comparator's built-in offset of about 60mV divided by the 1.235 reference

voltage. (Refer to the block diagram in the front of the datasheet.) This trip level remains “5% below normal”

regardless of the programmed output voltage of the 2951. For example, the error flag trip level is typically 4.75V

for a 5V output or 11.4V for a 12V output. The out of regulation condition may be due either to low input voltage,

current limiting, or thermal limiting.

Figure 46 below gives a timing diagram depicting the ERROR signal and the regulated output voltage as the

LP2951-N input is ramped up and down. For 5V versions, the ERROR signal becomes valid (low) at about 1.3V

input. It goes high at about 5V input (the input voltage at which V_OUT= 4.75V). Since the LP2951-N's dropout

voltage is load-dependent (see curve in typical performance characteristics), the input voltage trip point (about

5V) will vary with the load current. The output voltage trip point (approx. 4.75V) does not vary with load.

The error comparator has an open-collector output which requires an external pull up resistor. This resistor may

be returned to the output or some other supply voltage depending on system requirements. In determining a

value for this resistor, note that while the output is rated to sink 400 μA, this sink current adds to battery drain in

a low battery condition. Suggested values range from 100k to 1 MΩ. The resistor is not required if this output is

unused.

Submit Documentation Feedback

Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

www.ti.com

SNVS764N –JANUARY 2000–REVISED MAY 2013

*When V_IN≤ 1.3V, the error flag pin becomes a high impedance, and the error flag voltage rises to its pull-up voltage.

Using V_OUTas the pull-up voltage (see Figure 47), rather than an external 5V source, will keep the error flag voltage

under 1.2V (typ.) in this condition. The user may wish to divide down the error flag voltage using equal-value resistors

(10 kΩ suggested), to ensure a low-level logic signal during any fault condition, while still allowing a valid high logic

level during normal operation.

Figure 46. ERROR Output Timing

Programming the Output Voltage (LP2951-N)

The LP2951-N may be pin-strapped for the nominal fixed output voltage using its internal voltage divider by tying

the output and sense pins together, and also tying the feedback and V_TAPpins together. Alternatively, it may be

programmed for any output voltage between its 1.235V reference and its 30V maximum rating. As seen in

Figure 47, an external pair of resistors is required.

The complete equation for the output voltage is

where

•

V_REFis the nominal 1.235V reference voltage and I_FBis the feedback pin bias current, nominally -20nA

(7)

The minimum recommended load current of 1 μA forces an upper limit of 1.2 MΩ on the value of R2, if the

regulator must work with no load (a condition often found in CMOS in standby). I_FBwill produce a 2% typical

error in V_OUTwhich may be eliminated at room temperature by trimming R₁. For better accuracy, choosing R2 =

100 kΩ reduces this error to 0.17% while increasing the resistor program current to 12 μA. Since the LP2951-N

typically draws 60 μA at no load with Pin 2 open-circuited, this is a small price to pay.

*See Application Hints

**Drive with TTL-high to shut down. Ground or leave open if shutdown feature is not to be used.

Note: Pins 2 and 6 are left open.

Figure 47. Adjustable Regulator

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Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

SNVS764N –JANUARY 2000–REVISED MAY 2013

www.ti.com

Stray capacitance to the LP2951-N Feedback terminal can cause instability. This may especially be a problem

when using high value external resistors to set the output voltage. Adding a 100 pF capacitor between the Output

pin and the Feedback pin,and increasing the output capacitor to at least 3.3 μF, will fix this problem.

Reducing Output Noise

In reference applications it may be advantageous to reduce the AC noise present at the output. One method is to

reduce the regulator bandwidth by increasing the size of the output capacitor. This is the only way noise can be

reduced on the 3 lead LP2950-N but is relatively inefficient, as increasing the capacitor from 1 μF to 220 μF only

decreases the noise from 430 μV_(RMS)to 160 μV_(RMS)for a 100 kHz bandwidth at 5V output.

Noise can be reduced fourfold by a bypass capacitor across R1, since it reduces the high frequency gain from 4

to unity. Pick

(8)

or about 0.01 μF. When doing this, the output capacitor must be increased to 3.3 μF to maintain stability. These

changes reduce the output noise from 430 μV to 100 μV rms for a 100 kHz bandwidth at 5V output. With the

bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at

higher output voltages.

WSON Mounting

The NGT (No Pullback) 8-Lead WSON package requires specific mounting techniques which are detailed in

Application Note 1187 (literature number SNOA401). Referring to the PCB Design Recommendations section

(literature number SNOA401), it should be noted that the pad style which should be used with the WSON

package is the NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads to

be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection.

The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the

amount of additional copper area connected to the DAP.

The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive

die attach adhesive. The DAP has no direct electrical (wire) connection to any of the eight pins. There is a

parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that

the DAP be connected directly to the ground at device lead 4 (i.e. GND). Alternately, but not recommended, the

DAP may be left floating (i.e. no electrical connection). The DAP must not be connected to any potential other

than ground.

For the LP2951-N in the NGT 8-Lead WSON package, the junction-to-case thermal rating, θ_JC, is 14.2°C/W,

where the case is the bottom of the package at the center of the DAP. The junction-to-ambient thermal

performance for the LP2951-N in the NGT 8-Lead WSON package, using the JEDEC JESD51 standards is

summarized in the following table:

Board Type

Thermal Vias

θ_JC

θ_JA

JEDEC 2-Layer JESD 51-3

None

14.2°C/W

185°C/W

68°C/W

60°C/W

51°C/W

48°C/W

JEDEC 4-Layer JESD 51-7

Submit Documentation Feedback

Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

www.ti.com

SNVS764N –JANUARY 2000–REVISED MAY 2013

Typical Applications

Figure 48. 1A Regulator with 1.2V Dropout

Figure 49. 300mA Regulator with 0.75V Dropout

*Minimum input-output voltage ranges from 40mV to 400mV, depending on load current. Current limit is typically

160mA.

Figure 50. Wide Input Voltage Range Current Limiter

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Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

SNVS764N –JANUARY 2000–REVISED MAY 2013

www.ti.com

Figure 51. Low Drift Current Source

*Minimum input-output voltage ranges from 40mV to 400mV, depending on load current. Current limit is typically

160mA.

Figure 52. 5 Volt Current Limiter

Submit Documentation Feedback

Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

www.ti.com

SNVS764N –JANUARY 2000–REVISED MAY 2013

•

Early warning flag on low input voltage

Main output latches off at lower input voltages

Battery backup on auxiliary output

Operation: Reg. #1's V_OUTis programmed one diode drop above 5V. Its error flag becomes active when V_IN

≤

5.7V. When V_INdrops below 5.3V, the error flag of Reg. #2 becomes active and via Q1 latches the main output

off. When V_INagain exceeds 5.7V Reg. #1 is back in regulation and the early warning signal rises, unlatching

Reg. #2 via D3.

Figure 53. Regulator with Early Warning and Auxiliary Output

Figure 54. Latch Off When Error Flag Occurs

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Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

SNVS764N –JANUARY 2000–REVISED MAY 2013

www.ti.com

For 5V_out, use internal resistors. Wire pin 6 to 7, & wire pin 2 to +V_outBus.

Figure 55. 2 Ampere Low Dropout Regulator

*High input lowers V_outto 2.5V

Figure 56. 5V Regulator with 2.5V Sleep Function

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Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

www.ti.com

SNVS764N –JANUARY 2000–REVISED MAY 2013

Figure 57. Open Circuit Detector for 4 → 20mA Current Loop

*Optional Latch off when drop out occurs. Adjust R3 for C2 Switching when V_inis 6.0V

**Outputs go low when V_INdrops below designated thresholds.

Figure 58. Regulator with State-of-Charge Indicator

Submit Documentation Feedback

Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

SNVS764N –JANUARY 2000–REVISED MAY 2013

www.ti.com

For values shown, Regulator shuts down when V_in< 5.5V and turns on again at 6.0V. Current drain in disconnected

mode is ≈ 150μA.

*Sets disconnect Voltage

**Sets disconnect Hysteresis

Figure 59. Low Battery Disconnect

LM34 for 125°F Shutdown

LM35 for 125°C Shutdown

Figure 60. System Overtemperature Protection Circuit

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Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

www.ti.com

SNVS764N –JANUARY 2000–REVISED MAY 2013

Schematic Diagram

Submit Documentation Feedback

Product Folder Links: LP2950-N LP2951-N

LP2950-N, LP2951-N

SNVS764N –JANUARY 2000–REVISED MAY 2013

www.ti.com

REVISION HISTORY

Changes from Revision M (April 2013) to Revision N

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 23

Submit Documentation Feedback

Product Folder Links: LP2950-N LP2951-N

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

PACKAGING INFORMATION

Orderable Device

LP2950ACZ-3.0/NOPB

LP2950ACZ-3.3/NOPB

LP2950ACZ-5.0/LFT1

LP2950ACZ-5.0/LFT3

LP2950ACZ-5.0/LFT7

LP2950ACZ-5.0/NOPB

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

ACTIVE

TO-92

1800

Green (RoHS

& no Sb/Br)

SNCU

Level-1-NA-UNLIM

2950A

CZ3.0

ACTIVE

1800

2000

1800

Green (RoHS

& no Sb/Br)

-40 to 125

2950A

CZ3.3

Green (RoHS

& no Sb/Br)

2950A

CZ5.0

Green (RoHS

& no Sb/Br)

2950A

CZ5.0

Green (RoHS

& no Sb/Br)

2950A

CZ5.0

Green (RoHS

& no Sb/Br)

-40 to 125

2950A

CZ5.0

LP2950CDT-3.0

ACTIVE

TO-252

NDP

TBD

Call TI

CU SN

Call TI

-40 to 125

LP2950CDT-3.0/NOPB

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

LP2950

CDT-3.0

LP2950CDT-3.3

ACTIVE

TO-252

NDP

TBD

Call TI

CU SN

Call TI

-40 to 125

LP2950

CDT-3.3

LP2950CDT-3.3/NOPB

LP2950CDT-5.0/NOPB

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

LP2950

CDT-3.3

Green (RoHS

& no Sb/Br)

LP2950

CDT-5.0

LP2950CDTX-3.0

ACTIVE

TO-252

NDP

2500

TBD

Call TI

CU SN

Call TI

-40 to 125

LP2950CDTX-3.0/NOPB

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

LP2950

CDT-3.0

LP2950CDTX-3.3

ACTIVE

TO-252

NDP

2500

TBD

Call TI

CU SN

Call TI

-40 to 125

LP2950CDTX-3.3/NOPB

Green (RoHS

& no Sb/Br)

Level-2-260C-1 YEAR

LP2950

CDT-3.3

LP2950CDTX-5.0

LP2950CDTX-5.0/NOPB

LP2950CN

ACTIVE

TO-252

PDIP

NDP

2500

TBD

Call TI

CU SN

Call TI

Level-2-260C-1 YEAR

Call TI

-40 to 125

LP2950

CDT-5.0

Green (RoHS

& no Sb/Br)

LP2950

CDT-5.0

TBD

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2000

1800

2000

1800

2000

1800

(1)

(2)

(3)

(4/5)

2951CN

LP2950CZ-3.0/LFT3

LP2950CZ-3.0/NOPB

LP2950CZ-3.3/LFT1

LP2950CZ-3.3/LFT3

LP2950CZ-3.3/NOPB

LP2950CZ-5.0/LFT1

LP2950CZ-5.0/LFT3

LP2950CZ-5.0/LFT7

LP2950CZ-5.0/LFT8

LP2950CZ-5.0/NOPB

LP2951ACM

ACTIVE

TO-92

SOIC

Green (RoHS

& no Sb/Br)

SNCU

Call TI

CU SN

Call TI

CU SN

Level-1-NA-UNLIM

Call TI

2950

CZ3.0

Green (RoHS

& no Sb/Br)

-40 to 125

2950

CZ3.0

Green (RoHS

& no Sb/Br)

2950

CZ3.3

Green (RoHS

& no Sb/Br)

2950

CZ3.3

Green (RoHS

& no Sb/Br)

-40 to 125

2950

CZ3.3

Green (RoHS

& no Sb/Br)

2950

CZ5.0

Green (RoHS

& no Sb/Br)

2950

CZ5.0

Green (RoHS

& no Sb/Br)

2950

CZ5.0

Green (RoHS

& no Sb/Br)

2950

CZ5.0

Green (RoHS

& no Sb/Br)

-40 to 125

2950

CZ5.0

TBD

2951

ACM>D

LP2951ACM-3.0

TBD

Call TI

2951A

CM30>D

LP2951ACM-3.0/NOPB

LP2951ACM-3.3

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

2951A

CM30>D

TBD

2951A

CM33>D

LP2951ACM-3.3/NOPB

LP2951ACM/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

2951A

CM33>D

Green (RoHS

& no Sb/Br)

2951

ACM>D

LP2951ACMM

ACTIVE

VSSOP

DGK

1000

TBD

Call TI

-40 to 125

L0DA

LP2951ACMM-3.0

TBD

L0BA

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

LP2951ACMM-3.0/NOPB

ACTIVE

VSSOP

DGK

1000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125

L0BA

LP2951ACMM-3.3

ACTIVE

VSSOP

DGK

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

L0CA

LP2951ACMM-3.3/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951ACMM/NOPB

ACTIVE

VSSOP

DGK

1000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125

L0DA

LP2951ACMMX

LP2951ACMMX-3.0

ACTIVE

VSSOP

DGK

3500

TBD

Call TI

CU SN

Call TI

-40 to 125

L0DA

L0BA

TBD

LP2951ACMMX-3.0/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951ACMMX-3.3

ACTIVE

VSSOP

DGK

3500

TBD

Call TI

CU SN

Call TI

-40 to 125

L0CA

LP2951ACMMX-3.3/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951ACMMX/NOPB

LP2951ACMX

ACTIVE

VSSOP

SOIC

PDIP

DGK

3500

2500

Green (RoHS

& no Sb/Br)

CU SN

Call TI

CU SN

Call TI

CU SN

Call TI

Level-1-260C-UNLIM

Call TI

-40 to 125

L0DA

2951

TBD

ACM>D

LP2951ACMX-3.0

LP2951ACMX-3.0/NOPB

LP2951ACMX-3.3

LP2951ACMX-3.3/NOPB

LP2951ACMX/NOPB

LP2951ACN

TBD

Call TI

2951A

CM30>D

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

2951A

CM30>D

TBD

2951A

CM33>D

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

2951A

CM33>D

Green (RoHS

& no Sb/Br)

2951

ACM>D

TBD

2951ACN

LP2951ACN/NOPB

LP2951ACSD

PDIP

Green (RoHS

& no Sb/Br)

Level-1-NA-UNLIM

Call TI

2951ACN

WSON

NGT

1000

TBD

Call TI

2951AC

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

LP2951ACSD/NOPB

ACTIVE

WSON

NGT

1000

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

-40 to 125

2951AC

LP2951ACSDX

LP2951ACSDX-3.3

ACTIVE

WSON

NGT

4500

TBD

Call TI

-40 to 125

2951AC

51AC33

TBD

LP2951ACSDX-3.3/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951ACSDX/NOPB

LP2951CM

ACTIVE

WSON

SOIC

NGT

4500

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

-40 to 125

2951AC

TBD

Call TI

CU SN

Call TI

CU SN

2951

CM>D

LP2951CM-3.0

TBD

Call TI

2951C

M30>D

LP2951CM-3.0/NOPB

LP2951CM-3.3

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

2951C

M30>D

TBD

2951C

M33>D

LP2951CM-3.3/NOPB

LP2951CM/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

2951C

M33>D

Green (RoHS

& no Sb/Br)

2951

CM>D

LP2951CMM

LP2951CMM-3.0

ACTIVE

VSSOP

DGK

1000

TBD

Call TI

CU SN

Call TI

-40 to 125

L0DB

L0BB

TBD

LP2951CMM-3.0/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951CMM-3.3/NOPB

LP2951CMM/NOPB

ACTIVE

VSSOP

DGK

1000

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125

L0CB

L0DB

Green (RoHS

& no Sb/Br)

LP2951CMMX

LP2951CMMX-3.0

ACTIVE

VSSOP

DGK

3500

TBD

Call TI

CU SN

Call TI

-40 to 125

L0DB

L0BB

TBD

LP2951CMMX-3.0/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

LP2951CMMX-3.3

ACTIVE

VSSOP

DGK

3500

TBD

Call TI

CU SN

Call TI

-40 to 125

L0CB

LP2951CMMX-3.3/NOPB

ACTIVE

DGK

3500

2500

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951CMMX/NOPB

LP2951CMX

VSSOP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU SN

Call TI

CU SN

Call TI

CU SN

Call TI

Level-1-260C-UNLIM

Call TI

-40 to 125

L0DB

2951

TBD

CM>D

LP2951CMX-3.0

TBD

Call TI

2951C

M30>D

LP2951CMX-3.0/NOPB

LP2951CMX-3.3

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

2951C

M30>D

TBD

2951C

M33>D

LP2951CMX-3.3/NOPB

LP2951CMX/NOPB

LP2951CN

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

Call TI

2951C

M33>D

Green (RoHS

& no Sb/Br)

2951

CM>D

TBD

2951CN

LP2951CN/NOPB

Green (RoHS

& no Sb/Br)

Level-1-NA-UNLIM

2951CN

LP2951CSD

LP2951CSD-3.0

ACTIVE

WSON

NGT

1000

TBD

Call TI

-40 to 125

2951ACB

51AC30B

TBD

LP2951CSD-3.0/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951CSD-3.3

ACTIVE

WSON

NGT

1000

TBD

Call TI

-40 to 125

51AC33B

LP2951CSD-3.3/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951CSD/NOPB

ACTIVE

WSON

NGT

1000

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

-40 to 125

2951ACB

LP2951CSDX

ACTIVE

WSON

NGT

4500

TBD

Call TI

-40 to 125

2951ACB

51AC30B

LP2951CSDX-3.0

TBD

Addendum-Page 5

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

LP2951CSDX-3.0/NOPB

ACTIVE

WSON

NGT

4500

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

-40 to 125

51AC30B

LP2951CSDX-3.3

ACTIVE

WSON

NGT

4500

TBD

Call TI

-40 to 125

51AC33B

LP2951CSDX-3.3/NOPB

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2951CSDX/NOPB

ACTIVE

WSON

NGT

4500

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

-40 to 125

2951ACB

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

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Addendum-Page 6

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2013

Addendum-Page 7

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP2950CDTX-3.0/NOPB TO-252

LP2950CDTX-3.3/NOPB TO-252

NDP

DGK

2500

1000

3500

330.0

178.0

330.0

16.4

12.4

6.9

5.3

10.5

3.4

2.7

1.4

8.0

16.0

12.0

LP2950CDTX-5.0

TO-252

LP2950CDTX-5.0/NOPB TO-252

LP2951ACMM

VSSOP

LP2951ACMM-3.0

3.4

LP2951ACMM-3.0/NOPB VSSOP

LP2951ACMM-3.3 VSSOP

LP2951ACMM-3.3/NOPB VSSOP

3.4

LP2951ACMM/NOPB

LP2951ACMMX

VSSOP

3.4

LP2951ACMMX-3.0

3.4

LP2951ACMMX-3.0/NOP VSSOP

3.4

LP2951ACMMX-3.3

VSSOP

DGK

3500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

LP2951ACMMX-3.3/NOP VSSOP

LP2951ACMMX/NOPB VSSOP

DGK

3500

2500

330.0

12.4

5.3

6.5

3.4

5.4

1.4

2.0

8.0

12.0

LP2951ACMX

SOIC

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP2951ACMX-3.0

LP2951ACMX-3.0/NOPB

LP2951ACMX-3.3

SOIC

2500

1000

4500

1000

3500

2500

1000

4500

330.0

178.0

330.0

178.0

330.0

178.0

330.0

12.4

6.5

4.3

5.3

6.5

4.3

5.4

4.3

3.4

5.4

4.3

2.0

1.3

1.4

2.0

1.3

8.0

12.0

SOIC

LP2951ACMX-3.3/NOPB

LP2951ACMX/NOPB

LP2951ACSD

SOIC

WSON

NGT

DGK

LP2951ACSD/NOPB

LP2951ACSDX

LP2951ACSDX-3.3

LP2951ACSDX-3.3/NOPB WSON

LP2951ACSDX/NOPB

LP2951CMM

WSON

VSSOP

LP2951CMM-3.0

LP2951CMM-3.0/NOPB VSSOP

LP2951CMM-3.3/NOPB VSSOP

LP2951CMM/NOPB

LP2951CMMX

VSSOP

LP2951CMMX-3.0

LP2951CMMX-3.0/NOPB VSSOP

LP2951CMMX-3.3 VSSOP

LP2951CMMX-3.3/NOPB VSSOP

LP2951CMMX/NOPB

LP2951CMX

VSSOP

SOIC

LP2951CMX-3.0

SOIC

LP2951CMX-3.0/NOPB

LP2951CMX-3.3

SOIC

LP2951CMX-3.3/NOPB

LP2951CMX/NOPB

LP2951CSD

SOIC

WSON

NGT

LP2951CSD-3.0

LP2951CSD-3.0/NOPB

LP2951CSD-3.3

LP2951CSD-3.3/NOPB

LP2951CSD/NOPB

LP2951CSDX

LP2951CSDX-3.0

LP2951CSDX-3.0/NOPB WSON

LP2951CSDX-3.3 WSON

LP2951CSDX-3.3/NOPB WSON

LP2951CSDX/NOPB WSON

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP2950CDTX-3.0/NOPB

LP2950CDTX-3.3/NOPB

LP2950CDTX-5.0

TO-252

VSSOP

SOIC

NDP

DGK

2500

1000

3500

2500

367.0

210.0

367.0

185.0

367.0

38.0

35.0

38.0

35.0

LP2950CDTX-5.0/NOPB

LP2951ACMM

LP2951ACMM-3.0

LP2951ACMM-3.0/NOPB

LP2951ACMM-3.3

LP2951ACMM-3.3/NOPB

LP2951ACMM/NOPB

LP2951ACMMX

LP2951ACMMX-3.0

LP2951ACMMX-3.0/NOPB

LP2951ACMMX-3.3

LP2951ACMMX-3.3/NOPB

LP2951ACMMX/NOPB

LP2951ACMX

LP2951ACMX-3.0

SOIC

LP2951ACMX-3.0/NOPB

LP2951ACMX-3.3

SOIC

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

29-May-2013

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP2951ACMX-3.3/NOPB

LP2951ACMX/NOPB

LP2951ACSD

SOIC

2500

1000

4500

1000

3500

2500

1000

4500

367.0

210.0

367.0

210.0

367.0

210.0

367.0

185.0

367.0

185.0

367.0

185.0

367.0

35.0

WSON

VSSOP

SOIC

NGT

DGK

LP2951ACSD/NOPB

LP2951ACSDX

LP2951ACSDX-3.3

LP2951ACSDX-3.3/NOPB

LP2951ACSDX/NOPB

LP2951CMM

LP2951CMM-3.0

LP2951CMM-3.0/NOPB

LP2951CMM-3.3/NOPB

LP2951CMM/NOPB

LP2951CMMX

LP2951CMMX-3.0

LP2951CMMX-3.0/NOPB

LP2951CMMX-3.3

LP2951CMMX-3.3/NOPB

LP2951CMMX/NOPB

LP2951CMX

LP2951CMX-3.0

SOIC

LP2951CMX-3.0/NOPB

LP2951CMX-3.3

SOIC

LP2951CMX-3.3/NOPB

LP2951CMX/NOPB

LP2951CSD

SOIC

WSON

NGT

LP2951CSD-3.0

LP2951CSD-3.0/NOPB

LP2951CSD-3.3

LP2951CSD-3.3/NOPB

LP2951CSD/NOPB

LP2951CSDX

LP2951CSDX-3.0

LP2951CSDX-3.0/NOPB

LP2951CSDX-3.3

LP2951CSDX-3.3/NOPB

LP2951CSDX/NOPB

Pack Materials-Page 4

MECHANICAL DATA

NDP0003B

TD03B (Rev F)

www.ti.com

MECHANICAL DATA

NGT0008A

SDC08A (Rev A)

www.ti.com

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LP2950ACZ-5.0/LFT7 [TI]

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