LP2987AIMX-5.0/NOPB [TI]
具有电源正常指示和使能功能的 200mA、16V、低压降稳压器 | D | 8 | -40 to 125;
| 型号： | LP2987AIMX-5.0/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有电源正常指示和使能功能的 200mA、16V、低压降稳压器 | D | 8 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总36页 (文件大小：1352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP2987, LP2988
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SNVS004J –MARCH 1999–REVISED APRIL 2013
LP2987/LP2988 Micropower, 200 mA Ultra Low-Dropout Voltage Regulator with
Programmable Power-On Reset Delay; Low Noise Version Available (LP2988)
Check for Samples: LP2987, LP2988
1
FEATURES
DESCRIPTION
The LP2987/8 are fixed-output 200 mA precision LDO
voltage regulators with power-ON reset delay which
can be implemented using a single external capacitor.
2
•
Ultra Low Dropout Voltage
•
Power-ON Reset Delay Requires Only One
Component
The LP2988 is specifically designed for noise-critical
applications. A single external capacitor connected to
the Bypass pin reduces regulator output noise.
•
Bypass Pin for Reduced Output Noise
(LP2988)
•
•
•
•
•
•
•
•
•
Specified Continuous Output Current 200 mA
Specified Peak Output Current > 250 mA
SOIC-8 and VSSOP-8 Surface Mount Packages
<2 μA Quiescent Current when Shutdown
Low Ground Pin Current at All Loads
Using an optimized VIP (Vertically Integrated PNP)
process,
these
regulators
deliver
superior
performance:
Dropout Voltage: 180 mV @ 200 mA load, and 1
mV @ 1 mA load (typical).
0.5% Output Voltage Accuracy (“A” Grade)
Wide Supply Voltage Range (16V Max)
Overtemperature/overcurrent Protection
−40°C to +125°C Junction Temperature Range
Ground Pin Current: 1 mA @ 200 mA load, and 200
μA @ 10 mA load (typical).
Sleep Mode: The LP2987/8 draws less than 2 μA
quiescent current when shutdown pin is held low.
Error Flag/Reset: The error flag goes low when the
output drops approximately 5% below nominal. This
pin also provides a power-ON reset signal if a
capacitor is connected to the DELAY pin.
APPLICATIONS
•
•
•
Cellular Phone
Palmtop/Laptop Computer
Camcorder, Personal Stereo, Camera
Precision Output: Standard product versions of the
LP2987 and LP2988 are available with output
voltages of 5.0V, 3.8V, 3.3V, 3.2V, 3.0V, or 2.8V, with
specified accuracy of 0.5% (“A” grade) and 1%
(standard grade) at room temperature.
Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
www.ti.com
Connection Diagram (LP2987)
Figure 1. Top View
SOIC-8/VSSOP-8 Package
Surface Mount Packages
See Package Drawing Number D0008A/DGK0008A
1
8
SHUTDOWN
N/C
DELAY
2
7
ERROR
SENSE
GROUND
6
5
3
4
INPUT
OUTPUT
Figure 2. Top View
8-Lead WSON Surface Mount Package
See Package Drawing Number NGN0008A
Connection Diagram (LP2988)
Figure 3. Top View
SOIC-8/VSSOP-8 Package
Surface Mount Packages
See Package Drawing Number D0008A/DGK0008A
BYPASS
DELAY
1
2
8
7
SHUTDOWN
ERROR
GROUND
INPUT
3
4
6
5
SENSE
OUTPUT
Figure 4. Top View
8-Lead WSON Surface Mount Package
See Package Drawing Number NGN0008A
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SNVS004J –MARCH 1999–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Storage Temperature Range
−65°C to +150°C
−40°C to +125°C
Operating Junction
Temperature Range
Lead Temperature
(Soldering, 5 seconds)
260°C
2 kV
(3)
ESD Rating
(4)
Power Dissipation
Internally Limited
Input Supply Voltage
(Survival)
−0.3V to +16V
Input Supply Voltage
(Operating)
2.1V to +16V
−0.3V to +16V
−0.3V to +6V
Shutdown Pin
Sense Pin
Output Voltage
(5)
(Survival)
−0.3V to +16V
IOUT (Survival)
Short Circuit Protected
Input-Output Voltage
(6)
(Survival)
−0.3V to +16V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The ESD rating of the Bypass pin is 500V (LP2988 only). The ESD rating of the VIN pin is 1kV and the Delay pin is ESD rated at 1.5kV.
(4) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using:
The value of θJ−A for the SOIC-8 (D) package is 160°C/W, and the VSSOP-8 (DGK) package is 200°C/W.
The value θJ−A for the WSON (NGN) package is specifically dependent on PCB trace area, trace material, and the number of layers and
thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187
(literature number SNOA401). Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the LM2987/8 output must be diode-clamped
to ground.
(6) The output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Forcing the output
above the input will turn on this diode and may induce a latch-up mode which can damage the part (see APPLICATION HINTS).
ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
(1)
(1)
LM2987/8AI-X.X
LM2987/8I-X.X
Symbol
ΔVO
Parameter
Conditions
Typical
Units
%VNOM
%/V
Min
−0.5
−0.8
−1.8
Max
0.5
0.8
1.8
Min
−1.0
−1.6
−2.8
Max
1.0
Output Voltage Tolerance
0.1 mA < IL < 200 mA
1.6
2.8
ΔVO/ΔVIN
Output Voltage Line
Regulation
VO(NOM) + 1V ≤ VIN ≤ 16V
0.014
0.014
0.032
0.007
0.032
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
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ELECTRICAL CHARACTERISTICS (continued)
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
(1)
(1)
LM2987/8AI-X.X
LM2987/8I-X.X
Symbol
VIN–VO
Parameter
Conditions
IL = 100 µA
Typical
1
Units
Min
Max
2.0
Min
Max
2.0
Dropout Voltage
(2)
3.5
3.5
120
170
230
350
120
150
800
1400
2.1
IL = 75 mA
IL = 200 mA
IL = 100 µA
IL = 75 mA
IL = 200 mA
VS/D < 0.3V
120
170
230
350
120
150
800
90
mV
180
100
500
1
IGND
Ground Pin Current
µA
1400
2.1
mA
µA
3.7
3.7
0.05
400
400
1.5
1.5
IO(PK)
IO(MAX)
en
Peak Output Current
Short Circuit Current
VOUT ≥ VO(NOM) − 5%
250
250
mA
(3)
RL = 0 (Steady State)
LP2987 Output Noise
Voltage (RMS)
BW = 300 Hz to
50 kHz, VOUT = 3.3V
COUT = 10 µF
100
µV(RMS)
LP2988 Output Noise
Voltage (RMS)
BW = 300 Hz to 50 kHz,
VOUT = 3.3V
COUT = 10 µF
20
CBYPASS = .01 µF
ΔVOUT/ΔVIN
ΔVOUT/ΔT
IDELAY
Ripple Rejection
f = 1 kHz, COUT = 10 µF
CBYP = 0 (LP2988)
(4)
65
20
dB
Output Voltage
Temperature Coefficient
ppm/°C
Delay Pin Current Source
1.6
2.8
1.6
2.8
2.2
µA
1.4
3.0
1.4
3.0
SHUTDOWN INPUT
VS/D
S/D Input Voltage
VH = O/P ON
VL = O/P OFF
VS/D = 0
1.4
0.55
0
1.6
1.6
(5)
V
0.18
−1
0.18
−1
IS/D
S/D Input Current
µA
VS/D = 5V
5
15
15
(2) Dropout voltage is defined as the input to output differential at which the output voltage drops 100 mV below the value measured with a
1V differential.
(3) See TYPICAL PERFORMANCE CHARACTERISTICS curves.
(4) Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range.
(5) To prevent mis-operation, the Shutdown input must be driven by a signal that swings above VH and below VL with a slew rate not less
than 40 mV/µs (see APPLICATION HINTS).
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ELECTRICAL CHARACTERISTICS (continued)
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V.
(1)
(1)
LM2987/8AI-X.X
LM2987/8I-X.X
Symbol
Parameter
Conditions
Typical
Units
Min
Max
Min
Max
ERROR COMPARATOR
IOH
Output “HIGH” Leakage
VOH = 16V
1
1
0.01
150
µA
2
2
VOL
Output “LOW” Voltage
Upper Threshold Voltage
Lower Threshold Voltage
Hysteresis
VIN = VO(NOM) − 0.5V,
IO(COMP) = 300 µA
220
350
−3.5
−2.5
−4.9
−3.3
220
350
mV
VTHR
(MAX)
−5.5
−7.7
−5.5
−7.7
−3.5
−2.5
−4.9
−3.3
−4.6
VTHR
(MIN)
−8.9
−8.9
%VOUT
−6.6
−13.0
−13.0
HYST
2.0
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
VOUT
vs
Temperature
Dropout Voltage
vs
Temperature
Figure 5.
Figure 6.
Dropout Voltage
vs
Load Current
Dropout Characteristics
Figure 7.
Figure 8.
Ground Pin Current vs
Temperature and Load
Ground Pin Current vs
Load Current
Figure 9.
Figure 10.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Input Current
Input Current
vs
vs
VIN
VIN
Figure 11.
Figure 12.
Load Transient Response
Load Transient Response
Figure 13.
Figure 14.
Line Transient Response
Line Transient Response
Figure 15.
Figure 16.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Turn-On Waveform
Turn-On Waveform
Figure 17.
Figure 18.
Short Circuit Current
Short Circuit Current
Figure 19.
Figure 20.
Short Circuit Current
vs Output Voltage
Instantaneous Short Circuit Current
vs Temperature
Figure 21.
Figure 22.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Shutdown Pin Current vs
Shutdown Pin Voltage
DC Load Regulation
Figure 23.
Figure 24.
Shutdown Voltage
vs Temperature
Input to Output Leakage
vs Temperature
Figure 25.
Figure 26.
Delay Pin Current
vs
Delay Pin Current vs
Delay Pin Voltage
VIN
Figure 27.
Figure 28.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Delay Sink Current
Delay Sink Current
vs Temperature
vs
Temperature
Figure 29.
Figure 30.
Output Impedance
vs
Output Impedance
vs
Frequency
Frequency
Figure 31.
Figure 32.
Ripple Rejection (LP2987)
Ripple Rejection (LP2988)
Figure 33.
Figure 34.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Output Noise Density (LP2987)
Output Noise Voltage (LP2988)
Figure 35.
Figure 36.
Output Noise Density (LP2988)
Output Noise Density (LP2988)
Figure 37.
Figure 38.
Turn-On Time (LP2988)
Turn-On Time (LP2988)
Figure 39.
Figure 40.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA.
Turn-On Time (LP2988)
Figure 41.
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SNVS004J –MARCH 1999–REVISED APRIL 2013
BASIC APPLICATION CIRCUITS
Figure 42.
*Capacitance value shown is minimum required to assure stability, but may be increased without limit. Larger output
capacitor provides improved dynamic response.
**Shutdown must be actively terminated (see APPLICATION HINTS). Tie to INPUT (pin 4) if not used.
Figure 43.
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APPLICATION HINTS
WSON Package Devices
The LP2987/LP2988 is offered in the 8 lead WSON surface mount package to allow for increased power
dissipation compared to the SOIC-8 and the VSSOP-8. For details on thermal performance as well as mounting
and soldering specifications, refer to Application Note AN-1187 (literature number SNOA401).
EXTERNAL CAPACITORS
As with any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
INPUT CAPACITOR: An input capacitor (≥ 2.2 µF) is required between the LP2987/8 input and ground (amount
of capacitance may be increased without limit).
This capacitor must be located a distance of not more than 0.5” from the input pin and returned to a clean analog
ground. Any good quality ceramic or tantalum may be used for this capacitor.
OUTPUT CAPACITOR: The output capacitor must meet the requirement for minimum amount of capacitance
and also have an appropriate E.S.R. (equivalent series resistance) value.
Curves are provided which show the allowable ESR range as a function of load current for 3V and 5V outputs.
Figure 44. ESR Curves For 5V Output
Figure 45. ESR Curves For 3V Output
IMPORTANT: The output capacitor must maintain its ESR in the stable region over the full operating
temperature range of the application to assure stability.
The minimum required amount of output capacitance is 4.7 µF. Output capacitor size can be increased without
limit.
It is important to remember that capacitor tolerance and variation with temperature must be taken into
consideration when selecting an output capacitor so that the minimum required amount of output capacitance is
provided over the full operating temperature range. A good Tantalum capacitor will show very little variation with
temperature, but a ceramic may not be as good (see next section).
The output capacitor should be located not more than 0.5” from the output pin and returned to a clean analog
ground.
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CAPACITOR CHARACTERISTICS
TANTALUM: A solid tantalum capacitor is the best choice for the output capacitor on the LM2987/8. Available
from many sources, their typical ESR is very close to the ideal value required on the output of many LDO
regulators.
Tantalums also have good temperature stability: a 4.7 µF was tested and showed only a 10% decline in
capacitance as the temperature was decreased from +125°C to −40°C. The ESR increased only about 2:1 over
the same range of temperature.
However, it should be noted that the increasing ESR at lower temperatures present in all tantalums can cause
oscillations when marginal quality capacitors are used (where the ESR of the capacitor is near the upper limit of
the stability range at room temperature).
CERAMIC: The ESR of ceramic capacitor can be low enough to cause an LDO regulator to oscillate: a 2.2 µF
ceramic was measured and found to have an ESR of 15 mΩ.
If a ceramic capacitor is to be used on the LP2987/8 output, a 1Ω resistor should be placed in series with the
capacitor to provide a minimum ESR for the regulator.
A disadvantage of ceramic capacitors is that their capacitance varies a lot with temperature: Large ceramic
capacitors are typically manufactured with the Z5U temperature characteristic, which results in the capacitance
dropping by 50% as the temperature goes from 25°C to 80°C.
This means you have to buy a capacitor with twice the minimum COUT to assure stable operation up to 80°C.
ALUMINUM: The large physical size of aluminum electrolytics makes them unsuitable for most applications.
Their ESR characteristics are also not well suited to the requirements of LDO regulators. The ESR of a typical
aluminum electrolytic is higher than a tantalum, and it also varies greatly with temperature.
A typical aluminum electrolytic can exhibit an ESR increase of 50X when going from 20°C to −40°C. Also, some
aluminum electrolytics can not be used below −25°C because the electrolyte will freeze.
POWER-ON RESET DELAY
A power-on reset function can be easily implemented using the LP2987/8 by adding a single external capacitor to
the Delay pin. The Error output provides the power-on reset signal when input power is applied to the regulator.
The reset signal stays low for a pre-set time period after power is applied to the regulator, and then goes high
(see Timing Diagram below).
Figure 46. Timing Diagram for Power-Up
The external capacitor cDLY sets the delay time (TDELAY). The value of capacitor required for a given time delay
may be calculated using the formula:
CDLY = TDELAY/(5.59 X 105)
To simplify design, a plot is provided below which shows values of CDLY versus delay time.
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Figure 47. Plot of CDLY vs TDELAY
DETAILS OF ERR/RESET CIRCUIT OPERATION: (Refer to LP2987/8 Equivalent Circuit).
Figure 48. LP2987/8 Equivalent Circuit
The output of comparator U2 is the ERR/RESET flag. Since it is an open-collector output, it requires the use of a
pull-up resistor (RP). The 1.23V reference is tied to the inverting input of U2, which means that its output is
controlled by the voltage applied to the non-inverting input.
The output of U1 (also an open-collector) will force the non-inverting input of U2 to go low whenever the
LP2987/8 regulated output drops about 5% below nominal.
U1's inverting input is also held at 1.23V. The other input samples the regulated output through a resistive divider
(RA and RB). When the regulated output is at nominal voltage, the voltage at the divider tap point will be 1.23V. If
this voltage drops about 60 mV below 1.23V, the output of U1 will go low forcing the output of U2 low (which is
the ERROR state).
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Power-ON reset delay occurs when a capacitor (shown as CDLY) is connected to the Delay pin. At turn-ON, this
capacitor is initially fully discharged (which means the voltage at the Delay pin is 0V). The output of U1 keeps
CDLY fully discharged (by sinking the 2.2 µA from the current source) until the regulator output voltage comes up
to within about 5% of nominal. At this point, U1's output stops sinking current and the 2.2 µA starts charging up
CDLY
.
When the voltage across CDLY reaches 1.23V, the output of U2 will go high (note that D1 limits the maximum
voltage to about 2V).
SELECTING CDLY: The maximum recommended value for this capacitor is 1 µF. The capacitor must not have
excessively high leakage current, since it is being charged from a 2.2 µA current source.
Aluminum electrolytics can not be used, but good-quality tantalum, ceremic, mica, or film types will work.
SHUTDOWN INPUT OPERATION
The LP2987/8 is shut off by driving the Shutdown input low, and turned on by pulling it high. If this feature is not
to be used, the Shutdown input should be tied to VIN to keep the regulator output on at all times.
To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and
below the specified turn-on/turn-off voltage thresholds listed as VH and VL, respectively (see Electrical
Characteristics).
It is also important that the turn-on (and turn-off) voltage signals applied to the Shutdown input have a slew rate
which is not less than 40 mV/µs.
CAUTION
The regulator output state can not be ensured if a slow-moving AC (or DC) signal is
applied that is in the range between VH and VL.
REVERSE INPUT-OUTPUT VOLTAGE
The PNP power transistor used as the pass element in the LP2987/8 has an inherent diode connected between
the regulator output and input.
During normal operation (where the input voltage is higher than the output) this diode is reverse-biased.
However, if the output is pulled above the input, this diode will turn ON and current will flow into the regulator
output.
In such cases, a parasitic SCR can latch which will allow a high current to flow into VIN (and out the ground pin),
which can damage the part.
In any application where the output may be pulled above the input, an external Schottky diode must be
connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2987/8 to
0.3V (see Absolute Maximum Ratings).
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SNVS004J –MARCH 1999–REVISED APRIL 2013
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BYPASS CAPACITOR (LP2988)
The capacitor connected to the Bypass pin must have very low leakage. The current flowing out of the Bypass
pin comes from the Bandgap reference, which is used to set the output voltage. Since the Bandgap circuit has
only a few microamps flowing in it, loading effects due to leakage current will cause a change in the regulated
output voltage.
Curves are provided which show the effect of loading the Bypass pin on the regulated output voltage.
Care must be taken to ensure that the capacitor selected for bypass will not have significant leakage current over
the operating temperature range of the application.
A high quality ceramic capacitor which uses either NPO or COG type dielectiric material will typically have very
low leakage. Small surface-mount polypropolene or polycarbonate film capacitors also have extremely low
leakage, but are slightly larger in size than ceramics.
18
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Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LP2987 LP2988
LP2987, LP2988
www.ti.com
SNVS004J –MARCH 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision I (April 2013) to Revision J
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
Copyright © 1999–2013, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Links: LP2987 LP2988
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP2987AILD-3.0/NOPB
LP2987AILD-5.0/NOPB
LP2987AILDX-5.0/NOPB
LP2987AIMM-5.0/NOPB
LP2987AIMX-5.0/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
VSSOP
SOIC
NGN
NGN
NGN
DGK
D
8
8
8
8
8
1000 RoHS & Green
1000 RoHS & Green
4500 RoHS & Green
1000 RoHS & Green
2500 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L007A
Samples
Samples
Samples
Samples
Samples
SN
SN
SN
SN
L009A
L009A
L44A
2987A
IM5.0
LP2987ILD-3.3/NOPB
LP2987IM-3.0/NOPB
LP2987IM-3.3/NOPB
LP2987IM-5.0/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
SOIC
SOIC
SOIC
NGN
D
8
8
8
8
1000 RoHS & Green
SN
SN
SN
SN
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L008A
B
Samples
Samples
Samples
Samples
95
95
95
RoHS & Green
RoHS & Green
RoHS & Green
2987I
M3.0
D
2987I
M3.3
D
2987I
M5.0
LP2987IMM-3.3/NOPB
LP2987IMM-5.0/NOPB
LP2987IMMX-3.3/NOPB
LP2987IMX-3.0/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
8
8
1000 RoHS & Green
1000 RoHS & Green
3500 RoHS & Green
2500 RoHS & Green
SN
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L43B
L44B
L43B
Samples
Samples
Samples
Samples
2987I
M3.0
LP2987IMX-5.0/NOPB
LP2988AIM-5.0
ACTIVE
NRND
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500 RoHS & Green
SN
Call TI
SN
Level-1-260C-UNLIM
Level-1-235C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
2987I
M5.0
Samples
95
95
Non-RoHS
& Green
2988A
IM5.0
LP2988AIM-5.0/NOPB
ACTIVE
RoHS & Green
2988A
IM5.0
Samples
LP2988AIMM-3.0/NOPB
LP2988AIMM-3.3/NOPB
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
1000 RoHS & Green
1000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
L49A
Samples
Samples
L50A
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP2988AIMM-5.0/NOPB
LP2988AIMX-3.3/NOPB
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
1000 RoHS & Green
2500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
L51A
Samples
Samples
SN
2988A
IM3.3
LP2988ILD-3.8/NOPB
LP2988IM-5.0/NOPB
ACTIVE
ACTIVE
WSON
SOIC
NGN
D
8
8
1000 RoHS & Green
SN
SN
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
L083A B
Samples
Samples
95
RoHS & Green
2988I
M5.0
LP2988IMM-3.0/NOPB
LP2988IMM-3.3/NOPB
LP2988IMM-5.0
ACTIVE
ACTIVE
NRND
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
1000 RoHS & Green
1000 RoHS & Green
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
L49B
L50B
L51B
Samples
Samples
1000
Non-RoHS
& Green
Call TI
LP2988IMM-5.0/NOPB
LP2988IMMX-3.3/NOPB
LP2988IMX-5.0/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
1000 RoHS & Green
3500 RoHS & Green
2500 RoHS & Green
SN
SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
L51B
L50B
Samples
Samples
Samples
2988I
M5.0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2987AILD-3.0/NOPB
LP2987AILD-5.0/NOPB
WSON
WSON
NGN
NGN
NGN
DGK
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1000
1000
4500
1000
2500
1000
1000
1000
3500
2500
2500
1000
1000
1000
2500
1000
178.0
178.0
330.0
178.0
330.0
178.0
178.0
178.0
330.0
330.0
330.0
178.0
178.0
178.0
330.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
4.3
4.3
4.3
5.3
6.5
4.3
5.3
5.3
5.3
6.5
6.5
5.3
5.3
5.3
6.5
4.3
4.3
4.3
4.3
3.4
5.4
4.3
3.4
3.4
3.4
5.4
5.4
3.4
3.4
3.4
5.4
4.3
1.3
1.3
1.3
1.4
2.0
1.3
1.4
1.4
1.4
2.0
2.0
1.4
1.4
1.4
2.0
1.3
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LP2987AILDX-5.0/NOPB WSON
LP2987AIMM-5.0/NOPB VSSOP
LP2987AIMX-5.0/NOPB
LP2987ILD-3.3/NOPB
SOIC
WSON
NGN
DGK
DGK
DGK
D
LP2987IMM-3.3/NOPB VSSOP
LP2987IMM-5.0/NOPB VSSOP
LP2987IMMX-3.3/NOPB VSSOP
LP2987IMX-3.0/NOPB
LP2987IMX-5.0/NOPB
SOIC
SOIC
D
LP2988AIMM-3.0/NOPB VSSOP
LP2988AIMM-3.3/NOPB VSSOP
LP2988AIMM-5.0/NOPB VSSOP
DGK
DGK
DGK
D
LP2988AIMX-3.3/NOPB
LP2988ILD-3.8/NOPB
SOIC
WSON
NGN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP2988IMM-3.0/NOPB VSSOP
LP2988IMM-3.3/NOPB VSSOP
DGK
DGK
DGK
DGK
DGK
D
8
8
8
8
8
8
1000
1000
1000
1000
3500
2500
178.0
178.0
178.0
178.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
6.5
3.4
3.4
3.4
3.4
3.4
5.4
1.4
1.4
1.4
1.4
1.4
2.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
LP2988IMM-5.0
VSSOP
LP2988IMM-5.0/NOPB VSSOP
LP2988IMMX-3.3/NOPB VSSOP
LP2988IMX-5.0/NOPB
SOIC
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP2987AILD-3.0/NOPB
LP2987AILD-5.0/NOPB
LP2987AILDX-5.0/NOPB
LP2987AIMM-5.0/NOPB
LP2987AIMX-5.0/NOPB
LP2987ILD-3.3/NOPB
LP2987IMM-3.3/NOPB
LP2987IMM-5.0/NOPB
LP2987IMMX-3.3/NOPB
LP2987IMX-3.0/NOPB
LP2987IMX-5.0/NOPB
LP2988AIMM-3.0/NOPB
LP2988AIMM-3.3/NOPB
LP2988AIMM-5.0/NOPB
LP2988AIMX-3.3/NOPB
LP2988ILD-3.8/NOPB
LP2988IMM-3.0/NOPB
LP2988IMM-3.3/NOPB
WSON
WSON
WSON
VSSOP
SOIC
NGN
NGN
NGN
DGK
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1000
1000
4500
1000
2500
1000
1000
1000
3500
2500
2500
1000
1000
1000
2500
1000
1000
1000
208.0
208.0
356.0
208.0
367.0
208.0
208.0
208.0
367.0
367.0
367.0
208.0
208.0
208.0
367.0
208.0
208.0
208.0
191.0
191.0
356.0
191.0
367.0
191.0
191.0
191.0
367.0
367.0
367.0
191.0
191.0
191.0
367.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
WSON
VSSOP
VSSOP
VSSOP
SOIC
NGN
DGK
DGK
DGK
D
SOIC
D
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
WSON
VSSOP
VSSOP
NGN
DGK
DGK
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP2988IMM-5.0
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
D
8
8
8
8
1000
1000
3500
2500
208.0
208.0
367.0
367.0
191.0
191.0
367.0
367.0
35.0
35.0
35.0
35.0
LP2988IMM-5.0/NOPB
LP2988IMMX-3.3/NOPB
LP2988IMX-5.0/NOPB
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LP2987IM-3.0/NOPB
LP2987IM-3.3/NOPB
LP2987IM-5.0/NOPB
LP2988AIM-5.0
D
D
D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
8
8
8
8
8
8
95
95
95
95
95
95
95
495
495
495
495
495
495
495
8
8
8
8
8
8
8
4064
4064
4064
4064
4064
4064
4064
3.05
3.05
3.05
3.05
3.05
3.05
3.05
LP2988AIM-5.0
LP2988AIM-5.0/NOPB
LP2988IM-5.0/NOPB
Pack Materials-Page 5
PACKAGE OUTLINE
NGN0008A
WSON - 0.8 mm max height
SCALE 3.000
PLASTIC SMALL OUTLINE - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
PIN 1 ID
DETAIL A
PIN 1 ID
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.2 0.05
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
6X 0.8
4
5
2X
2.4
SYMM
9
3
0.05
SEE
DETAIL A
8
1
0.35
0.25
8X
(0.25)
(0.25)
0.6
0.4
(0.2)
8X
0.1
C A B
C
0.05
PIN 1 ID
(0.15)
4214794/A 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NGN0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(2.2)
SYMM
8X (0.5)
8X (0.3)
1
8
SYMM
9
(3)
(1.25)
5
6X (0.8)
4
(R0.05) TYP
(
0.2) VIA
TYP
(0.85)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214794/A 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
NGN0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
0.59
SYMM
METAL
TYP
8X (0.5)
8X (0.3)
1
8
4X (1.31)
SYMM
9
(0.755)
6X (0.8)
5
4
(R0.05) TYP
4X (0.98)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214794/A 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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