LP2996MRX/NOPB [TI]

具有 DDR2 关断引脚的 1.5A DDR 终端稳压器 | DDA | 8 | 0 to 125;


型号：	LP2996MRX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有 DDR2 关断引脚的 1.5A DDR 终端稳压器 \| DDA \| 8 \| 0 to 125 双倍数据速率光电二极管接口集成电路稳压器
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LP2996-N

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SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013

LP2996-N DDR Termination Regulator

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FEATURES

DESCRIPTION

The LP2996-N linear regulator is designed to meet

the JEDEC SSTL-2 specifications for termination of

DDR-SDRAM. The device contains a high-speed

operational amplifier to provide excellent response to

load transients. The output stage prevents shoot

through while delivering 1.5A continuous current and

transient peaks up to 3A in the application as

required for DDR-SDRAM termination. The LP2996-N

also incorporates a V_SENSEpin to provide superior

load regulation and a V_REFoutput as a reference for

the chipset and DIMMs.

•

Source and Sink Current

Low Output Voltage Offset

No External Resistors Required

Linear Topology

Suspend to Ram (STR) Functionality

Low External Component Count

Thermal Shutdown

Available in SOIC-8, SO PowerPAD-8 or

WQFN-16 packages

An additional feature found on the LP2996-N is an

active low shutdown (SD) pin that provides Suspend

To RAM (STR) functionality. When SD is pulled low

APPLICATIONS

•

DDR-I and DDR-II Termination Voltage

SSTL-2 and SSTL-3 Termination

HSTL Termination

the V_TToutput will tri-state providing

high

impedance output, but, V_REFwill remain active. A

power savings advantage can be obtained in this

mode through lower quiescent current.

Typical Application Circuit

LP2996

V_REF= 1.25V

V_REF

0.01mF

220mF

V_DDQ

V_DDQ= 2.5V

V_DD= 2.5V

V_SENSE

AV_IN

PV_IN

V_TT

V_TT= 1.25V

GND

47mF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP2996-N

SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013

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Connection Diagram

VTT

GND

PVIN

AVIN

VDDQ

VSENSE

VREF

VSENSE

N/C

VTT

Figure 2. SOIC-8 Layout

GND

VREF

VDDQ

N/C

10 11 12

VTT

GND

PVIN

AVIN

VDDQ

VSENSE

VREF

GND

Figure 1. WQFN-16 Layout (Top View)

Figure 3. SO PowerPAD-8 Layout

PIN DESCRIPTIONS

SOIC-8 Pin

or SO

PowerPAD-8

WQFN Pin

Name

Function

GND

Ground

Shutdown

VSENSE

VREF

VDDQ

AVIN

PVIN

VTT

Feedback pin for regulating V_TT

Buffered internal reference voltage of V_DDQ/2

Input for internal reference equal to V_DDQ/2

Analog input pin

11, 12

Power input pin

14, 15

Output voltage for connection to termination resistors

No internal connection

1, 3, 6, 9, 13, 16

Exposed pad thermal connection. Connect to Ground.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings⁽¹⁾⁽²⁾

AVIN to GND

−0.3V to +6V

-0.3V to AVIN

−0.3V to +6V

−65°C to +150°C

150°C

PVIN to GND

VDDQ⁽³⁾

Storage Temp. Range

Junction Temperature

SOIC-8 Thermal Resistance (θ_JA

)

151°C/W

SO PowerPAD-8 Thermal Resistance (θ_JA

)

43°C/W

WQFN-16 Thermal Resistance (θ_JA

)

51°C/W

Lead Temperature (Soldering, 10 sec)

ESD Rating⁽⁴⁾

260°C

1kV

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which

the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions

see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.

(4) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

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Operating Range

Junction Temp. Range⁽¹⁾

AVIN to GND

0°C to +125°C

2.2V to 5.5V

0 to AVIN

PVIN Supply Voltage

SD Input Voltage

0 to AVIN

(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at

θ_JA= 151.2° C/W junction to ambient with no heat sink.

Electrical Characteristics

Specifications with standard typeface are for T_J= 25°C and limits in boldface type apply over the full Operating

Temperature Range (T_J= 0°C to +125°C)⁽¹⁾. Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V⁽²⁾

Symbol

Parameter

V_REFVoltage

Conditions

Min

Typ

Max

Units

V_REF

VIN = VDDQ = 2.3V

VIN = VDDQ = 2.5V

VIN = VDDQ = 2.7V

1.135

1.235

1.335

1.158

1.258

1.358

1.185

1.285

1.385

Z_VREF

V_TT

V_REFOutput Impedance

V_TTOutput Voltage

I_REF= -30 to +30 μA

2.5

kΩ

I_OUT= 0A

VIN = VDDQ = 2.3V

VIN = VDDQ = 2.5V

VIN = VDDQ = 2.7V

I_OUT= ±1.5A⁽³⁾

1.125

1.225

1.325

1.159

1.259

1.359

1.190

1.290

1.390

VIN = VDDQ = 2.3V

VIN = VDDQ = 2.5V

VIN = VDDQ = 2.7V

1.125

1.225

1.325

1.159

1.259

1.359

1.190

1.290

1.390

Vos_TT/V_TT

V_TTOutput Voltage Offset

I_OUT= 0A

-20

-25

(V_REF-V_TT

)

I_OUT= -1.5A⁽³⁾

I_OUT= +1.5A⁽³⁾

I_Q

Quiescent Current⁽⁴⁾

I_OUT= 0A⁽¹⁾

320

100

115

500

µA

kΩ

µA

Z_VDDQ

I_SD

VDDQ Input Impedance

Quiescent Current in

Shutdown⁽⁴⁾

SD = 0V

150

I_{Q_SD}

V_IH

Shutdown Leakage Current

µA

Minimum Shutdown High

Level

1.9

V_IL

I_V

Maximum Shutdown Low

Level

0.8

V_TTLeakage Current in

Shutdown

SD = 0V

V_TT= 1.25V

µA

I_SENSE

T_SD

V_SENSEInput Current

165

Thermal Shutdown

See⁽⁵⁾

Celcius

T_SD_HYS

Thermal Shutdown Hysteresis

(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using

Statistical Quality Control (SQC) methods. The limits are used to calculate Texas Instruments' Average Outgoing Quality Level (AOQL).

(2) VIN is defined as VIN = AVIN = PVIN.

(3) V_TTload regulation is tested by using a 10 ms current pulse and measuring V_TT

(4) Quiescent current defined as the current flow into AVIN.

(5) The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction to ambient thermal

resistance, θ_JA, and the ambient temperature, T_A. Exceeding the maximum allowable power dissipation will cause excessive die

temperature and the regulator will go into thermal shutdown.

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Typical Performance Characteristics

Iq vs AV_INin SD

Iq vs AV_IN

400

350

300

250

200

150

100

1050

900

750

600

450

300

150

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

AV_IN(V)

Figure 4.

Figure 5.

V_IHand V_IL

V_REFvs I_REF

3.5

1.40

1.35

1.30

1.25

1.20

1.15

1.10

2.5

1.5

0.5

2.5

3.5

4.5

5.5

-30

-20

-10

AV_IN(V)

I_REF(uA)

Figure 6.

Figure 7.

V_REFvs V_DDQ

V_TTvs I_OUT

2.5

1.275

1.270

1.265

1.260

1.255

1.250

1.245

1.5

0.5

-100 -75 -50 -25

25 50 75 100

V_DDQ(V)

I_OUT(mA)

Figure 8.

Figure 9.

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Typical Performance Characteristics (continued)

V_TTvs V_DDQ

Iq vs AV_INin SD Temperature

400

350

300

250

200

150

100

2.5

0^oC

125^oC

1.5

0.5

2.5

3.5

4.5

5.5

AV_IN(V)

V_DDQ(V)

Figure 10.

Figure 11.

Maximum Sourcing Current vs AV_IN

(V_DDQ= 2.5V, PV_IN= 1.8V)

Iq vs AV_INTemperature

85^oC

1050

900

750

600

450

300

150

1.4

1.2

25^oC

0.8

0.6

0.4

0.2

0^oC

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

AV_IN(V)

Figure 12.

Figure 13.

Maximum Sourcing Current vs AV_IN

(V_DDQ= 2.5V, PV_IN= 2.5V)

Maximum Sourcing Current vs AV_IN

(V_DDQ= 2.5V, PV_IN= 3.3V)

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

2.8

2.6

2.4

2.2

2.5

3.5

4.5

5.5

3.5

4.5

5.5

AV_IN(V)

Figure 15.

Figure 14.

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Typical Performance Characteristics (continued)

Maximum Sinking Current vs AV_IN

(V_DDQ= 2.5V)

Maximum Sourcing Current vs AV_IN

(V_DDQ= 1.8V, PV_IN= 1.8V)

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

2.5

3.5

4.5

5.5

2.5

3.5

4.5

5.5

AV_IN(V)

Figure 16.

Figure 17.

Maximum Sinking Current vs AV_IN

(V_DDQ= 1.8V)

Maximum Sourcing Current vs AV_IN

(V_DDQ= 1.8V, PV_IN= 3.3V)

2.4

2.2

2.8

2.6

2.4

2.2

1.8

1.6

1.4

1.2

2.5

3.5

4.5

5.5

3.5

4.5

5.5

AV_IN(V)

Figure 19.

Figure 18.

BLOCK DIAGRAM

V_DDQ

AV_IN

PV_IN

50k

V_REF

V_TT

V_SENSE

GND

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LP2996-N

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SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013

Description

The LP2996-N is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The

output, V_TTis capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The

output stage has been designed to maintain excellent load regulation while preventing shoot through. The

LP2996-N also incorporates two distinct power rails that separates the analog circuitry from the power output

stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the

LP2996-N to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). For new

designs, the LP2997 or LP2998 is recommended for DDR-II applications. The LP2996-N can also be used to

provide a termination voltage for other logic schemes such as SSTL-3 or HSTL.

Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the

memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting

at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single

parallel termination. This involves one R_Sseries resistor from the chipset to the memory and one R_Ttermination

resistor. Typical values for R_Sand R_Tare 25 Ohms, although these can be changed to scale the current

requirements from the LP2996-N. This implementation can be seen below in Figure 20.

V_DD

V_TT

R_T

MEMORY

R_S

CHIPSET

V_REF

Figure 20. SSTL-Termination Scheme

PIN DESCRIPTIONS

AVIN AND PVIN

AVIN and PVIN are the input supply pins for the LP2996-N. AVIN is used to supply all the internal control

circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT.

These pins have the capability to work off separate supplies depending on the application. Higher voltages on

PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages

close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally

limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN

directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only

limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to

connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of

excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will

enter a shutdown state identical to the manual shutdown where V_TTis tri-stated and V_REFremains active.

VDDQ

VDDQ is the input used to create the internal reference voltage for regulating V_TT. The reference voltage is

generated from a resistor divider of two internal 50kΩ resistors. This ensures that V_TTwill track VDDQ / 2

precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting

VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage

tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2

applications VDDQ will be a 2.5V signal, which will create a 1.25V termination voltage at V_TT(See Electrical

Characteristics Table for exact values of V_TTover temperature).

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V_SENSE

The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications

the termination resistors will connect to V_TTin a long plane. If the output voltage was regulated only at the output

of the LP2996-N then the long trace will cause a significant IR drop resulting in a termination voltage lower at

one end of the bus than the other. The V_SENSEpin can be used to improve this performance, by connecting it to

the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load

regulation is not used then the V_SENSEpin must still be connected to V_TT. Care should be taken when a long

V_SENSEtrace is implemented in close proximity to the memory. Noise pickup in the V_SENSEtrace can cause

problems with precise regulation of V_TT. A small 0.1uF ceramic capacitor placed next to the V_SENSEpin can help

filter any high frequency signals and preventing errors.

SHUTDOWN

The LP2996-N contains an active low shutdown pin that can be used to tri-state VTT. During shutdown V_TT

should not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current

of the LP2996-N will drop, however, V_DDQwill always maintain its constant impedance of 100kΩ for generating

the internal reference. Therefore to calculate the total power loss in shutdown both currents need to be

considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal

pull-up current, therefore to turn the part on the shutdown pin can either be connected to AVIN or left open.

V_REF

V_REFprovides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to

provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an

extremely high impedance, there should be little current drawn from V_REF. For improved performance, an output

bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of

0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal shutdown

events for the suspend to RAM functionality.

V_TT

V_TTis the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing

current while regulating the output precisely to VDDQ / 2. The LP2996-N is designed to handle peak transient

currents of up to ± 3A with a fast transient response. The maximum continuous current is a function of V_INand

can be viewed in the Typical Performance Characteristics section. If a transient is expected to last above the

maximum continuous current rating for a significant amount of time then the output capacitor should be sized

large enough to prevent an excessive voltage drop. Despite the fact that the LP2996-N is designed to handle

large transient output currents it is not capable of handling these for long durations, under all conditions. The

reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal

power loss. If large currents are required for longer durations, then care should be taken to ensure that the

maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to

the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than V_TTwill tri-

state until the part returns below the hysteretic trip-point.

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COMPONENT SELECTIONS

INPUT CAPACITOR

The LP2996-N does not require a capacitor for input stability, but it is recommended for improved performance

during large load transients to prevent the input rail from dropping. The input capacitor should be located as

close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A

typical value recommended for AL electrolytic capacitors is 50 µF. Ceramic capacitors can also be used, a value

in the range of 10 µF with X5R or better would be an ideal choice. The input capacitance can be reduced if the

LP2996-N is placed close to the bulk capacitance from the output of the 2.5V DC-DC converter. If the two supply

rails (AVIN and PVIN) are separated then the 47uF capacitor should be placed as close to possible to the PVIN

rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from

coupling into the device.

OUTPUT CAPACITOR

The LP2996-N has been designed to be insensitive of output capacitor size or ESR (Equivalent Series

Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be

determined solely on the application and the requirements for load transient response of V_TT. As a general

recommendation the output capacitor should be sized above 100 µF with a low ESR for SSTL applications with

DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent

at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few

of these are highlighted below:

AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which

indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance

specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2996-N. To improve the

ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware

of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their

ESR rapidly increase at cold temperatures.

Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have

excellent AC performance for bypassing noise because of very low ESR (typically less than 10 mΩ). However,

some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.

Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with

another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic

capacitors.

Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These

offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance

are critical, although their cost is typically higher than any other capacitor.

Thermal Dissipation

Since the LP2996-N is a linear regulator any current flow from V_TTwill result in internal power dissipation

generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature,

care should be taken to derate the part dependent on the maximum expected ambient temperature and power

dissipation. The maximum allowable internal temperature rise (T_Rmax) can be calculated given the maximum

ambient temperature (T_Amax) of the application and the maximum allowable junction temperature (T_Jmax).

T_Rmax= T_Jmax− T_Amax

(1)

From this equation, the maximum power dissipation (P_Dmax) of the part can be calculated:

P_Dmax= T_Rmax/ θ_JA

(2)

The θ_JAof the LP2996-N will be dependent on several variables: the package used; the thickness of copper; the

number of vias and the airflow. For instance, the θ_JAof the SOIC-8 is 163°C/W with the package mounted to a

standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value

can be reduced to 151.2°C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard.

Figure 21 shows how the θ_JAvaries with airflow for the two boards mentioned.

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180

170

160

150

140

130

120

110

100

SOP Board

JEDEC Board

200

400

600

800

1000

AIRFLOW (Linear Feet per Minute)

Figure 21. θ_JAvs Airflow (SOIC-8)

Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an

internal ground plane. Using larger traces and more copper on the top side of the board can also help. With

careful layout it is possible to reduce the θ_JAfurther than the nominal values shown in Figure 21

Layout is also extremely critical to maximize the output current with the WQFN package. By simply placing vias

under the DAP the θ_JAcan be lowered significantly. Figure 22 shows the WQFN thermal data when placed on a

4-layer JEDEC board with copper thickness of 0.5/1/1/0.5 oz. The number of vias, with a pitch of 1.27 mm, has

been increased to the maximum of 4 where a θ_JAof 50.41°C/W can be obtained. Via wall thickness for this

calculation is 0.036 mm for 1oz. Copper.

100

NUMBER OF VIAS

Figure 22. WQFN-16 θ_JAvs # of Vias (4 Layer JEDEC Board))

Additional improvements in lowering the θ_JAcan also be achieved with a constant airflow across the package.

Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 23 shows how the θ_JAvaries

with airflow.

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100

200

300

400

500

600

AIRFLOW (Linear Feet Per Minute)

Figure 23. θ_JAvs Airflow Speed (JEDEC Board with 4 Vias)

Optimizing the θ_JAand placing the LP2996-N in a section of a board exposed to lower ambient temperature

allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by

summing the three main sources of loss: output current at V_TT, either sinking or sourcing, and quiescent current

at AVIN and VDDQ. During the active state (when shutdown is not held low) the total internal power dissipation

can be calculated from the following equations:

P_D= P_AVIN+ P_VDDQ+ P_VTT

where

P_AVIN= I_AVIN* V_AVIN

(3)

(4)

(5)

P_VDDQ= V_VDDQ* I_VDDQ= V_VDDQ2x R_VDDQ

To calculate the maximum power dissipation at V_TTboth conditions at V_TTneed to be examined, sinking and

sourcing current. Although only one equation will add into the total, V_TTcannot source and sink current

simultaneously.

P_VTT= V_VTTx I_LOAD(Sinking) or

(6)

(7)

P_VTT= ( V_PVIN- V_VTT) x I_LOAD(Sourcing

The power dissipation of the LP2996-N can also be calculated during the shutdown state. During this condition

the output V_TTwill tri-state, therefore that term in the power equation will disappear as it cannot sink or source

any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at

AVIN and the constant impedance that is seen at the VDDQ pin.

P_D= P_AVIN+ P_VDDQ

(8)

(9)

P_AVIN= I_AVINx V_AVIN

P_VDDQ= V_VDDQ* I_VDDQ= V_VDDQ2x R_VDDQ

(10)

Typical Application Circuits

Several different application circuits have been shown in Figure 24 through Figure 33 to illustrate some of the

options that are possible in configuring the LP2996-N. Graphs of the individual circuit performance can be found

in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how

the maximum output current is affected by changes in AVIN and PVIN.

SSTL-2 APPLICATIONS

For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all

the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation and component count

and selection. An example of this circuit can be seen in Figure 24.

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LP2996

V_REF= 1.25V

V_REF

C_REF

V_DDQ

V_DDQ= 2.5V

V_SENSE

AV_IN

PV_IN

V_DD= 2.5V

V_TT

V_TT= 1.25V

GND

C_OUT

C_IN

Figure 24. Recommended SSTL-2 Implementation

If power dissipation or efficiency is a major concern then the LP2996-N has the ability to operate on split power

rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can

be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered

when sourcing current from V_TT. The disadvantage of this circuit is that the maximum continuous current is

reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications.

Increasing the output capacitance can also help if periods of large load transients will be encountered.

LP2996

V_REF= 1.25V

V_REF

C_REF

V_DDQ

V_DDQ= 2.5V

V_SENSE

AV_IN

PV_IN

AV_IN= 2.2V to 5.5V

PV_IN= 1.8V

V_TT

V_TT= 1.25V

GND

C_IN

C_OUT

Figure 25. Lower Power Dissipation SSTL-2 Implementation

The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to

use 2.5V, is to connect the LP2996-N power rail to 3.3V. In this situation AVIN will be limited to operation on the

3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum

continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the

LP2996-N from experiencing large current levels which cause the junction temperature to exceed the maximum.

Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V

rail.

LP2996

V_REF= 1.25V

V_REF

C_REF

V_DDQ

V_DDQ= 2.5V

V_SENSE

AV_IN

PV_IN

AV_IN= 3.3V or 5V

PV_IN= 3.3V

V_TT

V_TT= 1.25V

GND

C_OUT

C_IN

Figure 26. SSTL-2 Implementation with higher voltage rails

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DDR-II APPLICATIONS

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996-N in applications

utilizing DDR-II memory. Figure 25 and Figure 26 show several implementations of recommended circuits with

output curves displayed in the Typical Performance Characteristics. Figure 25 shows the recommended circuit

configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be

connected to either a 3.3V or 5V rail. For new designs, the LP2997 or LP2998 is recommended for DDR-II

applications.

LP2996

V_REF= 0.9V

V_REF

C_REF

V_DDQ

V_DDQ= 1.8V

V_SENSE

AV_IN

PV_IN

AV_IN= 2.2V to 5.5V

PV_IN= 1.8V

V_TT

V_TT= 0.9V

GND

C_OUT

C_IN

Figure 27. Recommended DDR-II Termination

If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be

taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower V_TT

output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3V.

The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous

current.

LP2996

V_REF= 0.9V

V_REF

C_REF

V_DDQ

V_DDQ= 1.8V

V_SENSE

AV_IN

PV_IN

AV_IN= 3.3V or 5.5V

PV_IN= 3.3V

V_TT

V_TT= 0.9V

GND

C_OUT

C_IN

Figure 28. DDR-II Termination with higher voltage rails

LEVEL SHIFTING

If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling

factor than 0.5 times V_DDQfor regulating the output voltage. Several options are available to scale the output to

any voltage required. One method is to level shift the output by using feedback resistors from V_TTto the V_SENSE

pin. This has been illustrated in Figure 29 and Figure 30. Figure 29 shows how to use two resistors to level shift

V_TTabove the internal reference voltage of VDDQ/2. To calculate the exact voltage at V_TTthe following equation

can be used.

V_TT= VDDQ/2 ( 1 + R1/R2)

(11)

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LP2996

V_DDQ

AV_IN

PV_IN

V_DD

V_TT

R₁

R₂

V_SENSE

C_OUT

GND

C_IN

Figure 29. Increasing VTT by Level Shifting

Conversely, the R2 resistor can be placed between V_SENSEand V_DDQto shift the V_TToutput lower than the

internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below:

V_TT= VDDQ/2 (1 - R1/R2)

(12)

LP2996

R₂

R₁

V_DDQ

AV_IN

PV_IN

V_SENSE

V_DD

V_TT

C_OUT

GND

C_IN

Figure 30. Decreasing VTT by Level Shifting

HSTL APPLICATIONS

The LP2996-N can be easily adapted for HSTL applications by connecting V_DDQto the 1.5V rail. This will

produce a V_TTand V_REFvoltage of approximately 0.75V for the termination resistors. AVIN and PVIN should be

connected to a 2.5V rail for optimal performance.

LP2996

V_REF= 0.75V

V_REF

C_REF

V_DDQ

V_DDQ= 1.5V

V_SENSE

AV_IN

PV_IN

V_DD= 2.5V

V_TT

V_TT= 0.75V

GND

C_OUT

C_IN

Figure 31. HSTL Application

QDR APPLICATIONS

Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this

increase in bus lines has the effect of increasing the current levels required for termination. The recommended

approach in terminating multiple channels is to use a dedicated LP2996-N for each channel. This simplifies

layout and reduces the internal power dissipation for each regulator. Separate V_REFsignals can be used for each

DIMM bank from the corresponding regulator with the chipset reference provided by a local resistor divider or

one of the LP2996-N signals. Because V_REFand V_TTare expected to track and the part to part variations are

minor, there should be little difference between the reference signals of each LP2996-N.

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SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013

OUTPUT CAPACITOR SELECTION

For applications utilizing the LP2996-N to terminate SSTL-2 I/O signals the typical application circuit shown in

Figure 30 can be implemented.

LP2996

V_REF= 1.25V

V_REF

0.01mF

220mF

V_DDQ

V_DDQ= 2.5V

V_SENSE

AV_IN

PV_IN

V_DD= 2.5V

V_TT

V_TT= 1.25V

GND

47mF

Figure 32. Typical SSTL-2 Application Circuit

This circuit permits termination in a minimum amount of board space and component count. Capacitor selection

can be varied depending on the number of lines terminated and the maximum load transient. However, with

motherboards and other applications where V_TTis distributed across a long plane it is advisable to use multiple

bulk capacitors and addition to high frequency decoupling. Figure 31 shown below depicts an example circuit

where 2 bulk output capacitors could be situated at both ends of the V_TTplane for optimal placement. Large

aluminum electrolytic capacitors are used for their low ESR and low cost.

LP2996

V_REF= 1.25V

0.01mF

V_REF

V_DDQ

V_DDQ= 2.5V

AV_IN

PV_IN

V_DD= 2.5V

V_SENSE

V_TT

V_TT= 1.25V

330mF

GND

47mF

330mF

Figure 33. Typical SSTL-2 Application Circuit for Motherboards

In most PC applications an extensive amount of decoupling is required because of the long interconnects

encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic

capacitors in the range of 1000uF are typically used.

PCB Layout Considerations

1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.

2. V_SENSEshould be connected to the V_TTtermination bus at the point where regulation is required. For

motherboard applications an ideal location would be at the center of the termination bus.

3. V_DDQcan be connected remotely to the V_DDQrail input at either the DIMM or the Chipset. This provides the

most accurate point for creating the reference voltage.

4. For improved thermal performance excessive top side copper should be used to dissipate heat from the

package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these

can be located underneath the package if manufacturing standards permit.

5. Care should be taken when routing the V_SENSEtrace to avoid noise pickup from switching I/O signals. A

0.1uF ceramic capacitor located close to the

can also be used to filter any unwanted high frequency

SENSE

signal. This can be an issue especially if long _SENSEtraces are used.

6. V_REFshould be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This

capacitor should be located as close as possible to the V_REFpin.

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SNOSA40J –NOVEMBER 2002–REVISED MARCH 2013

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REVISION HISTORY

Changes from Revision I (March 2013) to Revision J

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 15

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PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

PACKAGING INFORMATION

Orderable Device

LP2996LQ/NOPB

LP2996LQX/NOPB

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

WQFN

NHP

1000

Green (RoHS

& no Sb/Br)

Level-3-260C-168 HR

L00006B

ACTIVE

NHP

4500

Green (RoHS

& no Sb/Br)

Level-3-260C-168 HR

0 to 125

L00006B

LP2996M

NRND

SOIC

TBD

Call TI

CU SN

Call TI

0 to 125

2996M

LP2996M/NOPB

ACTIVE

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

LP2996MR

NRND SO PowerPAD

ACTIVE SO PowerPAD

DDA

TBD

Call TI

CU SN

Call TI

0 to 125

LP2996

LP2996MR/NOPB

Green (RoHS

& no Sb/Br)

Level-3-260C-168 HR

LP2996MRX

NRND SO PowerPAD

ACTIVE SO PowerPAD

DDA

2500

TBD

Call TI

CU SN

Call TI

0 to 125

LP2996

LP2996MRX/NOPB

Green (RoHS

& no Sb/Br)

Level-3-260C-168 HR

LP2996MX/NOPB

ACTIVE

SOIC

2500

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

0 to 125

2996M

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP2996LQ/NOPB

LP2996LQX/NOPB

LP2996MRX

WQFN

NHP

DDA

1000

4500

2500

178.0

330.0

12.4

4.3

6.5

4.3

5.4

1.3

2.0

8.0

12.0

Power

PAD

LP2996MRX/NOPB

LP2996MX/NOPB

Power

PAD

DDA

2500

330.0

12.4

6.5

5.4

2.0

8.0

12.0

SOIC

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Sep-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP2996LQ/NOPB

LP2996LQX/NOPB

LP2996MRX

WQFN

NHP

DDA

1000

4500

2500

213.0

367.0

191.0

367.0

55.0

35.0

SO PowerPAD

SOIC

LP2996MRX/NOPB

LP2996MX/NOPB

Pack Materials-Page 2

MECHANICAL DATA

DDA0008A

MRA08A (Rev D)

www.ti.com

MECHANICAL DATA

NHP0016A

LQA16A (REV A)

www.ti.com

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