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LP3853ET-2.5/NOPB [TI]

具有电源正常指示和使能功能的 3A、7V、超低压降稳压器 | NDH | 5 | -40 to 125;
LP3853ET-2.5/NOPB
型号： LP3853ET-2.5/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有电源正常指示和使能功能的 3A、7V、超低压降稳压器 | NDH | 5 | -40 to 125

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LP3853, LP3856  
www.ti.com  
SNVS173G –FEBRUARY 2003–REVISED APRIL 2013  
LP3853/LP3856 3A Fast Response Ultra Low Dropout Linear Regulators  
Check for Samples: LP3853, LP3856  
1
FEATURES  
DESCRIPTION  
The LP3853/LP3856 series of fast ultra low-dropout  
linear regulators operate from a +2.5V to +7.0V input  
supply. Wide range of preset output voltage options  
are available. These ultra low dropout linear  
regulators respond very quickly to step changes in  
load, which makes them suitable for low voltage  
microprocessor applications. The LP3853/LP3856 are  
developed on a CMOS process which allows low  
quiescent current operation independent of output  
load current. This CMOS process also allows the  
LP3853/LP3856 to operate under extremely low  
dropout conditions.  
2
•
•
•
•
•
•
•
•
•
•
•
•
Ultra Low Dropout Voltage  
Stable with Selected Ceramic Capacitors  
Low Ground Pin Current  
Load Regulation of 0.08%  
10nA Quiescent Current in Shutdown Mode  
Ensured Output Current of 3A DC  
Available in TO-263 and TO-220 Packages  
Output Voltage Accuracy ± 1.5%  
Error Flag Indicates Output Status  
Sense Option Improves Load Regulation  
Overtemperature/overcurrent Protection  
−40°C to +125°C Junction Temperature Range  
Dropout Voltage: Ultra low dropout voltage; typically  
39mV at 300mA load current and 390mV at 3A load  
current.  
Ground Pin Current: Typically 4mA at 3A load  
current.  
APPLICATIONS  
•
•
•
•
•
•
•
•
•
Microprocessor Power Supplies  
Stable with Ceramic Output Capacitors  
GTL, GTL+, BTL, and SSTL Bus Terminators  
Power Supplies for DSPs  
Shutdown Mode: Typically 10nA quiescent current  
when the shutdown pin is pulled low.  
Error Flag:Error flag goes low when the output  
voltage drops 10% below nominal value.  
SCSI Terminator  
SENSE: Sense pin improves regulation at remote  
loads.  
Post Regulators  
High Efficiency Linear Regulators  
Battery Chargers  
Precision Output Voltage: Multiple output voltage  
options are available ranging from 1.8V to 5.0V with a  
ensured accuracy of ±1.5% at room temperature, and  
±3.0% over all conditions (varying line, load, and  
temperature).  
Other Battery Powered Applications  
Typical Application Circuits  
V
INPUT  
3.3V ± 10%  
OUT  
V
V
OUT  
IN  
1.8V, 3.0A  
C
*
C *  
OUT  
10 mF  
IN  
10 mF  
LP3853-1.8  
SD  
ERROR  
GND  
ERROR**  
SD**  
* TANTALUM OR  
CERAMIC  
**SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this  
function is not used. See Application Hints for more information.  
V
INPUT  
3.3V ± 10%  
OUT  
1.8V, 3.0A  
V
V
OUT  
IN  
C
*
C *  
OUT  
10 mF  
IN  
10 mF  
LP3856-1.8  
SD  
SENSE  
GND  
SD**  
* TANTALUM OR  
CERAMIC  
**SD pin must be pulled high through a 10kΩ pull-up resistor. See Application Hints for more information.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2013, Texas Instruments Incorporated  
LP3853, LP3856  
SNVS173G –FEBRUARY 2003–REVISED APRIL 2013  
www.ti.com  
Connection Diagram  
Figure 1. Top View  
TO220-5 Package  
Bent, Staggered Leads  
Figure 2. Top View  
TO263-5 Package  
Table 1. Pin Description for TO220-5 and TO263-5 Packages  
LP3853  
LP3856  
Pin #  
Name  
SD  
Function  
Name  
SD  
Function  
1
2
3
4
5
Shutdown  
Shutdown  
VIN  
Input Supply  
Ground  
VIN  
Input Supply  
Ground  
GND  
VOUT  
ERROR  
GND  
VOUT  
SENSE  
Output Voltage  
ERROR Flag  
Output Voltage  
Remote Sense Pin  
Block Diagram  
LP3853  
Figure 3.  
2
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SNVS173G –FEBRUARY 2003–REVISED APRIL 2013  
LP3856  
Figure 4.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
(1)  
Absolute Maximum Ratings  
Storage Temperature Range  
−65°C to +150°C  
Lead Temperature  
(Soldering, 5 sec.)  
260°C  
2 kV  
(2)  
ESD Rating  
(3)  
Power Dissipation  
Internally Limited  
−0.3V to +7.5V  
−0.3V to 7.5V  
−0.3V to +6.0V  
Short Circuit Protected  
VIN  
Input Supply Voltage (Survival)  
Shutdown Input Voltage (Survival)  
(4) (5)  
Output Voltage (Survival),  
IOUT (Survival)  
,
Maximum Voltage for ERROR Pin  
Maximum Voltage for SENSE Pin  
VOUT  
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which  
the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,  
see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions.  
(2) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.  
(3) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be  
derated at θjA = 50°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-  
mount package must be derated at θjA = 60°C/W (with 0.5in2, 1oz. copper area), junction-to-ambient. See Application Hints.  
(4) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.  
(5) The output PMOS structure contains a diode between the VIN and VOUT terminals. This diode is normally reverse biased. This diode will  
get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can  
typically withstand 200mA of DC current and 1Amp of peak current.  
Operating Ratings  
(1)  
Input Supply Voltage  
2.5V to 7.0V  
−0.3V to 7.0V  
3A  
Shutdown Input Voltage  
Maximum Operating Current (DC)  
Junction Temperature  
−40°C to +125°C  
(1) The minimum operating value for VIN is equal to either [VOUT(NOM) + VDROPOUT] or 2.5V, whichever is greater.  
Copyright © 2003–2013, Texas Instruments Incorporated  
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Electrical Characteristics  
LP3853/LP3856  
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.  
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V.  
(2)  
LP3853/6  
(1)  
Symbol  
Parameter  
Conditions  
Typ  
Units  
Min  
Max  
Output Voltage Tolerance  
VOUT +1V ≤ VIN ≤ 7.0V  
10 mA ≤ IL ≤ 3A  
-1.5  
-3.0  
+1.5  
+3.0  
VO  
0
%
%
%
(3)  
Output Voltage Line Regulation  
0.02  
0.06  
ΔV OL  
VOUT +1V ≤ VIN ≤ 7.0V  
10 mA ≤ IL ≤ 3A  
IL = 300 mA  
IL = 3A  
(3)  
Output Voltage Load Regulation  
0.08  
0.14  
ΔVO/ ΔIOUT  
(3)  
50  
65  
39  
390  
4
Dropout Voltage  
VIN - VOUT  
mV  
mA  
(4)  
450  
600  
9
10  
IL = 300 mA  
IL = 3A  
Ground Pin Current In Normal  
Operation Mode  
IGND  
9
10  
4
V
SD ≤ 0.3V  
-40°C ≤ TJ ≤ 85°C  
O ≥ VO(NOM) - 4%  
0.01  
10  
Ground Pin Current In Shutdown  
Mode  
IGND  
µA  
A
50  
IO(PK)  
Peak Output Current  
V
4.5  
6
Short Circuit Protection  
ISC  
Short Circuit Current  
A
V
Shutdown Input  
VSDT Rising from 0.3V until  
Output = ON  
1.3  
1.3  
2
VSDT  
Shutdown Threshold  
VSDT Falling from 2.0V until  
Output = OFF  
0.3  
TdOFF  
TdON  
ISD  
Turn-off delay  
Turn-on delay  
SD Input Current  
IL = 3A  
20  
25  
1
µs  
µs  
nA  
IL = 3A  
VSD = VIN  
Error Flag  
VT  
(5)  
(5)  
Threshold  
10  
5
5
2
16  
8
%
%
VTH  
Threshold Hysteresis  
Error Flag Saturation  
Flag Reset Delay  
VEF(Sat)  
Td  
Isink = 100µA  
0.02  
1
0.1  
V
µs  
nA  
mA  
Ilk  
Error Flag Pin Leakage Current  
Error Flag Pin Sink Current  
1
Imax  
VError = 0.5V  
1
(1) Typical numbers are at 25°C and represent the most likely parametric norm.  
(2) Limits are ensured by testing, design, or statistical correlation.  
(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.  
Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current. The line  
and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the  
output voltage tolerance specification.  
(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.  
Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is  
nothing but the input to output differential, since the minimum input voltage is 2.5V.  
(5) Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints.  
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SNVS173G –FEBRUARY 2003–REVISED APRIL 2013  
Electrical Characteristics  
LP3853/LP3856 (continued)  
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.  
Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 10 mA, COUT = 10µF, VSD = 2V.  
(2)  
LP3853/6  
(1)  
Symbol  
Parameter  
Conditions  
Typ  
Units  
Min  
Max  
AC Parameters  
VIN = VOUT + 1V  
COUT = 10uF  
73  
VOUT = 3.3V, f = 120Hz  
PSRR  
Ripple Rejection  
dB  
VIN = VOUT + 0.5V  
COUT = 10uF  
57  
VOUT = 3.3V, f = 120Hz  
ρn(l/f  
Output Noise Density  
Output Noise Voltage  
f = 120Hz  
0.8  
µV  
BW = 10Hz – 100kHz  
VOUT = 2.5V  
150  
en  
µV (rms)  
BW = 300Hz – 300kHz  
VOUT = 2.5V  
100  
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Typical Performance Characteristics  
Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V,  
VIN = VO(NOM) + 1V, IL = 10 mA.  
Ground Current  
Dropout Voltage  
vs  
Output Load Current  
vs  
Output Load Current  
VOUT = 5V  
600  
500  
400  
4.9  
4.85  
4.8  
4.75  
4.7  
300  
125oC  
4.65  
4.6  
25oC  
200  
100  
4.55  
4.5  
-40oC  
0
4.45  
4.4  
0
1
2
3
LOAD CURRENT (A)  
0
0.5  
1
1.5  
2
2.5  
3
OUTPUT LOAD CURRENT (A)  
Figure 5.  
Figure 6.  
Ground Current  
vs  
Output Voltage  
IL = 3A  
Shutdown IQ  
vs  
Junction Temperature  
6
5
4
3
2
1
0
10  
1
0.1  
0.01  
0.001  
-40 -20  
0
20 40 60 80 100 125  
TEMPERATURE (oC)  
1.8  
2.3  
2.8  
3.3  
3.8  
4.3  
5.0  
OUTPUT VOLTAGE (V)  
Figure 7.  
Figure 8.  
Errorflag Threshold  
vs  
Junction Temperature  
DC Load Reg.  
vs  
Junction Temperature  
3
2.5  
2
14  
12  
10  
8
1.5  
1
6
4
0.5  
0
2
0
-40 -20  
0
20 40 60 80 100 125  
-40 -20  
0
20 40 60 80 100 125  
JUNCTION TEMPERATURE (oC)  
JUNCTION TEMPERATURE (oC)  
Figure 9.  
Figure 10.  
6
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Typical Performance Characteristics (continued)  
Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V,  
VIN = VO(NOM) + 1V, IL = 10 mA.  
DC Line Regulation  
vs  
VIN  
vs  
Temperature  
VOUT Over Temperature  
3
2.5  
2
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1.5  
1
-40oC  
25oC  
0.5  
0
125oC  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
VIN (V)  
-40 -20  
0
20 40 60 80 100 125  
JUNCTION TEMPERATURE (oC)  
Figure 11.  
Figure 12.  
Noise  
vs  
Frequency  
Load Transient Response  
CIN = COUT = 10µF, OSCON  
3.000  
2.500  
2.000  
1.500  
1.000  
0.500  
0.000  
VOUT  
100mV/DIV  
IL = 100mA  
CIN = COUT = 10mF  
ILOAD  
1A/DIV  
100  
1k  
10k  
100k  
TIME (50ms/DIV)  
FREQUENCY (Hz)  
Figure 13.  
Figure 14.  
Load Transient Response  
CIN = COUT = 100µF, OSCON  
Load Transient Response  
CIN = COUT = 100µF, POSCAP  
VOUT  
100mV/DIV  
VOUT  
100mV/DIV  
ILOAD  
1A/DIV  
ILOAD  
1A/DIV  
TIME (50ms/DIV)  
TIME (50ms/DIV)  
Figure 15.  
Figure 16.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V,  
VIN = VO(NOM) + 1V, IL = 10 mA.  
Load Transient Response  
Load Transient Response  
CIN = COUT = 100µF, TANTALUM  
CIN = COUT = 10µF, TANTALUM  
VOUT  
100mV/DIV  
VOUT  
100mV/DIV  
ILOAD  
1A/DIV  
ILOAD  
1A/DIV  
TIME (50ms/DIV)  
TIME (50ms/DIV)  
Figure 17.  
Figure 18.  
Load Transient Response  
CIN = COUT = 10µF, OSCON  
Load Transient Response  
CIN = COUT = 100µF, OSCON  
VOUT  
100mV/DIV  
VOUT  
100mV/DIV  
ILOAD  
3A/DIV  
ILOAD  
3A/DIV  
TIME (50ms/DIV)  
TIME (50ms/DIV)  
Figure 19.  
Figure 20.  
Load Transient Response  
CIN = COUT = 100µF, POSCAP  
Load Transient Response  
CIN = COUT = 10µF, TANTALUM  
VOUT  
100mV/DIV  
VOUT  
100mV/DIV  
ILOAD  
3A/DIV  
ILOAD  
3A/DIV  
TIME (50ms/DIV)  
TIME (50ms/DIV)  
Figure 21.  
Figure 22.  
8
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Typical Performance Characteristics (continued)  
Unless otherwise specified: TJ = 25°C, COUT = 10µF, CIN = 10µF, S/D pin is tied to VIN, VOUT = 2.5V,  
VIN = VO(NOM) + 1V, IL = 10 mA.  
Load Transient Response  
Load Transient Response  
CIN = 4 x 10µF CERAMIC, COUT = 3 x 10µF CERAMIC  
CIN = COUT = 100µF, TANTALUM  
V
OUT  
100 mV/DIV  
V
OUT  
= 2.5V  
VOUT  
100mV/DIV  
1
T
I
OUT  
ILOAD  
3A/DIV  
1A/DIV  
T
2
TIME (50ms/DIV)  
TIME (5 ms/DIV)  
Figure 23.  
Figure 24.  
Load Transient Response  
CIN = 4 x 10µF CERAMIC, COUT = 3 x 10µF CERAMIC  
Load Transient Response  
CIN = 2 x 10µF CERAMIC, COUT = 2 x 10µF CERAMIC  
V
OUT  
V
OUT  
100 mV/DIV  
100 mV/DIV  
1
V
OUT  
= 2.5V  
V
= 2.5V  
OUT  
T
T
1
I
OUT  
I
1A/DIV  
OUT  
I
OUT  
@ 1A  
T
1A/DIV  
2
T
2
TIME (2 ms/DIV)  
TIME (1 ms/DIV)  
Figure 25.  
Figure 26.  
Load Transient Response  
CIN = 2 x 10µF CERAMIC, COUT = 2 x 10µF CERAMIC  
V
OUT  
@ 2.5V  
T
1
I
OUT  
@ 1A  
T
2
TIME (1 ms/DIV)  
Figure 27.  
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APPLICATION INFORMATION  
Application Hints  
EXTERNAL CAPACITORS  
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be  
correctly selected for proper performance.  
INPUT CAPACITOR: An input capacitor of at least 10µF is required. Ceramic or Tantalum may be used, and  
capacitance may be increased without limit  
OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from  
the device and connected directly to the output and ground pins using traces which have no other currents  
flowing through them (see PCB Layout section).  
The minimum amount of output capacitance that can be used for stable operation is 10µF. For general usage  
across all load currents and operating conditions, the part was characterized using a 10µF Tantalum input  
capacitor. The minimum and maximum stable ESR range for the output capacitor was then measured which kept  
the device stable, assuming any output capacitor whose value is greater than 10µF (see Figure 28 below).  
10  
STABLE REGION  
1.0  
COUT > 10mF  
0.1  
.01  
.001  
3
0
1
2
LOAD CURRENT (A)  
Figure 28. ESR Curve for COUT (with 10µF Tantalum Input Capacitor)  
It should be noted that it is possible to operate the part with an output capacitor whose ESR is below these limits,  
assuming that sufficient ceramic input capacitance is provided. This will allow stable operation using ceramic  
output capacitors (see next section).  
OPERATION WITH CERAMIC OUTPUT CAPACITORS  
LP385X voltage regulators can operate with ceramic output capacitors if the values of input and output  
capacitors are selected appropriately. The total ceramic output capacitance must be equal to or less than a  
specified maximum value in order for the regulator to remain stable over all operating conditions. This maximum  
amount of ceramic output capacitance is dependent upon the amount of ceramic input capacitance used as well  
as the load current of the application. This relationship is shown in Figure 29, which graphs the maximum stable  
value of ceramic output capacitance as a function of ceramic input capacitance for load currents of 1A, 2A, and  
3A. For example, if the maximum load current is 1A, a 10µF ceramic input capacitor will allow stable operation  
for values of ceramic output capacitance from 10µF up to about 500µF.  
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100  
3A  
2A  
1A  
10  
100  
1000  
10  
MAX. ALLOWABLE CERAMIC  
OUTPUT CAPACITANCE (mF)  
Figure 29. Maximum Ceramic Output Capacitance vs Ceramic Input Capacitance  
If the maximum load current is 2A and a 10µF ceramic input capacitor is used, the regulator will be stable with  
ceramic output capacitor values from 10µF up to about 50µF. At 3A of load current, the ratio of input to output  
capacitance required approaches 1:1, meaning that whatever amount of ceramic output capacitance is used  
must also be provided at the input for stable operation. For load currents between 1A, 2A, and 3A, interpolation  
may be used to approximate values on the graph. When calculating the total ceramic output capacitance present  
in an application, it is necessary to include any ceramic bypass capacitors connected to the regulator output.  
SELECTING A CAPACITOR  
It is important to note that capacitance tolerance and variation with temperature must be taken into consideration  
when selecting a capacitor so that the minimum required amount of capacitance is provided over the full  
operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation  
with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also  
typically have large temperature variation of capacitance value.  
Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,  
as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.  
Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so  
severe they may not be feasible for some applications (see Capacitor Characteristics Section).  
CAPACITOR CHARACTERISTICS  
CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly  
than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR  
(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a  
function of voltage and temperature.  
Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or  
Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V  
also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of  
the temperature range.  
X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically  
maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of  
course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.  
TANTALUM: Solid Tantalum capacitors are typically recommended for use on the output because their ESR is  
very close to the ideal value required for loop compensation.  
Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value  
that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X  
going from the high to low temperature limits.  
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The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if  
the ESR of the capacitor is near the upper limit of the stability range at room temperature).  
ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are  
larger in physical size, not widely available in surface mount, and have poor AC performance (especially at  
higher frequencies) due to higher ESR and ESL.  
Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also  
varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X  
when going from 25°C down to −40°C.  
It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which  
indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance  
specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP385X. Derating must be  
applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.  
Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating  
temperature where ESR is maximum.  
TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW  
As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating  
voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may  
momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V  
are not affected by this behavior.  
PCB LAYOUT  
Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.  
The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator  
using traces which do not have other currents flowing in them (Kelvin connect).  
The best way to do this is to lay out CIN and COUT near the device with short traces to the VIN, VOUT, and ground  
pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its  
capacitors have a "single point ground".  
It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane  
were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground  
potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground  
technique for the regulator and it's capacitors fixed the problem.  
Since high current flows through the traces going into VIN and coming from VOUT, Kelvin connect the capacitor  
leads to these pins so there is no voltage drop in series with the input and output capacitors.  
RFI/EMI SUSCEPTIBILITY  
RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's  
performance because of the small dimensions of the geometries inside the device. In applications where circuit  
sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must  
be taken to ensure that this does not affect the IC regulator.  
If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes  
from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC.  
If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current  
pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the  
regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency.  
This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the  
output capacitor(s).  
In applications where the load is switching at high speed, the output of the IC may need RF isolation from the  
load. It is recommended that some inductance be placed between the output capacitor and the load, and good  
RF bypass capacitors be placed directly across the load.  
12  
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SNVS173G –FEBRUARY 2003–REVISED APRIL 2013  
PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces.  
Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At  
MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the  
ground plane.  
In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not  
radiate directly into adjacent layers which carry analog power and ground.  
OUTPUT NOISE  
Noise is specified in two ways-  
Spot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at  
a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a  
function of frequency.  
Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually  
several decades of frequencies.  
Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and  
total output noise is measured in µV(rms).  
The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a  
low frequency component and a high frequency component, which depend strongly on the silicon area and  
quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the  
current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a  
smaller package. Increasing the current drawn by the internal reference increases the total supply current  
(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3853/LP3856 achieves  
low noise performance and low quiescent current operation.  
The total output noise specification for LP3853/LP3856 is presented in the Electrical Characteristics table. The  
Output noise density at different frequencies is represented by a curve under typical performance characteristics.  
SHORT-CIRCUIT PROTECTION  
The LP3853 and LP3856 are short circuit protected and in the event of a peak over-current condition, the short-  
circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts  
down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the  
thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section  
on thermal information for power dissipation calculations.  
ERROR FLAG OPERATION  
The LP3853/LP3856 produces a logic low signal at the Error Flag pin when the output drops out of regulation  
due to low input voltage, current limiting, or thermal limiting. This flag has a built in hysteresis. The timing  
diagram in Figure 30 shows the relationship between the ERROR flag and the output voltage. In this example,  
the input voltage is changed to demonstrate the functionality of the Error Flag.  
The internal Error flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high  
through a pull up resistor. Although the ERROR flag pin can sink current of 1mA, this current is energy drain  
from the input supply. Hence, the value of the pull up resistor should be in the range of 10kΩ to 1MΩ. The  
ERROR pin must be connected to ground if this function is not used. It should also be noted that when the  
shutdown pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown  
mode.  
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Figure 30. Error Flag Operation  
SENSE PIN  
In applications where the regulator output is not very close to the load, LP3856 can provide better remote load  
regulation using the SENSE pin. Figure 31 depicts the advantage of the SENSE option. LP3853 regulates the  
voltage at the output pin. Hence, the voltage at the remote load will be the regulator output voltage minus the  
drop across the trace resistance. For example, in the case of a 3.3V output, if the trace resistance is 100mΩ, the  
voltage at the remote load will be 3V with 3A of load current, ILOAD. The LP3856 regulates the voltage at the  
sense pin. Connecting the sense pin to the remote load will provide regulation at the remote load, as shown in  
Figure 31. If the sense option pin is not required, the sense pin must be connected to the VOUT pin.  
Figure 31. Improving remote load regulation using LP3856  
14  
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SHUTDOWN OPERATION  
A CMOS Logic low level signal at the Shutdown (SD) pin will turn-off the regulator. Pin SD must be actively  
terminated through a 10kΩ pull-up resistor for a proper operation. If this pin is driven from a source that actively  
pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be  
tied to Vin if not used.  
The Shutdown (SD) pin threshold has no voltage hysteresis. If the Shutdown pin is actively driven, the voltage  
transition must rise and fall cleanly and promptly.  
DROPOUT VOLTAGE  
The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within  
2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and  
the Rds(on) of the internal MOSFET.  
REVERSE CURRENT PATH  
The internal MOSFET in LP3853 and LP3856 has an inherent parasitic diode. During normal operation, the input  
voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is  
pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets  
forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to  
200mA continuous and 1A peak.  
POWER DISSIPATION/HEATSINKING  
LP3853 and LP3856 can deliver a continuous current of 3A over the full operating temperature range. A heatsink  
may be required depending on the maximum power dissipation and maximum ambient temperature of the  
application. Under all possible conditions, the junction temperature must be within the range specified under  
operating conditions. The total power dissipation of the device is given by:  
PD = (VIN−VOUT)IOUT+ (VIN)IGND  
where IGND is the operating ground current of the device (specified under Electrical Characteristics).  
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the  
application, and the maximum allowable junction temperature (TJmax):  
TRmax = TJmax− TAmax  
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the  
formula:  
θJA = TRmax / PD  
LP3853 and LP3856 are available in TO-220 and TO-263 packages. The thermal resistance depends on amount  
of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W  
for TO-220 package and ≥ 60 °C/W for TO-263 package no heatsink is needed since the package can dissipate  
enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is  
required.  
HEATSINKING TO-220 PACKAGE  
The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a  
PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263  
package.  
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,  
θHA≤ θJA − θCH − θJC.  
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal  
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO220 package. The value for  
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value  
is unknown, 2°C/W can be assumed.  
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HEATSINKING TO-263 PACKAGE  
The TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered  
to the copper plane for heat sinking. Figure 32 shows a curve for the θJA of TO-263 package for different copper  
area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking.  
Figure 32. θJA vs Copper (1 Ounce) Area for TO-263 package  
As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The  
minimum value for θJA for the TO-263 package mounted to a PCB is 32°C/W.  
Figure 33 shows the maximum allowable power dissipation for TO-263 packages for different ambient  
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.  
Figure 33. Maximum power dissipation vs ambient temperature for TO-263 package  
16  
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SNVS173G –FEBRUARY 2003–REVISED APRIL 2013  
REVISION HISTORY  
Changes from Revision F (April 2013) to Revision G  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 16  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Mar-2022  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
NDH  
NDH  
NDH  
NDH  
KTT  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LP3853ES-1.8  
NRND  
DDPAK/  
TO-263  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
45  
Non-RoHS  
& Green  
Call TI  
Level-3-235C-168 HR  
Level-3-245C-168 HR  
Level-3-235C-168 HR  
Level-3-245C-168 HR  
Level-3-235C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-1-NA-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
LP3853ES  
-1.8  
LP3853ES-1.8/NOPB  
LP3853ES-2.5  
ACTIVE  
NRND  
DDPAK/  
TO-263  
45  
RoHS-Exempt  
& Green  
SN  
Call TI  
SN  
LP3853ES  
-1.8  
DDPAK/  
TO-263  
45  
Non-RoHS  
& Green  
LP3853ES  
-2.5  
LP3853ES-2.5/NOPB  
LP3853ES-3.3  
ACTIVE  
NRND  
DDPAK/  
TO-263  
45  
RoHS-Exempt  
& Green  
LP3853ES  
-2.5  
DDPAK/  
TO-263  
45  
Non-RoHS  
& Green  
Call TI  
SN  
LP3853ES  
-3.3  
LP3853ES-3.3/NOPB  
LP3853ES-5.0/NOPB  
LP3853ESX-1.8/NOPB  
LP3853ESX-2.5/NOPB  
LP3853ESX-3.3/NOPB  
LP3853ESX-5.0/NOPB  
LP3853ET-1.8/NOPB  
LP3853ET-2.5/NOPB  
LP3853ET-3.3/NOPB  
LP3853ET-5.0/NOPB  
LP3856ES-1.8/NOPB  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DDPAK/  
TO-263  
45  
RoHS-Exempt  
& Green  
LP3853ES  
-3.3  
DDPAK/  
TO-263  
45  
RoHS-Exempt  
& Green  
SN  
LP3853ES  
-5.0  
DDPAK/  
TO-263  
500  
500  
500  
500  
45  
RoHS-Exempt  
& Green  
SN  
LP3853ES  
-1.8  
DDPAK/  
TO-263  
RoHS-Exempt  
& Green  
SN  
LP3853ES  
-2.5  
DDPAK/  
TO-263  
RoHS-Exempt  
& Green  
SN  
LP3853ES  
-3.3  
DDPAK/  
TO-263  
RoHS-Exempt  
& Green  
SN  
LP3853ES  
-5.0  
TO-220  
TO-220  
TO-220  
TO-220  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
SN  
LP3853ET  
-1.8  
45  
SN  
Level-1-NA-UNLIM  
LP3853ET  
-2.5  
45  
SN  
Level-1-NA-UNLIM  
LP3853ET  
-3.3  
45  
SN  
Level-1-NA-UNLIM  
LP3853ET  
-5.0  
DDPAK/  
TO-263  
45  
RoHS-Exempt  
& Green  
SN  
Level-3-245C-168 HR  
LP3856ES  
-1.8  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Mar-2022  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
LP3856ES-2.5/NOPB  
LP3856ES-3.3  
ACTIVE  
DDPAK/  
TO-263  
KTT  
5
5
5
5
5
5
5
5
5
5
5
45  
RoHS-Exempt  
& Green  
SN  
Level-3-245C-168 HR  
Level-3-235C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-1-NA-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
LP3856ES  
-2.5  
NRND  
DDPAK/  
TO-263  
KTT  
45  
Non-RoHS  
& Green  
Call TI  
SN  
LP3856ES  
-3.3  
LP3856ES-3.3/NOPB  
LP3856ES-5.0/NOPB  
LP3856ESX-1.8/NOPB  
LP3856ESX-2.5/NOPB  
LP3856ESX-3.3/NOPB  
LP3856ESX-5.0/NOPB  
LP3856ET-2.5/NOPB  
LP3856ET-3.3/NOPB  
LP3856ET-5.0/NOPB  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DDPAK/  
TO-263  
KTT  
45  
RoHS-Exempt  
& Green  
LP3856ES  
-3.3  
DDPAK/  
TO-263  
KTT  
45  
RoHS-Exempt  
& Green  
SN  
LP3856ES  
-5.0  
DDPAK/  
TO-263  
KTT  
500  
500  
500  
500  
45  
RoHS-Exempt  
& Green  
SN  
LP3856ES  
-1.8  
DDPAK/  
TO-263  
KTT  
RoHS-Exempt  
& Green  
SN  
LP3856ES  
-2.5  
DDPAK/  
TO-263  
KTT  
RoHS-Exempt  
& Green  
SN  
LP3856ES  
-3.3  
DDPAK/  
TO-263  
KTT  
RoHS-Exempt  
& Green  
SN  
LP3856ES  
-5.0  
TO-220  
TO-220  
TO-220  
NDH  
NDH  
NDH  
RoHS & Green  
RoHS & Green  
RoHS & Green  
SN  
LP3856ET  
-2.5  
45  
SN  
Level-1-NA-UNLIM  
LP3856ET  
-3.3  
45  
SN  
Level-1-NA-UNLIM  
LP3856ET  
-5.0  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Mar-2022  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2023  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LP3853ESX-1.8/NOPB DDPAK/  
TO-263  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
5
5
5
5
5
5
5
5
500  
500  
500  
500  
500  
500  
500  
500  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
24.4  
24.4  
24.4  
24.4  
24.4  
24.4  
24.4  
24.4  
10.75 14.85  
10.75 14.85  
10.75 14.85  
10.75 14.85  
10.75 14.85  
10.75 14.85  
10.75 14.85  
10.75 14.85  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
16.0  
16.0  
16.0  
16.0  
16.0  
16.0  
16.0  
16.0  
24.0  
24.0  
24.0  
24.0  
24.0  
24.0  
24.0  
24.0  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
LP3853ESX-2.5/NOPB DDPAK/  
TO-263  
LP3853ESX-3.3/NOPB DDPAK/  
TO-263  
LP3853ESX-5.0/NOPB DDPAK/  
TO-263  
LP3856ESX-1.8/NOPB DDPAK/  
TO-263  
LP3856ESX-2.5/NOPB DDPAK/  
TO-263  
LP3856ESX-3.3/NOPB DDPAK/  
TO-263  
LP3856ESX-5.0/NOPB DDPAK/  
TO-263  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2023  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LP3853ESX-1.8/NOPB  
LP3853ESX-2.5/NOPB  
LP3853ESX-3.3/NOPB  
LP3853ESX-5.0/NOPB  
LP3856ESX-1.8/NOPB  
LP3856ESX-2.5/NOPB  
LP3856ESX-3.3/NOPB  
LP3856ESX-5.0/NOPB  
DDPAK/TO-263  
DDPAK/TO-263  
DDPAK/TO-263  
DDPAK/TO-263  
DDPAK/TO-263  
DDPAK/TO-263  
DDPAK/TO-263  
DDPAK/TO-263  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
5
5
5
5
5
5
5
5
500  
500  
500  
500  
500  
500  
500  
500  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
45.0  
45.0  
45.0  
45.0  
45.0  
45.0  
45.0  
45.0  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2023  
TUBE  
T - Tube  
height  
L - Tube length  
W - Tube  
width  
B - Alignment groove width  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
LP3853ES-1.8  
LP3853ES-1.8  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
NDH  
NDH  
NDH  
NDH  
KTT  
KTT  
KTT  
KTT  
KTT  
KTT  
NDH  
NDH  
NDH  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-220  
TO-220  
TO-220  
TO-220  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-263  
TO-220  
TO-220  
TO-220  
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
45  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
502  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
30  
30  
30  
30  
25  
25  
25  
25  
25  
25  
30  
30  
30  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
30048.2  
30048.2  
30048.2  
30048.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
8204.2  
30048.2  
30048.2  
30048.2  
9.19  
9.19  
9.19  
9.19  
9.19  
9.19  
9.19  
9.19  
9.19  
9.19  
10.74  
10.74  
10.74  
10.74  
9.19  
9.19  
9.19  
9.19  
9.19  
9.19  
10.74  
10.74  
10.74  
LP3853ES-1.8/NOPB  
LP3853ES-2.5  
LP3853ES-2.5  
LP3853ES-2.5/NOPB  
LP3853ES-3.3  
LP3853ES-3.3  
LP3853ES-3.3/NOPB  
LP3853ES-5.0/NOPB  
LP3853ET-1.8/NOPB  
LP3853ET-2.5/NOPB  
LP3853ET-3.3/NOPB  
LP3853ET-5.0/NOPB  
LP3856ES-1.8/NOPB  
LP3856ES-2.5/NOPB  
LP3856ES-3.3  
LP3856ES-3.3  
LP3856ES-3.3/NOPB  
LP3856ES-5.0/NOPB  
LP3856ET-2.5/NOPB  
LP3856ET-3.3/NOPB  
LP3856ET-5.0/NOPB  
Pack Materials-Page 3  
MECHANICAL DATA  
NDH0005D  
www.ti.com  
MECHANICAL DATA  
KTT0005B  
TS5B (Rev D)  
BOTTOM SIDE OF PACKAGE  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023, Texas Instruments Incorporated  

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