LP3874EMP-ADJ/NOPB [TI]

具有使能功能的 800mA、7V、可调节低压降稳压器 | NDC | 5 | -40 to 125;


型号：	LP3874EMP-ADJ/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有使能功能的 800mA、7V、可调节低压降稳压器 \| NDC \| 5 \| -40 to 125 光电二极管输出元件稳压器调节器
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中文：	中文翻译
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LP3874-ADJ

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SNVS246E –SEPTEMBER 2003–REVISED APRIL 2013

LP3874-ADJ 0.8A Fast Ultra Low Dropout Linear Regulators

Check for Samples: LP3874-ADJ

FEATURES

DESCRIPTION

The LP3874-ADJ fast ultra low-dropout linear

regulators operate from a +2.5V to +7.0V input

supply. These ultra low dropout linear regulators

respond very quickly to step changes in load, which

makes them suitable for low voltage microprocessor

applications. The LP3874-ADJ is developed on a

CMOS process which allows low quiescent current

operation independent of output load current. This

CMOS process also allows the LP3874-ADJ to

operate under extremely low dropout conditions.

•

Ultra Low Dropout Voltage

Low Ground Pin Current

Load Regulation of 0.04%

10nA Quiescent Current in Shutdown Mode

Specified Output Current of 0.8A DC

Available in DDPAK/TO-263, TO-220 and SOT-

223 Packages

•

Minimum Output Capacitor Requirements

Overtemperature/Overcurrent Protection

−40°C to +125°C Junction Temperature Range

Dropout Voltage: Ultra low dropout voltage; typically

24mV at 80mA load current and 240mV at 0.8A load

current.

APPLICATIONS

Ground Pin Current: Typically 6mA at 0.8A load

current.

•

Microprocessor Power Supplies

GTL, GTL+, BTL, and SSTL Bus Terminators

Power Supplies for DSPs

SCSI Terminator

Shutdown Mode: Typically 10nA quiescent current

when the shutdown pin is pulled low.

Adjustable Output Voltage: The output voltage may

be programmed via two external resistors.

Post Regulators

High Efficiency Linear Regulators

Battery Chargers

Other Battery Powered Applications

TYPICAL APPLICATION CIRCUIT

OUTPUT

0.8A

V_IN

V_OUT

INPUT

C_FF

R1*

R2*

LP3874-ADJ

ADJ

C_OUT

GND

10 mF

Tantalum

C_IN

10 mF

)

V_OUT= 1.216 x (1+

*See Application Hints

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3874-ADJ

SNVS246E –SEPTEMBER 2003–REVISED APRIL 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAMS

Top View

Figure 1. TO-220-5 Package

Bent, Staggered Leads

Figure 2. DDPAK/TO-263-5 Package

See Package Number KTT0005B

See Package Number NDH0005D

Top View

GND

V_INV_OUTADJ

Figure 3. SOT-223-5 Package

See Package Number NDC0005A

Table 1. PIN DESCRIPTIONS for TO-220-5 and DDPAK/TO-263-5 Packages

LP3874-ADJ

Pin #

Name

Function

Shutdown

V_IN

Input Supply

Ground

GND

V_OUT

ADJ

Output Voltage

Set Output Voltage

Table 2. PIN DESCRIPTIONS for SOT-223-5 Package

LP3874-ADJ

Pin #

Name

Function

V_IN

Shutdown

Input Supply

Output Voltage

Set Output Voltage

Ground

V_OUT

ADJ

GND

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SNVS246E –SEPTEMBER 2003–REVISED APRIL 2013

BLOCK DIAGRAM

Figure 4. LP3874-ADJ

(1)

ABSOLUTE MAXIMUM RATINGS

If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/

Distributors for availability and specifications.

Storage Temperature Range

−65°C to +150°C

Lead Temperature (Soldering, 5 sec.)

260°C

2 kV

(2)

ESD Rating

(3)

Power Dissipation

Internally Limited

−0.3V to +7.5V

−0.3V to 7.5V

Input Supply Voltage (Survival)

Shutdown Input Voltage (Survival)

(4) (5)

Output Voltage (Survival),

I_OUT(Survival)

−0.3V to +6.0V

Short Circuit Protected

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which

the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and test conditions,

see Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

(3) At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO-220 package must be

derated at θ_jA= 50°C/W (with 0.5in², 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the DDPAK/TO-263

surface-mount package must be derated at θ_jA= 60°C/W (with 0.5in², 1oz. copper area), junction-to-ambient. The SOT-223 package

must be derated at θ_jA= 90°C/W (with 0.5in², 1oz. copper area), junction-to-ambient.

(4) If used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.

(5) The output PMOS structure contains a diode between the V_INand V_OUTterminals. This diode is normally reverse biased. This diode will

get forward biased if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can

typically withstand 200mA of DC current and 1Amp of peak current.

RECOMMENDED OPERATING CONDITIONS

(1)

Input Supply Voltage (Operating),

Shutdown Input Voltage (Operating)

Maximum Operating Current (DC)

Operating Junction Temp. Range

2.5V to 7.0V

−0.3V to 7.0V

0.8A

−40°C to +125°C

(1) The minimum operating value for V_INis equal to either [V_OUT(NOM)+ V_DROPOUT] or 2.5V, whichever is greater.

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ELECTRICAL CHARACTERISTICS LP3874-ADJ

Limits in standard typeface are for T_J= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V_IN= V_O(NOM)+ 1V, I_L= 10 mA, C_OUT= 10µF, V_SD= 2V.

(1)

(2)

Symbol

Parameter

Conditions

Typ

LP3874-ADJ

Units

Min

Max

V_OUT+1V ≤ V_IN≤ 7V, 10 mA ≤ I_L≤ 0.8A

1.198

1.180

1.234

1.253

V_ADJ

Adjust Pin Voltage

1.216

I_ADJ

Adjust Pin Input Current

V_OUT+1V ≤ V_IN≤ 7V, 10 mA ≤ I_L≤ 0.8A

V_OUT+1V ≤ V_IN≤ 7.0V

100

ΔV _OL

Output Voltage Line Regulation

0.02

0.06

(3)

ΔV_O/ ΔI_OUT

Output Voltage Load Regulation 10 mA ≤ I_L≤ 0.8A

0.04

0.1

(3)

V_IN- V_OUT

I_L= 80 mA

240

(4)

Dropout Voltage

I_L= 0.8A

300

350

I_L= 80 mA

Ground Pin Current In Normal

Operation Mode

I_GND

I_L= 0.8A

I_GND

Ground Pin Current In Shutdown

Mode

_SD≤ 0.3V

-40°C ≤ T_J≤ 85°C

_O≥ V_O(NOM)- 4%

0.01

µA

I_O(PK)

Peak Output Current

Short Circuit Protection

I_SC

Short Circuit Current

2.3

Shutdown Input

Output = High

Output = Low

I_L= 0.8A

V_IN

V_SDT

Shutdown Threshold

0.3

T_dOFF

T_dON

Turn-off delay

Turn-on delay

SD Input Current

µs

I_L= 0.8A

I_SD

V_SD= V_IN

AC Parameters

V_IN= V_OUT+ 1V, C_OUT= 10uF

V_OUT= 3.3V, f = 120Hz

PSRR

Ripple Rejection

V_IN= V_OUT+ 0.5V, C_OUT= 10uF

V_OUT= 3.3V, f = 120Hz

ρ_n(l/f)

Output Noise Density

Output Noise Voltage

f = 120Hz

0.8

150

100

µV

BW = 10Hz – 100kHz, V_OUT= 2.5V

BW = 300Hz – 300kHz, V_OUT= 2.5V

e_n

µV (rms)

(1) Typical numbers are at 25°C and represent the most likely parametric norm.

(2) Limits are specified by testing, design, or statistical correlation.

(3) Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage.

Output voltage load regulation is defined as the change in output voltage from the nominal value due to change in load current.

(4) Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value.

Dropout voltage specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is

nothing but the input to output differential, since the minimum input voltage is 2.5V.

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SNVS246E –SEPTEMBER 2003–REVISED APRIL 2013

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified: T_J= 25°C, C_OUT= 10µF, C_IN= 10µF, S/D pin is tied to V_IN, V_OUT= 2.5V, V_IN= V_O(NOM)+ 1V, I_L=

10 mA

Ground Current

Dropout Voltage

Output Load Current

Output Voltage

I_L= 0.8A

500

400

125^oC

300

200

25^oC

-40^oC

100

0.5

1.0

1.8

2.3

2.8

3.3

3.8

4.3

4.8

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

Figure 5.

Figure 6.

Shutdown I_Q

Junction Temperature

DC Load Reg.

Junction Temperature

2.5

1.5

0.1

0.01

0.5

0.001

-40 -20

20 40 60 80 100 125

TEMPERATURE (^oC)

-40 -20

20 40 60 80 100 125

JUNCTION TEMPERATURE (^oC)

Figure 7.

Figure 8.

DC Line Regulation

Noise

Frequency

Temperature

2.5

3.000

2.500

2.000

1.500

1.000

0.500

0.000

IL = 100mA

C_IN= C_OUT= 10mF

1.5

0.5

100

10k

100k

-40 -20

20 40 60 80 100 125

JUNCTION TEMPERATURE (^oC)

FREQUENCY (Hz)

Figure 9.

Figure 10.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified: T_J= 25°C, C_OUT= 10µF, C_IN= 10µF, S/D pin is tied to V_IN, V_OUT= 2.5V, V_IN= V_O(NOM)+ 1V, I_L=

10 mA

Load Transient Response

C_IN= C_OUT= 10µF, OSCON

Load Transient Response

C_IN= C_OUT= 100µF, OSCON

V_OUT

100mV/DIV

V_OUT

100mV/DIV

I_LOAD

1A/DIV

TIME (50ms/DIV)

Figure 11.

Figure 12.

Load Transient Response

C_IN= C_OUT= 100µF, POSCAP

Load Transient Response

C_IN= C_OUT= 10µF, TANTALUM

V_OUT

100mV/DIV

V_OUT

100mV/DIV

I_LOAD

1A/DIV

I_LOAD

1A/DIV

TIME (50ms/DIV)

Figure 13.

Figure 14.

Load Transient Response

C_IN= C_OUT= 100µF, TANTALUM

V_OUT

100mV/DIV

I_LOAD

1A/DIV

TIME (50ms/DIV)

Figure 15.

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Application Hints

SETTING THE OUTPUT VOLTAGE

The output voltage is set using the resistors R1 and R2 (see TYPICAL APPLICATION CIRCUIT). The output is

also dependent on the reference voltage (typically 1.216V) which is measured at the ADJ pin. The output voltage

is given by the equation:

V_OUT= V_ADJx ( 1 + R1 / R2)

(1)

This equation does not include errors due to the bias current flowing in the ADJ pin which is typically about 10

nA. This error term is negligible for most applications. If R1 is > 100kΩ , a small error may be introduced by the

ADJ bias current.

The tolerance of the external resistors used contributes a significant error to the output voltage accuracy, with 1%

resistors typically adding a total error of approximately 1.4% to the output voltage (this error is in addition to the

tolerance of the reference voltage at V_ADJ).

TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW

As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating

voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may

momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V

are not affected by this behavior.

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be

correctly selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 10µF is required. Ceramic, Tantalum, or Electrolytic

capacitors may be used, and capacitance may be increased without limit.

OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from

the device and connected directly to the output and ground pins using traces which have no other currents

flowing through them (see TYPICAL APPLICATION CIRCUIT).

The minimum value of output capacitance that can be used for stable full-load operation is 10µF, but it may be

increased without limit. The output capacitor must have an ESR value as shown in the stable region of the curve

(below).Tantalum capacitors are recommended for the output capacitor.

1.0

C_OUT> 10mF

STABLE REGION

0.1

.01

.001

0.2

0.4

0.6

0.8

LOAD CURRENT (A)

Figure 16. ESR Curve

C_FF(Feed Forward Capacitor)

The capacitor C_FFis required to add phase lead and help improve loop compensation. The correct amount of

capacitance depends on the value selected for R1 (see TYPICAL APPLICATION CIRCUIT). The capacitor

should be selected such that the zero frequency as given by the equation shown below is approximately 45 kHz:

Fz = 45,000 = 1 / ( 2 x π x R1 x C_FF

)

(2)

A good quality ceramic with X5R or X7R dielectric should be used for this capacitor.

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SELECTING A CAPACITOR

It is important to note that capacitance tolerance and variation with temperature must be taken into consideration

when selecting a capacitor so that the minimum required amount of capacitance is provided over the full

operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation

with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also

typically have large temperature variation of capacitance value.

Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics,

as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors.

Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so

severe they may not be feasible for some applications (see CAPACITOR CHARACTERISTICS).

CAPACITOR CHARACTERISTICS

CERAMIC: For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly

than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR

(typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a

function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or

Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V

also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of

the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically

maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of

course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.

TANTALUM: Solid Tantalum capacitors are recommended for use on the output because their typical ESR is

very close to the ideal value required for loop compensation. They also work well as input capacitors if selected

to meet the ESR requirements previously listed.

Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value

that varies less than 10-15% across the full temperature range of 125°C to −40°C. ESR will vary only about 2X

going from the high to low temperature limits.

The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if

the ESR of the capacitor is near the upper limit of the stability range at room temperature).

ALUMINUM: This capacitor type offers the most capacitance for the money. The disadvantages are that they are

larger in physical size, not widely available in surface mount, and have poor AC performance (especially at

higher frequencies) due to higher ESR and ESL.

Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also

varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X

when going from 25°C down to −40°C.

It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which

indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance

specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP387X. Derating must be

applied to the manufacturer's ESR specification, since it is typically only valid at room temperature.

Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating

temperature where ESR is maximum.

PCB LAYOUT

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops.

The input and output capacitors must be directly connected to the input, output, and ground pins of the LP387X

using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out C_INand C_OUTnear the device with short traces to the V_IN, V_OUT, and ground

pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its

capacitors have a "single point ground".

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It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane

were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground

potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground

technique for the regulator and it's capacitors fixed the problem.

Since high current flows through the traces going into V_INand coming from V_OUT, Kelvin connect the capacitor

leads to these pins so there is no voltage drop in series with the input and output capacitors.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit's

performance because of the small dimensions of the geometries inside the device. In applications where circuit

sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must

be taken to ensure that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes

from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current

pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the

regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency.

The means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the

output capacitor(s).

In applications where the load is switching at high speed, the output of the IC may need RF isolation from the

load. It is recommended that some inductance be placed between the output capacitor and the load, and good

RF bypass capacitors be placed directly across the load.

PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces.

Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At

MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across the

ground plane.

In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not

radiate directly into adjacent layers which carry analog power and ground.

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all noise sources, measured at the regulator output, at

a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a

function of frequency.

Total output Noise or Broad-band noise is the RMS sum of spot noise over a specified bandwidth, usually

several decades of frequencies.

Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and

total output noise is measured in µV(rms).

The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a

low frequency component and a high frequency component, which depend strongly on the silicon area and

quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the

current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a

smaller package. Increasing the current drawn by the internal reference increases the total supply current

(ground pin current). Using an optimized trade-off of ground pin current and die size, LP3871/LP3874 achieves

low noise performance and low quiescent current operation.

The total output noise specification for LP3871/LP3874 is presented in the Electrical Characteristics table. The

Output noise density at different frequencies is represented by a curve under typical performance characteristics.

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SHORT-CIRCUIT PROTECTION

The LP3874-ADJ is short circuit protected and in the event of a peak over-current condition, the short-circuit

control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the

control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal

shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on

thermal information for power dissipation calculations.

SHUTDOWN OPERATION

A CMOS Logic level signal at the shutdown ( SD) pin will turn-off the regulator. Pin SD must be actively

terminated through a 10kΩ pull-up resistor for a proper operation. If this pin is driven from a source that actively

pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be

tied to Vin if not used.

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within

2% of the nominal output voltage. For CMOS LDOs, the dropout voltage is the product of the load current and

the Rds(on) of the internal MOSFET.

REVERSE CURRENT PATH

The internal MOSFET in LP3874-ADJ has an inherent parasitic diode. During normal operation, the input voltage

is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above

the input in an application, then current flows from the output to the input as the parasitic diode gets forward

biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200mA

continuous and 1A peak.

POWER DISSIPATION/HEATSINKING

The LP3874-ADJ can deliver a continuous current of 0.8A over the full operating temperature range. A heatsink

may be required depending on the maximum power dissipation and maximum ambient temperature of the

application. Under all possible conditions, the junction temperature must be within the range specified under

operating conditions. The total power dissipation of the device is given by:

(3)

P_D= (V_IN−V_OUT)I_OUT+ (V_IN)I_GND

where I_GNDis the operating ground current of the device (specified under Electrical Characteristics).

The maximum allowable temperature rise (T_Rmax) depends on the maximum ambient temperature (T_Amax) of the

application, and the maximum allowable junction temperature (T_Jmax):

T_Rmax= T_Jmax− T_Amax

(4)

The maximum allowable value for junction to ambient Thermal Resistance, θ_JA, can be calculated using the

formula:

θ_JA= T_Rmax/ P_D

(5)

The LP3874-ADJ is available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on

amount of copper area or heat sink, and on air flow. If the maximum allowable value of θ_JAcalculated above is ≥

60 °C/W for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the

package can dissipate enough heat to satisfy these requirements. If the value for allowable θ_JAfalls below these

limits, a heat sink is required.

HEATSINKING TO-220 PACKAGE

The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a

PC board. If a copper plane is to be used, the values of θ_JAwill be same as shown in next section for

DDPAK/TO-263 package.

The heatsink to be used in the application should have a heatsink to ambient thermal resistance,

θ_HA≤ θ_JA− θ_CH− θ_JC

(6)

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In this equation, θ_CHis the thermal resistance from the case to the surface of the heat sink and θ_JCis the thermal

resistance from the junction to the surface of the case. θ_JCis about 3°C/W for a TO-220 package. The value for

θ_CHdepends on method of attachment, insulator, etc. θ_CHvaries between 1.5°C/W to 2.5°C/W. If the exact value

is unknown, 2°C/W can be assumed.

HEATSINKING DDPAK/TO-263 PACKAGE

The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are

soldered to the copper plane for heat sinking. Figure 17 shows a curve for the θ_JAof DDPAK/TO-263 package for

different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area

for heat sinking.

Figure 17. θ_JAvs Copper (1 Ounce) Area for DDPAK/TO-263 package

As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. The

minimum value for θ_JAfor the DDPAK/TO-263 package mounted to a PCB is 32°C/W.

Figure 18 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient

temperatures, assuming θ_JAis 35°C/W and the maximum junction temperature is 125°C.

Figure 18. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package

HEATSINKING SOT223-5 PACKAGE

Figure 19 shows a curve for the θ_JAof SOT-223 package for different copper area sizes, using a typical PCB with

1 ounce copper and no solder mask over the copper area for heat sinking.

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SNVS246E –SEPTEMBER 2003–REVISED APRIL 2013

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Figure 19. θ_JAvs Copper(1 Ounce) Area for SOT-223 package

The following figures show different layout scenarios for SOT-223 package.

Figure 20. SCENARIO A, θ_JA= 148°C/W

Figure 21. SCENARIO B, θ_JA= 125°C/W

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SNVS246E –SEPTEMBER 2003–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision D (April 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 12

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP3874EMP-ADJ/NOPB

LP3874EMPX-ADJ/NOPB

LP3874ES-ADJ/NOPB

ACTIVE

SOT-223

NDC

KTT

1000 RoHS & Green

2000 RoHS & Green

Level-1-260C-UNLIM

Level-3-245C-168 HR

-40 to 125

LHKB

DDPAK/

TO-263

RoHS-Exempt

& Green

LP3874ES

ADJ

LP3874ESX-ADJ/NOPB

ACTIVE

DDPAK/

TO-263

KTT

500

RoHS-Exempt

& Green

Level-3-245C-168 HR

-40 to 125

LP3874ES

ADJ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3874EMP-ADJ/NOPB SOT-223 NDC

LP3874EMPX-ADJ/NOPB SOT-223 NDC

1000

2000

500

330.0

16.4

24.4

7.0

7.5

2.2

5.0

12.0

16.0

24.0

LP3874ESX-ADJ/NOPB DDPAK/

TO-263

KTT

10.75 14.85

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3874EMP-ADJ/NOPB

LP3874EMPX-ADJ/NOPB

LP3874ESX-ADJ/NOPB

SOT-223

NDC

KTT

1000

2000

500

367.0

35.0

45.0

DDPAK/TO-263

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Feb-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

KTT TO-263

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

LP3874ES-ADJ/NOPB

502

8204.2

9.19

Pack Materials-Page 3

MECHANICAL DATA

NDC0005A

www.ti.com

MECHANICAL DATA

KTT0005B

TS5B (Rev D)

BOTTOM SIDE OF PACKAGE

www.ti.com

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LP3874EMP-ADJ/NOPB [TI]

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