LP3882 [TI]
1.5A、超低压降稳压器;
| 型号： | LP3882 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.5A、超低压降稳压器 稳压器 |
| 文件： | 总22页 (文件大小：1049K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3882
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SNVS226F –MARCH 2003–REVISED APRIL 2013
LP3882 1.5A Fast-Response Ultra Low Dropout Linear Regulators
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1
FEATURES
DESCRIPTION
The LP3882 is a high current, fast response regulator
which can maintain output voltage regulation with
minimum input to output voltage drop. Fabricated on
a CMOS process, the device operates from two input
voltages: Vbias provides voltage to drive the gate of
the N-MOS power transistor, while Vin is the input
voltage which supplies power to the load. The use of
an external bias rail allows the part to operate from
ultra low Vin voltages. Unlike bipolar regulators, the
CMOS architecture consumes extremely low
quiescent current at any output load current. The use
of an N-MOS power transistor results in wide
bandwidth, yet minimum external capacitance is
required to maintain loop stability.
2
•
Ultra Low Dropout Voltage (110 mV at
1.5A typ)
•
•
•
•
•
Low Ground Pin Current
Load Regulation of 0.04%/A
60 nA Typical Quiescent Current in Shutdown
1.5% Output Accuracy (25°C)
TO-220, DDPAK/TO-263 and SO PowerPad
Packages
•
•
Over Temperature/Over Current Protection
−40°C to +125°C Junction Temperature Range
APPLICATIONS
The fast transient response of these devices makes
them suitable for use in powering DSP,
Microcontroller Core voltages and Switch Mode
Power Supply post regulators. The parts are available
in TO-220, DDPAK/TO-263 and SO PowerPad
packages.
•
•
•
•
•
•
•
DSP Power Supplies
Server Core and I/O Supplies
PC Add-in-Cards
Local Regulators in Set-Top Boxes
Microcontroller Power Supplies
High Efficiency Power Supplies
SMPS Post-Regulators
Dropout Voltage: 110 mV (typ) at 1.5A load current.
Ground Pin Current: 3 mA (typ) at full load.
Shutdown Current: 60 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature
accuracy.
TYPICAL APPLICATION CIRCUIT
At least 4.7 µF of input and output capacitance is required for stability.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LP3882
SNVS226F –MARCH 2003–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
Figure 1. 5-Pin TO-220, Top View
See NDH0005D Package
Figure 2. 5-Pin DDPAK/TO-263, Top View
See KTT0005B Package
V
V
V
1
2
3
4
8 N/C
OUT
7 V
OUT
IN
GND
6
5
S/D
BIAS
GND
GND
Figure 3. 8-Pin SO PowerPad, Top View
See DDA0008D Package
White Space
White Space
White Space
BLOCK DIAGRAM
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(1)
ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/
Distributors for availability and specifications.
VALUE / UNITS
Storage Temperature Range
−65°C to +150°C
260°C
Lead Temperature (Soldering, 5 seconds)
(2)
Human Body Model
2 kV
ESD Rating
(3)
Machine Model
200V
(4)
Power Dissipation
Internally Limited
−0.3V to +6V
−0.3V to +7V
−0.3V to +7V
Internally Limited
−0.3V to +6V
−40°C to +150°C
VIN Supply Voltage (Survival)
VBIAS Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
IOUT (Survival)
Output Voltage (Survival)(5)
Junction Temperature
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but does not ensure specific performance limits. For specifications, see Electrical
Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.
(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
(3) The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V.
(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.
θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be
assumed. θJ-A for DDPAK/TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square
inches in area. θJ-A value for typical SO PowerPad PC board mounting is 166°C/W. If power dissipation causes the junction temperature
to exceed specified limits, the device will go into thermal shutdown.
(5) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to
ground.
RECOMMENDED OPERATING CONDITIONS
VALUE / UNITS
VIN Supply Voltage
(VOUT + VDO) to 5.5V
0 to +6V
Shutdown Input Voltage
IOUT
1.5A
Operating Junction Temperature Range
VBIAS Supply Voltage
−40°C to +125°C
4.5V to 6V
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ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 4.7 µF, VS/D = VBIAS
.
Typical
(1)
(1)
Symbol
VO
Parameter
Conditions
MIN
MAX
Units
(2)
Output Voltage Tolerance
10 mA < IL < 1.5A
VO(NOM) + 1V ≤ VIN ≤ 5.5V
4.5V ≤ VBIAS ≤ 6V
1.198
1.186
1.234
1.246
1.216
1.478
1.455
1.522
1.545
1.5
V
1.773
1.746
1.827
1.854
1.8
(3)
ΔVO/ΔVIN
ΔVO/ΔIL
Output Voltage Line Regulation
Output Voltage Load Regulation
VO(NOM) + 1V ≤ VIN ≤ 5.5V
0.01
%/V
%/A
(4)
10 mA < IL < 1.5A
0.04
0.06
(5)
VDO
Dropout Voltage
IL = 1.5A (TO-220 and DDPAK/TO-263
only)
170
270
110
125
3
mV
IL = 1.5A (PSOP only)
190
320
IQ(VIN
)
Quiescent Current Drawn from VIN
Supply
10 mA < IL < 1.5A
7
8
mA
µA
V
S/D ≤ 0.3V
1
30
0.03
1
IQ(VBIAS
)
Quiescent Current Drawn from VBIAS 10 mA < IL < 1.5A
Supply
2
3
mA
V
S/D ≤ 0.3V
1
30
0.03
4.3
µA
A
ISC
Short-Circuit Current
VOUT = 0V
Shutdown Input
VSDT
Output Turn-off Threshold
Output = ON
1.3
0.7
0.7
20
15
1
V
Output = OFF
0.3
Td (OFF)
Td (ON)
IS/D
Turn-OFF Delay
Turn-ON Delay
S/D Input Current
RLOAD X COUT << Td (OFF)
RLOAD X COUT << Td (ON)
VS/D =1.3V
µs
µA
VS/D ≤ 0.3V
−1
AC Parameters
PSRR (VIN
)
Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz
VIN = VOUT + 1V, f = 1 kHz
80
65
70
65
1
dB
PSRR
Ripple Rejection for VBIAS Voltage
VBIAS = VOUT + 3V, f = 120 Hz
VBIAS = VOUT + 3V, f = 1 kHz
f = 120 Hz
(VBIAS
)
Output Noise Density
µV/Hz
en
Output Noise Voltage
VOUT = 1.8V
BW = 10 Hz − 100 kHz
BW = 300 Hz − 300 kHz
150
90
µV (rms)
(1) Limits are specified through testing, statistical correlation, or design.
(2) Typical numbers represent the most likely parametric norm for 25°C operation.
(3) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(4) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(5) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. The SO
PowerPad package devices have a slightly higher dropout voltage due to increased band wire resistance.
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SNVS226F –MARCH 2003–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Dropout vs IL
IGND vs VSD
200
160
125oC
25oC
VBIAS = 5V
120
80
-40oC
40
0
0
0.5
1.0
1.5
LOAD CURRENT (A)
Figure 4.
Figure 5.
VOUT vs Temperature
DC Load Regulation
Figure 6.
Figure 7.
Line Regulation vs VIN
Line Regulation vs VBIAS
Figure 8.
Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
IBIAS vs IL
IGND vs VSD
1.60
VBIAS = 5V
VIN = 2.3V
1.40
125oC
25oC
1.20
1.00
-40oC
0.80
0.60
0
0.5
1.0
1.5
LOAD CURRENT (A)
Figure 10.
Figure 11.
Noise Measurement
VOUTStartup Waveform
Figure 12.
Figure 13.
VOUTStartup Waveform
Line Regulation vs VBIAS
Figure 14.
Figure 15.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
Line Regulation vs VBIAS
VIN PSRR
Figure 16.
VIN PSRR
Figure 17.
VBIAS PSRR
Figure 18.
Figure 19.
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Application Hints
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EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
At least 4.7µF of output capacitance is required for stability (the amount of capacitance can be increased without
limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean
analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range
as shown in the graph below over the full operating temperature range for stable operation.
10
1.0
COUT > 4.7 mF
STABLE REGION
0.1
.01
.001
0
1
2
LOAD CURRENT (A)
Figure 20. Minimum ESR vs Output Load Current
Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements
and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR
increases very rapidly at temperatures below 10C. Aluminum caps can only be used in applications where lower
temperature operation is not required.
A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical
loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap,
it must be one whose ESR is specified at a frequency of 100 kHz or more.
Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output
capacitors on LP388X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the
amount of Tantalum capacitance connected from the output to ground.
OUTPUT "BYPASS" CAPACITORS
Many designers place small value "bypass" capacitors at various circuit points to reduce noise. Ceramic
capacitors in the value range of about 1000pF to 0.1µF placed directly on the output of a PNP or P-FET LDO
regulator can cause a loss of phase margin which can result in oscillations, even when a Tantalum output
capacitor is in parallel with it. This is not unique to Texas Instruments Semiconductor LDO regulators, it is true of
any P-type LDO regulator.
The reason for this is that PNP or P-FET regulators have a higher output impedance (compared to an NPN
regulator), which results in a pole-zero pair being formed by every different capacitor connected to the output.
The zero frequency is approximately:
Fz = 1 / (2 X π X ESR X C)
(1)
Where ESR is the equivalent series resistance of the capacitor, and C is the value of capacitance.
The pole frequency is:
Fp = 1 / (2 X π X RL X C)
(2)
Where RL is the load resistance connected to the regulator output.
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To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of
1MHz, which is delivering 0.5A of current from a 2.5V output (which means RL is 5 Ohms). We then place a .047
µF capacitor on the output. This creates a pole whose frequency is:
Fp = 1 / (2 X π X 5 X .047 X 10E-6) = 677 kHz
(3)
This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which
would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and
bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the
capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to
damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to
"decouple" them from the regulator output.
INPUT CAPACITOR
The input capacitor must be at least 4.7 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very
good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be
used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application
where temperatures go below about 10°C.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 6V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a
pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD = (VIN−VOUT)IOUT+ (VIN)IGND
where IGND is the operating ground current of the device.
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmax− TAmax
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD
These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount
of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W
for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can
dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat
sink is required.
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HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on
a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for
DDPAK/TO-263 package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance,
θHA≤ θJA − θCH − θJC.
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value
is unknown, 2°C/W can be assumed.
HEATSINKING DDPAK/TO-263 PACKAGE
The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are
soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263
package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the
copper area for heat sinking.
Figure 21. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package
As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.
The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.
Figure 22 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
Figure 22. Maximum Power Dissipation vs Ambient Temperature For DDPAK/TO-263 Package
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HEATSINKING PSOP PACKAGE
Heatsinking for the SO PowerPad package is accomplished by allowing heat to flow through the ground slug on
the bottom of the package into the copper on the PC board. The heat slug must be soldered down to a copper
plane to get good heat transfer. It can also be connected through vias to internal copper planes. Since the heat
slug is at ground potential, traces must not be routed under it which are not at ground potential. Under all
possible conditions, the junction temperature must be within the range specified under operating conditions.
Figure 23 shows a curve for the θJA of the PSOP package for different copper area sizes using a typical PCB
with one ounce copper in still air.
180
130
80
30
0
0.5
COPPER AREA (sq. in.)
1.5
1
Figure 23. θJA vs. Copper (1 ounce) Area for PSOP Package
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DDA
DDA
DDA
DDA
KTT
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3882EMR-1.2/NOPB
LP3882EMR-1.5/NOPB
LP3882EMR-1.8/NOPB
LP3882EMRX-1.2/NOPB
LP3882ES-1.2/NOPB
LP3882ES-1.5/NOPB
LP3882ESX-1.2/NOPB
LP3882ESX-1.5/NOPB
ACTIVE SO PowerPAD
8
8
8
8
5
5
5
5
95
RoHS & Green
RoHS & Green
RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
3882E
MR1.2
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
95
SN
SN
SN
SN
SN
SN
SN
3882E
MR1.5
95
3882E
MR1.8
2500 RoHS & Green
3882E
MR1.2
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
45
45
RoHS-Exempt
& Green
LP3882ES
-1.2
DDPAK/
TO-263
KTT
RoHS-Exempt
& Green
LP3882ES
-1.5
DDPAK/
TO-263
KTT
500
500
RoHS-Exempt
& Green
LP3882ES
-1.2
DDPAK/
TO-263
KTT
RoHS-Exempt
& Green
LP3882ES
-1.5
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3882EMRX-1.2/NOPB
SO
PowerPAD
DDA
KTT
KTT
8
5
5
2500
500
330.0
330.0
330.0
12.4
24.4
24.4
6.5
5.4
2.0
5.0
5.0
8.0
12.0
24.0
24.0
Q1
Q2
Q2
LP3882ESX-1.2/NOPB DDPAK/
TO-263
10.75 14.85
10.75 14.85
16.0
16.0
LP3882ESX-1.5/NOPB DDPAK/
TO-263
500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3882EMRX-1.2/NOPB
LP3882ESX-1.2/NOPB
LP3882ESX-1.5/NOPB
SO PowerPAD
DDPAK/TO-263
DDPAK/TO-263
DDA
KTT
KTT
8
5
5
2500
500
356.0
367.0
367.0
356.0
367.0
367.0
35.0
45.0
45.0
500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LP3882EMR-1.2/NOPB
LP3882EMR-1.5/NOPB
LP3882EMR-1.8/NOPB
LP3882ES-1.2/NOPB
LP3882ES-1.5/NOPB
DDA
DDA
DDA
KTT
KTT
HSOIC
HSOIC
HSOIC
TO-263
TO-263
8
8
8
5
5
95
95
95
45
45
495
495
495
502
502
8
8
4064
4064
3.05
3.05
3.05
9.19
9.19
8
4064
25
25
8204.2
8204.2
Pack Materials-Page 3
PACKAGE OUTLINE
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
A
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
3.4
2.8
9
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.71
2.11
4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.71)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(3.4)
SOLDER MASK
OPENING
TYP
9
SYMM
(1.3)
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-8
4214849/A 08/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008B
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
(R0.05) TYP
8
1
8X (0.6)
(3.4)
BASED ON
0.125 THICK
STENCIL
SYMM
9
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.03 X 3.80
2.71 X 3.40 (SHOWN)
2.47 X 3.10
0.125
0.150
0.175
2.29 X 2.87
4214849/A 08/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
KTT0005B
TS5B (Rev D)
BOTTOM SIDE OF PACKAGE
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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Copyright © 2022, Texas Instruments Incorporated
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