LP3892ESX-1.2 [TI]
LP3892 1.5A Fast-Response Ultra Low Dropout Linear Regulators; LP3892 1.5A快速响应超低压降线性稳压器
| 型号： | LP3892ESX-1.2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LP3892 1.5A Fast-Response Ultra Low Dropout Linear Regulators |
| 文件： | 总18页 (文件大小：1147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP3892
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
LP3892 1.5A Fast-Response Ultra Low Dropout Linear Regulators
Check for Samples: LP3892
1
FEATURES
DESCRIPTION
The LP3892 is a high current, fast response regulator
which can maintain output voltage regulation with
minimum input to output voltage drop. Fabricated on
a CMOS process, the device operates from two input
voltages: Vbias provides voltage to drive the gate of
the N-MOS power transistor, while Vin is the input
voltage which supplies power to the load. The use of
an external bias rail allows the part to operate from
ultra low Vin voltages. Unlike bipolar regulators, the
CMOS architecture consumes extremely low
quiescent current at any output load current. The use
of an N-MOS power transistor results in wide
bandwidth, yet minimum external capacitance is
required to maintain loop stability.
2
•
Ultra Low Dropout Voltage (140 mV at 1.5A
typ)
•
•
•
•
•
Low Ground Pin Current
Load Regulation of 0.04%/A
60 nA Typical Quiescent Current in Shutdown
1.5% Output Accuracy (25°C)
TO-220, DDPAK/TO-263 and SO PowerPAD-8
Packages
•
•
Over Temperature/Over Current Protection
−40°C to +125°C Junction Temperature Range
APPLICATIONS
The fast transient response of these devices makes
them suitable for use in powering DSP,
Microcontroller Core voltages and Switch Mode
Power Supply post regulators. The parts are available
in TO-220, DDPAK/TO-263 and SO PowerPAD-8
packages.
•
•
•
•
•
•
•
DSP Power Supplies
Server Core and I/O Supplies
PC Add-in-Cards
Local Regulators in Set-Top Boxes
Microcontroller Power Supplies
High Efficiency Power Supplies
SMPS Post-Regulators
Dropout Voltage:140mV (typ) at 1.5A load current.
Ground Pin Current: 3 mA (typ) at full load.
Shutdown Current: 60 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature
accuracy.
TYPICAL APPLICATION CIRCUIT
At least 10 µF of input and output capacitance is required for stability.
*Tantalum capacitors are recommended. Aluminum electrolytic capacitors may be used for restricted temperature
range. See application hints.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
LP3892
SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CONNECTION DIAGRAM
Figure 1. TO-220, Top View
Figure 2. DDPAK/TO-263, Top View
V
V
V
1
2
3
4
8 N/C
OUT
7 V
OUT
IN
GND
6
5
S/D
BIAS
GND
GND
Figure 3. SO PowerPAD-8, Top View
white space
white space
white space
white space
BLOCK DIAGRAM
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
(1)
ABSOLUTE MAXIMUM RATINGS
VALUE / UNITS
−65°C to +150°C
260°C
Storage Temperature Range
Lead Temp. (Soldering, 5 seconds)
ESD Rating
(2)
Human Body Model
2 kV
200V
(3)
Machine Model
(4)
Power Dissipation
Internally Limited
−0.3V to +6V
VIN Supply Voltage (Survival)
VBIAS Supply Voltage (Survival)
Shutdown Input Voltage (Survival)
IOUT (Survival)
−0.3V to +7V
−0.3V to +7V
Internally Limited
−0.3V to +6V
Output Voltage (Survival)
Junction Temperature
−40°C to +150°C
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For specifications, see Electrical
Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.
(2) The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
(3) The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V.
(4) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values.
θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be
assumed. θJ-A for DDPAK/TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square
inches in area. θJ-A value for typical SO PowerPAD-8 PC board mounting is 166°C/W. If power dissipation causes the junction
temperature to exceed specified limits, the device will go into thermal shutdown.
RECOMMENDED OPERATING CONDITIONS
VALUE / UNITS
VIN
(VOUT + VDO) to 5.5V
0 to +6V
Shutdown
IOUT
1.5A
Junction Temperature
VBIAS
−40°C to +125°C
4.5V to 6V
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
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ELECTRICAL CHARACTERISTICS
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 10µF, VS/D = VBIAS
.
Typical
(1)
(1)
Symbol
VO
Parameter
Conditions
MIN
MAX
Units
(2)
Output Voltage Tolerance
10 mA ≤ IL≤ 1.5A,
VO(NOM) + 1V ≤ VIN ≤ 5.5V,
4.5V ≤ VBIAS ≤ 6V
1.198
1.186
1.234
1.246
1.216
1.478
1.455
1.522
1.545
1.5
V
1.773
1.746
1.827
1.854
1.8
ΔVO/ΔVIN Output Voltage Line Regulation(3) (4) VO(NOM) + 1V ≤ VIN ≤ 5.5V
0.01
%/V
%/A
(5)
ΔVO/ΔIL
Output Voltage Load Regulation
10 mA ≤ IL≤ 1.5A
0.04
0.06
(6)
VDO
Dropout Voltage
IL = 1.5A (TO-220 and DDPAK/TO-263
only)
320
500
140
155
3
mV
IL = 1.5A (SO PowerPAD only)
340
550
IQ(VIN
)
Quiescent Current Drawn from VIN
Supply
10 mA ≤ IL≤ 1.5A
7
8
mA
µA
V
S/D ≤ 0.3V
1
30
0.03
1
IQ(VBIAS
)
Quiescent Current Drawn from VBIAS 10 mA ≤ IL≤ 1.5A
2
3
mA
Supply
V
S/D ≤ 0.3V
1
30
0.03
4.3
µA
A
ISC
Short-Circuit Current
VOUT = 0V
Shutdown Input
VSDT
Output Turn-off Threshold
Output = ON
1.3
0.7
0.7
20
15
1
V
Output = OFF
0.3
Td (OFF)
Td (ON)
IS/D
Turn-OFF Delay
Turn-ON Delay
S/D Input Current
RLOAD X COUT << Td (OFF)
RLOAD X COUT << Td (ON)
VS/D =1.3V
µs
µA
VS/D ≤ 0.3V
−1
AC Parameters
PSRR
(VIN
Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz
VIN = VOUT + 1V, f = 1 kHz
80
65
70
65
)
dB
PSRR
(VBIAS
Ripple Rejection for VBIAS Voltage
VBIAS = VOUT + 3V, f = 120 Hz
VBIAS = VOUT + 3V, f = 1 kHz
f = 120 Hz
)
Output Noise Density
Output Noise Voltage
µV/root−
1
Hz
en
BW = 10 Hz − 100 kHz, VOUT = 1.8V
BW = 300 Hz − 300 kHz, VOUT = 1.8V
150
90
µV (rms)
(1) Limits are specified through testing, statistical correlation, or design.
(2) Typical numbers represent the most likely parametric norm for 25°C operation.
(3) If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to
ground.
(4) Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
(5) Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load
to full load.
(6) Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. The SO
PowerPAD-8 package devices have a slightly higher dropout voltage due to increased band wire resistance.
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
IGND vs VSD
VOUT vs Temperature
Figure 4.
Figure 5.
DC Load Regulation
Line Regulation vs VIN
Figure 6.
Figure 7.
IBIAS vs IL
Line Regulation vs VBIAS
1.60
1.40
VBIAS = 5V
VIN = 2.3V
125oC
25oC
1.20
1.00
-40oC
0.80
0.60
0
0.5
1.0
1.5
LOAD CURRENT (A)
Figure 8.
Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
IGND vs VSD
Noise Measurement
Figure 10.
Figure 11.
VOUTStartup Waveform
VOUTStartup Waveform
Figure 12.
Figure 13.
Line Regulation vs VBIAS
Line Regulation vs VBIAS
Figure 14.
Figure 15.
6
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: TJ = 25°C, COUT = 10 µF, Cin = 10 µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V.
VIN PSRR
VIN PSRR
Figure 16.
Figure 17.
VBIAS PSRR
Figure 18.
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
Application Hints
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EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
At least 10µF of output capacitance is required for stability (the amount of capacitance can be increased without
limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean
analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range
as shown in Figure 19 over the full operating temperature range for stable operation.
10
1.0
COUT > 10 mF
STABLE REGION
0.1
.01
.001
0
1
2
LOAD CURRENT (A)
Figure 19. Minimum ESR vs Output Load Current
Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements
and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR
increases very rapidly at temperatures below 10°C. Aluminum caps can only be used in applications where lower
temperature operation is not required.
A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical
loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap,
it must be one whose ESR is specified at a frequency of 100 kHz or more.
Because the ESR of ceramic capacitors is only a few milliohms, they are not suitable for use as output capacitors
on LP389X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the amount of
Tantalum capacitance connected from the output to ground.
INPUT CAPACITOR
The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low
source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very
good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be
used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application
where temperatures go below about 10°C.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage
must be in the range of 4.5 - 6V to assure proper operation of the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage
is below approximately 4V.
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a
pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible conditions, the junction temperature must be within the range specified under
operating conditions. The total power dissipation of the device is given by:
PD = (VIN−VOUT)IOUT+ (VIN)IGND
(1)
where IGND is the operating ground current of the device.
The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the
application, and the maximum allowable junction temperature (TJmax):
TRmax = TJmax− TAmax
(2)
The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the
formula:
θJA = TRmax / PD
(3)
These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount
of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W
for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can
dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat
sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO-220 package can be reduced by attaching it to a heat sink or a copper plane on
a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for
DDPAK/TO-263 package.
The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH
− θJC.
In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal
resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO-220 package. The value for
θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value
is unknown, 2°C/W can be assumed.
HEATSINKING DDPAK/TO-263 PACKAGE
The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are
soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263
package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the
copper area for heat sinking.
Figure 20. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 Package
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As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement.
The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W.
Figure 22 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient
temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C.
Figure 21. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package
HEATSINKING SO PowerPAD PACKAGE
Heatsinking for the SO PowerPAD-8 package is accomplished by allowing heat to flow through the ground slug
on the bottom of the package into the copper on the PC board. The heat slug must be soldered down to a
copper plane to get good heat transfer. It can also be connected through vias to internal copper planes. Since
the heat slug is at ground potential, traces must not be routed under it which are not at ground potential. Under
all possible conditions, the junction temperature must be within the range specified under operating conditions.
Figure 22 shows a curve for the θJA of the SO PowerPAD package for different copper area sizes using a typical
PCB with one ounce copper in still air.
180
130
80
30
0
0.5
COPPER AREA (sq. in.)
1.5
1
Figure 22. θJA vs Copper (1 ounce) Area for SO PowerPAD Package
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SNVS236D –SEPTEMBER 2003–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
LP3892EMR-1.2/NOPB
LP3892EMR-1.5/NOPB
LP3892EMR-1.8/NOPB
LP3892EMRX-1.2/NOPB
LP3892EMRX-1.5/NOPB
LP3892ES-1.2/NOPB
LP3892ES-1.5/NOPB
LP3892ESX-1.2/NOPB
LP3892ESX-1.5/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE SO PowerPAD
DDA
8
8
8
8
8
5
5
5
5
95
Green (RoHS
& no Sb/Br)
SN | CU SN
SN | CU SN
SN | CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
Level-3-245C-168 HR
3892E
MR1.2
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
DDA
DDA
KTT
KTT
KTT
KTT
95
95
Green (RoHS
& no Sb/Br)
3892E
MR1.5
Green (RoHS
& no Sb/Br)
3892E
MR1.8
2500
2500
45
Green (RoHS
& no Sb/Br)
3892E
MR1.2
Green (RoHS
& no Sb/Br)
SN | CU SN
CU SN
3892E
MR1.5
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
LP3892ES
-1.2
DDPAK/
TO-263
45
Pb-Free (RoHS
Exempt)
CU SN
LP3892ES
-1.5
DDPAK/
TO-263
500
500
Pb-Free (RoHS
Exempt)
CU SN
LP3892ES
-1.2
DDPAK/
TO-263
Pb-Free (RoHS
Exempt)
CU SN
LP3892ES
-1.5
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3892EMRX-1.2/NOPB
LP3892EMRX-1.5/NOPB
SO
Power
PAD
DDA
DDA
8
8
330.0
330.0
12.4
12.4
6.5
6.5
5.4
5.4
2.0
2.0
8.0
8.0
12.0
12.0
Q1
Q1
SO
Power
PAD
LP3892ESX-1.2/NOPB DDPAK/
TO-263
KTT
KTT
5
5
500
500
330.0
330.0
24.4
24.4
10.75 14.85
10.75 14.85
5.0
5.0
16.0
16.0
24.0
24.0
Q2
Q2
LP3892ESX-1.5/NOPB DDPAK/
TO-263
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3892EMRX-1.2/NOPB
LP3892EMRX-1.5/NOPB
LP3892ESX-1.2/NOPB
LP3892ESX-1.5/NOPB
SO PowerPAD
SO PowerPAD
DDPAK/TO-263
DDPAK/TO-263
DDA
DDA
KTT
KTT
8
8
5
5
2500
2500
500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
45.0
45.0
500
Pack Materials-Page 2
MECHANICAL DATA
DDA0008B
MRA08B (Rev B)
www.ti.com
MECHANICAL DATA
KTT0005B
TS5B (Rev D)
BOTTOM SIDE OF PACKAGE
www.ti.com
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