LP3906SQ-VPFP/NOPB_技术文档

LP3906

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SNVS456M –AUGUST 2006–REVISED MAY 2013

Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible

Interface

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1

FEATURES

KEY SPECIFICATIONS

2

•

Compatible with Advanced Applications

Processors and FPGAs

•

DC/DC Converter (Buck)

–

1.5A Output Current

•

2 LDOs for Powering Internal Processor

Functions and I/Os

Programmable V_OUTfrom:

–

Buck1 : 0.8V–2.0V

Buck2 : 1.0V–3.5V

High Speed Serial Interface for Independent

Control of Device Functions and Settings

–

Up to 96% Efficiency

•

Precision Internal Reference

2 MHz PWM Switching Frequency

±3% Output Voltage Accuracy

Automatic Soft Start

Thermal Overload Protection

Current Overload Protection

24-lead 5 × 4 × 0.8 mm WQFN Package

Software Programmable Regulators

•

Linear Regulators (LDO)

–

Programmable V_OUTof 1.0V–3.5V

±3% Output Voltage Accuracy

300 mA Output Currents

APPLICATIONS

•

FPGA, DSP Core Power

Applications Processors

Peripheral I/O Power

25 mW (Typ) Dropout

DESCRIPTION

The LP3906 is a multi-function, programmable Power

Management Unit, optimized for low power FPGAs,

Microprocessors and DSPs.

Typical Application Circuits

VINLDO12

EN_T

1 mF

ENLDO1

ENLDO2

SYNC

VIN1

10 mF

ENSW1

ENSW2

LDO1

2.2 mH

SW1

FB1

10 mF

0.47 mF

GND_SW1

VINLDO1

VINLDO2

LDO2

1 mF

LP3906

VIN2

10 mF

2.2 mH

0.47 mF

SW2

FB2

SDA

SCL

10 mF

GND_SW2

AVDD

GND_L

GND_C

DAP

1 mF

Figure 1. Typical Application Circuit

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

2

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3906

SNVS456M –AUGUST 2006–REVISED MAY 2013

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For information about how schottky diodes can reduce noise in high load, high Vin applications, see Buck Output

Ripple Management.

DESCRIPTION (CONTINUED)

This device integrates two highly efficient 1.5A Step-Down DC/DC converters with dynamic voltage management

(DVM), two 300mA Linear Regulators and a 400kHz I²C compatible interface to allow a host controller access to

the internal control registers of the LP3906. The LP3906 additionally features programmable power-on

sequencing and is offered in a tiny 5 x 4 x 0.8mm WQFN-24 pin package.

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DC SOURCE

4.5 œ 5.5V

Li-ion/polymer cell 3.6V - 4.

+

2V

FPGA

LP3906 PMIC

Cvdd

4.7 mF

1 mF

10 mF

SYNC

23

12

20

13

1

19

7

Clock

divider

Lsw1 2.2 mH

1.2V

OSC

CPU

6

VBUCK1

CORE

SW1

Csw1

10 mF

BUCK1

*

AVDD

FB1

10

15

EN_T

11

ENLDO1

Lsw2 2.2 mH

3.3V

VBUCK2

2

16

22

24

Power

ON-OFF

Logic

I/O

ENLDO2

ENSW1

SW2

Csw2

10 mF

BUCK2

*

21

AVDD

FB2

vref

VINLDO1

ENSW2

Programmable

Application

Processor

VinLDO12

LDO1

14

3.3V

LDO1

Cldo1

0.47 mF

Thermal

Shutdown

RESET

9

8

VINLDO2

BIAS

SCL

SDA

I2C

LDO2

1.8V

LDO2

18

Cldo2

0.47 mF

Power On

Reset

Logic

Control

and

registers

3.3V

VBUCK2

17

GND_L

5

3

4

Flash

GND_SW1

GND_C

GND_SW2

Figure 2. Typical Application Circuit

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Connection Diagram

19 18

17 16 15 14

13

20

21

22

12

11

10

9

23

24

8

1

2

3

4

5

6

7

Figure 3. 24-Lead WQFN Package (Top View)

See Package Number NHZ0024B

Table 1. Default Voltage Options⁽¹⁾⁽²⁾

Part Number

Package

Marking

Buck1

Buck2

LDO1

LDO2

LP3906SQ-DJXI/NOPB

LP3906SQ-FXPI/NOPB

LP3906SQ-JXXI/NOPB

LP3906SQ-PPXP/NOPB

LP3906SQ-TKXII/NOPB⁽³⁾

LP3906SQ-VPFP/NOPB

LP3906SQE-PPXP/NOPB

LP3906SQE-VPFP/NOPB

LP3906SQX-DJXI/NOPB

LP3906SQX-FXPI/NOPB

LP3906SQX-JXXI/NOPB

LP3906SQX-PPXP/NOPB

LP3906SQX-TKXII/NOPB⁽³⁾

LP3906SQX-VPFP/NOPB

06-DJXI

0.9V

1.0V

1.2V

1.5V

1.25V

1.8V

1.5V

1.8V

0.9V

1.0V

1.2V

1.5V

1.25V

1.8V

3.3V

2.5V

3.3V

2.5V

1.8V

3.3V

2.5V

3.3V

2.5V

3.3V

2.5V

3.3V

1.8V

1.5V

3.3V

1.5V

3.3V

2.5V

3.3V

1.8V

1.5V

1.8V

2.5V

1.8V

2.5V

1.8V

2.5V

1.8V

2.5V

06-FXPI

06-JXXI

06-PPXP

06-TKXII⁽³⁾

06-VPFP

06-PPXP

06-VPFP

06-DJXI

06-FXPI

06-JXXI

06-PPXP

06-TKXII⁽³⁾

06-VPFP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Option only available with default EN_T of 001; all other options use 010.

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Pin Descriptions⁽¹⁾

Pin Name

Pin No.

1

I/O

I

Type

PWR

G

Description

VIN2

SW2

Power in from either DC source or Battery to Buck 2

Buck2 switcher output pin

2

O

G

O

I

GND_SW2

GND_C

GND_SW1

SW1

3

Buck2 NMOS Power Ground

4

G

Non switching core ground pin

5

G

Buck1 NMOS Power Ground

6

PWR

D

Buck1 switcher output pin

VIN1

7

Power in from either DC source or Battery to buck 1

I²C Data (Bidirectional)

SDA

8

I/O

I

SCL

9

D

I²C Clock

EN_T

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I

D

Enable for preset power on sequence.

Buck1 input feedback terminal

FB1

I

A

AVDD

I

PWR

D

Analog Power for Buck converters.

Power in from either DC source or Battery to input terminal of LDO1

LDO1 Output

VINLDO1

LDO1

I

O

I

ENLDO1

ENLDO2

GND_L

LDO2

LDO1 enable pin, a logic HIGH enables the LDO1

LDO2 enable pin, a logic HIGH enables the LDO2

LDO Ground

I

D

G

O

I

G

PWR

A

LDO2 Output

VINLDO2

VinLDO12

FB2

Power in from either DC source or battery to input terminal to LDO2

Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)

Buck2 input feedback terminal

I

ENSW1

SYNC

I

D

Enable Pin for Buck1 switcher, a logic HIGH enables Buck1

I

D

Frequency Synchronization pin which allows the user to connect an external

clock signal PLL to synchronize the PMIC internal oscillator.

ENSW2

DAP

24

I

D

Enable Pin for Buck2 switcher, a logic HIGH enables Buck2

DAP

GND

Connection isn't necessary for electrical performance, but it is recommended

for better thermal dissipation.

(1) A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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ABSOLUTE MAXIMUM RATINGS^(1)(2)(3)

V_IN, SDA, SCL

−0.3V to +6V

GND to GND SLUG

±0.3V

Power Dissipation (P_{D_MAX}

)

(T_A=85°C, T_MAX=125°C, )⁽⁴⁾

1.43 W

150°C

Junction Temperature (T_J-MAX

Storage Temperature Range

Maximum Lead Temperature (Soldering)

ESD Ratings

)

−65°C to +150°C

260°C

(5)

Human Body Model

2 kV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (θ_JA× P_D-MAX). See APPLICATION

NOTES.

(5) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MILSTD - 883 3015.7)

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OPERATING RATINGS^(1)(2)(3)

Bucks

V_IN

2.7V to 5.5V

0 to (V_IN+ 0.3V)

−40°C to +125°C

−40°C to +85°C

V_EN

Junction Temperature (T_J) Range

Ambient Temperature (T_A) Range⁽⁴⁾

Thermal Properties^{(5)(6) (4)}

Junction-to-Ambient Thermal Resistance

(θ_JA)NHZ0024B

28°C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(4) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(5) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 160°C (typ.) and

disengages at T_J= 140°C (typ.)

(6) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (θ_JA× P_D-MAX). See APPLICATION

NOTES.

GENERAL ELECTRICAL CHARACTERISTICS^(1)(2)(3)(4)

Unless otherwise noted, V_IN= 3.6V, Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.

Parameter

Test Conditions

V_DDFalling Edge

Min

Typ

1.9

160

20

Max

Units

V

V_POR

T_SD

Power-On Reset Threshold

Thermal Shutdown Threshold

Themal Shutdown Hysteresis

°C

T_SDH

°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is specified. Operating Ratings do not imply specified performance limits. For specified performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not specified, but do represent the most

likely norm.

(4) This specification is ensured by design.

I²C COMPATIBLE INTERFACE ELECTRICAL SPECIFICATIONS⁽¹⁾

Unless otherwise noted, V_IN= 3.6V. Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C

Parameter

Test Conditions

Min

Typ

Max

Units

kHz

µs

F_CLK

Clock Frequency

400

t_BF

Bus-Free Time Between Start and Stop

Hold Time Repeated Start Condition

CLK Low Period

See⁽¹⁾

1.3

0.6

1.3

0.6

0

t_HOLD

t_CLKLP

t_CLKHP

t_SU

µs

CLK High Period

µs

Set Up Time Repeated Start Condition

Data Hold time

µs

t_DATAHLD

t_DATASU

T_SU

µs

Data Set Up Time

100

0.6

ns

Set Up Time for Start Condition

µs

T_TRANS

Maximum Pulse Width of Spikes that

Must be Suppressed by the Input Filter of

Both DATA & CLK Signals.

50

ns

(1) This specification is ensured by design.

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LOW DROP OUT REGULATORS, LDO1 AND LDO2

Unless otherwise noted, V_IN= 3.6, C_IN= 1.0 µF, C_OUT= 0.47 µF. Typical values and limits appearing in normal type apply for

T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to

(1)(2) (3)(4)(5)(6) (7)

+125°C.

Parameter

Test Conditions

Min

1.74

−3

Typ

Max

5.5

3

Units

V

V_IN

Operational Voltage Range

VINLDO1 and VINLDO2 PMOS

pins⁽⁸⁾

V_OUTAccuracy

Output Voltage Accuracy (Default V_OUT

Line Regulation

)

Load current = 1 mA

%

ΔV_OUT

V_IN= (V_OUT+ 0.3V) to 5.0V,

⁽⁷⁾, Load Current = 1 mA

0.15

%/V

Load Regulation

V_IN= 3.6V,

Load Current = 1 mA to I_MAX

0.011

200

%/mA

I_SC

Short Circuit Current Limit

Dropout Voltage

LDO1-2, V_OUT= 0V

Load Current = 50 mA⁽⁵⁾

F = 10 kHz, Load Current = I_MAX

10 Hz < F < 100 KHz

I_OUT= 0 mA

500

25

mA

mV

dB

V_IN– V_OUT

PSRR

θn

Power Supply Ripple Rejection

Supply Output Noise

Quiescent Current “On”

Quiescent Current “Off”

Turn On Time

45

80

µVrms

µA

(6) (9)

I_Q

40

I_OUT= I_MAX

EN is de-asserted⁽¹⁰⁾

60

µA

0.03

300

µA

T_ON

Start up from shut-down

µs

C_OUT

Output Capacitor

Capacitance for stability 0°C ≤ T_J

≤ 125°C

0.33

0.47

1.0

µF

−40°C ≤ T_J≤ 125°C

0.68

5

µF

ESR

500

mΩ

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

(7) V_INminimum for line regulation values is 1.8V.

.

(8) Pins 13, 19 can operate from Vin min of 1.74 to a Vin max of 5.5V this rating is only for the series pass pmos power fet. It allows the

system design to use a lower voltage rating if the input voltage comes from a buck output.

(9) The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to

disable each block of the IC please contact the factory applications for IQ details.

(10) The Iq exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2µA

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BUCK CONVERTERS SW1, SW2

Unless otherwise noted, V_IN= 3.6, C_IN= 10 µF, C_OUT= 10 µF, L_OUT= 2.2 µH ceramic. Typical values and limits appearing in

normal type apply for T_J= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

(1) (2) (3) (4) (5)

operation, −40°C to +125°C.

Parameter

Test Conditions

Default V_OUT

Min

Typ

Max

Units

%

V_OUT

Output Voltage Accuracy

Line Regulation

−3

+3

2.7< V_IN< 5.5

I_O=10 mA

0.089

%/V

Load Regulation

100 mA < I_O< I_MAX

Load Current = 250 mA

EN is de-asserted

0.0013

96

%/mA

%

Eff

Efficiency

I_SHDN

f_OSC

Shutdown Supply Current

Sync Mode Clock Frequency

0.01

2.0

µA

Synchronized from 13 MHz system

clock

MHz

Internal Oscillator Frequency

Peak Switching Current Limit

Quiescent Current “On”

Pin-Pin Resistance PFET

Pin-Pin Resistance NFET

Turn On Time

2.0

33

MHz

A

I_PEAK

(5)

I_Q

No load PFM Mode

µA

mΩ

µs

R_DSON(P)

R_DSON(N)

T_ON

200

180

500

Start up from shut-down

Capacitance for stability

C_IN

Input Capacitor

10

µF

C_O

Output Capacitor

µF

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not specifications, but do represent the most

likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to

disable each block of the IC please contact the factory applications for IQ details.

I/O ELECTRICAL CHARACTERISTICS

Unless otherwise noted: Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing in boldface

(1)

type apply over the entire junction temperature range for operation, T_J= 0°C to +125°C.

Limit

Parameter

Test Conditions

Units

Min

1.2

Max

0.4

V_IL

V_IH

Input Low Level

Input High Level

V

(1) This specification is ensured by design.

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO

T_A= 25°C unless otherwise noted

Output Voltage Change

vs

Output Voltage Change

vs

Temperature (LDO2)

Vin = 4.3V, Vout = 1.8V, 100 mA load

Temperature (LDO1)

Vin = 4.3V, Vout = 3.3V, 100 mA load

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C)

Figure 4.

Figure 5.

Load Transient (LDO1)

3.6 Vin, 3.3 Vout, 0 – 100 mA load

Load Transient (LDO2)

3.6 Vin, 1.8 Vout, 0 – 100 mA load

Figure 6.

Figure 7.

Line Transient (LDO1)

3.6 - 4.5 Vin, 3.3 Vout, 150 mA load

Line Transient (LDO2)

3 – 4.2 Vin, 1.8 Vout, 150 mA load

Figure 8.

Figure 9.

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO (continued)

T_A= 25°C unless otherwise noted

Enable Start-up time (LDO1) )

0-3.6 Vin, 3.3 Vout, 1mA load

Enable Start-up time (LDO2)

0 – 3.6 Vin, 1.8 Vout, 1 mA load

Figure 10.

Figure 11.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK

T_A= 25°C unless otherwise noted

Output Voltage

vs.

Supply Voltage

(Vout = 1.0 V)

Shutdown Current

vs.

Temp

0.15

0.12

0.09

0.06

0.03

0.00

I

= 20 mA

OUT

I

= 750 mA

OUT

1.040

1.035

1.030

1.025

1.020

1.015

1.010

1.005

1.000

0.995

0.990

I

= 1.5A

OUT

VIN = 5.5V

VIN = 3.6V

VIN = 2.7V

-40

-20

0

20

40

60

80

2.5

3.0

3.5

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

Figure 12.

Figure 13.

Output Voltage

vs.

Supply Voltage

(Vout = 1.8V)

Output Voltage

vs.

Supply Voltage

(Vout = 3.5V)

1.835

1.830

1.825

1.820

1.815

1.810

1.805

1.800

3.550

3.540

3.530

3.520

3.510

3.500

3.490

I

= 20 mA

OUT

I

= 750 mA

OUT

I

= 1.5A

OUT

I

= 20 mA

OUT

I

= 1.5 A

OUT

I

= 750 mA

5.0

OUT

2.5

3.0

3.5

4.0

4.5

5.0

5.5

4.0

4.5

5.5

SUPPLY VOLTAGE (V)

Figure 14.

Figure 15.

Buck 1 Efficiency

vs

Buck 1 Efficiency

vs

Output Current

(Forced PWM Mode, Vout =1.2V, L= 2.2µH)

(Forced PWM Mode, Vout =2.0V, L= 2.2µH)

100

90

V

IN

= 2.8V

80

70

60

50

40

30

20

10

0

V

= 2.8V

80

70

60

50

40

30

20

10

0

IN

V

= 5.5V

= 3.6V

IN

V

= 5.5V

= 3.6V

IN

V

IN

V

IN

-3

-2

-1

0

1

2

3

4

-2

-1

0

1

2

3

4

10 10

10

OUTPUT CURRENT (mA)

Figure 16.

Figure 17.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued)

T_A= 25°C unless otherwise noted

Buck 1 Efficiency

vs

Output Current

(PFM to PWM mode, Vout =1.2V, L= 2.2µH)

Output Current

(PFM to PWM mode, Vout =2.0V, L= 2.2µH)

100

V

= 2.8V

IN

V

IN

= 2.8V

90

80

70

60

50

40

30

90

80

70

60

50

40

30

V

= 5.5V

IN

V

= 5.5V

IN

V

= 3.6V

V

IN

= 3.6V

IN

-2

10

-1

10

0

1

10

2

10

3

4

10

-3

-2

-1

0

1

2

3

4

10

OUTPUT CURRENT (mA)

Figure 18.

Figure 19.

Buck 2 Efficiency

vs

Buck 2 Efficiency

vs

Output Current

(Forced PWM Mode, Vout =1.8V, L= 2.2µH)

(Forced PWM Mode, Vout =3.3V, L= 2.2µH)

100

90

V

= 4.3V

IN

V

= 4.3V

IN

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

V

= 5.5V

V

IN

= 5.5V

IN

-2

-1

0

1

2

3

4

-2

-1

0

1

2

3

4

10

OUTPUT CURRENT (mA)

Figure 20.

Figure 21.

Buck 2 Efficiency

vs

Buck 2 Efficiency

vs

Output Current

(PFM to PWM Mode, Vout =1.8V, L= 2.2µH)

(PFM to PWM Mode, Vout =3.3V, L= 2.2µH)

100

V

IN

= 4.3V

V

= 4.3V

IN

90

80

70

60

50

40

90

80

70

60

50

40

V

IN

= 5.5V

V

= 5.5V

IN

-2

-1

0

1

2

3

4

-2

-1

0

1

2

3

4

10

OUTPUT CURRENT (mA)

Figure 22.

Figure 23.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued)

T_A= 25°C unless otherwise noted

Load Transient Response

Vout = 1.2 (PWM Mode)

Mode Change by Load Transient

Vout = 1.2V (PWM to PFM)

Figure 24.

Figure 25.

Line Transient Response

Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load

Line Transient Response

Vin = 3 – 3.6 V, Vout = 3.3 V, 250 mA load

Figure 26.

Figure 27.

Start up into PWM Mode

Vout = 1.8 V, 1.2 A load

Start up into PWM Mode

Vout = 3.3 V, 1.2 A load

Figure 28.

Figure 29.

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK (continued)

T_A= 25°C unless otherwise noted

Start up into PFM Mode

Vout = 1.8 V, 30 mA load

Start up into PFM Mode

Vout = 3.3 V, 30 mA load

Figure 30.

Figure 31.

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HIGH VIN-HIGH LOAD OPERATION

Additional information is provided when the IC is operated at extremes of Vin and regulator loads. These are

described in terms of the Junction Temperature and Buck Output Ripple Management.

Junction Temperature

The maximum junction temperature TJ-MAX-OP of 125ºC of the IC package.

The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and

Total chip power must be controlled to keep TJ below this maximum:

TJ-MAX-OP = TA-MAX + (θJA) [ °C/ Watt] * (PD-MAX) [Watts]

Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a

minor amount for chip overhead. Chip overhead is Bias, TSD & LDO analog.

PD-MAX = P_LDO1+ P_LD02+ P_BUCK1+ P_BUCK2+ (0.0001A * Vin) [Watts].

Power dissipation of LDO1

P_LDO1= (Vin_LDO1- Vout_LDO1) * Iout_LDO1[V*A]

Power dissipation of LDO2

P_LDO2= (Vin_LDO2- Vout_LDO2) * Iout_LDO2[V*A]

Power dissipation of Buck1

P_Buck1= P_IN– P_OUT

=

Vout_Buck1* Iout_Buck1* (1 -η₁) / η₁[V*A]

η₁= efficiency of buck 1

Power dissipation of Buck2

P_Buck2= P_IN– P_OUT

=

Vout_Buck2* Iout_Buck2* (1 - η₂) / η₂[V*A]

η₂= efficiency of buck 2

η is the efficiency for the specific condition taken from efficiency graphs.

Buck Output Ripple Management

If Vin and ILoad increase, the output ripple associated with the Buck Regulators also increases. Figure 32 shows

the safe operating area. To ensure operation in the area of concern it is recommended that the system designer

circumvents the output ripple issues to install schottky diodes on the Bucks(s) that are expected to perform under

these extreme corner conditions.

(Schottky diodes are recommended to reduce the output ripple if the system requirements include this shaded

area of operation. Vin > 5.2 V and Iload > 1.24 A)

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5.5

5.0

4.5

4.0

3.5

3.0

0

0.5

1.0

1.5

LOAD CURRENT (A)

Figure 32. LP3906 Buck Converter

V_INvs I_LOADOperating Ranges

Thermal Performance of the WQFN Package

The LP3906 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize

power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at

the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.

Compared to the traditional leaded packages where the die attach pad is embedded inside the molding

compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on

thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (θJA) can be improved by a

factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land

and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer

diameter for thermal vias are 1.27mm and 0.33mm respectively. Typical copper via barrel plating is 1oz, although

thicker copper may be used to further improve thermal performance. The LP3906 die attach pad is connected to

the substrate of the IC and therefore, the thermal land and vias on the PCB board need to be connected to

ground (GND pin).

For more information on board layout techniques, refer to Application Note AN–1187 (Literature Number

SNOA401) “Leadless Lead frame Package (WQFN).” This application note also discusses package handling,

solder stencil and the assembly process.

DC/DC Converters

OVERVIEW

The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators

LDO1 and LDO2 and two Buck converters SW1 and SW2. The table here under lists the output characteristics of

the various regulators.

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Table 2. SUPPLY SPECIFICATION

Output

Supply

Load

I_MAX

V_OUTRange(V)

Resolution (mV)

Maximum Output Current (mA)

LDO1

LDO2

SW1

analog

digital

1.0 to 3.5

0.8 to 2.0

1.0 to 3.5

100

50

300

1500

SW2

100

LINEAR LOW DROP-OUT REGULATORS (LDOS)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

register. The output voltages of both LDOs are register programmable. The default output voltages are factory

programmed during Final Test, which can be tailored to the specific needs of the system designer.

VLDO

LDO

VIN

Register

controlled

+

-

ENLDO

Vref

GND

NO-LOAD STABILITY

The LDOs will remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example CMOS RAM keep-alive applications.

LDO1 AND LDO2 CONTROL REGISTERS

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100mV from 1.0V to 3.5V by programming bits D4-0 in the LDO Control registers. Both

LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is

also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the

register is logic 1 by default. The output voltage can be altered while the LDO is enabled.

SW1, SW2: Synchronous Step Down Magnetic DC/DC Converters

FUNCTIONAL DESCRIPTION

The LP3906 incorporates two high efficiency synchronous switching buck regulators, SW1 and SW2 that deliver

a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1500mA depending on the

input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability).

There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70mA or higher, delivering voltage precision of +/-3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (I_Q= 15 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering

the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced

through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of

the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

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Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload

protection.

CIRCUIT OPERATION DESCRIPTION

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of

V_IN- V_OUT

L

(1)

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET

switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor

draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor

current down with a slope of

-V_OUT

L

(2)

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

PWM OPERATION

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input

voltage is introduced.

INTERNAL SYNCHRONOUS RECTIFICATION

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

CURRENT LIMITING

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 2.0 A (typ). If the output is

shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration

until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby

preventing runaway.

A current limit feature allows the buck to protect itself and external components during overload conditions PWM

mode implements cycle-by-cycle current limiting using an internal comparator that trips at 2000mA (typical).

PFM OPERATION

At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply

current to maintain high efficiency.

The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or

more clock cycles:

1. The inductor current becomes discontinuous

or

2. The peak PMOS switch current drops below the I_MODElevel

V_IN

(Typically I_MODE< 66 mA +

)

160W

(3)

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During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output

FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output

voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on.

It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the I_PFMlevel

set for PFM mode. The typical peak current in PFM mode is:

V_IN

I_PFM= 66 mA +

80W

(4)

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the ‘high’ PFM comparator threshold (see Figure 33), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM

threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output

switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this

‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load

conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage

to ~1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (see Figure 33) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.

SW1, SW2 OPERATION

SW1 and SW2 have selectable output voltages ranging from 0.8V to 3.5V (typ.). Both SW1 and SW2 in the

LP3906 are I²C register controlled and are enabled by default through the internal state machine of the LP3906

following a Power-On event that moves the operating mode to the Active state. (see POWER ON). The SW1 and

SW2 output voltages revert to default values when the power on sequence has been completed. The default

output voltage for each buck converter is factory programmable. (See APPLICATION NOTES).

SW1, SW2 can be enabled/disabled through the corresponding control register.

The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the

functional description. The modulation mode can be overridden by setting I²C bit to a logic 1 in the corresponding

buck control register, forcing the buck to operate in PWM mode regardless of the load condition.

High PFM Threshold

PFM Mode at Light Load

~1.016 * Vout

Load current

increases

Low1 PFM Threshold

~1.008 * Vout

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

High PFM

Nfet on

drains

inductor

current

until

I inductor = 0

Low PFM

Threshold,

turn on

Pfet on

until

Voltage

Threshold

reached,

go into

Ipfm limit

reached

PFET

Low2 PFM Threshold

Vout

sleep mode

PWM Mode at

Moderate to Heavy

Loads

Low2 PFM Threshold,

switch back to PWMmode

Figure 33.

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SHUTDOWN MODE

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is

activated. It is recommended to disable the converter during the system power up and under voltage conditions

when the supply is less than 2.8V.

SOFT START

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing start-up stresses and surges. The two LP3906 buck converters have a soft-start circuit that limits in-

rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated

only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch

current limit in steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch current limit). The start-up time

thereby depends on the output capacitor and load current demanded at start-up.

LOW DROPOUT OPERATION

The LP3906 can operate at 100% duty cycle (noswitching; PMOS switch completely on) for low drop out support

of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum

input voltage needed to support the output voltage is:

V_{IN, MIN}= I_LOAD* (R_{DSON, PFET}+ R_INDUCTOR) + V_OUT

Where:

I_LOAD

Load current

R_{DSON, PFET}

Drain to source resistance of

PFET switch in the triode region

R_INDUCTOR

Inductor resistance

FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES

The LP3906 provides several options for power on sequencing. The two bucks can be individually controlled with

ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power on sequence, all four enables should be tied LOW so that the regulators don’t

automatically enable when power is supplied. The user can then program the chip through I²C and raise EN_T

from LOW to HIGH to activate the power on sequencing.

POWER ON

EN_T assertion causes the LP3906 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks are internally pulled up, which causes the part to turn

ON automatically. If the user wishes to have a preset timing sequence to power on the regulators, the external

regulator enables must be tied LOW. Otherwise, simply tie the enables of each specific regulator HIGH.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the

default is set at 1 ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power on sequence, while

a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators will have no effect on the chip.

Table 3. Default Power ON Sequence:

t₁(ms)

t₂(ms)

t₃(ms)

t₄(ms)

1.5

2.0

3

6

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NOTE

LP3906 The default Power on delays can be reprogrammed at final test or by using I²C

registers to 1, 1.5, 2, 3, 6, or 11 ms.

The regulators can also be programmed through I²C to turn on and off. By default, the I²C enables for the

regulators are ON.

The regulators are on following the pattern below:

Regulators on = (I²C enable) AND (External pin enable OR EN_T high).

NOTE

The EN_T power-up sequencing may also be employed immediately after V_INis applied to

the device. However, V_INmust be stable for approximately 8ms minimum before EN_T be

asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power-on for

power sequencing function to operate properly.

2

I C

Regulator ON

EN_T

Ext Enable

Pins

LP3906 Default Power-Up Sequence

EN_T

t

1

Vout Buck1

Vout Buck2

t

2

t

3

Vout LDO1

Vout LDO2

t

4

Table 4. Power-On Timing Specification

Symbol

t₁

Description

Min

Typ

1.5

2

Max

Units

ms

Programmable Delay from EN_T assertion to V_CC_Buck1 On

Programmable Delay from EN_T assertion to V_CC_Buck2 On

Programmable Delay from EN_T assertion to V_CC_LDO1 On

Programmable Delay from EN_T assertion to V_CC_LDO2 On

t₂

t₃

t₄

ms

3

ms

6

ms

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NOTE

LP3906 The default Power on delays can be reprogrammed at final test or I²C to 1, 1.5, 2,

3, 6, or 11 ms.

LP3906 Default Power-Off Sequence

EN_T

Vout Buck1

t

1

Vout Buck2

Vout LDO1

t

2

t

3

Vout LDO2

t

4

Symbol

Description

Min

Typ

1.5

2

Max

Units

ms

t₁

t₂

t₃

t₄

Programmable Delay from EN_T deassertion to V_CC_Buck1 Off

Programmable Delay from EN_T deassertion to V_CC_Buck2 Off

Programmable Delay from EN_T deassertion to V_CC_LDO1 Off

Programmable Delay from EN_T deassertion to V_CC_LDO2 Off

ms

3

ms

6

ms

NOTE

LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or

10 ms. Default setting is the same as the on sequence.

Power-On-Reset

The LP3906 is equipped with an internal Power-On-Reset (“POR”) circuit that will reset the logic when VDD <

V_POR. This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of

the Logic and the internal oscillator that clocks the Sequential Logic in the Control section.

I²C Compatible Serial Interface

I²C SIGNALS

The LP3906 features an I²C compatible serial interface, using two dedicated pins: SCL and SDA for I²C clock

and data respectively. Both signals need a pull-up resistor according to the I²C specification. The LP3906

interface is an I²C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400 kbit/s. See

I²C specification from Philips for further details.

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I²C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the

data line can only be changed when CLK is LOW.

SCL

SDA

data

valid

data

valid

data

change

allowed

change

allowed

change

allowed

Figure 34. I²C Signals: Data Validity

I²C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while the SCL is HIGH. The I2C master always generates START and STOP

bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

SDA

SCL

S

P

START condition

STOP condition

Figure 35. START and STOP Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgement. A receiver which has been

addressed must generate an acknowledgement (“ACK”) after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). Please note that according to industry I2C standards for 7-bit

addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most

significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte

selects the register to which the data will be written. The third byte contains data to write to the selected register.

LP3906 has a chip address of 60’h, which is factory programmed.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

bit7

bit6

bit5

bit4

bit3

bit2

bit1

1

0

I²C SLAVE address (chip address)

Figure 36. I²C Chip Address

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ack from slave

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ack from slave

start msb Chip Address lsb

w

ack msb Register Add lsb ack msb

DATA

lsb ack stop

SCL

SDA

1

3 4 5 6

2

7

8

9

1 2 3 ...

start

id = h‘60

w

ack

addr = h‘02

ack

address h‘AA data

ack stop

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP3906 chip address : 0x60

Figure 37. I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

ack from slave

ack from slave repeated start

ack from slave data from slave ack from master

start msb Chip Address lsb

w

ack msb Register Add lsb ack rs

msb Chip Address lsb

r

ack msb

DATA

lsb ack stop

.

SCL

SDA

start

id = h‘60

w

ack

register addr = h‘10

ack rs

id = h‘60

r

ack

data addr h‘6A

ack stop

Figure 38. I²C Read Cycle

LP3906 Control Registers

Register Address Register Name

Read/Write

R

Register Description

0x02

0x07

0x10

0x11

0x20

0x23

0x24

0x25

0x29

0x2A

0x2B

0x38

0x39

0x3A

ICRA

SCR1

Interrupt Status Register A

System Control 1 Register

R/W

R

BKLDOEN

BKLDOSR

VCCR

Buck and LDO Output Voltage Enable Register

Buck and LDO Output Voltage Status Register

Voltage Change Control Register 1

Buck 1 Target Voltage 1 Register

Buck 1 Target Voltage 2 Register

Buck 1 Ramp Control

R/W

B1TV1

B1TV2

B1RC

B2TV1

Buck 2 Target Voltage 1 Register

Buck 2 Target Voltage 2 Register

Buck 2 Ramp Control

B2TV2

B2RC

BFCR

Buck Function Register

LDO1VCR

LDO2VCR

LDO1 Voltage control Registers

LDO2 Voltage control Registers

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INTERRUPT STATUS REGISTER (ISRA) 0X02

This register informs the user of the temperature status of the chip.

D7-2

—

D1

D0

—

Name

Access

Data

Temp 125°C

R

—

Reserved

Status bit for thermal warning PMIC T>125°C

0 – PMIC Temp. < 125°C

Reserved

1 – PMIC Temp. > 125°C

Reset

0

CONTROL 1 REGISTER (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through

assertion of the EN_T pin.

D7

D6-4

D3

D2

D1

D0

Name

Access

Data

—

EN_DLY

R/W

—

FPWM2

R/W

FPWM1

R/W

ECEN

R/W

—

Reserved

Selects the preset

delay sequence from

EN_T assertion

Reserved

Buck 2 PWM /PFM

Mode select

0 – Auto Switch PFM -

PWM operation

Buck 1 PWM /PFM

Mode select

0 – Auto Switch PFM -

PWM operation

External Buck Clock

Select

0 – Internal 2 MHz

Oscillator clock

1 – External 13 MHz

Oscillator clock

(shown below)

1 – PWM Mode Only

Reset

0

010

1

0

EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION

Delay (ms)

EN_DLY<2:0>

Buck1

1

Buck2

LDO1

LDO2

000

001

010

011

100

101

110

111

1

1.5

2

1

2

3

1

3

2

1

6

1

2

1

1.5

3

6

2

1

2

6

1.5

2

1.5

11

2

3

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

D7

D6

D5

D4

D3

D2

D1

—

D0

Name

Access

Data

—

LDO2EN

R/W

—

LDO1EN

R/W

—

BK2EN

R/W

BK1EN

R/W

—

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reset

0

1

0

1

0

1

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BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7

D6

D5

D4

D3

—

D2

D1

—

D0

Name

Access

Data

BKS_OK

R

LDOS_OK

R

LDO2_OK

R

LDO1_OK

R

BK2_OK

R

BK1_OK

R

0 – Buck 1-2

Not Valid

0 – LDO 1-2

Not Valid

0 – LDO2 Not

Valid

0 – LDO1 Not

Valid

Reserve 0 – Buck2 Not

Reserve 0 – Buck1 Not

d

Valid

d

Valid

1 – Bucks Valid 1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid

1 – Buck2 Valid

1 – Buck1 Valid

Reset

0

BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20

This register selects and controls the output target voltages for the buck regulators.

D7-6

—

D5

D4

D3-2

—

D1

D0

Name

Access

Data

B2VS

R/W

B2GO

R/W

B1VS

R/W

B1GO

R/W

—

Reserved

Buck2 Target Voltage

Select

Buck2 Voltage Ramp

CTRL

Reserved

Buck1 Target Voltage

Select

Buck1 Voltage Ramp

CTRL

0 – B2VT1

0 – Hold

0 – B1VT1

0 – Hold

1 – B2VT2

1 – Ramp to B2VS

selection

1 – B1VT2

1 – Ramp to B1VS

selection

Reset

00

0

00

0

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BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23

This register allows the user to program the output target voltage of Buck 1.

D7-5

D4-0

BK1_VOUT1

Name

Access

Data

—

R/W

Reserved

Buck1 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

Factory Programmed Default

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BUCK 1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24

This register allows the user to program the output target voltage of Buck 1.

D7-5

D4-0

Name

Access

Data

—

BK1_VOUT2

R/W

Reserved

Buck1 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

Factory Programmed Default

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BUCK 1 RAMP CONTROL REGISTER (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck 1.

D7

- - - -

D6-4

- - - -

D3-0

B1RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

30

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BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29

This register allows the user to program the output target voltage of Buck 2.

D7-5

D4-0

Name

Access

Data

—

BK2_VOUT1

R/W

Reserved

Buck2 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory Programmed Default

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BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A

This register allows the user to program the output target voltage of Buck 2.

D7-5

D4-0

BK2_VOUT2

Name

Access

Data

—

R/W

Reserved

Buck2 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory Programmed Default

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BUCK 2 RAMP CONTROL REGISTER (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck 2

D7

- - - -

D6-4

- - - -

D3-0

B2RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

BUCK FUNCTION REGISTER (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less

Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the

frequency ramps up and down, centered at 2 MHz.

Spread Spectrum

frequency

Peak frequency deviation

2 kHz triangle

wave

10 kHz triangle

wave

2 MHz

Time

D7-2

—

D1

D0

Name

Access

Data

BK_SLOMOD

R/W

BK_SSEN

R/W

—

Reserved

Buck Spread Spectrum Modulation

0 – 10 kHz triangular wave

1 – 2 kHz triangular wave

Spread Spectrum Function Output

0 – Disabled

1 – Enabled

Reset

000010

1

0

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LDO1 CONTROL REGISTER (LDO1VCR) – 0X39

This register allows the user to program the output target voltage of LDO 1.

D7-5

D4-0

LDO1_OUT

Name

Access

Data

—

R/W

Reserved

LDO1 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory Programmed Default

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LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A

This register allows the user to program the output target voltage of LDO 2.

D7-5

D4-0

Name

Access

Data

—

LDO2_OUT

R/W

Reserved

LDO2 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory Programmed Default

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APPLICATION NOTES

SYSTEM CLOCK INPUT (SYNC) PIN

Pin 23 of the chip allows for a system clock input in order to synchronize the buck converters in PWM mode. This

is useful if the user wishes to force the bucks to work synchronously with the system. Otherwise, the user should

tie the pin to GND and the bucks will operate on an internal 2 MHz clock.

The signal applied to the SYNC pin must be 13 MHz as per application processor specifications, but we can be

contacted to modify that specification if so desired. Upon inputting the 13 MHz clock signal, the bucks will scale it

down and continue to run at 2 MHz based off the 13 MHz clock.

ANALOG POWER SIGNAL ROUTING

All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from

another source. (i.e. external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.7 and 5.5 V, as specified on pg. 6 of the datasheet.

The other V_INs (V_INLDO1, V_INLDO2, V_IN1, V_IN2) can actually have inputs lower than 2.7V, as long as it's higher

than the programmed output (+0.3V, to be safe).

The analog and digital grounds should be tied together outside of the chip to reduce noise coupling.

COMPONENT SELECTION

Inductors for SW1 and SW2

There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing

the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are

typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested

from the manufacturer.

There are two methods to choose the inductor saturation current rating:

Method 1

The saturation current is greater than the sum of the maximum load current and the worst case average to peak

inductor current. This can be written as follows:

I_sat> I_outmax+ I_ripple

V_IN- V_OUT

2L

’ _x≈^V^OUT

’

◊

1

≈ ’ ≈

x

where

I_ripple

⁼« _f◊ «

V

◊ «

IN

(5)

I_RIPPLE: Average to peak inductor current

I_OUTMAX: Maximum load current

V_IN: Maximum input voltage to the buck

L:

f:

Min inductor value including worse case tolerances (30% drop can be considered for method 1)

Minimum switching frequency (1.6 MHz)

V_OUT: Buck Output voltage

Method 2

A more conservative and recommended approach is to choose an inductor that has saturation current rating

greater than the maximum current limit of 2375 mA.

Given a peak-to-peak current ripple (I_PP) the inductor needs to be at least:

36

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’ _x≈^V^OUT’ ≈ ’

V_IN- V_OUT

I_PP

1

≈

«

◊ ^x« _f◊

L í

V

IN

◊ «

(6)

Inductor

Value

Unit

Description

SW1,2 inductor

Notes

D.C.R. 70 mΩ

L_SW1,2

2.2

µH

External Capacitors

The regulators on the LP3906 require external capacitors for regulator stability. These are specifically designed

for portable applications requiring minimum board space and smallest components. These capacitors must be

correctly selected for good performance.

LDO CAPACITOR SELECTION

Input Capacitor

An input capacitor is required for stability. It is recommended that a 1.0 μF capacitor be connected between the

LDO input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low

impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,

it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain

approximately 1.0 μF over the entire operating temperature range.

Output Capacitor

The LDOs on the LP3906 are designed specifically to work with very small ceramic output capacitors. A 1.0 µF

ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the

application circuit.

It is also possible to use tantalum or film capacitors at the device output, C_OUT(or V_OUT), but these are not as

attractive for reasons of size and cost.

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩ to 500 mΩ for stability.

Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least

expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The

ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR

requirement for stability for the LDOs.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, the graph below shows a typical graph comparing different

capacitor case sizes in a Capacitance vs. DC Bias plot.

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0603, 10V, X5R

100%

80%

60%

40%

20%

0402, 6.3V, X5R

0

1.0

2.0

3.0

4.0

5.0

DC BIAS (V)

Figure 39. Graph Showing a Typical Variation in Capacitance vs. DC Bias

As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the

minimum value given in the recommended capacitor specifications table. Note that the graph shows the

capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended

that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R

has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic

capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance

can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over

Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

Input Capacitor Selection for SW1 and SW2

A ceramic input capacitor of 10 µF, 6.3V is sufficient for the magnetic dc/dc converters. Place the input capacitor

as close as possible to the input of the device. A large value may be used for improved input voltage filtering.

The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The

input filter capacitor supplies current to the PFET switch of the dc/dc converter in the first half of each cycle and

reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent Series

Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor

with sufficient ripple current rating should be selected. The Input current ripple can be calculated as:

r²

V_OUT

V_IN

V_OUT

V_IN

≈

’

◊

I_rms= I_outmax

1 -

+

«

12

(V_inœ V_out) x V_out

where

r =

L x f x I_outmaxx V_in

(7)

The worse case is when V_IN= 2V_OUT

38

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SNVS456M –AUGUST 2006–REVISED MAY 2013

Output Capacitor Selection for SW1, SW2

A 10 µF, 6.3V ceramic capacitor should be used on the output of the sw1 and sw2 magnetic dc/dc converters.

The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be

used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type

capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias

curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic dc/dc converter smoothes out current flow from the inductor to the

load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these

functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

I_ripple

V_pp-c

=

4 x f x C

(8)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

V_PP–ESR= 2 × I_RIPPLE× R_ESR

(9)

Because the V_PP-Cand V_PP-ESRare out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

V_pp-c²+ V_pp-esr

2

V_pp-rms

=

(10)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (R_ESR). The R_ESRis frequency dependent as well as temperature dependent.

The R_ESRshould be calculated with the applicable switching frequency and ambient temperature.

Capacitor

Min Value

0.47

Unit

µF

Description

LDO1 output capacitor

LDO2 output capacitor

SW1 output capacitor

SW2 output capacitor

Recommended Type

Ceramic, 6.3V, X5R

C_LDO1

C_LDO2

C_SW1

C_SW2

0.47

µF

Ceramic, 6.3V, X5R

10.0

µF

10.0

µF

I²C Pullup Resistor

Both I²C_SDA and I²C_SCL terminals need to have pullup resistors connected to VINLDO12 or to the power

supply of the I²C master. The values of the pull-up resistors (typ. ∼1.8kΩ) are determined by the capacitance of

the bus. Too large of a resistor combined with a given bus capacitance will result in a rise time that would violate

the max. rise time specification. A too small resistor will result in a contention with the pull-down transistor on

either slave(s) or master.

Operation without I²C Interface

Operation of the LP3906 without the I²C interface is possible if the system can operate with default values for the

LDO and Buck regulators. (See Factory Programmable Options .) The I²C-less system must rely on the correct

default output values of the LDO and Buck converters.

Factory Programmable Options

The following options are EPROM programmed during final test of the LP3906. The system designer that needs

specific options is advised to contact the local Texas Instruments sales office.

Factory programmable options

Enable delay for power on

SW1 ramp speed

Current value

code 010 (see BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20)

8 mV/µs

SW2 ramp speed

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SNVS456M –AUGUST 2006–REVISED MAY 2013

www.ti.com

The I²C Chip ID address is offered as a metal mask option. The current value equals 0x60.

MODE BOUNCE

PFM-PWM transition at low load current.

To improve efficiency at lower load currents LP3906 buck converters employ an automatically invoked PFM

mode for the low load operation. The PFM mode operates with a much lower value quiescent current (I_Q) than

the PWM mode of operation that is used in the higher load currents.

As shown in the datasheet section about SW operation, there is a DC voltage difference between the two modes

of operation, with Vout PFM being typically 1.2% higher than Vout PWM. So there is a DC voltage level transition

and some associated dynamic perturbation at the mode transition point.

The transition between the two modes of operation has an associated hysterisis in the transition current value,

That is, the transition point for increasing current (PFM to PWM) is at a higher value that the decreasing current

(PWM to PFM). This hysterisis is to ensure that in the event that the load current values equals the PFM PWM

transition value, the device will not make multiple transitions between modes; this reduces the noise at this load

by eliminating multiple transitions between modes (also known as mode bounce).

Under some conditions of high Vin and Low Vout the hystersis value is reduced and some amount of mode

bounce can occur. Under these conditions, the regulator still maintains DC regulation, however the output ripple

is more pronounced. Refer to the attached Vout vs Vin chart below that shows the operational area that may

exhibit this increased output ripple. If the application is expected to be operated in the area of concern AND have

a static load current of the transition current value, the user can avoid the possible noise increase by invoking the

components’ “Force PWM mode”.

3.5

3.0

2.5

2.0

1.5

1.0

0

5.0

3.5

4.0

4.5

(V)

5.5

V

IN

Figure 40. LP3906 Buck Converter

V_OUTvs V_INOperating Range

during PFM-PWM-PPM Transition

40

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SNVS456M –AUGUST 2006–REVISED MAY 2013

REVISION HISTORY

Changes from Revision L (May 2013) to Revision M

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 40

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41

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PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3906SQ-DJXI/NOPB

LP3906SQ-FXPI/NOPB

LP3906SQ-JXXI/NOPB

WQFN

NHZ

24

1000

250

178.0

330.0

12.4

4.3

5.3

1.3

8.0

12.0

Q1

LP3906SQ-PPXP/NOPB WQFN

LP3906SQ-TKXII/NOPB WQFN

LP3906SQ-VPFP/NOPB WQFN

LP3906SQE-PPXP/NOPB WQFN

LP3906SQE-VPFP/NOPB WQFN

LP3906SQX-DJXI/NOPB WQFN

LP3906SQX-FXPI/NOPB WQFN

LP3906SQX-JXXI/NOPB WQFN

LP3906SQX-PPXP/NOPB WQFN

LP3906SQX-TKXII/NOPB WQFN

LP3906SQX-VPFP/NOPB WQFN

250

4500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3906SQ-DJXI/NOPB

LP3906SQ-FXPI/NOPB

LP3906SQ-JXXI/NOPB

LP3906SQ-PPXP/NOPB

LP3906SQ-TKXII/NOPB

LP3906SQ-VPFP/NOPB

LP3906SQE-PPXP/NOPB

LP3906SQE-VPFP/NOPB

LP3906SQX-DJXI/NOPB

LP3906SQX-FXPI/NOPB

LP3906SQX-JXXI/NOPB

LP3906SQX-PPXP/NOPB

LP3906SQX-TKXII/NOPB

LP3906SQX-VPFP/NOPB

WQFN

NHZ

24

1000

250

210.0

367.0

185.0

367.0

35.0

250

4500

Pack Materials-Page 2

MECHANICAL DATA

NHZ0024B

SQA24B (Rev A)

www.ti.com

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型号：	LP3906SQ-VPFP/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有 I2C 兼容接口的双路高电流降压直流/直流和双路线性稳压器 \| NHZ \| 24 \| -40 to 85 开关控制器开关式稳压器开关式控制器电源电路开关式稳压器或控制器
文件：	总47页 (文件大小：3088K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP3906SQ-VPFP/NOPB [TI]

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