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LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

LP3907 双路1 A 和600 mA 降压转换器和双路300 mA LDO 具有 I2C 接口

1 特性

3 说明

1

•

输入电压范围：2.8V 至 5.5V

LP3907 器件是专为低功耗 FPGA、微处理器和 DSP

优化的多功能、可编程电源管理单元 (PMU)。该器件

集成了两个具有动态电压调节 (DVS) 功能的高效 1A、

600mA 降压直流/直流转换器、两个 300mA 线性稳压

器和一个 400kHz I²C 接口，使主机控制器可以访问该

器件的内部控制寄存器。LP3907 还具有可编程的加

电序列。

兼容高级应用处理器和现场可编程门阵列 (FPGA)

2 个低压降线性稳压器 (LDO)，用于为内部处理器

的运行和 I/O 供电

•

高速串行接口用于对器件功能和设置进行独立控制

精密的内部基准电压

热过载保护

电流过载保护

具备诸多功能，其中包括可编程的加电序列、通信控

制 (I2C)、动态电压调节、过流保护、电源正常指示、

同步整流、热关断以及欠压锁定。对于需要轻负载的

应用，此款高效同步开关降压稳压器可进入 PFM 模

式，以较低的开关频率和电源电流运行，从而在极轻负

载下保持高效率。

软件可编程稳压器

针对 Buck1 和 Buck2 的外部上电复位功能（带延

迟功能的电源正常指示）

•

配有欠压闭锁检测器，用于监视输入电源电压

降压直流/直流转换器（降压）

–

可编程 V_OUT：

器件信息⁽¹⁾

–

Buck1：1A 时为 0.8V 至 2V

器件型号

LP3907

封装

WQFN (24)

DSBGA (25)

封装尺寸（标称值）

4.00mm x 4.00mm

2.49mm × 2.49mm

Buck2：600mA 时为 1V 至 3.5V

–

效率高达 96%

2.1MHz 脉冲宽度调制 (PWM) 开关频率

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

低负载条件下

从 PWM 模式自动切换到脉冲频率调制 (PFM)

模式

典型应用电路

–

±3% 的输出电压精度

VINLDO12

EN_T

自动软启动

VDD

100k

1 mF

ENLDO1

ENLDO2

•

线性稳压器 (LDO)

nPOR

VIN1

–

可编程 V_OUT1V 至 3.5V

（JJ11、FX6W 和 JX6X 选项除外）

ENSW1

ENSW2

LDO1

10 mF

2.2 mH

–

300mA 输出电流

SW1

FB1

30mV（典型值）压降

使用 LP3907 并借助 WEBENCH^®电源设计器

创建定制设计方案

10 mF

0.47 mF

VINLDO1

VINLDO2

LDO2

GND_SW1

1 mF

LP3907

VIN2

2 应用

10 mF

•

现场可编程门阵列 (FPGA)，数字信号处理器

2.2 mH

0.47 mF

SW2

FB2

(DSP) 内核电源

SDA

SCL

10 mF

•

应用处理器

GND_SW2

AVDD

外设 I/O 电源

助听器

GND_L

GND_C

DAP

电子测量装置

备用电池供电型设备

1 mF

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVS511

LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 19

8.3 Feature Description................................................. 20

8.4 Device Functional Modes........................................ 28

8.5 Programming .......................................................... 29

8.6 Register Maps ........................................................ 32

Application and Implementation ........................ 42

9.1 Application Information............................................ 42

9.2 Typical Application ................................................. 42

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

器件比较台式机....................................................... 4

Pin Configuration and Functions......................... 6

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions (Bucks).......... 8

7.4 Thermal Information.................................................. 9

7.5 General Electrical Characteristics............................ 9

7.6 Low Dropout Regulators, LDO1 And LDO2........... 10

7.7 Buck Converters SW1, SW2.................................. 10

7.8 I/O Electrical Characteristics.................................. 11

7.9 Power-On Reset (POR) Threshold/Function ........ 11

7.10 I²C Interface Timing Requirements ..................... 11

7.11 Typical Characteristics — LDO............................. 12

7.12 Typical Characteristics — Bucks .......................... 14

7.13 Typical Characteristics — Buck1 .......................... 15

7.14 Typical Characteristics — Buck2 .......................... 16

7.15 Typical Characteristics — Bucks .......................... 17

Detailed Description ............................................ 19

8.1 Overview ................................................................. 19

9

10 Power Supply Recommendations ..................... 48

10.1 Analog Power Signal Routing ............................... 48

11 Layout................................................................... 49

11.1 DSBGA Layout Guidelines.................................... 49

11.2 Layout Example .................................................... 50

11.3 Thermal Considerations of WQFN Package......... 50

12 器件和文档支持 ..................................................... 51

12.1 器件支持................................................................ 51

12.2 文档支持................................................................ 51

12.3 商标....................................................................... 51

12.4 接收文档更新通知 ................................................. 51

12.5 社区资源................................................................ 51

12.6 静电放电警告......................................................... 51

12.7 Glossary................................................................ 51

13 机械、封装和可订购信息....................................... 52

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision T (November 2016) to Revision U

Page

•

已添加 Webench 链接 ............................................................................................................................................................ 1

已删除删除已过时的 OPN 表 3 ............................................................................................................................................. 5

Changes from Revision S (April 2016) to Revision T

Page

•

已更改更改了改进的 SEO 的数据表标题，将动态电压“管理”更改为“调节”，向“说明”中添加了新段落.................................. 1

Changes from Revision R (May 2015) to Revision S

Page

•

已添加将附加条目添加至应用 .............................................................................................................................................. 1

Changed symbol "θn" to "e_N" in Low Dropout Regulators, LDO1 And LDO2 Electrical Char table ..................................... 10

Changes from Revision Q (January 2015) to Revision R

Page

•

Added last sentence to "NOTE" .......................................................................................................................................... 23

Changes from Revision P (November 2014) to Revision Q

Page

•

已更改将更新的附加值更改至新的默认器件选项 ................................................................................................................... 4

Changed Handling Ratings table to ESD Ratings table; update Thermal Information........................................................... 8

2

LP3907

www.ti.com.cn

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

Changes from Revision O (May 2013) to Revision P

Page

•

已添加器件信息表和处理额定值表，特性描述，器件功能模式，应用和实施，电源相关建议，布局，器件和文档支持

以及机械、封装和可订购信息部分；已将一些曲线移至应用曲线部分。 ................................................................................ 1

3

LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

www.ti.com.cn

5 器件比较台式机

表 1. 默认 I²C 地址

封装类型

默认 I²C 地址

24 引线 WQFN

25 凸点 DSBGA

60

61

表 2. 电源块

电源块运行

禁用

电源块输入

注释

启用

VIN+⁽¹⁾

VIN+

VINLDO12

AVDD

VIN1

VIN+

始终供电

VIN+

VIN2

VIN+

LDO1

≤ VIN+

如果启用，V_IN最小值为 1.74V

LDO2

(1) VIN+ 是设备支持的最大电压。

4

LP3907

www.ti.com.cn

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

表 3. 默认器件选项

部件号⁽¹⁾⁽²⁾

BUCK1

1.2V

1V

BUCK2

3.3V

1.8V

2.8V

1.8V

2.2V

LDO1

1.8V

LDO2

2.5V

降压模式

强制 PWM

自动模式

强制 PWM

自动模式

强制 PWM

默认 EN_T 延迟

默认 UVLO

启用

LP3907SQ-TJXIP/NOPB

LP3907SQ-JXQX/NOPB

LP3907SQ-PJXIX/NOPB

LP3907SQ-PFX6W/NOPB

LP3907SQ-BJXQX/NOPB

LP3907TL-JJ11/NOPB

LP3907TLX-JJ11/NOPB

LP3907TL-JSXS/NOPB

LP3907TL-JJCP/NOPB

LP3907TL-PLNTO/NOPB

001

010

2.6V

3.3V

启用

1.8V

2.65V⁽³⁾

3.3V

启用

3.2V

启用

1.2V

1.3V

2.6V

3.3V

禁用

2.85V⁽³⁾

3.3V

2.85V⁽³⁾

2.8V

启用

1.2V

2.5V

启用

2.9V

2.4V

启用

(1) 要获得最新的封装和订购信息，请参见本文档末尾的封装选项附录，或者浏览 TI 网站 www.ti.com.cn。

(2) 封装图样、散热数据和符号可从网站 www.ti.com/packaging 中获取。

(3) 电压为固定值，不可编程。

5

LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

www.ti.com.cn

6 Pin Configuration and Functions

RTW Package

24-Pin WQFN

Top View

18

17

16

15

14

13

1

2

3

4

5

6

YZR Package

25-Pin DSBGA

Top View

VIN

LDO12

VIN

LDO2

GND_S

W1

5

SW1

VIN1

VIN

LDO12

EN_S

W1

4

EN_T

FB1

AVDD

FB2

LDO2

EN_

LDO2

EN_

LDO1

GND_C

nPOR

SDA

3

EN_

SW2

SCL

LDO1

2

1

VIN

LDO1

GND_

SW2

GND_

L

SW2

D

VIN2

E

A

B

C

6

LP3907

www.ti.com.cn

WQFN

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

Pin Functions

I/O

TYPE⁽¹⁾

DESCRIPTION

DSBGA

NAME

NUMBER NUMBER

1

2

B4, B5

C4

VINLDO12

EN_T

I

PWR

D

Analog power for internal functions (VREF, BIAS, I²C, Logic)

Enable for preset power on sequence. (See .)

nPOR power on reset pin for both Buck1 and Buck 2. Open drain logic

output 100-kΩ pullup resistor. nPOR is pulled to ground when the voltages

on these supplies are not good. See Flexible Power-On Reset (Power Good

with Delay) section for more info.

3

C3

nPOR

O

D

4

C5

D5

E5

D4

E4

D3

E3

E2

D2

E1

D1

C1

C2

B2

B1

A1

A2

B3

A3

A4

A5

GND_SW1

SW1

G

PWR

D

Buck1 NMOS Power Ground

5

O

Buck1 switcher output pin

6

VIN1

I

Power in from either DC source or battery to Buck1

Enable pin for Buck1 switcher, a logic HIGH enables Buck1

Buck1 input feedback terminal

7

ENSW1

FB1

I

8

I

A

9

GND_C

AVDD

FB2

G

Non switching core ground pin

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DAP

I

PWR

A

Analog power for Buck converters

Buck2 input feedback terminal

I

ENSW2

VIN2

I

D

Enable pin for Buck2 switcher, a logic HIGH enables Buck2

Power in from either DC source or Battery to Buck2

Buck2 switcher output pin

I

PWR

G

SW2

O

GND_SW2

SDA

G

Buck2 NMOS power ground

I²C cata (bidirectional)

I²C clock

I/O

D

SCL

I

D

GND_L

VINLDO1

LDO1

G

LDO ground

I

PWR

D

Power in from either DC source or battery to input terminal to LDO1

LDO1 output

O

ENLDO1

ENLDO2

LDO2

I

LDO1 enable pin, a logic HIGH enables the LDO1

LDO2 enable pin, a logic HIGH enables the LDO2

LDO2 output

I

O

D

PWR

GND

VINLDO2

DAP

I

Power in from either DC source or battery to input terminal to LDO2.

GND

Connection is not necessary for electrical performance, but it is

recommended for better thermal dissipation.

(1) A: Analog Pin

D: Digital Pin

G: Ground Pin

PWR: Power Pin

I: Input Pin

I/O: Input/Output Pin

O: Output Pin.

7

LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN

MAX

6

UNIT

V

V_IN, SDA, SCL

–0.3

GND to GND SLUG

±0.3

1.43

0.78

150

260

150

V

Power dissipation (WQFN (RTW))(P_{D_MAX}

Power dissipation (DSBGA (YZR))⁽³⁾(P_{D_MAX}

)

(T_A= 85°C, T_MAX= 125°C)⁽³⁾

(T_A= 85°C, T_MAX= 125°C)

W

)

W

Junction temperature, T_J-MAX

°C

Maximum lead temperature (soldering)

Storage temperature, T_stg

−65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions (Bucks). Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (R_θJA× P_D-MAX).

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions (Bucks)

over operating free-air temperature range (unless otherwise noted)^(1)(2)(3)(4)

MIN

MAX

UNIT

V_IN

2.8

0

5.5

(V_IN+ 0.3 V)

125

V

V_EN

Junction temperature, T_J

Ambient temperature, T_A

−40

°C

(5)

85

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) Minimum (Minimum) and Maximum (Maximum) limits are ensured by design, test, or statistical analysis. Typical numbers are not

ensured, but do represent the most likely norm.

(4) Buck V_IN≥ V_OUT+ 1 V.

(5) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

8

LP3907

www.ti.com.cn

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

7.4 Thermal Information

See^(1)(2)(3)

LP3907

THERMAL METRIC⁽⁴⁾

RTW

24 PINS

32.7

YZR

25 PINS

58.7

0.3

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

31.2

11.2

8.0

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

0.6

ψ_JB

11.2

8.0

R_θJC(bot)

1.4

N/A

(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

(2) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 160°C (typical) and

disengages at T_J= 140°C (typical).

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP− (R_θJA× P_D-MAX).

(4) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 General Electrical Characteristics

Unless otherwise noted, V_IN= 3.6 V and T_J= 25°C.^(1)(2)(3)(4)

PARAMETER

TEST CONDITIONS

MIN

TYP

3

MAX UNIT

I_Q

VINLDO12 shutdown current

Power-on reset threshold

Thermal shutdown threshold

Thermal shutdown hysteresis

V_IN= 3.6 V

µA

V

V_POR

T_SD

T_SDH

V_DDfalling edge⁽⁴⁾

1.9

160

20

°C

Rising

Falling

2.9

2.7

UVLO

Undervoltage lockout

V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the GND pin.

(3) This specification is ensured by design.

(4) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the

regulators shut off, and is also different from the nPOR function, which signals if the regulators are in a specified range.

9

LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

www.ti.com.cn

MAX UNIT

7.6 Low Dropout Regulators, LDO1 And LDO2

Unless otherwise noted, V_IN= 3.6 V, C_IN= 1 µF, C_OUT= 0.47 µF, and T_J= 25°C.^{(1)(2)(3)(4)(5)(6)(7)}

PARAMETER

TEST CONDITIONS

VINLDO1 and VINLDO2 PMOS pins⁽⁸⁾

Load current = 1 mA

MIN

1.74⁽⁹⁾

TYP

V_IN

Operational voltage range

5.5⁽⁹⁾

V

V_OUTAccuracy Output voltage accuracy (default

V_OUT

–3%⁽⁹⁾

3%⁽⁹⁾

)

Line regulation

V_IN= (V_OUT+ 0.3 V) to 5 V,

⁽⁷⁾, load current = 1 mA

0.15⁽⁹⁾

%/V

ΔV_OUT

Load regulation

V_IN= 3.6 V,

Load current = 1 mA to I_MAX

0.011⁽⁹⁾%/mA

mA

I_SC

Short circuit current limit

Dropout voltage

LDO1-2, V_OUT= 0 V

500

30

Load current = 50 mA

V_IN– V_OUT

200⁽⁹⁾

mV

(5)

PSRR

e_N

Power supply ripple rejection

Supply output noise

Quiescent current on

Quiescent current off

Turnon time

ƒ = 10 kHz, load current = I_MAX

10 Hz < F < 100 KHz

I_OUT= 0 mA

45

80

dB

µVrms

µA

40

(6) (10)

I_Q

I_OUT= I_MAX

EN is de-asserted⁽¹¹⁾

60

µA

0.03

300

µA

T_ON

Start-up from shutdown

µs

Capacitance for stability

0°C ≤ T_J≤ 125°C

0.33⁽⁹⁾

0.47

1

µF

C_OUT

Output capacitor

−40°C ≤ T_J≤ 125°C

0.68

5⁽⁹⁾

µF

ESR

500⁽⁹⁾

mΩ

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum (MIN) and maximum (MAX) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do

represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

.

(7) V_INminimum for line regulation values is 1.8 V.

(8) Pins 24, 19 can operate from V_INmin of 1.74 V to a V_INmax of 5.5 V. This rating is only for the series pass PMOS power FET. It allows

the system design to use a lower voltage rating if the input voltage comes from a buck output.

(9) Limits apply over the entire junction temperature range for operation, −40°C to +125°C.

(10) The I_Qcan be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled

with the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3907 is powered using a battery.

(11) The I_Qexhibits a higher current draw when the EN pin is de-asserted because the I²C buffer pins draw an additional 2 µA.

7.7 Buck Converters SW1, SW2

Unless otherwise noted, V_IN= 3.6 V, C_IN= 10 µF, C_OUT= 10 µF, L_OUT= 2.2-µH ceramic, and T_J= 25°C.^{(1)(2)(3)(4)(5)(6)}

PARAMETER

Feedback voltage

Line regulation

TEST CONDITIONS

MIN

–3%⁽⁷⁾

TYP

MAX

3%⁽⁷⁾

UNIT

V_FB

2.8 V < V_IN< 5.5 V

0.089

%/V

I_OUT= 10 mA

V_OUT

Load regulation

100 mA < I_OUT< I_MAX

Load current = 250 mA

EN is de-asserted

0.0013

96%

0.01

2.1

%/mA

Eff

Efficiency

I_SHDN

ƒ_OSC

Shutdown supply current

Internal oscillator frequency

µA

1.7⁽⁷⁾

MHz

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum (Min) and Maximum (Max) limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do

represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

.

(6) Buck V_IN≥ V_OUT+ 1 V.

(7) Limits apply over the entire junction temperature range for operation, −40°C to +125°C.

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Buck Converters SW1, SW2 (continued)

Unless otherwise noted, V_IN= 3.6 V, C_IN= 10 µF, C_OUT= 10 µF, L_OUT= 2.2-µH ceramic, and T_J= 25°C.^{(1)(2)(3)(4)(5)(6)}

PARAMETER

TEST CONDITIONS

MIN

TYP

1.5

1

MAX

UNIT

I_PEAK

Buck1 peak switching current limit

Buck2 peak switching current limit

Quiescent current “on”

Pin-pin resistance PFET

Pin-pin resistance NFET

Turnon time

A

(8)

I_Q

No load PFM mode

33

µA

mΩ

µs

R_DSON(P)

R_DSON(N)

T_ON

200

180

500

Start up from shutdown

Capacitance for stability

C_IN

Input capacitor

10

µF

C_OUT

Output capacitor

µF

(8) The I_Qcan be defined as the standing current of the LP3907 when the I²C bus is active and all other power blocks have been disabled

with the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the device is powered using a battery.

7.8 I/O Electrical Characteristics

Unless otherwise noted: Limits apply over the entire junction temperature range for operation, T_J= −40°C to +125°C.⁽¹⁾

PARAMETER

Input low level

Input high level

TEST CONDITIONS

MIN

MAX

UNIT

V_IL

V_IH

0.4

V

1.2

(1) This specification is ensured by design.

7.9 Power-On Reset (POR) Threshold/Function

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

nPOR

nPOR = Power on reset forBuck1 and Default

Buck2

50

ms

V_BUCK1AND V_BUCK2rising

94%

85%

0.23

nPOR

threshold

Percentage of target voltage Buck1

or Buck2

V_BUCK1OR V_BUCK2falling

Load = IoL = 500 mA

VOL

Output level low

0.5

V

7.10 I²C Interface Timing Requirements

Unless otherwise noted, V_IN= 3.6 V and T_J= 25°C.⁽¹⁾

MIN

NOM

MAX UNIT

ƒ_CLK

Clock frequency

400

kHz

µs

ns

µs

t_BF

Bus-free time between start and stop

Hold time repeated start condition

CLK low period

1.3

0.6

1.3

0.6

0

t_HOLD

t_CLKLP

t_CLKHP

t_SU

CLK high period

Set-up time repeated start condition

Data hold time

See⁽¹⁾

t_DATAHLD

t_DATASU

T_SU

Data set-up time

100

0.6

Set-up time for start condition

T_TRANS

Maximum pulse width of spikes that

must be suppressed by the input filter

of both DATA & CLK signals

50

ns

(1) This specification is ensured by design.

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7.11 Typical Characteristics — LDO

T_A= 25°C unless otherwise noted.

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C)

V_IN= 3.6 V

V_OUT= 2.6 V

100-mA Load

V_IN= 3.6 V

V_OUT= 2.6 V

100-mA Load

Figure 1. Output Voltage Change vs Temperature (LDO1)

Figure 2. Output Voltage Change vs Temperature (LDO2)

V_IN= 3.6 V

V_OUT= 2.6 V

0 to 150-mA Load

V_IN= 3.6 V

V_OUT= 3.3 V

0 to 150-mA Load

Figure 3. Load Transient (LDO1)

Figure 4. Load Transient (LDO2)

V_IN= 3.6 to 4.2 V

V_OUT= 2.6 V

300-mA Load

V_IN= 3.6 to 4.2 V

V_OUT= 3.3 V

300-mA Load

Figure 5. Line Transient (LDO1)

Figure 6. Line Transient (LDO2)

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Typical Characteristics — LDO (continued)

T_A= 25°C unless otherwise noted.

V_IN= 0 to 3.6 V

V_OUT= 2.6 V

1-mA Load

V_IN= 0 to 3.6 V

V_OUT= 3.3 V

1-mA Load

Figure 7. Enable Start-Up Time (LDO1)

Figure 8. Enable Start-Up Time (LDO2)

300

VIN = 1.74V

250

200

150

100

1.00 1.10 1.20 1.30 1.40 1.50 1.60

V_OUT(V)

V_IN= 1.74 V

Figure 9. LDO Maximum Load

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7.12 Typical Characteristics — Bucks

V_IN= 2.8 V to 5.5 V, T_A= 25°C

0.15

1.05

1.03

1.01

0.99

0.97

0.95

0.12

I

= 20 mA

OUT

I

= 750 mA

OUT

VIN = 5.5V

0.09

VIN = 3.6V

0.06

I

= 1.0A

OUT

VIN = 2.7V

0.03

0.00

-40

-20

0

20

40

60

80

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

V_OUT= 1 V

Figure 10. Shutdown Current vs. Temp

Figure 11. Output Voltage vs. Supply Voltage

1.85

3.35

1.83

1.81

1.79

1.77

1.75

3.33

I

= 20 mA

OUT

I

= 20 mA

OUT

I

= 300 mA

OUT

3.31

3.29

3.27

3.25

I

= 750 mA

OUT

I

= 600 mA

OUT

4.5

I

= 1.0A

4.4

OUT

2.7

3.3

3.8

4.9

4.0

5.0

5.5

SUPPLY VOLTAGE (V)

V_OUT= 1.8 V

Figure 12. Output Voltage vs. Supply Voltage

V_OUT= 3.5 V

Figure 13. Output Voltage vs. Supply Voltage

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7.13 Typical Characteristics — Buck1

V_IN= 2.8 V to 5.5 V, T_A= 25°C, V_OUT= 1.2 V, 2 V

100

90

100

90

80

70

60

50

40

30

20

10

80

V

IN

= 2.8V

V_IN

70

60

50

40

30

20

10

V

= 3.6V

IN

= 3.6V

V_IN

V

= 5.5V

IN

= 5.5V

V_IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

V_OUT= 1.2 V

L= 2.2 µH

V_OUT= 2V

L= 2.2 µH

Figure 14. Efficiency vs Output Current (Forced PWM Mode)

Figure 15. Efficiency vs Output Current (Forced PWM Mode)

100

90

= 2.8V

V_IN

V

= 2.8V

IN

80

70

60

50

40

80

70

60

50

40

= 3.6V

V_IN

V

= 3.6V

IN

= 5.5V

V_IN

V

= 5.5V

IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

V_OUT= 2 V

L= 2.2 µH

V_OUT= 1.2 V

L= 2.2 µH

Figure 17. Efficiency vs Output Current (PWM-to-PFM Mode)

Figure 16. Efficiency vs Output Current (PWM-to-PFM Mode)

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7.14 Typical Characteristics — Buck2

V_IN= 4.5 V to 5.5 V, T_A= 25°C, V_OUT= 1.8 V, 3.3 V

100

90

80

70

60

50

40

30

20

10

100

90

80

= 4.5V

V_IN

70

= 4.5V

V_IN

60

50

40

30

20

10

= 5.5V

V_IN

= 5.5V

V_IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

V_OUT= 1.8 V

L= 2.2 µH

V_OUT= 3.3 V

L= 2.2 µH

Figure 18. Efficiency vs Output Current (Forced PWM Mode)

Figure 19. Efficiency vs Output Current (Forced PWM

Mode)

100

90

= 4.5V

V_IN

= 5.5V

V_IN

= 4.5V

V_IN

80

70

60

50

40

80

70

60

50

40

= 5.5V

V_IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

V_OUT= 2 V

L= 2.2 µH

V_OUT= 1.2 V

L= 2.2 µH

Figure 21. Efficiency vs Output Current (PWM-to-PFM Mode)

Figure 20. Efficiency vs Output Current (PWM-to-PFM Mode)

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7.15 Typical Characteristics — Bucks

V_IN= 3.6 V, T_A= 25°C, V_OUT= 1.2 V unless otherwise noted.

V_OUT= 1.2 V

I_LOAD= 300 to 500 mA

V_OUT= 1.2 V

I_LOAD= 50 to 150 mA

Figure 22. Load Transient Response (PWM Mode)

Figure 23. Mode Change By Load Transient (PFM-to-PWM

Mode)

V_IN= 3.6 to 4.2 V

V_OUT= 1.2 V

250-mA Load

V_IN= 3.6 to 4.2 V

V_OUT= 3.3 V

250-mA Load

Figure 24. Line Transient Response

Figure 25. Line Transient Response

V_OUT= 1.2 V

1-A Load

V_OUT= 3.3 V

600-mA Load

Figure 26. Start-Up Into PWM Mode

Figure 27. Start-Up Into PWM Mode

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Typical Characteristics — Bucks (continued)

V_IN= 3.6 V, T_A= 25°C, V_OUT= 1.2 V unless otherwise noted.

V_OUT= 3.3 V

30-mA load

V_OUT= 1.2 V

30-mA Load

Figure 29. Start-Up Into PFM Mode

Figure 28. Start-Up Into PFM Mode

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8 Detailed Description

8.1 Overview

The LP3907 supplies the various power needs of the application by means of two linear low drop regulators

(LDO1 and LDO2) and two buck converters (SW1 and SW2). Table 4 lists the output characteristics of the

various regulators.

Table 4. Supply Specification

OUTPUT

(1)

SUPPLY

LOAD

I_MAX

V_OUTRANGE (V)

RESOLUTION (mV)

MAXIMUM OUTPUT CURRENT (mA)

LDO1

LDO2

SW1

analog

digital

1 to 3.5

0.8 to 2

1 to 3.5

100

50

300

1000

600

SW2

100

(1) For default values of the regulators, consult 表 3.

8.2 Functional Block Diagram

DC SOURCE

4.5V - 5.5V

+

Li-ion/polymer cell 3.3V - 4.2V

Cvdd

4.7mF

1mF

1uF

mF

10 mF

10

ULVO

Lsw1 2.2 mH

1.2V

OSC

VBUCK1

SW1

VFB1

10 mF

Vin OK

BUCK1

AVDD

ENLDO1

2.2 mH

Lsw1

3.3V

VBUCK2

ENLDO2

ENSW 1

Power

ON-OFF

Logic

SW2

VFB2

10 mF

BUCK2

AVDD

ENSW 2

EN_T

VINLDO1

Thermal

Shutdown

3.3V

LDO1

Cldo1

0.47 mF

RESET

VinLDO12

BIAS

VINLDO2

2

I

C_SCL

I²C

1.8V

LDO2

2

I

C_SDA

LDO2

Cldo2

0.47 mF

RDY1 RDY2

VDD

Logic Control

and

Registers

100k

nPOR

Power On

Reset

GND_SW1

GND_SW2

GND_C

GND_L

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8.3 Feature Description

8.3.1 DC-DC Converters

8.3.1.1 Linear Low Dropout Regulators (LDOs)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

register. The output voltages of both LDOs are register programmable. The default output voltages are factory

programmed during final test, which can be tailored to the specific needs of the system designer.

VLDO

VIN

LDO

Register

controlled

+

-

ENLDO

VREF

GND

Figure 30. LDO Block Diagram

8.3.1.2 No-Load Stability

The LDOs remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example, CMOS RAM keep-alive applications.

8.3.1.3 LDO and LDO2 Control Registers

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100 mV from 1 V to 3.5 V by programming bits D4-D0 in the LDO Control registers.

Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control

is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in

the register is logic 1 by default. The output voltage can be altered while the LDO is enabled.

8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters

8.3.2.1 Functional Description

The LP3907 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver

a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1000 mA and 600 mA,

respectively, depending on the input voltage and output voltage (voltage headroom), and the inductor chosen

(maximum current capability).

There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (I_Q= 15 µA typical) and a longer battery life. The standby operating mode turns off the device,

offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be

forced through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of

the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage.

Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload

protection.

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Feature Description (continued)

8.3.2.2 Circuit Operation Description

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of

V_IN- V_OUT

L

(1)

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET

switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor

draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor

current down with a slope of

-V_OUT

L

(2)

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

8.3.2.3 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input

voltage is introduced.

8.3.2.4 Internal Synchronous Rectification

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

8.3.2.5 Current Limiting

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 1.5 A for Buck1 and at 1 A for

Buck2 (typical). If the output is shorted to ground the device enters a timed current limit mode where the NFET is

turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has

more time to decay, thereby preventing runaway.

8.3.2.6 PFM Operation

At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply

current to maintain high efficiency.

The part automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or

more clock cycles:

A. The inductor current becomes discontinuous, or

B. The peak PMOS switch current drops below the I_MODElevel

V_IN

(Typically I_MODE< 66 mA +

)

160W

(3)

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Feature Description (continued)

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage with the feedback pin and control the switching of the

output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM

output voltage. If the output voltage is below the low PFM comparator threshold, the PMOS power switch is

turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds

the I_PFMlevel set for PFM mode. The typical peak current in PFM mode is:

V_IN

I_PFM= 66 mA +

80W

(4)

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the high PFM comparator threshold (see Figure 31), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the high PFM threshold,

the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are

turned off and the part enters an extremely low power mode. Quiescent supply current during this sleep mode is

less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When

the output drops below the low PFM threshold, the cycle repeats to restore the output voltage to approximately

1.6% above the nominal PWM output voltage.

If the load current increases during PFM mode (see Figure 31) causing the output voltage to fall below the ‘low2’

PFM threshold, the part automatically transitions into fixed-frequency PWM mode.

8.3.2.7 SW1, SW2 Operation

SW1 and SW2 have selectable output voltages ranging from 0.8 V to 3.5 V (typical). Both SW1 and SW2 in the

LP3907 are I²C register controlled and are enabled by default through the internal state machine of the device

following a power-on event that moves the operating mode to the Active state. (See Flexible Power Sequencing

of Multiple Power Supplies.) The SW1 and SW2 output voltages revert to default values when the power-on

sequence has been completed. The default output voltage for each buck converter is factory programmable.

(See Application and Implementation.)

8.3.2.8 SW1, SW2 Control Registers

SW1, SW2 can be enabled/disabled through the corresponding control register.

The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the

functional description. The modulation mode can be overridden by setting I²C bit to a logic 1 in the corresponding

buck control register, forcing the buck to operate in PWM mode regardless of the load condition.

High PFM Threshold

PFM Mode at Light Load

~1.016 * Vout

Load current

increases

Low1 PFM Threshold

~1.008 * Vout

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

High PFM

Voltage

Threshold

reached,

go into

Nfet on

drains

inductor

current

until

I inductor = 0

Low PFM

Threshold,

turn on

Pfet on

until

Ipfm limit

reached

PFET

Low2 PFM Threshold

Vout

sleep mode

PWM Mode at

Moderate to Heavy

Loads

Low2 PFM Threshold,

switch back to PWMmode

Figure 31. Operation in PFM Mode and Transfer to PWM Mode

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Feature Description (continued)

8.3.2.9 Soft Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing start-up stresses and surges. The two LP3907 buck converters have a soft-start circuit that limits in-

rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated

only if EN goes from logic low to logic high after V_INreaches 2.8V. Soft start is implemented by increasing switch

current limit in steps of 180 mA, 300 mA, and 720 mA for Buck1; 161 mA, 300 mA, and 536 mA for Buck2

(typical switch current limit). The start-up time thereby depends on the output capacitor and load current

demanded at start-up.

8.3.2.10 Low Dropout Operation

The LP3907 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support

of the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage. When

the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input

voltage needed to support the output voltage is:

V_{IN, MIN}= I_LOAD× (R_{DSON, PFET}+ R_INDUCTOR) + V_OUT

where

•

I_LOAD= Load current

R_{DSON, PFET}= Drain to source resistance of PFET switch in the triode region

R_INDUCTOR= Inductor resistance

(5)

8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies

The LP3907 provides several options for power on sequencing. The two bucks can be individually controlled with

ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power on sequence, the chip is programmable through I²C and raise EN_T from LOW to

HIGH to activate the power on sequencing.

8.3.2.12 Power-Up Sequencing Using the EN_T Function

EN_T assertion causes the LP3907 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are

500 KΩ internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the

preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply

tie the enables of each specific regulator HIGH to turn on automatically.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched, and the

default is set at 1 ms. As shown in Figure 32 and Figure 33, a rising EN_T edge starts a power-on sequence,

while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators has no effect on the chip.

The regulators can also be programmed through I²C to turn on and off. By default, I²C enables for the regulators

turned ON.

The regulators are on following the pattern below:

Regulators on = (I²C enable) AND (External pin enable OR EN_T high).

NOTE

The EN_T power-up sequencing may also be employed immediately after V_INis applied to

the device. However, V_INmust be stable for approximately 8 ms minimum before EN_T be

asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power on for

power sequencing function to operate properly. If the device is powered, the EN_T logic

must be stable for 12 ms minimum before switching state.

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Feature Description (continued)

2

I C

Regulator ON

Ext_Enable

Pins

0

1

Start Programmed

Timing Sequence

EN_T

Figure 32. Power Rail Enable Logic

EN_T

t

1

Vout Buck1

Vout Buck2

t

2

t

3

Vout LDO1

Vout LDO2

t

4

Figure 33. LP3907 Default Power-Up Sequence

Table 5. Power-On Timing Specification

DESCRIPTION

MIN

NOM

TYP

UNIT

ms

t₁

t₂

t₃

t₄

Programmable delay from EN_T assertion to V_CC_Buck1 On

Programmable delay from EN_T assertion to V_CC_Buck2 On

Programmable delay from EN_T assertion to V_CC_LDO1 On

Programmable delay from EN_T assertion to V_CC_LDO2 On

1.5

2

ms

3

ms

6

ms

EN_T

Vout Buck1

t

1

Vout Buck2

Vout LDO1

t

2

t

3

Vout LDO2

t

4

Figure 34. LP3907 Default Power-Off Sequence

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Table 6. Power-Off Timing Specification

DESCRIPTION

MIN

NOM

MAX

UNIT

ms

t₁

t₂

t₃

t₄

Programmable delay from EN_T deassertion to V_CC_Buck1 Off

Programmable delay from EN_T deassertion to V_CC_Buck2 Off

Programmable delay from EN_T deassertion to V_CC_LDO1 Off

Programmable delay from EN_T deassertion to V_CC_LDO2 Off

1.5

2

ms

3

ms

6

ms

8.3.3 Flexible Power-On Reset (Power Good with Delay)

The LP3907 is equipped with an internal power-on-reset (POR) circuit which monitors the output voltage levels

on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs

are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The time

delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by default.

The system designer can choose the external pullup resistor (that is, 100 kΩ) for the nPOR pin.

t2

t1

Case1

EN1

EN2

RDY1

RDY2

nPOR

0V

Counter

delay

t2

t1

Case2

EN1

EN2

RDY1

0V

RDY2

nPOR

Counter

delay

t2

t1

Case3

EN1

EN2

RDY1

RDY2

nPOR

Counter

delay

Figure 35. nPOR with Counter Delay

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Figure 35 shows the simplest application of the POR, where both switcher enables are tied together. In Case 1,

EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does

not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the vice versa

scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

Case 3 shows a typical application of the POR, where both switcher enables are tied together. Even if RDY1

ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay before

going HIGH, as explained below.

t0 t1

t2

t3

t4

EN1

RDY1

Counter

delay

Counter

delay

nPOR

EN2

RDY2

Figure 36. Faults Occurring in Counter Delay After Start-Up

Figure 36 details the power good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2

are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows:

COMPARATOR LEVEL

BUCK SUPPLY LEVEL

Greater than 94%

Less than 85%

HIGH

LOW

The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also

works for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay

counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is

then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this

interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

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t0 t1

t2

t3

t4

EN1

RDY1

nPOR

Counter

delay

Case 1:

EN2

RDY2

Mask Time

nPOR

Mask

Window

Counter

delay

Case 2:

EN2

RDY2

0V

Mask

Window

Mask Time

Counter

delay

nPOR

Figure 37. nPOR Mask Window

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained in

Figure 37.

Case 1 shows the case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the

nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. nPOR

is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on the status of

both RDY1 and RDY2 lines.

Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never

goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and RDY1,

and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW after the

masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

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Delay Mask Counter

EN1

RDY1

S

R

Q

EN2

nPOR

RDY2

Delay

POR

Delay Mask Counter

Figure 38. Design Implementation of the Flexible Power-On Reset

An internal power-on reset of the device is used with EN1, and EN2 to produce a reset signal (LOW) to the delay

timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S

= R = 1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to

generate outputs to the final AND gate to generate the nPOR.

8.3.4 Undervoltage Lockout

The LP3907 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the

raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply

voltage is less than 2.8 VDC.

The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8 VDC

trip point for a V_INOK – Not OK detector. This V_INOK signal is then used to gate the enable signals to the four

regulators of the device. When VINLDO12 is greater than 2.8 VDC the four enables control the four regulators,

when VINLDO12 is less than 2.8 VDC the four regulators are disabled by the V_INdetector being in the “Not OK”

state. The circuit has built-in hysteresis to prevent chattering occurring.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch is on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It

is recommended to disable the converter during the system power up and undervoltage conditions when the

supply is less than 2.8 V.

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8.5 Programming

8.5.1 I²C-Compatible Serial Interface

8.5.1.1 I²C Signals

The LP3907features an I²C-compatible serial interface, using two dedicated pins: SCL and SDA for I²C clock and

data respectively. Both signals need a pullup resistor according to the I²C specification. The LP3907 interface is

an I²C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400kbit/s. See I²C

specification from NXP Semiconductors for further details.

8.5.1.2 I²C Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL); for example, the state

of the data line can only be changed when CLK is LOW.

2

I C_SCL

2

I C_SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

Figure 39. I²C Signals: Data Validity

8.5.1.3 I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

2

transitioning from LOW to HIGH while the SCL is HIGH. The C master always generates START and STOP

bits. The I²C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I²C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

2

I C_SDA

2

I C_SCL

S

P

START condition

STOP condition

Figure 40. Start and Stop Conditions

8.5.1.4 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been

addressed must generate an acknowledgment (“ACK”) after each byte has been received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W).

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Programming (continued)

NOTE

According to industry I²C standards for 7-bit addresses, the MSB of an 8-bit address is

removed, and communication actually starts with the 7th most significant bit. For the

eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte

selects the register to which the data is written. The third byte contains data to write to the

selected register.

The LP3907 has factory-programmed I²C addresses. The WQFN chip has a chip address of 60'h, while the

DSBGA chip has a chip address of 61'h.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

bit7

bit6

bit5

bit4

bit3

bit2

bit1

1

0

I²C SLAVE address (chip address)

Figure 41. I²C Chip Address (see note above)

ack from slave

start msb Chip Address lsb

w

ack msb Register Add lsb ack msb

DATA

lsb ack stop

SCL

SDA

1

3 4 5 6

2

7

8

9

1 2 3 ...

start

id = h‘60

w

ack

addr = h‘02

ack

address h‘AA data

ack stop

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP3907 WQFN chip address: 0x60; DSBGA chip address: 0x61

Figure 42. I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

ack from slave

ack from slave repeated start

ack from slave data from slave ack from master

start msb Chip Address lsb

w

ack msb Register Add lsb ack rs

msb Chip Address lsb

r

ack msb

DATA

lsb ack stop

.

SCL

SDA

start

id = h‘60

w

ack

register addr = h‘10

ack rs

id = h‘60

r

ack

data addr h‘6A

ack stop

Figure 43. I²C Read Cycle

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Programming (continued)

8.5.2 Factory Programmable Options

Table 7 shows options EPROM programmed during final test of the LP3907. The system designer that needs

specific options is advised to contact the TI sales office.

Table 7. Factory-Programmable Options

FACTORY PROGRAMMABLE OPTIONS

Enable delay for power on

CURRENT VALUE

code 010 (see Control 1 Register (SCR1) 0x07)

SW1 ramp speed

SW2 ramp speed

8 mV/µs

The I²C Chip ID address is offered as a metal mask option. The current address for the WQFN chip equals 0x60,

while the address for the DSBGA chip is 0x61.

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8.6 Register Maps

8.6.1 LP3907 Control Registers

REGISTER

ADDRESS

REGISTER

NAME

READ/WRITE

REGISTER DESCRIPTION

0x02

0x07

0x10

0x11

0x20

0x23

0x24

0x25

0x29

0x2A

0x2B

0x38

0x39

0x3A

ICRA

SCR1

R

Interrupt Status Register A

System Control 1 Register

R/W

R

BKLDOEN

BKLDOSR

VCCR

Buck and LDO Output Voltage Enable Register

Buck and LDO Output Voltage Status Register

Voltage Change Control Register 1

Buck1 Target Voltage 1 Register

Buck1 Target Voltage 2 Register

Buck1 Ramp Control

R/W

B1TV1

B1TV2

B1RC

B2TV1

Buck2 Target Voltage 1 Register

Buck2 Target Voltage 2 Register

Buck2 Ramp Control

B2TV2

B2RC

BFCR

Buck Function Register

LDO1VCR

LDO2VCR

LDO1 Voltage Control Registers

LDO2 Voltage Control Registers

8.6.1.1 Interrupt Status Register (ISRA) 0x02

This register informs the System Engineer of the temperature status of the chip.

D7-D2

D1

D0

Name

Access

Data

—

Temp 125°C

R

—

Reserved

0

Status bit for thermal warning

PMIC T>125°C

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reserved

0

Reset

0

8.6.1.2 Control 1 Register (SCR1) 0x07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

D7

D6-D4

EN_DLY

D3

D2

D1

D0

Name

Access

Data

—

FPWM2

R/W

FPWM1

R/W

ECEN

R/W

Reserved

Selects the preset

delay sequence from

EN_T assertion

Reserved

Buck2 PWM /PFM Mode Buck 1 PWM /PFM

Reserved

select

Mode select

0 – Auto Switch PFM -

PWM operation

1 – PWM Mode Only

0 – Auto Switch PFM -

PWM operation

1 – PWM Mode Only

(shown below)

Reset

0

Factory-Programmed

Default

1

Factory-Programmed

Default

Factory-Programmed

Default

0

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8.6.1.3 EN_DLY Preset Delay Sequence After EN_T Assertion

DELAY (ms)

EN_DLY<2:0>

BUCK1

BUCK2

LDO1

LDO2

000

001

010

011

100

101

110

111

1

1.5

2

1

2

3

1

3

2

1

6

1

2

1.5

3

6

2

1

2

6

1.5

2

1.5

11

2

3

8.6.1.4 Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10

This register controls the enables for the Bucks and LDOs.

D7

D6

LDO2EN

R/W

D5

D4

LDO1EN

R/W

D3

D2

BK2EN

D1

D0

BK1EN

R/W

Name

Access

Data

—

R/W

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reset

0

1

0

1

0

1

8.6.1.5 Buck and LDO Status Register (BKLDOSR) – 0x11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7

BKS_OK

R

D6

LDOS_OK

R

D5

LDO2_OK

R

D4

LDO1_OK

R

D3

D2

BK2_OK

D1

D0

Name

Access

Data

—

BK1_OK

R

0 – Buck 1-2

Not Valid

0 – LDO 1-2

Not Valid

0 – LDO2 Not

Valid

0 – LDO1 Not

Valid

Reserve 0 – Buck2 Not

Reserve 0 – Buck1 Not

d

Valid

d

Valid

1 – Bucks Valid 1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid

1 – Buck2 Valid

1 – Buck1 Valid

Reset

0

8.6.1.6 Buck Voltage Change Control Register 1 (VCCR) – 0x20

This register selects and controls the output target voltages for the buck regulators.

D7-6

D5

D4

D3-2

D1

D0

Name

Access

Data

—

B2VS

R/W

B2GO

R/W

—

B1VS

R/W

B1GO

R/W

Reserved

Buck2 Target Voltage

Select

Buck2 Voltage Ramp

CTRL

Reserved

Buck1 Target Voltage

Select

Buck1 Voltage Ramp

CTRL

0 – B2VT1

0 – Hold

0 – B1VT1

0 – Hold

1 – B2VT2

1 – Ramp to B2VS

selection

1 – B1VT2

1 – Ramp to B1VS

selection

Reset

00

0

00

0

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8.6.1.7 Buck1 Target Voltage 1 Register (B1TV1) – 0x23

This register allows the user to program the output target voltage of Buck1.

D7-D5

D4-D0

BK1_VOUT1

Name

Access

Data

—

R/W

Reserved

Buck1 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

Factory-Programmed Default

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8.6.1.8 Buck1 Target Voltage 2 Register (B1TV2) – 0x24

This register allows the user to program the output target voltage of Buck1.

D7-D5

D4-D0

BK1_VOUT2

Name

Access

Data

—

R/W

Reserved

Buck1 Output Voltage (V)

(1)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

Reset

000

Factory-Programmed Default

(1) If using Ext Ctrl, contact TI Sales for support.

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8.6.1.9 Buck1 Ramp Control Register (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck1.

D7

- - - -

D6-D4

- - - -

D3-D0

B1RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

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8.6.1.10 Buck2 Target Voltage 1 Register (B2TV1) – 0x29

This register allows the user to program the output target voltage of Buck2.

D7-D5

D4-D0

Name

Access

Data

—

BK2_VOUT1

R/W

Reserved

Buck2 Output Voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

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8.6.1.11 Buck2 Target Voltage 2 Register (B2TV2) – 0x2A

This register allows the user to program the output target voltage of Buck2.

D7-5

D4-0

BK2_VOUT2

Name

Access

Data

—

R/W

Reserved

Buck2 Output Voltage (V)

(1)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

Ext Ctrl

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

(1) If using Ext Ctrl, contact TI Sales for support.

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8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck2.

D7

- - - -

D6-D4

- - - -

D3-D0

B2RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4h'0

Ramp Rate mV/us

Instant

4h'1

1

2

4h'2

4h'3

3

4h'4

4

4h'5

5

4h'6

6

4h'7

7

4h'8

8

4h'9

9

4h'A

10

4h'B - 4h'F

Reset

0

010

1000

8.6.1.13 Buck Function Register (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less

Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the

frequency ramps up and down, centered at 2 MHz.

Spread Spectrum

frequency

Peak frequency deviation

2 kHz triangle

wave

10 kHz triangle

wave

2 MHz

Time

Figure 44. Spread Spectrum Modulation Frequency

This register also allows dynamic scaling of the nPOR Delay Timing. The LP3907 is equipped with an internal

POR circuit which monitors the output voltage levels on the buck regulators, allowing the user to more actively

monitor the power status of the chip.

The UVLO feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the

four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging

the power source (such as battery), but can be disabled if the user wishes.

Note that if the supply to VDD_M is close to 2.8 V with a heavy load current on the regulators, the chip is in

danger of powering down due to UVLO. If the user wishes to keep the chip active under those conditions, enable

the Bypass UVLO feature.

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D0

D7-D5

—

D4

D3-D2

D1

BK_SLOMOD

Name

Access

Data

BP_UVLO

R/W

TPOR

R/w

BK_SSEN

R/W

—

R/W

Reserved

Bypass UVLO

monitoring

nPOR Delay Timing

00 - 50 µs

Buck Spread Spectrum

Modulation

Spread Spectrum

Function Output

0 - Allow UVLO

1 - Disable UVLO

01 - 50 ms

10 - 100 ms

11 - 200 ms

0 – 10 kHz triangular wave 0 – Disabled

1 – 2 kHz triangular wave

1 – Enabled

Reset

000

Factory-Programmed

Default

01

1

0

8.6.1.14 LDO1 Control Register (LDO1VCR) – 0x39

This register allows the user to program the output target voltage of LDO 1.

For “JJ11” voltage options LDO1 has a fixed output voltage of 2.85 V.

D7-D5

D4-D0

LDO1_OUT

R/W

Name

Access

Data

—

Reserved

LDO1 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

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8.6.1.15 LDO2 Control Register (LDO2VCR) – 0x3A

This register allows the user to program the output target voltage of LDO 2.

For “JJ11” voltage options LDO2 has a fixed output voltage of 2.85 V.

D7-D5

D4-D0

Name

Access

Data

—

LDO2_OUT

R/W

Reserved

LDO2 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

5’h1A–5’h1F

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

Reset

000

Factory-Programmed Default

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP3907 provides three control methods to turn ON/OFF four power rails:

1. EN_T Control: Provides pre-defined power up/down sequence. (Note: V_IN/Battery voltage must be settled

approximately 8 ms, minimum, before EN_T be asserted high).

2. Individual GPIO/EN pin control: four EN pins provide max control flexibility without I²C.

3. I²C control: besides simple ON/OFF control, also provides access to all the user programmable registers.

See Register Maps for details.

9.2 Typical Application

VINLDO12

EN_T

VDD

100k

1 mF

ENLDO1

ENLDO2

nPOR

VIN1

ENSW1

ENSW2

LDO1

10 mF

2.2 mH

SW1

FB1

10 mF

0.47 mF

VINLDO1

VINLDO2

LDO2

GND_SW1

1 mF

LP3907

VIN2

10 mF

2.2 mH

0.47 mF

SW2

FB2

SDA

SCL

10 mF

GND_SW2

AVDD

GND_L

GND_C

DAP

1 mF

Figure 45. LP3907 Typical Application

9.2.1 Design Requirements

Ten ceramic capacitors and two inductors are required for this application. These three external components

must be selected very carefully for property operation. See Detailed Design Procedure.

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Typical Application (continued)

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LP3907 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Component Selection

9.2.2.2.1 Inductors for SW1 And SW2

There are two main considerations when choosing an inductor; the inductor must not saturate and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Care must be taken when reviewing

the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are

typically specified at 25ºC, so ratings at maximum ambient temperature of the application must be requested

from the manufacturer.

There are two methods to choose the inductor saturation current rating:

9.2.2.2.1.1 Method 1:

The saturation current is greater than the sum of the maximum load current and the worst case average-to-peak

inductor current. This can be written as follows:

I_sat> I_outmax+ I_ripple

V_IN- V_OUT

2L

’ _x≈^V^OUT

’

◊

1

≈ ’

≈

«

x

where

I_ripple

⁼« _f◊

V

◊ «

IN

where

•

I_RIPPLE= Maximum load current

I_OUTMAX= Average to peak inductor current

V_IN= Maximum input voltage to the buck

L = Min inductor value including worse case tolerances (30% drop can be considered for method 1)

f = Minimum switching frequency (1.6 MHz)

V_OUT= Buck output voltage

(6)

9.2.2.2.1.2 Method 2:

A more conservative and recommended approach is to choose an inductor that has saturation current rating

greater than the maximum current limit of 1250 mA for Buck1 and 1750 mA for Buck2.

Given a peak-to-peak current ripple (I_PP) the inductor needs to be at least

V_IN- V_OUT

I_PP

’ _x≈^V^OUT

’

◊

≈ ’

1

« _f◊

≈

«

x

L í

V

◊ «

IN

(7)

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Typical Application (continued)

space

Table 8. Suggested Inductor Values

INDUCTOR

VALUE (µH)

2.2

DESCRIPTION

NOTES

DCR: 70 mΩ

L_SW1,2

SW1,2 inductor

9.2.2.2.2 External Capacitors

The regulators on the LP3907 require external capacitors for regulator stability. These are specifically designed

for portable applications requiring minimum board space and smallest components. These capacitors must be

correctly selected for good performance.

9.2.2.3 LDO Capacitor Selection

9.2.2.3.1 Input Capacitor

An input capacitor is required for stability. It is recommended that a 1-μF capacitor be connected between the

LDO input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low

impedance source of power (such as a battery or a very large capacitor). If a tantalum capacitor is used at the

input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains

approximately 1 μF over the entire operating temperature range.

9.2.2.3.2 Output Capacitor

The LDOs on the LP3907 are designed specifically to work with very small ceramic output capacitors. A 0.47-µF

ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in the

application circuit.

It is also possible to use tantalum or film capacitors at the device output, C_OUT(or V_OUT), but these are not as

attractive for reasons of size and cost.

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩ to 500 mΩ for stability.

9.2.2.3.3 Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least

expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The

ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR

requirement for stability for the LDOs.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, Figure 46 is a typical graph comparing different capacitor case

sizes.

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0603, 10V, X5R

100%

80%

60%

40%

20%

0402, 6.3V, X5R

0

1.0

2.0

3.0

4.0

5.0

DC BIAS (V)

Figure 46. Graph Showing Typical Variation in Capacitance vs. DC Bias

As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the

minimum value given in the recommended capacitor specifications table. Note that the graph shows the

capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended

that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (for example, 0402) may not be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of −55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a

similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors,

larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by

more than 50% as the temperature varies from 25°C to 85°C. Therefore, X7R is recommended over Z5U and

Y5V in applications where the ambient temperature changes significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. Note, also, that the ESR of a typical tantalum increases about 2:1 as the

temperature goes from 25°C down to −40°C, so some guard band must be allowed.

9.2.2.3.4 Input Capacitor Selection for SW1 And SW2

A ceramic input capacitor of 10 µF, 6.3 V is sufficient for the magnetic DC-DC converters. Place the input

capacitor as close to the input of the device as possible. A large value may be used for improved input voltage

filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The

input filter capacitor supplies current to the PFET switch of the DC-DC converter in the first half of each cycle

and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR provides the best

noise filtering of the input voltage spikes due to fast current transients. A capacitor with sufficient ripple current

rating must be selected. The Input current ripple can be calculated as:

r²

V_OUT

≈

«

’

◊

(V_inœ V_out) x V_out

I_rms= I_outmax

1 +

where

r =

V_IN

12

L x f x I_outmaxx V_in

(8)

The worse case is when V_IN= 2 V_OUT

.

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9.2.2.3.5 Output Capacitor Selection for SW1, SW2

A 10-μF, 6.3-V ceramic capacitor must be used on the output of the SW1 and SW2 magnetic DC-DC converters.

The output capacitor must be mounted as close to the output of the device as possible. A large value may be

used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type

capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer, and DC bias

curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the

load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these

functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

I_ripple

V_pp-c

=

4 x f x C

(9)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

V_PP–ESR= 2 × I_RIPPLE× R_ESR

(10)

Because the V_PP-Cand V_PP-ESRare out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

V_pp-c²+ V_pp-esr

2

V_pp-rms

=

(11)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (R_ESR). The R_ESRis frequency dependent as well as temperature dependent.

Calculate the R_ESRwith the applicable switching frequency and ambient temperature.

Table 9. Suggested Capacitor Values

CAPACITOR

C_LDO1

MIN VALUE (µF)

DESCRIPTION

RECOMMENDED TYPE

Ceramic, 6.3 V, X5R

0.47

10

LDO1 output capacitor

LDO2 output capacitor

SW1 output capacitor

SW2 output capacitor

C_LDO2

C_SW1

C_SW2

10

9.2.2.3.6 I²C Pullup Resistor

Both SDA and SCL pins must have pullup resistors connected to VINLDO12 or to the power supply of the I²C

master. The values of the pullup resistors (typical approximately 1.8 kΩ) are determined by the capacitance of

the bus. A resistor that is too large, combined with a given bus capacitance, results in a rise time that would

violate the maximum rise time specification. A too-small resistor results in a contention with the pulldown

transistor on either slave(s) or master.

9.2.2.4 Operation Without I²C Interface

Operation of the LP3907 without the I²C interface is possible if the system can operate with default values for the

LDO and Buck regulators (see Factory Programmable Options.) The I²C-less system must rely on the correct

default output values of the LDO and Buck converters.

9.2.2.4.1 High V_INHigh-Load Operation

Additional information is provided when the IC is operated at extremes of V_INand regulator loads. These are

described in terms of the junction temperature and, buck output ripple management.

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9.2.2.4.2 Junction Temperature

The maximum junction temperature T_J-MAX-OPof 125°C of the device package Equation 12 through Equation 17

demonstrate junction temperature determination, ambient temperature T_A-MAX, and total chip power must be

controlled to keep T_Jbelow this maximum:

T_J-MAX-OP= T_A-MAX+ (R_θJA) [°C/ Watt] × (P_D-MAX) [Watts]

(12)

Total device power dissipation P_D-MAXis the sum of the individual power dissipation of the four regulators plus a

minor amount for chip overhead. Chip overhead is Bias, TSD, and LDO analog.

P_D-MAX= P_LDO1+ P_LD02+ P_BUCK1+ P_BUCK2+ (0.0001A × V_IN) [Watts].

(13)

(14)

(15)

Power dissipation of LDO1:

P_LDO1= (V_INLDO1– V_OUTLDO1) × I_OUTLDO1[V × A]

Power dissipation of LDO2:

P_LDO2= (V_INLDO2– V_OUTLDO2) × I_OUTLDO2[V × A]

Power dissipation of Buck1:

P_Buck1= P_IN– P_OUT= V_OUTBuck1× I_OUTBuck1× (1 – η₁) / η₁[V × A]

where

•

η₁= efficiency of buck 1

(16)

(17)

Power dissipation of Buck2:

P_Buck2= P_IN– P_OUT= V_OUTBuck2× I_OUTBuck2× (1 – η₂) / η₂[V × A]

where

•

η₂= efficiency of Buck2

where

•

η is the efficiency for the specific condition taken from efficiency graphs.

9.2.3 Application Curves

100

90

80

70

60

50

40

100

90

80

70

60

50

40

30

20

10

= 4.5V

V_IN

V

= 2.8V

IN

= 5.5V

V_IN

V

= 3.6V

IN

V

= 5.5V

IN

0.1

1

10

100

1000

0.1

1

10

100

1000

OUTPUT CURRENT (mA)

V_OUT= 2 V

L= 2.2 µH

V_OUT= 2 V

L= 2.2 µH

Figure 48. Efficiency vs Output Current

(PWM-to-PFM Mode)

Figure 47. Efficiency vs Output Current

(Forced PWM Mode)

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10 Power Supply Recommendations

If the EN_T is used to power up the device instead individual ENs , then VIN must be stable for approximately 8

ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power on for power sequencing

function to operate properly.

10.1 Analog Power Signal Routing

All power inputs must be tied to the main VDD source (for example, battery), unless the user wishes to power it

from another source. (that is, external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they must be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.8 V and 5.5 V, as specified in the Recommended

Operating Conditions (Bucks) table earlier in the data sheet.

The other VINs (VINLDO1, VINLDO2) can have inputs lower than 2.8 V, as long as the input it higher than the

programmed output (0.3 V).

The analog and digital grounds must be tied together outside of the chip to reduce noise coupling.

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11 Layout

11.1 DSBGA Layout Guidelines

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter device, resulting in poor regulation or

instability.

Good layout for the LP3907 device bucks can be implemented by following a few simple design rules below.

Refer to Figure 49 for top-layer board buck layout.

1. Place the LP3907 bucks, inductor, and filter capacitors close together and make the traces short. The traces

between these components carry relatively high switching currents and act as antennas. Following this rule

reduces radiated noise. Special care must be given to place the input filter capacitor very close to the VIN

and GND pin.

2. Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor through the LP3907 bucks and inductor to the output

filter capacitor and back through ground, forming a current loop. In the second half of each cycle, current is

pulled up from ground through the LP3907 bucks by the inductor to the output filter capacitor and then back

through ground forming a second current loop. Routing these loops so the current curls in the same direction

prevents magnetic field reversal between the two half-cycles and reduces radiated noise.

3. Connect the ground pins of the LP3907 bucks and filter capacitors together using generous component-side

copper fill as a pseudo-ground plane. Then, connect this to the ground-plane (if one is used) with several

vias. This reduces ground-plane noise by preventing the switching currents from circulating through the

ground plane. It also reduces ground bounce at the LP3907 bucks by giving it a low-impedance ground

connection.

4. Use wide traces between the power components and for power connections to the DC-DC converter circuit.

This reduces voltage errors caused by resistive losses across the traces.

5. Route noise sensitive traces, such as the voltage feedback path, away from noisy traces between the power

components. The voltage feedback trace must remain close to the circuit of the LP3907 buck and must be

direct but must be routed opposite to noisy components. This reduces EMI radiated onto the DC-DC

converter’s own voltage feedback trace. A good approach is to route the feedback trace on another layer and

to have a ground plane between the top layer and layer on which the feedback trace is routed. In the same

manner for the adjustable part it is desired to have the feedback dividers on the bottom layer.

6. Place noise sensitive circuitry, such as radio IF blocks, away from the DC-DC converter, CMOS digital blocks

and other noisy circuitry. Interference with noise-sensitive circuitry in the system can be reduced through

distance.

For more detailed layout specifications and information, refer to AN-1112 DSBGA Wafer Level Chip Scale

Package.

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11.2 Layout Example

Figure 49. LP3907 DSBGA Layout Example

11.3 Thermal Considerations of WQFN Package

The LP3907 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize

power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at

the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.

Compared to the traditional leaded packages where the die attach pad is embedded inside the molding

compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on

thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (R_θJA) can be improved by a

factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land

and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer

diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. Typical copper via barrel plating is 1 oz,

although thicker copper may be used to further improve thermal performance. The LP3907 die attach pad is

connected to the substrate of the device, and therefore, the thermal land and vias on the PCB board must be

connected to ground (GND pin).

For more information on board layout techniques, refer to AN–1187 Leadless Lead Frame Package (LLP) on

http://www.ti.com. This application note also discusses package handling, solder stencil, and the assembly

process.

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12 器件和文档支持

12.1 器件支持

12.1.1 开发支持

12.1.1.1 使用 WEBENCH® 工具创建定制设计

单击此处，使用 LP3907 器件并借助 WEBENCH® 电源设计器创建定制设计方案。

1. 首先键入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化关键参数设计，如效率、封装和成本。

3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案导出至常用 CAD 格式

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com/WEBENCH。

12.2 文档支持

12.2.1 相关文档

请参阅如下相关文档：

•

AN-1112 DSBGA 晶圆级芯片级封装

《AN–1187 无引线型引线框架封装 (LLP)》

12.3 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 接收文档更新通知

如需接收文档更新通知，请导航至ti.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.5 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

51

LP3907

ZHCSEA3U –JUNE 2007–REVISED JANUARY 2018

www.ti.com.cn

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

52

MECHANICAL DATA

YZR0025xxx

0.600±0.075

D

E

TLA25XXX (Rev D)

D: Max = 2.521 mm, Min = 2.46 mm

E: Max = 2.521 mm, Min = 2.46 mm

4215055/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

B

A

PIN 1 INDEX AREA

4.1

3.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

7

12

20X 0.5

6

13

2X

25

2.5

2.6 0.1

1

18

0.3

24X

0.2

24

19

PIN 1 ID

(OPTIONAL)

0.1

C A B

C

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24

19

24X (0.6)

1

18

24X (0.25)

(1.05)

SYMM

25

(3.8)

20X (0.5)

(R0.05)

TYP

6

13

(

0.2) TYP

VIA

7

12

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

19

(R0.05) TYP

24

24X (0.6)

1

18

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

25

(3.8)

6

13

METAL

TYP

7

12

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP3907SQ-PFX6W/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	LP3907 具有 I2C 接口的双路 1A 和 600mA 降压转换器和双路 300mA LDO \| RTW \| 24 \| -40 to 85 开关转换器
文件：	总61页 (文件大小：4147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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