LP3910SQ-AK/NOPB [TI]
面向基于硬盘的便携式媒体播放器的电源管理 IC (PMIC) | NJV | 48;
| 型号： | LP3910SQ-AK/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 面向基于硬盘的便携式媒体播放器的电源管理 IC (PMIC) | NJV | 48 便携式 集成电源管理电路 |
| 文件： | 总77页 (文件大小：3658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP3910
SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
LP3910 Power Management IC for Hard-Drive-Based Portable Media Players
1 Features
2 Applications
1
•
Two Low-Dropout Regulators With Programmable
Output Voltages:
•
•
•
Hard Drive-Based Media Players
Portable Gaming Players
–
–
LDO1 for General Purpose Applications
LDO2 for Low-Noise Analog Applications
Portable Navigation Devices
3 Description
•
•
Green and Red LED-Charger Status Drivers
4-Channel 8-Bit Dual Slope
Analog-to-Digital (ADC) Converter
The LP3910 is a programmable system power
management unit optimized for HDD-based portable
media players. The device incorporates two low-
dropout LDO voltage regulators, two integrated buck
DC-DC converters with dynamic voltage scaling
(DVS), one wide load-range buck-boost DC-DC
converter with programmable output voltage, a 4-
channel, 8-bit ADC, and a dual-source lithium-ion or
lithium-polymer battery charger.
•
•
•
•
2 High-Efficiency DVS Buck Converters
Wide Load Range Buck-Boost DC-DC Converter
400-kHz I2C-Compatible Interface
Linear Constant-Current and Constant-Voltage
Charger for Single-Cell Lithium-Ion Batteries
•
•
•
•
•
•
•
USB and Adapter Charging
The LP3910 also incorporates some advanced
battery management functions such as battery
temperature measurement, reverse current blocking
for USB, LED-charger status indication, thermally
regulated internal power FETs, battery-voltage
monitoring, overcurrent protection, and a 10-hour
safety timer. The device is programmable through a
400-kHz I2C-compatible interface.
System Power Supply Management
Voltage and Thermal Supervisory Circuits
Continuous Battery Voltage Monitoring
Interrupt Request Output With 8 Sources
50-mΩ Battery Path Resistance
100-mA to 1000-mA Full-Rate Charge Current
Using Wall Adapter
The LP3910 is available in a thermally-enhanced
6-mm × 6-mm × 0.8-mm 48-pin WQFN package.
•
Selectable 0.05C and 0.1C End-of-Charge (EOC)
Current
Device Information(1)
•
•
•
USB Current Limits of 100, 500, and 800 mA
USB Pre-Qualification Current of 50 mA
PART NUMBER
LP3910
PACKAGE
BODY SIZE (NOM)
WQFN (48)
6.00 mm × 6.00 mm
Selectable 4.1-V, 4.2-V or 4.38-V Battery-
Termination Voltages
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
0.35% Battery-Termination Accuracy
±1 LSB INL/DNL on 8-Bit ADC
Simplified Block Diagram
[t3910
USB Controller
Apps Processor
Buck1
Buck2
Memory
Touch
Audio
HDD
Battery
Battery Monitor
Linear Charger
LDO1
LDO2
ACDC Wall Adapter
Buck-Boost
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3910
SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.18 Electrical Characteristics: ADC ............................. 14
7.19 I2C Timing Requirements...................................... 14
7.20 USB Timing Requirements ................................... 15
7.21 Typical Characteristics ......................................... 16
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 26
8.3 Feature Description................................................. 27
8.4 Device Functional Modes........................................ 43
8.5 Programming........................................................... 50
8.6 Register Maps......................................................... 53
Application and Implementation ........................ 61
9.1 Application Information............................................ 61
9.2 Typical Application .................................................. 61
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Tables................................... 3
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 8
7.6 Electrical Characteristics: I2C Interface ................... 8
7.7 Electrical Characteristics: Li-Ion Battery Charger .... 9
7.8 Detection and Timing.............................................. 10
7.9 Output Electrical Characteristics: CHG, STAT........ 10
8
9
10 Power Supply Recommendations ..................... 68
11 Layout................................................................... 68
11.1 Layout Guidelines ................................................ 68
11.2 Layout Example ................................................... 69
11.3 Thermal Performance of the WQFN Package ...... 70
12 Device and Documentation Support ................. 71
12.1 Device Support...................................................... 71
12.2 Documentation Support ........................................ 71
12.3 Community Resources.......................................... 71
12.4 Trademarks........................................................... 71
12.5 Electrostatic Discharge Caution............................ 71
12.6 Glossary................................................................ 71
7.10 Output Electrical Characteristics: NRST, IRQB,
ONSTAT................................................................... 10
7.11 Input Electrical Characteristics: USBSUSP,
USBISEL.................................................................. 11
7.12 Input Electrical Characteristics: POWERACK,
ONOFF, LDO2EN, BUCK1EN................................. 11
7.13 Electrical Characteristics: LDO1 Low Dropout Linear
Regulators................................................................ 11
7.14 Electrical Characteristics: LDO2 Low Dropout Linear
Regulator.................................................................. 12
7.15 Electrical Characteristics: Buck1 Converter ......... 12
7.16 Electrical Characteristics: Buck2 Converter.......... 13
7.17 Electrical Characteristics: Buck-Boost .................. 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 71
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (March 2013) to Revision M
Page
•
Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information
tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply
Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information sections................................................................................................................................................................ 1
Changes from Revision K (February 2012) to Revision L
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 68
2
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
5 Device Comparison Tables
Table 1. Device Default Voltage Options
ORDER NUMBER
LP3910SQ-AA
LDO1
2 V
LDO2
3.3 V
3.3 V
3 V
BUCK1
1.2 V
1.2 V
1.6 V
1.6 V
1.5 V
1.5 V
1 V
BUCK2
3.3 V
3.3 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
BUCK-BOOST
3.3 V
ICHRG
100 mA
100 mA
100 mA
100 mA
100 mA
100 mA
1000 mA
1000 mA
LP3910SQX-AA
LP3910SQ-AK
LP3910SQX-AK
LP3910SQ-AM
LP3910SQX-AM
LP3910SQ-AN
LP3910SQX-AN
2 V
3.3 V
2.5 V
2.5 V
3.3 V
3.3 V
1.2 V
1.2 V
3.3 V
3 V
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
3.3 V
3.3 V
3.3 V
1 V
3.3 V
Table 2. Device Option Parameters for AP Option
SYMBOL
DESCRIPTION
Default LDO1
VALUE
2.8 V
1.5 V
1.45 V
1.8 V
3.3 V
100 mA
6 ms
LDO1
LDO2
Buck1
Buck2
Buck-Boost
ICHRG
T1
Default LDO2
Default Buck1
Default Buck2
Default Buck-Boost
Default charge current
Turnon delay for LDO1 and LDO2
Turnon delay for Buck1
Turnon delay for Buck2
Turnon delay for Buck-Boost
Turnon delay for NRST
Turnoff delay for LDO1 and LDO2
Turnoff delay for Buck1
Turnoff delay for Buck2
Turnoff delay for Buck-Boost
Turnoff delay for NRST
battery low threshold
Full-rate threshold
T2
3 ms
T3
1 ms
T4
0 ms
T5
10 ms
10 ms
10 ms
10 ms
10 ms
3 ms
T1
T2
T3
T4
T5
VBATTLOW
VFULLRATE
ILED
2.5 V
2.55 V
2 V
Default LED current
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
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The following options are programmed for the LP3910. The system designer that needs specific options is
advised to contact the local Texas Instruments sales office.
Table 3. Factory Programmable Options
FACTORY PROGRAMMABLE OPTIONS
LDO1 output voltage after power up
LDO2 output voltage after power up
BUCK1 output voltage after power up
BUCK2 output voltage after power up
BUCK-BOOST power voltage after power up
Battery low threshold
DEFAULT VALUE (AA)
2 V
3.3 V
1.2 V
3.3 V
3.3 V
2.9 V
Delay for LDO1 and LDO2
Delay for BUCK1
5 ms
15 ms
20 ms
25 ms
60 ms
100 mA
0.1C
Delay for BUCK2
Delay for BUCK-BOOST
Delay for NRST
Default full-rate charge current
EOC default
VTERM default
4.2 V
ONOFF edge/level
Level
ONOFF polarity
Positive
Positive
Positive
No
BUCK1 enable polarity
LDO2 enable polarity
Ignore ten-hour timer
LED default current
10 mA
No
Buck-boost 500-mA output current
Thermistor 10 k/100 k
100 k
The I2C Chip ID address is offered as a metal mask option. The current value equals 60 hex.
4
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
6 Pin Configuration and Functions
NJV Package
48-Pin WQFN
Top View
31
27 26 25
36 35 34 33 32
30 29 28
37
24
38
39
40
41
42
43
44
45
46
47
48
23
22
21
20
19
18
17
16
15
14
13
1
2
3
6
11 12
4
5
9
10
7
8
Pin Functions
PIN
NAME
I/O
TYPE(1)
DESCRIPTION
NO.
Battery temperature sense pin. This pin is normally connected to the thermistor pin of
the battery cell.
1
TS
I
A
2
3
4
5
6
7
8
9
VBATT1
AGND
O
—
O
I
A
G
Positive battery terminal. This pin must be externally shorted to VBATT2 and VBATT3
Analog ground
VREFH
LDO2EN
VLDO2
A
Connection to bypass capacitor for internal high reference
Digital input to enable/disable LDO2
D
O
I
A
LDO2 output
VIN1
PWR
A
Power input to LDO1 and LDO2. VIN1 pin must be externally shorted to the VDD pins.
LDO1 output
VLDO1
O
I
POWERACK
D
Digital power acknowledgement input (see Power-On, Power-Off Sequencing)
A 4.64-kΩ resistor must be connected between this pin and GND. A fraction of the
charge current flows through this resistor to enable the ADC to measure the charge
current.
10
ISENSE
I
A
11
12
ADC2
ADC1
I
I
A
A
Channel 2 input to ADC
Channel 1 input to ADC
Open
Drain
13
14
15
16
IRQB
NRST
CHG
O
O
O
O
Open drain active low interrupt request
Open
Drain
Open drain active low reset during standby
This output indicates that a valid charger supply source (USB adapter) has been
detected, and the device is charging. (Red LED)
D
D
Battery Status output indicator - off during constant current (CC), 50% duty cycle during
constant voltage (CV), 100% duty cycle with a fully charged Li-ion battery (Green LED)
STAT
17
18
19
20
BUCK1EN
VFB1
I
I
D
A
G
A
Digital input to enable/disable BUCK1
Buck1 Feedback input terminal
Buck1 Ground
BCKGND1
VBUCK1
—
O
Buck1 Output
(1) A: Analog; D: Digital: G: Ground; PWR: Power
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Pin Functions (continued)
PIN
I/O
TYPE(1)
DESCRIPTION
NO.
21
22
23
24
25
NAME
VIN2
I
I
PWR
PWR
A
Power input to Buck1. VIN2 pin must be externally shorted to the VDD pins.
VIN3
Power input to Buck2. VIN3 pin must be externally shorted to the VDD pins.
VBUCK2
BCKGND2
VFB2
O
—
I
Buck2 Output
G
Buck2 Ground
A
Buck2 Feedback input terminal
Power ONOFF pin configured either as level (High or Low) triggered or edge (High or
Low) triggered.
26
ONOFF
I
D
27
28
29
I2C_SCL
VDDIO
I2C_SDA
I
I
D
D
D
I2C-compatible interface clock terminal
Supply to input / output stages of digital I/O
I2C-compatible interface data terminal
I/O
Open
Drain
30
ONSTAT
O
Open Drain output that reflects the debounced state of ONOFF pin.
31
32
33
34
35
36
37
VBBFB
VBBOUT
VBBL2
I
O
I
A
A
Buck-Boost Feedback input terminal
Buck-Boost Output voltage
A
Buck-Boost inductor
BBGND1
VBBL1
—
I
G
Buck-Boost high current ground
A
Buck-Boost inductor
VIN4
I
PWR
D
Power input to Buck-Boost. VIN4 pin must be externally shorted to the VDD pins.
This pin must be pulled high during USB suspend mode.
USBSUSP
I
Pulling this pin low limits the USB charge current to 100 mA. Pulling this pin high limits
the USB charge current to 500 mA.
38
USBISEL
I
D
39
40
BBGND2
DGND
—
—
G
G
BUCK-BOOST Core Ground
Digital ground
Power input to supply application. This pin must be externally shorted to VDD1 and
VDD2.
41
42
VDD3
VDD2
I
I
PWR
PWR
Power input to supply application This pin must be externally shorted to VDD1 and
VDD3.
43
44
45
46
47
VBATT3
VBATT2
USBPWR
VDD1
O
O
I
A
A
Positive battery terminal. This pin must be externally shorted to V\BATT1 and VBATT2.
Positive battery terminal. This pin must be externally shorted to VBATT1 and VBATT3.
USB power input pin
PWR
PWR
A
I
Power input to supply application This pin is shorted to VDD2 and VDD3.
Wall adapter power input pin
CHG_DET
I
A 121-kΩ resistor must be connected between this pin and AGND. The resistor value
determines the reference current for the internal bias generator.
48
IREF
I
A
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
6.5
UNIT
V
Supply voltage
Battery voltage
CHG_DET
VBATT1, 2, 3
5
V
USBPWR, VIN1,VIN2,VIN3,VIN4, VDD1,VDD2,VDD3
All other pins
6.2
V
Voltage
VDD + 0.3
2.6
V
Power dissipation (TA = 70°C)(4)
W
ºC
Storage temperature, Tstg
–45
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) In applications where high power dissipation or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
=
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (RθJA × PD-MAX).
(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typical) and
disengages at TJ = 140°C (typical).
7.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine model
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN
4.5
4.35
0
NOM
MAX
6
UNIT
V
CHG_DET
USBPWR
6
V
VBATT1, 2, 3
4.5
6
V
VIN1, VIN2, VIN3, VIN4, VDD1, VDD2, VDD3
VDDIO
2.5
2.5
–40
–40
V
VDD
125
85
V
Junction temperature, TJ
Ambient temperature, TA
Power dissipation, TJ-MAX and TA-MAX
°C
°C
W
1.6
(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(2) Minimum and maximum limits are specified by design, test, or statistical analysis. Nominal numbers are not ensured, but do represent
the most likely norm.
(3) Nominal values and limits are for TJ = 25°C.
7.4 Thermal Information
LP3910
THERMAL METRIC(1)
NJV (WQFN)
48 PINS
25
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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7.5 Electrical Characteristics
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, and limits apply for TJ = 25°C.(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All circuits off except for POR and battery
monitor. No adapter or USB power
connected.
Battery standby supply
current
IQ_BATT
6
20
µA
All circuits off except for POR and battery
monitor. No adapter or USB power
connected.
Battery standby supply
current
IQ_BATT
20
µA
TJ = 0°C to 125°C
VPOR
TSD
Power-on reset threshold
VDD falling edge
1.9
V
Thermal shutdown
threshold
160
°C
Thermal shutdown
hysteresis
TSDH
20
°C
TTH-ALERT
VDDIO
Thermal interrupt threshold
IO supply
115
°C
V
2.5
VDD
Internal system clock
frequency
FCLK
2
MHz
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
(3) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(4) This specification is ensured by design. Not tested during production.
7.6 Electrical Characteristics: I2C Interface
Unless otherwise noted, VDDIO = 3.6 V, and minimum and maximum limits apply for TJ = 0°C to 125°C.(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
I2C_SDA & I2C_SCL
I2C_SDA & I2C_SCL
I2C_SDA & I2C_SCL
MIN
TYP
MAX
UNIT
VIL
Low level input voltage
High level input voltage
Low level output voltage
0.3 × VDDIO
V
V
V
V
VIH
0.7 × VDDIO
0
VOL
VHYS
0.2 × VDDIO
Schmitt trigger input hysterisis I2C_SDA & I2C_SCL
0.1 × VDDIO
(1) All voltages are with respect to the potential at the GND pin.
(2) Minimum and maximum limits are specified by design, test, or statistical analysis.
(3) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
(4) This specification is ensured by design.
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
7.7 Electrical Characteristics: Li-Ion Battery Charger
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF, RIREF = 121 kΩ. Typical limits apply for
TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum external USB
supply voltage
TJ = 25°C
USB current limit = 500 mA
VUSB
4.15
4.25
4.35
V
USBPWR detect
hysteresis
VUSB_HYST
110
4.5
150
30
mV
V
TJ = 25°C
Adapter current limit = 1 A
VFWD Schottky = 350 mV
Minimum external adapter
supply voltage range
CHG_DET
VCHG_HYST
IUSB_SUSP
4.4
4.6
CHG_DET input
hysteresis
mV
µA
USB suspend mode, VUSB = 5 V
USBSUSP = USBPWR
USBISEL = 0 V
Quiescent current in USB
suspend mode
60
–0.35%
−0.5%
−0.5%
4.2
4.1
4.38
0.35%
0.5%
0.5%
TJ = 25°C
IPROG = 500 mA, ICHG = 50 mA
Battery charge termination
voltage tolerance
(selected in CHCTL
Register (01)H Charger
Control Register)
V
V
VTERM_TOL
–1%
–1.5%
–1.5%
4.2
4.1
4.38
1%
1.5%
1.5%
TJ = 0°C to 125°C
IPROG = 500 mA, ICHG = 50 mA
Full-rate charging current
from wall adapter input
(see Full-Rate Charging
Mode)
CHG_DET = 5.25 V
VBATT = 3.6 V, IPROG = 500 mA
ICHG_WA
450
500
550
mA
USB = 5 V, VBATT = 3.6 V
IPROG = 500 mA, USB_ISEL = 800 mA
450
405
500
450
550
495
mA
mA
Full-rate charging current
from usbpwr input (see
Full-Rate Charging Mode)
ICHG_USB
USB = 5 V, VBATT = 3.6 V
IPROG = 500 mA, USB_ISEL = 500 mA
USB_ISEL = 100 mA
USB_ISEL = 500 mA
USB_ISEL = 800 mA
90
450
720
95
475
760
100
500
800
USB ILIMIT
USB charge-current limit
Pre-qualification current
mA
VBATT = 2.5 V, wall-adapter charge
current
Percentage of programmed full-rate
current
8%
10%
12%
IPREQUAL
VBATT = 2.5 V, USB charge current
40
50
60
mA
V
VBATT rising, transition from pre-
qualification to full-rate charging
(standard)
2.75
2.85
2.95
Full-rate qualification
threshold
VFULL_RATE
VBATT rising, transition from pre-
qualification to full-rate charging (AP
version only)
2.45
2.55
2.65
VTH_H
VTH_L
ITSENSE
TREG
Upper TS comparator limit
Lower TS comparator limit
2.82
0.315
0.255
2.87
0.33
0.27
2.93
0.345
0.285
V
V
45°C CHSPV Reg D3 = 0
50°C CHSPV Reg D3 = 1
Battery temperature sense
current
7.75
105
8
8.25
125
µA
°C
Regulated charger
junction temperature
TJ = 25°C
115
(1) All voltages are with respect to the potential at the GND pin.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3) Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
(4) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
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7.8 Detection and Timing
Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IPROG = 500 mA
10% EOC setting
40
50
60
mA
IEOC
End-of-charge current
IPROG = 500 mA
5% EOC setting
20
25
30
mA
V
VTERM = 4.1 V
VTERM = 4.2 V
VTERM = 4.38 V
3.82
3.94
4.14
3.9
4
3.94
4.06
4.26
Battery restart charging
voltage
VRESTART
4.2
7.9 Output Electrical Characteristics: CHG, STAT
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical limits apply for TJ = 25°C;
minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.(1)(2)(3)(4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VLED = 2 V
CHSPV Register (02)h bit 5 = 1
(standard)
4
5
6
ILED
Output high level
mA
VLED = 2 V
CHSPV Register (02)h bit 5 = 1 (AP
version only)
0.75
8
1
10
2
1.25
12
VLED = 2 V
CHSPV Register (02)h bit 5 = 0
(standard)
ILED
Output high level
mA
VLED = 2 V
CHSPV Register (02)h bit 5 = 0 (AP
version only)
1.6
2.4
ILEAKAGE
LEDFREQ
Leakage current
VLED = 1.5 V, LED off
0.1
1
5
µA
Hz
Blinking frequency
0.8
1.2
(1) All voltages are with respect to the potential at the GND pin.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3) Minimum and maximum limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the
most likely norm.
(4) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.10 Output Electrical Characteristics: NRST, IRQB, ONSTAT
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF. Minimum and maximum limits apply over
the entire junction temperature range for operation, TJ = 0°C to 125°C.(1)(2)(3)(4)
PARAMETER
Output low level
Leakage current
TEST CONDITIONS
IOL = 4 mA
VDD = 2.5 V, output logic high
MIN
TYP
MAX
0.4
1
UNIT
V
VOL
ILEAKAGE
–1
µA
(1) All voltages are with respect to the potential at the GND pin.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(3) Minimum and maximum limits are specified by design, test, or statistical analysis.
(4) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
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7.11 Input Electrical Characteristics: USBSUSP, USBISEL
Unless otherwise noted, VUSB = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_DET = 10 µF. Minimum and maximum limits apply
over the entire junction temperature range for operation, TJ = 0°C to 125°C.(1)(2)(3)(4)(5)
PARAMETER
Input low level
Input high level
Input leakage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIL
0.3 × VUSB
VIH
0.7 × VUSB
V
ILEAKAGE
−1
1
µA
(1) LDO2EN, BUCK1EN, and USBSUSP have weak internal pulldowns while pins POWERACK, ONOFF do not have weak pulldowns.
(2) All voltages are with respect to the potential at the GND pin.
(3) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(4) Minimum and maximum limits are specified by design, test, or statistical analysis.
(5) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.12 Input Electrical Characteristics: POWERACK, ONOFF, LDO2EN, BUCK1EN
Unless otherwise noted, VDD = 5 V, VBATT = 3.6 V, CBATT = 4.7 µF, CCHG_IN = 10 µF. Minimum and maximum limits apply over
the entire junction temperature range for operation, TJ = 0°C to 125°C.(1)(2)(3)(4)(5)
PARAMETER
Input low level
Input high level
Input leakage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIL
0.4
VIH
1.4
–1
V
ILEAKAGE
1
µA
(1) LDO2EN, BUCK1EN, and USBSUSP have weak internal pulldowns, while pins POWERACK, ONOFF do not have this.
(2) All voltages are with respect to the potential at the GND pin.
(3) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
(4) Minimum and maximum limits are specified by design, test, or statistical analysis.
(5) Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
7.13 Electrical Characteristics: LDO1 Low Dropout Linear Regulators
Unless otherwise noted, VIN1 = 3.6 V, IMAX = 150 mA, VOUT = default value, CVDD = 10 µF, CLDO1 = 1 µF, ESR = 5 mΩ – 500
mΩ, CVREFH = 100 nF. Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN1
Operational voltage
2.5
6
V
Output voltage
programming range
TJ = 25°C
1.2 V to 3.3 V in 100-mV steps
VOUT Range
1.2
3.3
V
1 mA ≤ IOUT ≤ IMAX over full line and
load regulation.
VOUT Accuracy Output voltage accuracy
–3%
3%
VOUT = default value
VIN = (VOUT + 500 mV) to 5.5 V
Load current = IMAX
Line regulation
ΔVOUT
3
mV
mV
VIN = 3.6 V,
Load current = 1 mA to IMAX
Load regulation
10
ISC
Short-circuit current limit
Dropout voltage
VOUT = 0 V
600
750
60
mA
mV
VIN – VOUT
Load current = IMAX
150
200
Power supply ripple
rejection
PSRR
F = 10 kHz, load current = IMAX
30
dB
RSHUNT
LDO output impedance
LDO disabled, VOUT = default value
Ω
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7.14 Electrical Characteristics: LDO2 Low Dropout Linear Regulator
Unless otherwise noted VIN1 = 3.6V, IMAX = 150 mA, VOUT = default value, CVDD = 10 µF, CLDO2 = 1 µF, ESR = 5 mΩ to 500
mΩ, CVREFH = 100 nF. Typical limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless
otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN2
Operational voltage
2.5
6
V
Output voltage programming
range
TA = 25°C
1.3 V to 3.3 V in 100-mV steps
VOUT range
1.3
3.3
3%
V
Output voltage accuracy
1 mA ≤ IOUT ≤ IMAX over full line
and load regulation
VOUT accuracy
–3%
(default VOUT
)
VIN = (VOUT + 500 mV) to 5.5 V,
Load current = IMAX
Line regulation
Load regulation
3
mV
mV
ΔVOUT
VIN = 3.6 V,
Load current = 1 mA to IMAX
10
ISC
Short-circuit current limit
Dropout voltage
VOUT = 0 V
600
750
60
mA
mV
VIN – VOUT
Load current = IMAX
150
200
F = 1 kHz, load current = IMAX
F = 10 kHz, load current = IMAX
50
PSRR
Power supply ripple rejection
dB
35
Analog supply output noise
voltage
eN
10 Hz < F < 100 kHz
50
µVRMS
LDO disabled, VOUT = default
value
RSHUNT
LDO output impedance
Ω
7.15 Electrical Characteristics: Buck1 Converter
Unless otherwise noted, VIN2 = 3.6 V, VOUT = default value, CVIN2 = 10 µF, CSW1 = 10 µF, LSW1 = 2.2 µH. Typical limits apply
for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. Modulation mode is
PWM mode with automatic switch to PFM at light loads.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN2
Input voltage
2.7
6
V
Output voltage programming
range
TJ = 25°C
0.8 V to 2 V in 50-mV Steps
VOUT range
0.8
2
V
IOUT = 200 mA including line and
load regulation
Static output voltage tolerance
Line regulation
–3%
3%
ΔVOUT
IOUT = 10 mA
VIN2 = 2.5 V − VDD
0.2
%/V
Load regulation
100 mA < IOUT < 300 mA
0.002
%/mA
mA
Continuous output current
Peak output current limit
Maximum ILOAD, PFM mode
600
850
IOUT
IPFM
IQ
1000
75
1150
mA
mA
IOUT = 0 mA
30
90
1
Quiescent current
µA
BUCK1 disabled
PWM mode
FOSC
η
Internal oscillator frequency
Peak efficiency
2
MHz
90%
TON
Turnon time
To 95% level(1)
1
ms
(1) This specification is ensured by design.
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7.16 Electrical Characteristics: Buck2 Converter
Unless otherwise noted, VIN3 = 3.6 V, VOUT = default value, CVIN3 = 10 µF, CSW1 = 10 µF, LSW2 = 2.2 µH. Typical limits apply
for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. Modulation mode is
PWM mode with automatic switch to PFM at light loads.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN3
Input voltage
2.7
6
V
Output voltage programming
range
VOUT Range
1.8 V – 3.3 V in 100-mV steps
0.8
2
V
IOUT = 200 mA including line and
load regulation
Static output voltage tolerance
Line regulation
–3%
3%
ΔVOUT
IOUT = 10 mA
VIN3 = 2.5 V − VDD
0.2
%/V
Load regulation
100 mA < IOUT < 300 mA
0.002
%/mA
mA
Continuous output current
Peak output current limit
Maximum ILOAD, PFM mode
600
850
IOUT
IPFM
IQ
1000
75
1150
mA
mA
IOUT = 0 mA
Buck2 disabled
PWM mode
30
90
1
Quiescent current
µA
FOSC
η
Internal oscillator frequency
Peak efficiency
2
MHz
90%
TON
Turnon time
To 95% level(1)
1
ms
(1) This specification is ensured by design..
7.17 Electrical Characteristics: Buck-Boost
Unless otherwise noted, VIN4 = 3.6 V, CVIN4 = 10 µF, CBB = 22 µF, LBB = 2.2 µH. Typical limits apply for TJ = 25°C; minimum
and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified. Modulation mode is PWM mode with automatic
switch to PFM at light loads.
PARAMETER
TEST CONDITIONS
IOUTMAX = 1000 mA
MIN
2.9
TYP
MAX
5.7
UNIT
V
VIN4
Input voltage
IOUTMAX = 800 mA
2.7
5.7
V
Output voltage programming
range
TJ = 25°C
1.80 V to 3.30 V in 50-mV steps
VOUT Range
1.8
3.3
4%
V
IOUT = 0 mA to 1000 mA including
line and load regulation
Static output voltage tolerance
–4%
ΔVOUT
Line regulation
IOUT = 10 mA
0.2
%/V
%/mA
mA
Load regulation
100 mA < IOUT < 1000 mA
0.0016
Continuous output current
1000
1800
IOUT
VOUT = 3.3 V
1-A load at VIN = 2.7 V
Peak inductor current limit
Maximum ILOAD, PFM mode
2400
mA
mA
IPFM
IQ
75
80
IOUT = 0 mA PFM no switching
Buck-Boost disabled
PWM mode
Quiescent current
µA
1
1
FOSC
η
Internal oscillator frequency
Peak efficiency
2
MHz
93%
TON
Turnon time
To 95% level(1)
ms
(1) This specification is ensured by design.
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7.18 Electrical Characteristics: ADC
All limits apply for TJ = 25°C unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
1.22
1.2
TYP
1.225
1.225
MAX
1.23
1.23
1
UNIT
V
TJ = 25°C
VREF
Reference voltage
TJ = 0°C to 125°C
VREF = 1.225(1)
V
INL
Core ADC integral non-linearity
Core ADC differential non-linearity VREF = 1.225(1)
–1
LSB
LSB
DNL
–0.5
0.5
General purpose ADC input
voltage range
VGP_IN
VREF
2.435
1.217
2.435
1.217
2 × VREF
2.465
V
V
V
V
V
Battery maximum voltage scalar
VBATT = 3.5 V
2.45
1.225
2.45
output
VBATT
,
RANGE 0
Battery minimum voltage scalar
VBATT = 2.6 V
1.232
output
Battery maximum voltage scalar
VBATT = 4.4 V
2.465
output
VBATT,
RANGE 1
Battery minimum voltage scalar
VREF = 2.6 V
1.225
1.232
output
VISENSE = 0.6463 V
ISENSE maximum voltage scalar
ICHG = 0.605 A,
2.373
1.186
2.373
1.186
2.45
1.225
2.45
2.519
1.260
2.519
V
V
V
V
output
RSENSE = 4.64 kΩ
VISENSE
,
RANGE 0
VISENSE = 0 V
ISENSE minimum voltage scalar
ICHG = 0 A,
output
RSENSE = 4.64 kΩ
VISENSE = 1.175 V
ISENSE maximum voltage scalar
ICHG = 1.1 A,
output
RSENSE = 4.64 kΩ
VISENSE
,
RANGE 1
VISENSE = 0 V
ISENSE minimum voltage scalar
ICHG = 0 A,
1.225
1.26
1.23
output
RSENSE = 4.64 kΩ
ADC1 and
ADC2MIN
ADC1 and ADC2 minimum
VREFH = 1.225 V
1.218
2.436
1.225
2.45
V
V
voltage scalar output
ADC1 and
ADC2MAX
ADC1 and ADC2 maximum
VREFH = 1.225 V
2.46
5
voltage scalar output
tCONV
tWARM
Conversion time(1)
ms
ms
Warm-up time
2
(1) This specification is ensured by design.
7.19 I2C Timing Requirements
Unless otherwise noted, VDDIO = 3.6 V and minimum and maximum limits apply for TJ = 0°C to 125°C.(1)
MIN
NOM
MAX
400
UNIT
kHz
µs
FCLK
Clock frequency
tBF
Bus-free time between START and STOP
Hold time repeated START condition
CLK low period
1.3
0.6
1.3
0.6
0.6
0
tHOLD
tCLK-LP
tCLK-HP
tSU
µs
µs
CLK high period
µs
Set-up time repeated START condition
Data hold time
µs
tDATA-HOLD
tDATA-SU
tSU
µs
Data set-up time
100
0.6
ns
Set-up time for STOP condition
µs
Maximum pulse width of spikes that must be suppressed by the input filter
tTRANS
of both data and CLK signals
TJ = 25°C
50
µs
(1) These specifications are ensured by design.
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7.20 USB Timing Requirements
Nominal limits apply for TJ = 25°C; minimum and maximum limits apply for TJ = 0°C to 125°C, unless otherwise specified.
MIN
28
28
8
NOM
32
32
10
10
5
MAX
36
36
12
12
6
UNIT
ms
TCHG_IN
Deglitch adapter insertion
TUSB
Deglitch USB power insertion
ms
TPQ_FULL
TFULL_PQ
TBATTLOWF
TBATTLOWR
TBATTEMP
TONOFF_F
TONOFF_R
TRESTART
TCCCV
Deglitch time for pre-qualification to full-rate charge transition
Deglitch time for full-rate to pre-qualification transition
Deglitch time for VBATT falling below VBATTLOW threshold
Deglitch time for VBATT rising above VBATTLOW threshold
Deglitch time for recovery from battery temperature fault
Deglitching on falling edge of ONOFF pin
ms
8
ms
4
ms
4
5
6
ms
8
10
32
32
10
10
10
5
12
36
36
12
12
12
6
ms
28
28
8
ms
Deglitching on rising edge of ONOFF pin
ms
Deglitching on falling VBATT crossing VRESTART
Deglitching of CC→CV charging transition
Deglitching of CV→EOC (End of Charge)
ms
8
ms
TCVEOC
8
ms
TPOWERACK Deglitching of POWERACK pin
4
ms
TTSHD
TTOPOFF
T10HR
T1HR
Deglitching of thermal shutdown
Topoff timer
2
ms
17
9
21
10
1
25
11
min
hours
hour
10-hour safety timer
1-hour prequalification safety timer
0.9
1.1
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7.21 Typical Characteristics
TA = 25°C unless otherwise noted
7.21.1 Battery-Charger Characteristics
4.25
4.24
4.23
4.22
4.21
4.20
4.19
4.18
4.17
4.16
4.15
-7.50
-7.70
-7.90
-8.10
-8.30
-8.50
-20
10
40
70
100
130
-50
0
50
100
150
TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 2. TS Pin Current vs Temperature
Figure 1. VTERM 4.2 V vs Temperature
540
-7.50
520
25°C
0°C
125°C
-7.70
-7.90
-8.10
-8.30
-8.50
125°C
25°C
500
480
460
-20°C
440
4.0
4.5
5.0
5.5
6.0
2.75 3.00 3.25 3.50 3.75 4.00 4.25
CHG_DET PIN VOLTAGE (V)
VBATT (V)
CHG_DET = 5 V
CC
Figure 3. TS Pin Current vs CHG_DET
Figure 4. CHG vs VBATT
55.0
56.0
54.0
52.0
50.0
48.0
25°C
53.0
51.0
49.0
47.0
45.0
25°C
0°C
125°C
0°C
125°C
1.0
1.5
2.0
2.5
3.0
4.0
4.5
5.0
5.5
6.0
USBPWR (V)
VBATT(V)
Prequal IPROG = 500 mA
Figure 5. IU vs VBATT
CHG_DET = 5 V
VBATT = 2.5 V Prequal
Figure 6. ICHG vs USBPWR
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Battery-Charger Characteristics (continued)
540
540
520
500
480
460
440
520
0°C
500
25°C
480
460
440
125°C
0
25
50
75
100
125
150
4.0
4.5
5.0
CHG_DET (V)
5.5
6.0
JUNCTION TEMPERATURE (°C)
VBATT = 3.75 V, CC
CHG_DET = 5 V
VBATT = 3.5 V, CC
Figure 8. ICHG vs Temperature
Figure 7. ICHG vs CHG_DET
600
500
400
300
200
100
0
55.0
53.0
51.0
49.0
47.0
45.0
Active Thermal Regulation
0
25
50
75
100
125
150
80
90
100
110
120
130
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
VBATT = 3.75 V, Prequal
CHG_DET = 5 V
Figure 10. Thermal Regulation of Charge Current
Figure 9. ICHG vs Temperature
520
500
480
460
440
420
0
25
50
75
100
125
150
JUNCTION TEMPERATURE (°C)
Ch1 = Charge Current (mA)
Ch3 = CHG_DET (V)
Ch4 = USBPWR (V)
Figure 11. USB ILIMIT vs Temperature
Figure 12. Wall Adapter Insertion With USBPWR Present
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7.21.2 LDO Characteristics
1.0
0.5
1.0
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
-40 -25 -10
5
20 35 50 65 80 95 110125
-40 -25 -10 5 20 35 50 65 80 95 110125
TEMPERATURE (°C)
TEMPERATURE (°C)
VIN = 4.3 V
VOUT = 3.3 V
Load = 100 mA
VIN = 4.3 V
VOUT = 1.8 V
Load = 100 mA
Figure 13. Output Voltage Change vs Temperature (LDO1)
Figure 14. Output Voltage Change vs Temperature (LDO2)
VIN = 3.6 V
VOUT = 3.3 V
Load = 0 to 100 mA
VIN = 3.6 V
VOUT = 1.8 V
Load = 0 to 100 mA
Figure 15. Load Transient (LDO1)
Figure 16. Load Transient (LDO2)
VIN = 3 to 4.2 V
VOUT = 1.8 V
Load = 150 mA
VIN = 3.6 to 4.5 V
VOUT = 3.3 V
Load = 150 mA
Figure 18. Line Transient (LDO2)
Figure 17. Line Transient (LDO1)
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7.21.3 Buck Characteristics
3.35
2.05
I
= 20 mA
OUT
3.33
3.31
3.29
3.27
3.25
2.04
I
= 600 mA
OUT
= 300 mA
I
= 600 mA
OUT
I
OUT
I
= 20 mA
2.03 OUT
2.02
2.01
I
= 300 mA
4.6
OUT
2.00
3.0
3.5
4.0
4.5
5.0
5.5
4.0
4.3
4.9
5.2
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
VOUT = 3.3 V
VOUT = 2 V
Figure 19. Output Voltage vs Supply Voltage
Figure 20. Output Voltage vs Supply Voltage
0.825
1.25
0.820
0.815
0.810
1.24
I
= 600 mA
OUT
I
= 300 mA
OUT
1.23
1.22
1.21
1.20
I
= 20 mA
OUT
I
= 600 mA
OUT
0.805
0.800
I
= 300 mA
OUT
I
= 20 mA
OUT
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
VOUT = 0.8 V
VOUT = 1.2 V
Figure 22. Output Voltage vs Supply Voltage
Figure 21. Output Voltage vs Supply Voltage
100
90
Vin = 3.2 V
Vin = 3.2 V
90
80
Vin = 4 V
Vin = 4 V
80
70
Vin = 5 V
Vin = 5 V
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
0.1
1.0
10
100
1000
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
VOUT = 1.2 V
L = 2.2 µH Forced PWM Mode
VOUT = 2 V
L = 2.2 µH
Forced PWM Mode
Figure 23. Buck1 Efficiency vs Output Current
Figure 24. Buck 1 Efficiency vs Output Current
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Buck Characteristics (continued)
85
95
90
85
80
75
70
65
60
55
50
Vin = 3.2 V
Vin = 3.2 V
Vin = 4 V
Vin = 5 V
80
Vin = 4 V
75
Vin = 5 V
70
65
60
55
50
45
40
0.1
1.0
10
100
1000
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
VOUT = 1.2 V
L = 2.2 µH
PFM-to-PWM Mode
VOUT = 2 V
L = 2.2 µH
PFM-to-PWM Mode
Figure 25. Buck1 Efficiency vs Output Current
Figure 26. Buck1 Efficiency vs Output Current
VIN = 4.2 V
PWM Mode
VOUT = 1.2 V
Load = 200 to 400 mA
VIN = 4.2 V
PFM-to-PWM Mode
VOUT = 1.2 V
Load = 50 to 150 mA
Figure 27. Buck1 Load Transient Response
Figure 28. Buck1 Load Transient Response
VIN = 4.2 V
VOUT = 3.3 V
Load = 50 to 150 mA
VIN = 4.2 V
PWM Mode
VOUT = 3.3 V
Load = 0 to 400 mA
PFM-to_PWM Mode
Figure 30. Buck2 Load Transient Response
Figure 29. Buck2 Load Transient Response
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Buck Characteristics (continued)
VIN = 3 to 3.6 V
VOUT = 1.2 V
Load = 250 mA
VIN = 3 to 3.6 V
VOUT = 3.3 V
Load = 250 mA
Figure 31. Line Transient Response
Figure 32. Line Transient Response
VOUT = 1.8 V
Load = 30 mA
VOUT = 3.3 V
Load = 30 mA
Figure 33. Start-up into PWM Mode
Figure 34. Start-up into PWM Mode
VOUT = 1.8 V
Load = 30 mA
VOUT = 3.3 V
Load = 30 mA
Figure 35. Start-up Into PFM Mode
Figure 36. Start-up Into PFM Mode
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7.21.4 Buck-Boost Characteristics
100
95
100
80
60
40
20
0
90
V
= 3.3 V
V
BATT
= 2.7 V
85
80
75
70
65
60
OUT
V
= 1.8 V
OUT
V
BATT
= 3.3 V
V
= 4.2 V
BATT
0.1
1
10
100
1000
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
OUTPUT CURRENT (mA)
V
IN
VOUT = 3.3 V
ILOAD= 100 mA
Figure 38. Forced PWM Efficiency vs ILOAD
Figure 37. Efficiency vs VIN
100
100
V
= 4.2 V
V
IN
= 2.7 V
IN
90
80
70
60
90
80
70
60
50
V
IN
= 2.7 V
V
IN
= 3.3 V
V
IN
= 3.6 V
V
= 4.2 V
IN
50
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
VOUT = 1.8 V
Figure 40. Automode Efficiency vs ILOAD
VOUT = 3.3 V
Figure 39. Automode Efficiency vs ILOAD
VIN = 4.2 V
VOUT = 3.3 V
ILOAD = 250 mA
VIN = 3.6 V
VOUT = 3.3 V
ILOAD = 250 mA
Figure 41. Switch Pins in Buck Mode Operation
Figure 42. Switch Pin on Edge of Buck Mode Operation
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Buck-Boost Characteristics (continued)
VIN = 3.35 V
VOUT = 3.3 V
ILOAD = 250 mA
VIN = 3.2 V
VOUT = 3.3 V
ILOAD = 250 mA
Figure 43. Switch Pin on Edge of Boost Mode Operation
Figure 44. Switch Pins in Boost Mode Operationa
VIN = 4.2 V
VOUT = 3.3 V
ILOAD = 0 to 500 mA
VIN = 3.6 V
VOUT = 3.3 V
ILOAD = 0 to 500 mA
Figure 45. Load Transient, Buck Response
Figure 46. Load Transient, Edge of Buck Response
VIN = 2.7 V
VOUT = 3.3 V
ILOAD = 0 to 500 mA
VIN = 3 V to 3.6 V
VOUT = 3.3 V
ILOAD = 500 mA
Figure 47. Load Transient, Boost Response
Figure 48. Line Transient, Boost Response
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8 Detailed Description
8.1 Overview
The LP3910 incorporates 2 low-dropout LDO voltage regulators, 2 integrated buck DC-DC converters with
dynamic voltage scaling (DVS), one wide load range buck-boost DC-DC converter with programmable output
voltage, a 4-channel 8-bit ADC and a dual source Li-ion or Li-polymer battery charger. The charger has the
capability to charge and maintain a single cell battery by seamlessly switching between regulated wall adapter
and USB power sources. The LP3910 also incorporates advanced battery management functions such as battery
temperature measurement, reverse current blocking for USB, LED charger status indication, thermally regulated
internal power FETs, battery-voltage monitoring, overcurrent protection, and a 10-hour safety timer.
The buck-boost DC-DC converter targets the power management of hard disk drives and maintains a typical
operating voltage of 3.3 V ±5% with a battery voltage below or above this output level. The buck- boost output
voltage can be selected to be as low as 1.8 V.
The 4-channel ADC measures the battery voltage and charge current, which can be used for fuel gauging. Two
undedicated channels can be used to measure other analog parameters such as discharge current, battery
temperature, keyboard resistor scanning and more. The various device parameters are programmable through a
400-kHz I2C-compatible interface.
8.1.1 Two Buck Converters
The LP3910 incorporates two high efficiency synchronous switching buck regulators, Buck1 and Buck2 that
deliver a constant voltage from a wall adapter or a single Li-ion battery to the portable system processors,
memory and I/O. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to
deliver up to 600 mA. Buck1 can output voltages from 0.8 V to 2 V while Buck2 can output voltages from 1.8 V to
3.3 V. Additional features include soft-start, undervoltage lockout, current-overload protection, and thermal-
overload protection.
8.1.2 Buck-Boost Converter
The synchronous buck-boost magnetic DC-DC converter supplies power to a hard drive that has a typical 3.3-V
operating voltage. This voltage is lower than the maximum battery (4.2 V typically for Li-polymer cells) and higher
than the minimum battery (typically 2.8 V). Therefore, in order to provide 3.3 V, regardless of the battery voltage,
the buck-boost converter either steps down the battery voltage or steps up the battery voltage. The buck-boost
automatically switches between PWM and PFM modes depending on the load and automatically switches
between buck and boost modes depending on the battery voltage. The buck-boost converter uses an input
voltage from 2.7 V to 5.7 V and generates an output voltage between 1.8 V and 3.3 V for up to 1-A loads.
8.1.3 LDO Regulators
LDO1 is a regulator that can respond to fast transients and is slated for digital loads and high bandwidth analog
loads. LDO2 is a linear regulator with a similar architecture but has a slower transient response time with a lower
noise performance to supply analog loads. Both regulators can supply up to 150-mA loads and have output
voltages that are register programmable through the I2C interface. The LDO1 output voltage is programmable
from 1.2 V to 3.3 V, and the LDO2 output voltage is programmable in steps of 100 mV from 1.3 V to 3.3 V.
8.1.4 Battery Charger
The LP3910 can safely charge and maintain a single-cell Li-ion or Li-polymer battery operating off a regulated 6-
V automotive adapter, an AC wall adapter, or USB power (VBUS). Input power source selection of USB/adapter
is seamless. If present, the charger uses the adapter power regardless of the presence of USB power. The
connection of either power source is detected by LP3910. The charger module is a linear charger with constant
current pre-qualification, constant current (CC) full-rate charging and constant voltage (CV) charging. CC and CV
regulation is performed using an internal power FET Q2 with reverse current blocking. The power FET Q1 acts
as a switch with programmable current limit for USB operation.
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Overview (continued)
8.1.5 ADC
The LP3910 is equipped with an 8-bit dual-slope integrating analog-to-digital converter (ADC). Dual-slope
converters provide effective filtering of > 500-kHz and < 125-kHz noise components on the input voltage and do
not require a sample-and-hold stage. The ADC core digitizes the input voltage ranging from VREF to 2 × VREF
,
where VREF is the voltage measured on the VREFH pin.
8.1.6 Supply Specification
Table 4 lists the output characteristics of various regulators.
Table 4. Supply Specification
VOUT (V)
IMAX MAXIMUM
OUTPUT CURRENT
(mA)
SUPPLY
LOAD
DEFAULT (V)
RANGE (V)
RESOLUTION (mV)
LDO1
LDO2
various
analog
1.2 to 3.3
1.3 to 3.3
0.8 to 2
100
100
50
150
150
600
600
1000
Factory-programmed
default
Buck1
CPU, DSP
I/O, logic, memory
HD
Buck2
1.8 to 3.3
1.8 to 3.3
100
50
Buck-Boost
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8.2 Functional Block Diagram
ADC1 12
ADC2 11
36 VIN4
35 VBBL1
33 VBBL2
32 VBBOUT
31 VBBFB
34 BBGND1
39 BBGND2
22 VIN3
VDD2 42
ADC
BUCK
BOOST
VDD3 41
VBATT3 43
VBATT2 44
ISENSE 10
CHG_DET 47
USBPWR 45
23 VBUCK2
25 VFB2
BUCK2
LINEAR
CHARGER
VDD1 46
24 BCK2GND
21 VIN2
VBATT1
TS
2
1
4
BATTERY
MONITOR
20 VBUCK1
18 VFB1
BUCK1
VREFHI
VREFH
17 BUCK1EN
19 BCK1GND
OSC
TSD
IREF 48
VDDIO 28
IREF
5
6
7
8
LDO2EN
VLDO2
VIN1
LDO2
LDO1
USBSUSP 37
USBISEL 38
CHG 15
VLDO1
LOGIC
STAT 16
30 ONSTAT
14 NRST
13 IRQB
ONOFF 26
I2C_SCL 27
I2C_SDA 29
I2C
9
POWERACK
3
40
AGND
DGND
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8.3 Feature Description
8.3.1 Buck1, Buck2: Synchronous Step-Down Magnetic DC-DC Converters
The LP3910 incorporates two high-efficiency synchronous switching buck regulators, Buck1 and Buck2, that
deliver a constant voltage from a wall adapter or a single Li-ion battery to the portable system processors,
memory and I/O. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to
deliver up to 600 mA depending on the input voltage and output voltage (voltage headroom), and the inductor
chosen (maximum current capability).
There are three modes of operation depending on the current required: PWM, PFM, and shutdown. PWM mode
handles current loads of approximately 70 mA or higher, delivering voltage precision of ±3% with 90% efficiency
or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current
consumption (IQ = 15 µA typical) and a longer battery life. The Standby operating mode turns off the device,
offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be
forced through the setting of the buck control register.
Both Buck1 and Buck2 can operate up to a 100% duty cycle (PMOS switch always on). Additional features
include soft-start, undervoltage lockout, current overload protection, and thermal overload protection.
8.3.1.1 Buck1, Buck2 Operation
Buck1 is recommended to be used as the processor core supply and has I2C selectable output voltages ranging
from 0.8 V to 2 V (typical). Buck2 is recommended for I/O power, Memory power and logic power. Its voltage
range can be programmed using the I2C interface from 1.8 V to 3.3 V (typical). The default output voltage for
each buck converter is factory programmable (see Application and Implementation).
The system designer can also determine the output voltage of either Buck1 or Buck2 through an external
feedback resistor ladder by clearing the output voltage selection field in the Buck1 or Buck2 control registers.
Lsw
VBUCK
Load
Csw
R1
Cff
VFB
R2
BCKGND
Figure 49. External Control Of Buck Output Voltage Through Feedback Resistor Ladder
8.3.1.2 Circuit Operation Description
A buck converter contains a control block, a switching PFET connected between input and output, a synchronous
rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first
portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow
from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of VIN – VOUT / L.
by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET
switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor
current down with a slope of –VOUT / L.
The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage
across the load.
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Feature Description (continued)
8.3.1.3 PWM Operation
During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This
allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional
to the input voltage. To eliminate this dependence, feed-forward voltage inversely proportional to the input
voltage is introduced.
8.3.1.4 Internal Synchronous Rectification
While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier
diode.
8.3.1.5 Current Limiting
A current limit feature allows the buck to protect itself and external components during overload conditions PWM
mode implements cycle-by-cycle current limiting using an internal comparator that trips at 1000 mA (typical).
8.3.1.6 PFM Operation
At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply
current to maintain high efficiency.
The device automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or
more clock cycles:
The inductor current becomes discontinuous or the peak PMOS switch current drops below the IMODE level:
VIN
(Typically IMODE < 66 mA +
)
160W
(1)
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output
voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on.
It remains on until the output voltage exceeds the high PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The typical peak current in PFM mode is:
VIN
+
IPFM = 66 mA
80W
(2)
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the high PFM comparator threshold (see Figure 50), the PMOS switch is again turned on and
the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM
threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output
switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this
sleep mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load
conditions. When the output drops below the low PFM threshold, the cycle repeats to restore the output voltage
to approximately 1.6% above the nominal PWM output voltage.
If the load current increases during PFM mode (see Figure 50) causing the output voltage to fall below the ‘low2’
PFM threshold, the device automatically transitions into fixed-frequency PWM mode.
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Feature Description (continued)
PFM Mode at Light Load
High PFM Threshold
approx. 1.016 x VOUT
Load
current
increases
Low1 PFM Threshold
approx. 1.008 x VOUT
Current load increases,
draws VOUT towards
Low2 PFM Threshold
Low PFM
Threshold,
turn on
NFET on
drains inductor
until
High PFM
Voltage
Threshold reached,
go into
PFET on
until
PFET
Ipfm limit
reached
I inductor=0
sleep mode
Low2 PFM
Threshold VOUT
Low2 PFM
PWM Mode at
Moderate to Heavy
Loads
Threshold,
switch back to
PWMmode
Figure 50. Operation in PFM Mode and Transfer to PWM Mode
8.3.2 Buck-Boost: Synchronous Buck-Boost Magnetic DC-DC Converter
The LP3910 is equipped with a synchronous buck-boost magnetic DC-DC converter to supply power to the hard
drive that has a typical 3.3-V operating voltage. This voltage is lower than the maximum battery (4.2 V typically
for Li-polymer cells) and higher than the minimum battery (typically 2.8 V). Therefore, in order to provide 3.3 V,
regardless of the battery voltage, the Buck-Boost converter either steps down the battery voltage or steps up the
battery voltage. The Buck-Boost automatically switches between PWM and PFM modes depending on the load
and automatically switches between buck and boost modes, depending on the battery voltage.
By setting bit D6 of the Buck-Boost control register, the Buck-Boost is forced to operate using PWM modulation
regardless of the load. By default this bit is cleared.
35
VBBL
1
Lbb
2.2 mH
33
32
BUCK/
BOOST
VBBL
2
VBBOUT
VBBFB
LOAD
Cbb
22 mF
31
Figure 51. Schematic Section for Buck-Boost Operation
8.3.3 Linear Low Dropout Regulators (LDOs)
LDO1 is a regulator that can respond to fast transients and is slated for digital loads and high bandwidth analog
loads. LDO2 is a linear regulator with a similar architecture but has a slower transient response time with a lower
noise performance to supply analog loads. The output voltages of both LDOs are register programmable through
the I2C interface. The default output voltages are factory programmed during final test.
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Feature Description (continued)
VIN
VLDO
LDO
Register
controlled
-
VREF
AGND
Vref
Figure 52. LDO Architecture Diagram
8.3.3.1 No-Load Stability
The LDOs remain stable and in regulation with no external load. This is an important consideration in some
circuits, for example, CMOS RAM keep-alive applications.
8.3.4 Li-Ion Linear Charger
8.3.4.1 Charger Architecture
The LP3910 can safely charge and maintain a single cell Li-ion or Li-polymer battery operating from a regulated
6-V car adapter, AC wall adapter, or USB power (VBUS). Input power source selection of USB/adapter is
seamless. If present, the charger uses the adapter power regardless of the presence of USB power. The
connection of either power source is detected by the LP3910 device.
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Feature Description (continued)
External or
USB Power
+
+
Iprog
CC
+
-
Batt
Thermal
+
regulation
Vref
+
-
Current
Control
Iref
CV
Li - Ion Cell
Ts
Vbatt Vref
Vrestart
Vfull
+
Ref 0.27V
Ref 2.87V
+
-
-
Charger
State
Machine and
registers
Batt_temp
+
+
-
-
I2C
CV: Constant Voltage regulation
CC: Constant Current regulation
Figure 53. Charger Architecture
The charger module is a linear charger with constant current pre-qualification, CC full-rate charging and CV
charging. CC and CV regulation is performed using an internal Power FET Q2 with reverse current blocking. The
termination voltage is controlled to within ±0.35% at room temperature.
The power FET Q1 acts as a switch with programmable current limit for USB operation.
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Feature Description (continued)
VDD
Adapter
CHG_DET
USBPWR
USB
Q1
Q2
VBATT
Li-Ion Cell
-
Figure 54. Switches for USB Charging Path
8.3.4.2 Charge Status Indication
Two LEDs connected to the LP3910 are used to indicate the status of the charging. The CHG pin is connected to
a red LED that is enabled when an external power source is connected and the battery is charging. The second
STAT pin is connected to a green LED. When the battery charging transitions from CC to CV mode, then the
green LED is blinking with a 50% duty cycle and a period of 1 second. When the battery is fully charged, then the
green LED is always on.
Both LEDs are off when there is no external power connected.
Table 5. Truth Table for the LED Status Indicators
CONDITION
No Charger or USB
RED LED
GREEN LED
OFF
OFF
OFF
Charger off
ON
Pre-Qualification
ON
OFF
Constant Current CC
ON
ON
OFF
Constant Voltage CV
50% duty cycle
ON
EOC / Top-OFF charging
Charge cycle complete
ERROR (Battery Temperature, Thermal shutdown)
Safety Timer Expired
ON
ON
ON
50% duty cycle
50% duty cycle
OFF
OFF
50% duty cycle indicates the LED is pulsed on and off for equal times at a frequency of 1 Hz.
The RED pin and GREEN pin are connected to a regulated driver to ensure that the brightness is independent
from the external power. The LEDs need to be connected between the CHG and STAT pins and GND.
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8.3.4.3 Thermal Charger Power FET Regulation
The internal power FET Q2 in the linear charger module is thermally regulated to the junction temperature of
115°C to ensure optimal charging of the battery. The charge current is limited by the charge current selected in
the charger control register but is also thermally limited to prevent the junction from overheating during high
charge currents at high ambient temperatures as the package power dissipation is limited.
Thermal regulation ensures maximum charge current and superior charge rate without exceeding the power
dissipation limits of LP3910 device.
8.3.4.4 Battery Charger Operating Modes
8.3.4.4.1 Pre-Qualification Mode
Lithium batteries cannot be subjected to a high current when the battery voltage is under a certain threshold,
otherwise the longevity of the battery would be compromised. Below this threshold of VFULLRATE, which typically
measures 2.85 V, the charger circuit supplies a pre-qualification charge current. If the wall adapter is charging
the battery, the charger circuit supplies a constant current of 10% of the programmed charge current. If the USB
is charging the battery, the charger circuit supplies a constant 50-mA charge current. When the battery voltage
reaches VFULL_RATE, the charger transitions from pre-qualification to full-rate charging. In pre-qualification mode,
the STAT2, STAT1, and STAT0 bits in the charger supervisory register are respectively low, low, high.
8.3.4.4.2 Full-Rate Charging Mode
The full-rate charge cycle is initiated following the successful completion of the pre-qualification mode. During
full-rate charging, the battery voltage steadily increases while charged with a CC. The three charger status bits
STAT2, STAT1, and STAT0 are respectively low, high, and low. The full-rate charge current is selected using the
charge control register, which defaults to 100 mA.
Charging Li-ion batteries at a rate of 1C is recommended (where C is the capacity of the battery). As an
example, it is recommended to charge a battery with a capacity of 800 mA at 800 mA, or 1C. Charging at a
higher rate may compromise the quality and lifetime of the battery.
8.3.4.4.3 Constant-Voltage (CV) Charging Mode
The battery voltage increases rapidly as a result of full-rate charging and once it reaches the programmable
termination voltage of either 4.1 V, 4.2 V or 4.38 V, the charger moves to constant-voltage charge mode. During
this mode, the charge current gradually decreases while the battery remains at the termination voltage. The
termination voltage can be selected to be either 4.1 V, 4.2 V or 4.38 V by programming bits D6 and D7 in the
Charger Control register to accommodate different battery chemistries. In CV charging mode, the Charge Control
Status bits STAT2, STAT1 and STAT0 are respectively logic 0, logic 1, and logic 1.
8.3.4.4.4 Top-Off Charging Mode
When the charge current reduces to the EOC threshold (programmable to 5% or 10% of programmed full rate
charge current), constant voltage charging continues for an additional 21 minute TOP-OFF time period. In TOP-
OFF charging mode, the Charge Control Status bits STAT2, STAT1 and STAT0 are respectively logic 1, logic 1
and logic 1. At the end of the TOP-OFF period, the charger transitions to Charge Cycle Complete.
8.3.4.4.5 Charge Cycle Complete
During charge cycle complete, the charger is automatically disabled, regardless of the state of the charge enable
bit. In charge cycle complete, the STAT2, STAT1 and STAT0 bits are respectively logic 1, logic 0, and logic 1.
When the battery voltage drops below the VRESTART threshold, charging resumes in full-rate charging mode.
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Battery voltage
1.0C
Battery charge current
Termination voltage
4.1V, 4.2V or 4.38V
Charging restart voltage
3.9V, 4.0V or 4.2V
2.85V
0.1 C PREQUAL CURRENT
0.05 C EOC CURRENT
Time
0V
Full Rate
CV
Full Rate
Constant Voltage Charging
Topoff
Battery discharge
Pre-qualification
End-Of-Charge
(EOC)
RED LED
ON
OFF
ON
ON
ON
GREEN LED
ON
OFF
50% Duty cycle
Figure 55. Charge Cycle Complete
8.3.4.5 Battery Temperature Monitoring (TS Pin)
The LP3910 is equipped with a battery thermistor terminal to continuously monitor the battery temperature by
measuring the voltage between the TS pin and GND. With the TS pin connected to the battery thermistor,
charging is allowed only if the battery temperature is within the acceptable temperature range set by a pair of
internal comparators inside the LP3910. The temperature window is 0°C to 45°C or 0°C to 50°C, depending on
the setting of D2 of the charger supervisory (CHSPV) register. There is 3°C of temperature hysteresis associated
with each temperature threshold. The default temperature range is 0°C to 50°C and can be changed to 0°C to
45°C by setting bit D3 in the CHSPV register. If the battery temperature is out of range, STAT2, STAT1, and
STAT0 bits in the CHSPV register are set to logic1, logic0, logic0, and charging is suspended.
The TS pin is only active during charging and draws no current from the battery when no external power source
is present.
If the TS pin is not used in the application, it must be connected to GND through a 100-kΩ pulldown resistor.
When the TS pin is left floating (battery removal), the charger is disabled as the TS voltage exceeds the lower
temperature limit.
Ts
ntc
hiRef
loRef
+
-
Logic
charger
control
+
-
Figure 56. Battery Temperature Monitor with TS Pin
8.3.4.6 Disabling Charger
Charging can be safely interrupted by clearing the Charge enable bit D1 in the Charge Control Register and can
subsequently resume upon setting this bit. When the charger is disabled, STAT2, STAT1, and STAT0 bits in the
CHSPV register are set to logic 0.
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8.3.4.7 Safety Timer
In order to prevent endless charging, which could degrade the battery quality and life time, the LP3910 contains
a safety timer that limits charging regardless whether the battery has reached its full capacity or not. In
prequalification the safety timer is 1 hour. In full rate or constant voltage charging the safety timer is a maximum
of 10 hours minus the time in prequalification.
When the timer times out of uninterrupted charging, an IRQ is generated to alert system processor. The status of
the timer can also be polled by reading the IRQ register if the system doesn’t support hardware interrupts.
The safety timer resets and starts counting from zero upon the following events:
1. Power ON (through connecting valid power to either USBPWR or CHGN_IN pins).
2. Interchanging USBPWR and CHG_IN sources.
3. The voltage of a charged battery drops below the restart value, and the charger is enabled.
4. Disabling and re-enabling of the charger by toggling bit D1 of the Charge Control Register.
5. Emerging from thermal shutdown.
6. Emerging from a battery temperature out-of-range, and the charger is enabled.
7. Emerging from USB suspend mode when charging with USB power.
8.3.4.8 Charging Maintenance
When a fully charged battery is being loaded by the system while the external power is present and while bit D1
in the charge control register is set to a 1 (charge enable) then the charging restarts when the battery voltage
drops below the charging restart threshold. The value of the threshold depends on the termination voltage
according to the following table:
Table 6. Charging Thresholds
VTERM
4.1 V
CHARGING RESTART VOLTAGE
3.9 V
4 V
4.2 V
4.38 V
4.2 V
8.3.5 ADC
The LP3910 is equipped with an 8-bit dual-slope integrating an ADC. Dual-slope converters provide effective
filtering of > 500-kHz and < 125-kHz noise components on the input voltage, and does not require a sample and
hold stage. The ADC core digitizes the input voltage ranging from VREF to 2VREF, where VREF is the voltage
measured on the VREFH pin. After an initial 2-ms warm-up for the first activation of the ADC enable bit, the dual-
slope converter integrates the input signal during the first phase for approximately 2 ms, followed by a second
phase that integrates VREF for 0 ms to 2 ms depending on the level of the input signal. As a result the total
conversion time varies from 2 ms to 4 ms.
START
Enable
8 Bit ADC
1&2
or
1&3
Integrator
Comparator
Dready
Overflow
Data
VO
Vsignal
+
-
2
1
+
-
Control
Logic
Vbias
3
Figure 57. Simplified ADC Block Diagram
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The ADC multiplexes 4 different sources:
1. The battery voltage
2. The battery charge current
3. External source ADC1
4. External source ADC2
The voltage ranges for the first two sources are scaled to match the input voltage interval of the ADC: [VREFH
,
2VREFH]. This is accomplished by using two internal scalars.
8.3.5.1 Battery Voltage Measurement
The battery voltage scalar transforms the battery voltage ranging from 2.6 V to 3.5 V to the reference voltage
interval: [VREFH, 2*VREFH]. A wider voltage range (2.6 V to 4.4 V) can be selected through I2C by setting the
voltage range bit D7 in register 0xA to 0’b1.
8.3.5.2 Battery Charge Current Measurement
The battery charge current is indirectly measured by measuring the voltage across the ISENSE resistor, RSENSE
.
A fixed portion of the battery charge current is mirrored over the RSENSE as in Equation 3:
VISENSE = K × ICHARGE × RSENSE
(3)
where K is a ratio between the ISENSE current and the charge current.
The battery charge current scalar transforms the voltage across the external ISENSE resistor to the [VREFH, 2 ×
VREFH] input voltage interval of the ADC.
VDD
1:4343
ADC
ISENSE
Vbatt
Rsense
Charge
control Loop
Figure 58. Battery Charge Scalar
8.3.5.3 External General-Purpose Sources
Two additional ADC sources are available on the ADC1 and ADC2 pins of the LP3910. These two external ADC
sources are not internally scaled and have an input voltage range of [VREFH, 2 × VREFH]. The system designer can
use these two sources for general-purpose applications such as resistive keyboard matrix scanning, temperature
measurements, battery load current, battery ID resistor measurement, and others.
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VBATT
ISET
MUX_CONTROL
2
Current range 0 / 1
Icharge
Scaler
Vbatt
Scaler
ADC
MUX
To ADC
core
Voltage range 0 / 1
ADC1
ADC2
Figure 59. ADC Analog Front-End Block Diagram
The source selection and the access to the conversion results are established through the I2C linked control
registers: ADCC and ADCD.
The ADC is by default disabled to minimize current consumption and must be enabled by setting D2 in the ADCC
register. Writing a logic 1 to bit D3 in the ADC initiates a conversion. It is advised to select the correct ADC
source before a conversion is started. The ADC sets bit D4 in the ADCC register upon the completion of a
conversion, which is typically 4 ms after the start of the conversion. At the same time an interrupt request is
generated. (See IRQ Register (0d)H Interrupt Request Register).
To save power, disable the ADC by setting bit 2 of D2 to 0. To make repetitive starts, set bit D3 to 0 then to 1 for
register 0Ah to initiate start of conversion. The interrupt driven protocol between LP3910 and the system
processor is the most efficient way to acquire data from successive measurements as shown in Figure 60:
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Start
I2C
transfers
CPU sends start
conversion command
to ADC
start
stop
cid
reg
data
Select adc source
ADC executes
conversion request
Conversion done
pulls down IRQB
line
System CPU
services IRQ
stop
start
start
Cid/R
stop
reg
cid
cid
reg
reg
start
data
CPU reads data
CPU
sends next
Y
start conversion
command
?
N
End
Figure 60. Data Measurement and Acquisition Sequence
8.3.6 Interrupt Request Output
The LP3910 has the ability to interrupt the system processor through the open drain IRQB pin, which transitions
to an active logic low level upon the following 8 events:
•
•
•
•
•
•
•
•
USB Power detected
USB disconnected
CHG_IN Power detected
CHG_IN disconnected
Battery low alarm
Thermal alarm
ADC conversion completed
Charger safety timer time-out
The events form the interrupt sources that correspond to a certain bit location in the interrupt request (IRQ)
register. All interrupt sources can be masked by the interrupt mask register (IMR). Masking the interrupt prevents
the interrupt event from asserting the IRQB pin, yet the event is still captured in the IRQ register, which allows
the processor to poll the interrupt sources.
After an active low IRQB has been detected by the system processor, the latter services the interrupt and
accesses the IRQ register to determine which source was responsible for the interrupt request. Reading the IRQ
register automatically clears the register to enable the capture of the next interrupt events.
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As new interrupts can occur while the I2C read cycle is clearing the IRQ register, a buffer register called interrupt
pending register (IPR), not accessible through the I2C-compatible interface holds the next interrupts. De-
asserting the IRQB output is immediately followed by a new transition of IRQB to logic low when an interrupt is
pending.
The Interrupts are not hardware prioritized. It is up to the firmware to determine the priority in case more than
one interrupt request is set.
Interrupt
sources
IMR
IRQ
CHG_IN power
detected
int0
int1
int2
int3
int4
int5
int6
int7
CHG_IN power
removed
USB Power
detected
IRQB
USB Power
removed
Battery Low
Thermal alarm
ADC conversion completed
Charger
safety timer
timeout
Interrupt
Pending
register
Figure 61. Interrupt Request Setting
8.3.6.1 Interrupts and Standby Mode
Interrupts are captured in standby mode and can be serviced when the system processor is enabled when the
LP3910 is in an active state.
8.3.6.2 Interrupt Sources
•
CHG_IN Power Detected and CHG_IN Disconnect (INT0 and INT1): An interrupt (INT0) is generated when
CHG_IN power is connected to the LP3910. Another interrupt (INT1) is generated upon CHG_IN power
removal.
•
•
USB Power Detected and USB Disconnect (INT2 and INT3): An interrupt (INT2) is generated when USB
power is connected to the LP3910. Another interrupt (INT3) is generated upon disconnecting the USB power.
Battery Low (INT4): When the battery voltage drops below the battery low threshold IRQ, an interrupt is
generated. This allows the processor to perform some routine tasks prior to going to standby mode.
•
•
Thermal Alarm (INT5): If the junction temperature of the LP3910 exceeds 115°C, an interrupt is generated.
ADC Conversion Done (INT6): The ADC generates an interrupt request upon the completion of a data
conversion.
•
Charger Timer Interrupt (INT7): A charger timeout occurs 10 hours after it started (see Li-Ion Linear Charger)
and subsequently requests an interrupt.
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8.3.7 Power-On-Reset
The LP3910 is equipped with an internal power-on-reset (POR ) circuit that resets the logic when VDD < VPOR
.
This ensures that the logic is properly initialized when VDD rises above the minimum operating voltage of the
logic and the internal oscillator that clocks the sequential logic in the control section.
8.3.8 Thermal Shutdown and Thermal Alarm
An internal temperature sensor monitors the junction temperature of the LP3910. This sensor forcibly invokes
standby mode in the unusual case of the junction temperature of the silicon exceeding the normal operating level
due to excessive loads on all power regulators, the Li-ion charger, or due to an abnormally high ambient
temperature. The thermal shutdown threshold is 160°C.
The thermal shutdown is preceded by a thermal alarm that generates an interrupt request if unmasked. The
temperature threshold for triggering the alarm is 115°C.
8.3.9 NRST Pin
The NRST pin is an open-drain output and is active low during standby, power-off and charger standby modes.
The NRST timing is determined by a factory programmable counter.
8.3.10 Operation Without I2C Interface
Operation of the LP3910 without the I2C interface is possible if the system can operate with default values for the
DC-DC converters and the charge (see Table 3). The I2C-less system must use the POWERACK pin to power
cycle the LP3910.
8.3.11 I2C Master Power Concern
The processor that contains the I2C master must be powered by BUCK1 or LDO2 as these converters require no
I2C access to enable/disable them. If the I2C master were to be powered by a DC-DC converter that is
enable/disabled through a control register, then a corrupted application software execution could by accident
disable the power to the I2C master, which in this case has no means to recover. It is possible that the regulator
connected to VDDIO may accidentally disable, in which case the processor should recognize that communication
has been broken, then power down the system to allow for a clean restart.
8.3.12 System Operation When the Load Current Exceeds the USB or Adapter Current Limit
In the event that the system requires current that exceeds the current limit of either the USB or the adapter
source, then the battery can provide the extra power provided that it has been charged. It is clear that a long
sustained overload eventually discharges the battery such that its extra power is no longer be sufficient to
properly operate the system. This is the case when the system is for instance operated from a USB host with a
100-mA current limit.
8.3.13 Power Routing
The LP3910 power can originate from three different sources: Adapter power, USB power, or battery power. The
objective of the power routing is to be able to:
•
•
Operate the portable system from external power regardless of the battery voltage.
Operate the portable system from USBPWR when the battery exceeds the full-rate qualification threshold
voltage (VFULLRATE).
•
•
Concurrently charging and operating the system when external power is present
Seamless selection of Adapter or USB power as the primary external power source
Power Routing supports 4 modes:
1. A regulated external adapter power is present and concurrently supplies the system power and the battery
charger.
2. USB power is present and supplies the system and the battery.
3. USB power is present but the system demand exceeds the USB current limit, so that the battery provides the
additional power to operate the system.
4. The battery is the sole supply source to the system when no external power source is present
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The current flows in the different modes are realized through internal FETS and an external Schottky as shown in
Figure 62:
ADAPTER
VDD
USBPWR
Q1
Q 2
VBATT
Li- Ion Cell
-
Figure 62. Charging and Sourcing Current Paths
The current provided by the external adapter power or USB power, when inserted, first supplies the system load;
the remainder is used for charging.
The different paths are configured through two internal power FETs, Q1 and Q2, and an external Schottky diode.
Q1 is a power FET that is only active during USB charging. Q2 functions either as a linear power FET during
charging or as a low RDSON switch when no external power is present, and the battery discharges to supply
power to the system.
Table 7. Power Routing Options
POWER ROUTE
Q1
OFF
ON
Q2
Regulated adapter supply & battery
charging
Regulated
Regulated
ON
USB supply & battery charging
No external supply and battery
discharging
OFF
The power routing function allocates power to the system through the VDD pin and to the battery. VDD1, VDD2,
VDD3, VIN1, VIN2, VIN3, and VIN4 must be connected together externally. VBATT1, VBATT2, and VBATT3
must be connected together externally.
8.3.14 Battery Monitor
The battery voltage is monitored and invokes the power-off mode when the battery low threshold is breached for
more than 5 ms (typical). The battery-low threshold DEFAULT is factory programmed. The battery low threshold
range is 2.5 V to 3.5 V with steps of 50 mV. The battery-low threshold in the table below refers to a decreasing
battery voltage. The threshold when the battery voltage is transitioning out of the VBATTLOW is 50 mV (typical)
higher than the values listed in the table below due to a built-in hysteresis of 50 mV (typical).
The battery low IRQ is triggered 200 mV above the battery low alarm threshold that powers down the device.
This gives the user time for a controlled shutdown.
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8.3.15 External Power and Battery Detection
When a wall adapter is detected, regardless of the battery voltage, the LP3910 moves to the active mode and
the power-up sequencer is started. Similar to the ONOFF pin, there is a 32-ms deglitch time to ensure a clean
wall adapter detection and the system processor must set the PACK bit (D4) in the PON register or the
POWERACK pin within 128 ms (maximum) of the start of the power-up sequencer.
When USB PWR is detected, and the battery is above the low-battery-alarm threshold, the LP3910 moves to the
active mode, and the power-up sequencer is started. As with the ONOFF pin, there is a 32-ms deglitch time to
ensure a clean USB detection, and the system processor must set the PACK bit (D4) in the PON register or the
POWERACK pin within 128 ms (maximum) of the start of the power-up sequencer. If the battery is below the
low-battery-alarm threshold, the system remains powered down until the USBPWR charges the battery up to the
low-battery-alarm threshold, at which point the power-up sequencer is started.
The four LSB bits of the PON register indicate which PON source moves the LP3910 device out of standby and
into active mode:
•
•
•
•
Battery insert
ONOFF push button
CHG_IN detect (connection of power adapter)
USB power (plug-in of powered USB cable)
These bits are cleared upon powering off.
Power Up Sequence
t0 t1 t2
t3 t4
t5
CHG_DET/USBPWR
External
Events
or
32 ms
ONOFF
deglitch
ONSTAT
(To Microprocessor)
32 ms
deglitch
VLDO1, VLDO2
(If LDO2ENB is logic 1 during NRST Low,
otherwise LDO2 are register or pin enabled)
T1
T2
T3
VBUCK1
VBUCK2
BUCK/BOOST
NRST
T4
T5
POWERACK
(From Microprocessor)
(Bit D4 in PON register or
POWERBACK pin)
128 ms
POWERACK deadline
5 ms
VREFH
Figure 63. Power-Up Sequence
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8.3.16 USB Suspend Mode
The LP3910 USB current consumption can be disabled during suspend mode through a dedicated pin
(USBSUSP). Applying a logic 1 to this pin disables the USB current path, and current is reduced to input leakage
current less than 30 µA on the USBPWR pin.
8.3.17 Setting the USB Current Limit
The USB current that is available from the USB on the VBUS wire is limited by default to 100 mA. More current
(up to 800 mA) can be negotiated through a session request protocol between host and peripheral. The USB
current limit must be signaled to the LP3910 by means of the USBISEL pin or the ILIMIT register as indicated
below:
•
If the USB current limit is 100 mA then the USB controller of the peripheral system must set the USBISEL
logic 0 or by setting the ILIMIT register bits [D1, D0] to 2’b00.
•
If the USB current limit is 500 mA, the USB controller must apply logic 1 to the USBISEL pin or change the
ILIMIT register accordingly. Under this condition, the LP3910 allows charging with a charge current that is
determined by the charge control register, not exceeding 500 mA.
The LP3910 prevents (through internal circuitry) the charge current from exceeding the USB current limit, even if
the current setting in the Charge Control Register exceeds 500 mA.
The controller can also select a USB current limit of 800 mA through I2C that exceeds current USB spec values.
8.3.18 Control Registers
The LP3910 contains 14 user-programmable registers that configure the functionality of the individual modules
inside the device. Registers are programmed through an I2C interface and have default values that are invoked
during an internal reset. Some of the default values can be tailored to the specific needs of the system designer.
8.4 Device Functional Modes
The LP3910 can be in 3 different operating modes as shown in Figure 64:
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Device Functional Modes (continued)
BATTERY INSERT VBATT> VBLA
POWER OFF
No Battery
BATTERY INSERT VBATT < VBLA
STANDBY
POWERACK PIN AND BIT = 0
NO WA / USB
WA AND USB REMOVED
ONOFF AND
WA INSERT
VBATT > VBLA
USB INSERT
AND VBATT > VBLA
(CHARGING IF NEEDED)
ACTIVE
POWERACK PIN OR BIT = 1
WA OR USB
VBATT < VBLA AND NO WA
POWERACK PIN AND BIT
FAILED TO GO HIGH DURING
POWERUP SEQUENCE
ONOFF
CHG
STANDBY
WA OR USB
Figure 64. Operating Mode State Diagram
8.4.1 State Machine Definitions
VBLA
Battery low alarm threshold
VBATT
WA
Battery voltage
Wall Adapter
USB
Universal Serial Bus Adapter
On off pin event
ONOFF
POWERACK Acknowledgment from the Host Processor
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Device Functional Modes (continued)
Vterm
4.2V (Typ.)
Active
VBLA
2.4-3.5V (factory
programmable)
Standby
Vuvlo
2.4V (Typ.)
Battery safety switch on/off threshold
2.1V
Vpor
0.9V
PowerOff
Figure 65. Voltage Threshold Levels
Table 8. Power State Table
POWER OFF
STANDBY
ACTIVE
On
CHARGER STANDBY
LDO1,2
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Buck1,2
Buck-Boost
Charger
On
On
On if Charger / USB
Present
On if Charger / USB
Present
ADC
Off
Low
Off
Off
On
Off
NRST
I2C interface
Low
High
Low
Off
On
On
Internal system oscillator
Battery monitor
Current consumption
Off
Off
On
On
On
On
On
Off
<1 µA
10 µA (typical)
See Specifications
See Specifications
8.4.1.1 Power-Off Mode
In power-off mode the main battery, the battery charger supply, and the USB supply are below their minimum on
levels. All internal circuits are disabled as the supply voltage is below the level to activate them. The LP3910 is in
power-off mode when the battery voltage is below the battery VUVLO (2.4 V, typical) except when a valid external
supply is detected.
8.4.1.2 Standby Mode
When the LP3910 is in standby mode, the chip is waiting for a valid power-on event to transition to active mode.
There are 3 valid wake-up signals. First is the ONOFF pin. Second is wall adapter insertion. Third is the USB
insertion. VBATT must be greater than the battery VUVLO in order to stay in standby mode; otherwise, the chip
transitions to power-off mode. Standby mode is skipped when advancing from power-off mode when a battery is
inserted that is above the battery low alarm threshold.
If the battery is below the battery low alarm threshold, power-off mode transitions to standby mode. However, hot
insertion of the battery with the adapter connected is NOT permitted. In standby mode, the current consumption
is reduced to IQ (10 µA, typical).
8.4.1.3 Active Mode
All LP3910 circuits are fully operational in active mode.
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8.4.2 Mode Sequencing
8.4.2.1 Power-On, Power-Off Sequencing
Each DC-DC converter (Buck1, Buck2, Buck-Boost, LDO1, LDO2) and the NRST pin of the LP3910 has its own
delay after which it is enabled following a power-on event or disabled following a power-off event. Following the
deglitching of the power-on event, the system bandgaps are enabled. Following this is a 5 ms delay that internal
circuitry requires to cleanly power up. The programmable delays are measured from this time point. Following the
deglitching of a power-down event (up to 5 ms if POWERACK pin is used), the power-down sequencer starts.
Each delay ranges from 0 ms to 63 ms in steps of 1 ms and is factory programmed to the desired values
submitted by the system designer. As shown in Figure 66, the power-on or power-off sequencing is designed
around a 6-bit up or down timer that is clocked at 1 kHz. A power-on or power-off event triggers the timer, which
counts up from 0 during a power-on sequence and counts down from 5'b11111 during a power-down cycle. The
timer output is connected to 5 comparators with factory-programmed timeout values that correspond to the on
and off delays for each DC-DC converter and the NRST pin. Once the timer has incremented beyond the
comparator timeout value during a power-on cycle, the output of the comparator enables the corresponding DC-
DC converter or raises the NRST pin to a logic high level. Subsequently, once the timer has decremented below
the comparator timeout value during a power-down cycle, the output of the comparator disables the
corresponding DC-DC converter or activates the NRST pin to a logic low level.
up
down
6 Bit Up /
Down
Counter
1 kHz
Clock
Divider
Oscillator
t1
t2
t3
t4
t5
LDO1, LDO2
Buck1
Comparator
Comparator
Comparator
Comparator
Comparator
Buck2
Buck - Boost
NRST
Figure 66. Power Sequencer Block Diagram
8.4.2.2 Power-On Timing
Each timeout T1 thru to T5 are factory programmed from 0 ms to 63 ms. The power-on defaults are shown in
Table 9.
Table 9. Power-On Timing Defaults
TIME (STANDARD
SYMBOL
DESCRIPTION
TIME (AP OPTION)
UNIT
OPTIONS)
T1
T2
T3
T4
T5
Delay for LDO1 and LDO2
Delay to Buck1
5
6
3
ms
ms
ms
ms
ms
15
20
25
60
Delay for Buck2
1
Delay for Buck-Boost
Delay for NRST
0
10
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8.4.2.3 Power-Off Timing
The timing delays during a power-off sequence are equal to 63 ms minus the timing delay during the power on
sequence (see Table 10).
Table 10. Power-Off Timing Defaults
TIME (STANDARD
SYMBOL
DESCRIPTION
TIME (AP option)
UNIT
OPTIONS)
T1
T2
T3
T4
T5
Delay for LDO1 and LDO2
Delay to Buck1
58
48
43
38
3
10
10
10
10
3
ms
ms
ms
ms
ms
Delay for Buck2
Delay for Buck-Boost
Delay for NRST
8.4.2.4 Transitioning From Standby to Active Mode (Power Up) Battery Power Present Only
When only battery power is present and the battery voltage VBATT > VBATTLOW, the LP3910 is waiting for one of
three valid wakeup signals. The first is the ONOFF pin. The second and third wakeups are the wall adapter and
USBPWR. The ONOFF pin is a factory-programmable wakeup source. It can be a rising edge, a falling edge, a
level high, or a level low event. Regardless of the mode, the signal requires a 32-ms deglitch time. A deglitched
version of the ONOFF pin is output on the open-drain output pin ONSTAT. ONOFF is usually connected to a
push button. Asserting the ONOFF pin starts the power-on sequencer. This enables the DC-DC converters,
including the Buck1 DC-DC converter that supplies power to the system processor. The system processor then
must set bit D4 (PACK bit) in the power-on event register through the I2C interface or apply a logic high to the
POWERACK pin to keep the device in the Active mode. These serve as power acknowledgment, confirming the
power-on request initiated by the ONOFF pin. If neither the PACK bit (D4) in the PON register or the
POWERACK pin is set within 128 ms (maximum) of the start of the power-up sequencer, the LP3910 is
automatically turned off, as the system has failed to acknowledge the power-on request. Connecting the battery
is considered a power-on event. However, hot insertion of the battery with the adapter connected is NOT
permitted.
8.4.2.5 Transitioning From Active Mode to Standby Mode
8.4.2.5.1 External Event Triggers the Transition From Active to Standby Mode
When the device is active, a subsequent re-assertion of the push button turns off the LP3910 indirectly by first
flagging the system processor though the ONSTAT pin. Upon detecting the ONSTAT transition, the system
processor must clear bit D4 (PACK) in the power on event register and apply a logic low to the POWERACK pin
to power down the LP3910, which then transitions to Standby Mode. Clearing the PACK register bit and
POWERACK pin while external supply sources are present (either USB or CHG_IN) does not power down the
LP3910, to keep the charger active. The system can as always disable all necessary DC-DC converters, except
Buck1, through the register control.
When external power is disconnected, LP3910 remains in its active state unless the battery voltage is below VBLA
(battery low alarm) or unless the PACK (either bit D4 in the PON register and the POWERACK pin) is cleared by
the system processor.
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Power Down Caused by External Event
t0 t5
t4 t3 t2
t1
32 ms
ONOFF
deglitch
32 ms
deglitch
ONSTAT
(To Microprocessor)
VLDO1, VLDO2
VBUCK1
T1
T2
VBUCK2
T3
T4
BUCK/BOOST
NRST
T5
POWERACK
(From Microprocessor)
(Bit D4 in PON register and
5 ms
POWERBACK pin)
5 ms
64 ms
VREFH
Figure 67. Power-Down Event Caused by External Event
8.4.2.5.2 Transition From Active to Standby Mode Due to Expiring POWERACK Deadline
With no external charger present when the system processor fails to acknowledge the power-on in time by
setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following
the start of the power-up sequencer, then the NRST is immediately de-asserted and after 2 ms all power sources
are disabled before transitioning to Standby Mode. This 2-ms delay allows the microprocessor to receive a clean
reset before the power is de-asserted. A new power-on event is then required to transition back to active mode.
With either external charger present when the system processor fails to acknowledge the power-on in time by
setting either the PACK bit (D4) in the PON register or the POWERACK pin before the 128-ms deadline following
the start of the power-up sequencer, the NRST is immediately de-asserted; after 2 ms all power sources are
disabled before transitioning to charger standby mode.
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Power Down Caused by Expiring PowerACK deadline
CHG_DET/USBPWR
or
External Events
ONOFF
ONSTAT
(To Microprocessor)
VLDO1, VLDO2
(If LDO2ENB is logic 1 during NRST Low,
otherwise LDO2 are pin or register enabled)
VBUCK1
VBUCK2
BUCK/BOOST
NRST
PowerACK
(From Microprocessor)
(Bit D4 in PON register and
POWERACK pin)
x
PowerACK deadline (expired)
Figure 68. Power Down Caused by Expiring PowerACK Deadline
8.4.2.5.3 Transition From Charger Standby Mode to Either Active or Standby Mode
While in charger standby mode, the battery is charged using the default values of IPROG, EOC, VTERM, battery
temperature range, and USB ISEL. In charger standby mode, all the regulators and the I2C are disabled. A new
power-on event is required to transition back to active mode. Removing the charger during charger standby
mode causes a transition back to standby mode.
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8.5 Programming
8.5.1 I2C-Compatible Serial Interface
8.5.1.1 I2C Signals
The LP3910 features an I2C-compatible serial interface, using two dedicated pins: I2C_SCL and I2C_SDA for I2C
clock and data, respectively. Both signals need a pullup resistor according to the I2C specification. The LP3910
interface is an I2C slave that is clocked by the incoming SCL clock.
Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400 kbit/s. See
I2C specification from NXP for further details.
8.5.1.2 I2C Data Validity
The data on I2C_SDA line must be stable during the HIGH period of the clock signal (I2C_SCL); that is, the state
of the data line can only be changed when CLK is LOW.
I2C_SCL
I2C_SDA
data
change
allowed
data
change
allowed
data
valid
data
change
allowed
data
valid
Figure 69. I2C Data Valid Diagram
8.5.1.3 I2C Start and Stop Conditions
START and STOP bits classify the beginning and the end of the I2C session. The START condition is defined the
as the I2C_SDA signal transitioning from HIGH to LOW while SCL line is HIGH. The STOP condition is defined
as the SDA transitioning from LOW to HIGH while I2C_SCL is HIGH. The I2C master always generates START
and STOP bits. The I2C bus is considered to be busy after a START condition and free after a STOP condition.
During data transmission, I2C master can generate repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
I2C_SDA
I2C_SCL
S
P
TART condition
STO condition
S
P
Figure 70. Start and Stop Conditions
8.5.1.4 Transferring Data
Every byte put on the I2C_SDA line must be eight bits long, with the most significant bit (MSB) being transferred
first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is
generated by the master. The transmitter releases the I2C_SDA line (HIGH) during the acknowledge clock pulse.
The receiver must pull down the I2C_SDA line during the 9th clock pulse, signifying acknowledgement. A receiver
which has been addressed must generate an acknowledgement (ACK) after each byte has been received.
8.5.1.5 Register Write Cycle
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a
READ. The second byte selects the register to which the data is written. The third byte contains data that is
written to the selected register.
LP3910 has a chip address of 60’h, which is set by a metal mask option.
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Programming (continued)
MSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR1
LSB
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1
1
0
0
0
0
0
2
I C SLAVE address (chip address)
Figure 71. I2C Chip Address
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb
w
ack msb Register Add lsb ack msb
DATA
lsb ack stop
SCL
SDA
1
3 4 5 6
2
7
8
9
1 2 3 ...
start
id = h‘60
w
ack
addr = h‘00
ack
address h‘AA data
ack stop
w = write (I2C_SDA = 0)
r = read (I2C_SDA = 1)
ack = acknowledge (I2C_SDA pulled down by either master or slave)
rs = repeated start
id = LP3910 chip address: 60’h
Figure 72. I2C Write Cycle
8.5.1.6 Register Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown
Figure 73.
ack from slave
ack from slave repeated start
ack from slave data from slave ack from master
start msb Chip Address lsb
w
ack msb Register Add lsb ack rs
msb Chip Address lsb
r
ack msb
DATA
lsb ack stop
SCL
SDA
start
id = h‘60
w
ack
register addr = h‘10
ack rs
id = h‘60
r
ack
data addr h‘6A
ack stop
Figure 73. I2C Read Cycle
8.5.1.7 Multi-Byte I2C Command Sequence
The I2C serial interface of the LP3910 device supports random register multi-byte command sequencing: during
a multi-byte write the Master sends the Start command followed by the device address, which is sent only once,
followed by the 8-bit register address, then 8 bits of data, The I2C slave must then accept the next random
register address followed by 8 bits of data and continue this process until the master sends a valid stop
condition.
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Programming (continued)
A typical multi-byte random register transfer is: Device Address, Register A Address, Ack, Register A Data,
Ack Register M Address, Ack, Register M Data, Ack Register X Address, Ack, Register X Data, Ack Register
Z Address, Ack, Register Z Data, Ack, Stop
NOTE
The PMIC is not required to detect the I2C device address for each transaction. A, M, X,
and Z are random numbers.
ack from slave
ack from slave
ack from slave
ack from slave
ack from slave
start msb Chip Address lsb
w
ack msb Register Add lsb ack msb
DATA
lsb ack msb Register Add lsb ack msb
DATA
lsb ack stop
Register 0x24
Register 0x2A
Figure 74. Example Multi-Byte Command Sequencing
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8.6 Register Maps
8.6.1 LDO1 Control Register
LDO1 can be configured through its own I2C control register. The output voltage is programmable in steps of 100
mV from 1.2 V to 3.3 V. LDO1 gets enabled during the power-on sequence. Disable/enable control is provided
through bit D5 in the LDO1 control register after selecting the appropriate D4–0 settings, which determine the
output voltage.
The output voltage can be altered while LDO1 is enabled. When LDO1 is disabled, it shunts the output to AGND
with a RSHUNT = 200 Ω (maximum).
8.6.2 BATTLOW Register (04)H Battery Low Alarm Register
D7–5
D4–0
R/W
Access
Data
Read Only 0
Reserved
Battery low threshold voltage (V)
Battery low IRQ threshold voltage (V)
5’h14–1F
5’h13
5’h12
5’h11
5’h10
5’h0F
5’h0E
5’h0D
5'h0C
5’h0B
5’h0A
5’h09
5’h08
5’h07
5’h06
5’h05
5’h04
5’h03
5’h02
5’h01
5’h00
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
Reset
Standard
Default
5’h0C
5’h1F
2.90
2.70
3.10
2.70
n/a
“AP” Default
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8.6.3 PON Register (00)H Power-On Event Register
D7–5
D4
D3
D2
D1
D0
Access
Data
Read Only 0
R/W
Read Only
Reserved
PACK
Battery Insert
PON by ONOFF
PON by CHG_IN PON by USB
Power
0: Disable Power, 0: default
go in standby, and
wait for power on
event.
0: default
0: default
0: default
1: Acknowledge
1: Battery Insert
1: ONOFF caused 1: Power On
1: Power On
Power On request caused by Battery Power On event
Insertion
caused by
CHG_IN power
detection
caused by USB
power detection
Reset
n/a
0
0
0
0
0
8.6.4 CHCTL Register (01)H Charger Control Register
D7–6
D5–2
D1
D0
Access
Data
R/W
Termination voltage
ICC: Full Rate Charge current
Charger enable
End of Charge
Select
00: 4.1V (Li Ion)
0000: 100 mA
0001: 200 mA
0010: 300 mA
0011: 400 mA
0100: 500 mA
0101: 600 mA
0110: 700 mA
0111: 800 mA
1000: 900 mA
1001: 1000 mA
0: disabled
1: enabled
0: 5%
1: 10%
01: 4.2V (Li Polymer )
10: 4.38V (Li Polymer)
11: reserved
Reset
01
Factory-Programmed Default
1
1
8.6.5 CHSPV Register (02)H Charger Supervisor Register
D7–6
D5
R/W
D4
D3
D2–0
Access
Data
Read only
R/W
R/W
Reserved
LED Current
LED ENABLE Battery
Charger status
0: Disabled
1:Enabled
temperature
range
0: 5 mA (Standard
default)
0: 0°C–50°C
Stat2
Stat1
Stat0
0: 1 mA (AP
default)
1: 10 mA
1: 0°C–45°C
0
0
0
0
0
1
0
1
0
Charger is off
(Standard default)
1: 2 mA (AP
default)
Prequalification
Constant current
charging
0
1
1
Constant voltage
charging
1
1
0
0
0
1
Error
Charge cycle
complete
1
1
1
1
0
1
Safety Timer
Expired
EOC / Top-off
Reset
n/a
1
1
0
2’b000
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8.6.6 ILIMIT Register (03)H Current Limit Register
D7–2
D1–0
Access
Read only 0
Data
Reserved
USB Current Limit
00: controlled by USBISEL pin
[low = 100 mA, high = 500 mA]
01: 100 mA
10: 500 mA
11: 800 mA
Reset
n/a
2’b00
8.6.7 ADCC Register (0a)H ADC Control Register
D7
D6
D5
D4
D3
D2
D1–0
Access
Data
R/W
R/W
Read Only
ADC Overflow Data Ready
R/W
R/W
VRANGE
IRANGE
Start
ADC Enable
0: Disabled
1: Enabled
ADC source
selection
Conversion
0: 2.6 V – 3.5
V
0: 0 mA – 605 mA 0: no overflow 0: no data
1: 0 mA – 1100 mA 1: overflow 1: data ready
0: default
00: battery voltage
1: 2.6 V – 4.4
V
1: start
conversion
01: battery charge
current
10: ADC1
11: ADC2
0
Reset
0
0
0
0
0
0
8.6.8 ADCD Register (0b)H ADC Output Data Register
Charge current 0 A to 1.1 A mirrored to 0 µA to 250 µA, ADC measures voltage drop across RSENSE 4.64 kΩ.
D7–0
Access
Data
Read Only 0
8’h00 = 2.6V
Battery voltage:
8’hFF = 3.5V
1 LSB = 0.9 / 256
= (3.5 mV) range 0
8’h00= 2.6V
8’h00 = 0
8’h00 = 0
8’hFF = 4.4 V
256 = (7.0 mV) range 1
1 LSB = 1.8 /
Battery charge current
8’hFF = 0.6463 V = 605 mA
range 0
8’hFF = 1.175V = 1100 mA
range 1
ADC1:
ADC2:
8’h00
8’h00 = VREFH = 1.225V
8’h00 = VREFH = 1.225V
8’hFF = 2*VREFH = 2.45 V
8’hFF = 2*VREFH = 2.45 V
(1 LSB = VREFH/256)
(1 LSB = VREFH/256)
Reset
8.6.9 IMR Register (0c)H Interrupt Mask Register
D7–0
r/w
Access
Data
1: Enable INTn (n=0…7) to pull IRQB low
0: Mask Interrupt source INTn
Reset
8’h00
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8.6.10 IRQ Register (0d)H Interrupt Request Register
D7–0
Access
Read only
Data
1: Interrupt IRQn (n=0…7) requested
0: No interrupt requested
Reset
8’h00
8.6.11 LDO1 Control Register (08)H
D7–6
D5
D4–0
Access
Data
Read Only 0
Reserved
R/W
Operation
0: disable
1: enable
LDO1 Output Voltage (V)
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
5’h12
5’h13
5’h14
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
5’h15 –5’h1F
Factory-Programmed Default
Reset
n/a
1
8.6.12 LDO2 Control Register
LDO2 can be configured through its own I2C control register. The output voltage is programmable in steps of 100
mV from 1.3 V to 3.3 V. LDO2 is by default disabled and can be enabled by setting bit D5 in the control register
after selecting the appropriate D4–0 settings, which determine the output voltage. LDO2 can also be enabled
through the external LDO2EN pin, which is the default enable control. With a logic 0 programmed to bit D5 in the
corresponding control register, enable/disable control is passed onto the LDO2EN pin; a logic 1 applied to this
pin enables LDO2 while a logic 0 disables the LDO2. Setting D5 to 1 in the LDO2 control register enables LDO2,
regardless of the state of the LDO2EN pin. If the system designer permanently connects the LDO2EN pin to
GND, then D5 is simply a enable/disable control bit. If the system design permanently connects the LDO2EN pin
to VDD, the LDO is enabled during the power-on sequence and is always on, regardless of the state of bit D5 in
the LDO2 control register. In that particular case, the LDO2 is sequenced with the same timing as LDO1 (see
Power-On, Power-Off Sequencing).
The output voltage can be altered while LDO2 is enabled. When LDO2 is disabled, it shunts the output to AGND
with a RSHUNT = 200 Ω (maximum).
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Table 11. LDO2 Control Register (09)H
D7–6
D5
D4–0
Access
Data
Read Only 0
R/W
Reserved
Operation
LDO1 Output Voltage (V)
0: enable/ disable determined by
state of LDO2EN pin
1: enable, override LDO2EN
state
5’h00
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
5’h12
5’h13
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
5’h14 –5’h1F
Reset
n/a
0
Factory-Programmed Default
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8.6.13 Buck1, Buck2 Control Registers and BUCK1EN Pin
Buck1 and Buck2 are configurable through I2C accessible registers. Bit fields D4–0 control the output voltage. Bit
D5 defines the Modulation mode of the buck, which by default automatically selects PWM or PFM mode
depending on the load as described above in the functional description. The modulation mode can be forced to
PWM mode regardless of the load by setting bit D5 to a logic 1 in the corresponding buck control register.
Bit D6 controls the enable/disable state of the buck, which is different for Buck1 and Buck2 as Buck1 has an
external enable pin: BUCK1EN.
For Buck1, by default or when D6 is programmed logic 0 in the Buck1 control register, enable/disable control is
passed onto the BUCK1EN pin. A logic 1 applied to this pin enables Buck1 while a logic 0 disables Buck1.
Setting D6 to 1 in the Buck1 control register enables BUCK1, regardless of the state of the BUCK1EN pin. If the
system designer permanently connects the BUCK1EN pin to GND, then D6 is simply a enable/disable control bit.
If the system design permanently connects the enable pin to VDD, then the Buck1 is enabled during the power-on
sequence and is always be on, regardless of the state of bit D6 in the Buck1 control register (see Power-On,
Power-Off Sequencing).
BUCK2 is by default enabled during the power-on sequence and can be enabled/disabled through bit D6 in the
Buck2 control register.
Table 12. Buck1 Control Register (05)H
D7
D6
D5
D4–0
Access
Data
Read Only 0
R/W
Reserved
Operation
Force PWM mode
0: Automatic Modulation
Mode
BUCK1 Output Voltage (V)
0: enable/disable
determined by state of
BUCK1EN pin
5’h00
Externally
controlled
1: Force PWM mode
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19–1F
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
1: enable, override
BUCK1EN state
Reset
n/a
0
0
Factory-Programmed Default
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Table 13. Buck2 Control Register (06)H
D7
D6
D5
D4–0
Access
Data
Read Only 0
R/W
Reserved
Operation
0: disabled
1: enabled
Force PWM mode
0: Automatic Modulation
Mode
BUCK2 Output Voltage (V)
5’h00
Externally
controlled
1: Force PWM mode
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h1x
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
Reset
n/a
1
0
Factory-Programmed Default
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8.6.14 Buck-Boost Control Register
The buck-boost is controlled through its dedicated control register. The buck-boost is enabled through the power-
on sequencing. The system processor is required to select the desired buck-boost output voltage through bits
D4–0 before enabling it by setting bit D6 in the control register. The buck-boost is also disabled when b’00000 is
programmed in the register field D4–0, regardless of the state of the bit D6. When the buck-boost is disabled, its
output is internally tied low through a 1-MΩ resistor. If D4–0 is set to b’00000 the 1 MΩ resistor is disconnected.
The default output voltage for the buck-boost is factory programmable.
Table 14. Buck–Boost Control Register (07)H
D7
D6
D5
D4–0
Access
Data
Read Only 0
R/W
Reserved
Force PWM
Operation
Buck–Boost Output Voltage (V)
0: Automatic
modulation mode
1: Force PWM
modulation
0: disable
1: enable
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A
5’h1B
5’h1C
5’h1D
5’h1E
5’h1F
disabled
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
Reset
n/a
0
1
Factory-Programmed Default
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP3910 is a programmable system power management unit optimized for HDD-based portable media
players. The device is intended to connect to an AC-DC wall adapter or USB power source in addition to a
lithium-Ion or lithium-polymer single-cell battery. The device can be configured over an I2C interface, or the
default configuration stored in EPROM can be used. Additional features such as current and voltage
measurements with the ADC or battery thermal monitoring can also be controlled via the I2C interface and
interrupt pins.
9.2 Typical Application
ADC1
12
ADC2
11
VIN4
VLDO2
VLDO1
10 µF
36
6
8
Audio Analog
Touchpad
1 µF
1 µF
VIN3
VIN2
10 µF
10 µF
1 µF
22
21
7
VIN1
VBBL1
35
33
32
31
34
39
VACDC_ADAPTER
2.2 µH
VDD1
46
42
41
47
10
45
VBBL2
VDD2
4.7 µF
4.7 µF
VBBOUT
VBBFB
3.3 V
HDD
VDD3
22 µF
CHG_DET
ISENSE
USBPWR
BBGND1
BBGND2
4.64 kΩ
5V_USB
D+
D-
VBUCK2
VFB2
3.1 V
4.7 µF
23
25
24
SDRAM/DDR
FLASH
IO
2.2 µH
USBSUSP
USBISEL
CHG
37
38
15
16
43
44
2
10 µF
USB Controller
LP3910
BCK2GND
VBUCK1
VFB1
1.2 V
20
18
19
28
2.2 µH
STAT
10 µF
4.7 µF
VBATT3
VBATT2
VBATT1
TS
BCK1GND
VDDIO
Battery
22 k 1.8 k 1.8 k 22 k 22 k
+
-
VDD
ONSTAT
I2C_SCL
I2C_SDA
NRST
1
30
27
29
14
13
9
GPIO
VDDIO
ONOFF
LDO2EN
BUCK1EN
VREFH
CPU
26
5
SCL
VDD
SDA
SoC
17
4
/RESET
/IRQ
IRQB
0.1 µF
IREF
POWERACK
121 kΩ
48
GPIO
GND
3
40
DGND
AGND
Figure 75. LP3910 Typical Application
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Typical Application (continued)
9.2.1 Design Requirements
For typical PMU applications, use the parameters listed in Table 15.
Table 15. Design Parameters
DESIGN PARAMETER
Minimum input voltage
Maximum input voltage
LDO1 output voltage
LDO2 output voltage
Buck1 output voltage
Buck2 output voltage
Buck-Boost output voltage
Charge current
EXAMPLE VALUE
2.7 V
5.5 V
2.5 V
3 V
1.6 V
1.8 V
3.3 V
100 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Inductors for Buck1, Buck2 and Buck-Boost
There are two main considerations when choosing an inductor; the inductor must not saturate and the inductor
current ripple is small enough to achieve the desired output voltage ripple. Care must be taken when reviewing
the different saturation current ratings that are specified by different manufacturers.
Saturation current ratings are typically specified at 25°C, so ratings at maximum ambient temperature of the
application must be requested from the manufacturer.
There are two methods to choose the inductor saturation current rating:
9.2.2.1.1 Method 1
The saturation current is greater than the sum of the maximum load current and the worst-case average-to-peak
inductor current. This can be written as Equation 4:
ISAT > IOUTMAX +IRIPPLE
≈
∆
«
’
÷
V
IN - VOUT
VOUT
V
1
≈
’
where IRIPPLE
=
*
*
∆
«
÷
◊
ƒ
2L
IN ◊
(4)
Considered when using the Buck-Boost in boost mode, use Equation 5:
ISAT > IRIPPLE +IAVE
≈
∆
«
’
÷
V
IN
1-
VOUT ◊
2Lƒ
where IRIPPLE = V
*
IN
VOUT
IAVE > IOUTMAX
*
V
IN
where
•
•
•
•
•
•
IRIPPLE: Average-to-peak inductor current
IOUTMAX: Maximum load current
VIN: Maximum input voltage in application
L: Minimum inductor value including worst case tolerances (30% drop can be considered for Method 1)
ƒ: Minimum switching frequency
VOUT: Output voltage
(5)
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9.2.2.1.2 Method 2
A more conservative and recommended approach is to choose an inductor that has saturation current rating
greater than the maximum current limit.
INDUCTOR
LSW1,2
LBB
VALUE
2.2 µH
2.2 µH
DESCRIPTION
Buck1,2 Inductor
Buck-Boost Inductor
NOTES
DCR 70 mΩ
DCR 70 mΩ
9.2.2.2 External Capacitors
The regulators on the LP3910 require external capacitors for regulator stability. These are specifically designed
for portable applications requiring minimum board space and smallest components. These capacitors must be
correctly selected for good performance.
9.2.2.2.1 LDO Capacitor Selection
9.2.2.2.1.1 Input Capacitor
An input capacitor is required for stability. It is recommended that a 1-µF capacitor be connected between the
LDO input pin and ground. (This capacitance value may be increased without limit.)
The input capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.
NOTE
Tantalum capacitors can suffer catastrophic failures due to surge currents when
connected to a low impedance source of power (such as a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it should be ensured by the
manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the equivalent series resistance (ESR) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains
approximately 1 µF over the entire operating temperature range.
9.2.2.2.1.2 Output Capacitor
The LDOs on the LP3910 are designed specifically to work with very small ceramic output capacitors. A 1-μF
ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the
application circuit.
Tantalum or film capacitors may also be used at the device output, COUT (or VOUT), but these are not as attractive
for reasons of size and cost.
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
9.2.2.2.1.3 Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LDOs.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
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In particular, the output capacitor selection must take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values also show some decrease over time due to aging. The
capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 76 shows a typical graph comparing different capacitor
case sizes.
0603, 10ë, ó5a
100%
80%
60%
40%
0402, 6.3ë, ó5w
20%
0
1.0
2.0
3.0
4.0
5.0
ꢀ/ ꢁL!{ (ë)
Figure 76. Typical Variation in Capacitance vs DC Bias
As shown in Figure 76, increasing the DC Bias condition can result in the capacitance value that falls below the
minimum value given in the recommended capacitor specifications table. Note that Figure 76 shows the
capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended
that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions,
as some capacitor sizes (for example, 0402) may not be suitable in the actual application.
Capacitance of a ceramic capacitor can vary with temperature. The capacitor type X7R, which operates over a
temperature range of −55°C to +125°C, only varies the capacitance to within ±15%. The capacitor type X5R has
a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors,
larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by
more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and
Y5V in applications where the ambient temperature changes significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47-μF to 4.7-μF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes
from +25°C down to −40°C, so some guard band must be allowed.
9.2.2.2.1.4 Noise Bypass Capacitors for VREFH Pin
Connecting respectively 100 nF and 1 nF grounded bypass capacitors to the VREFH pin significantly reduces
noise on the LDO outputs. VREFH is a high-impedance node connected to a bandgap reference used for the
LDOs. Any significant loading on this node causes a change on the regulated output voltages. For this reason,
DC leakage current through these pins must be kept as low as possible for best output voltage accuracy. The
types of capacitors best suited for the noise bypass capacitors are ceramic and film capacitors. High-quality
ceramic capacitors with either NPI or COG dielectric typically have very low leakage. Polypropylene and
polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low
leakage current. Residual solder flux is another potential source of leakage, which mandates thorough cleaning
of the assembled PCBs.
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9.2.2.2.2 Buck1, Buck2 and Buck-Boost Capacitor Selection
9.2.2.2.2.1 Input Capacitor Selection for Buck1, Buck2 and Buck-Boost
A ceramic input capacitor of 10 μF, 6.3 V is sufficient for the magnetic DC-DC converters. Place the input
capacitor as close as possible to the input of the device. A large value may be used for improved input voltage
filtering. The recommended capacitor types are X7R or X5R. Y5V-type capacitors must not be used. DC bias
characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The
input filter capacitor supplies current to the PFET switch of the DC-DC converter in the first half of each cycle
and reduces voltage ripple imposed on the input power source. Low ESR in a ceramic capacitor provides the
best noise filtering of the input voltage spikes due to fast current transients. A capacitor with sufficient ripple
current rating must be selected. The Input current ripple can be calculated as:
r2
12
VIN
VIN
IRMS = IOUTMAX
1 -
+
VOUT
VOUT
(VIN œ VOUT) * VOUT
L * f * IOUTMAX * VIN
)
where r =
(6)
The worse case is when VIN = 2 × VOUT
.
9.2.2.2.2.2 Output Capacitor Selection for Buck1, Buck2 and Buck-Boost
A 10-μF, 6.3-V ceramic capacitor must be used on the output of the Buck1 and Buck2 magnetic DC-DC
converters. The buck-boost needs a 22-μF capacitor. The output capacitor must be mounted as close as
possible to the output of the device. A large value may be used for improved input voltage filtering. The
recommended capacitor types are X7R or X5R. Y5V-type capacitors should not be used. DC bias characteristics
of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics
vary from manufacturer to manufacturer and DC bias curves should be requested from them and analyzed as
part of the capacitor selection process.
The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the
load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.
These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these
functions.
The output voltage ripple is caused by the charging and the discharging of the output capacitor and also due to
its ESR and can be calculated using Equation 7:
IRIPPLE
VPP-C
=
4
f C
* *
(7)
Voltage peak-to-peak ripple due to ESR can be expressed by Equation 8:
VPP-ESR = 2 × IRIPPLE × RESR
(8)
Because the VPP-C and VPP-ESR are out of phase, the RMS value can be used to get an approximate value of the
peak-to-peak ripple:
2
VPP-C2 + VPP-ESR
VPP-RMS
=
(9)
The output voltage ripple is dependent on the inductor current ripple and the ESR of the output capacitor (RESR).
The RESR is frequency dependent as well as temperature dependent. The RESR must be calculated with the
applicable switching frequency and ambient temperature.
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Table 16. Recommended Capacitors
CAPACITOR
CVDD
CCHG_DET
CUSB
MINIMUM VALUE (µF)
DESCRIPTION
Charger input capacitor
RECOMMENDED TYPE
Ceramic, 6.3 V, X5R
4.7
4.7
4.7
4.7
1
Charger input capacitor
USB power (VBUS) capacitor
Li-ion battery capacitor
LDO output capacitor
LDO output capacitor
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
CBATT
CLDO1
CLDO2
1
Bypass capacitor for internal voltage
reference
Ceramic, PolyPropylene and Polycarbonate
Film
CVREFH
0.1
CVIN2,3
CVBUCK1,2
CBB
10
10
22
1
Buck1, Buck2 input capacitor
BUCK1,2 output capacitor
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Ceramic, 6.3 V, X5R
Buck-Boost output capacitor
LDO bypass capacitor
CVIN1
CVIN4
10
Buck and Buck-Boost bypass capacitor
9.2.2.3 Schottky Diode on Charger Input CHG_IN
A Schottky diode is required in the external adapter path to block the reverse current from either the USB or the
battery source. The most critical parameter in the selection of the right Schottky diode is the leakage current,
which must be below 10 µA over the temperature range in order to prevent false detection of the presence of an
external adapter. In addition the Schottky diode must have a maximum voltage rating of 10 V or higher. The
current rating depends on the current limit of the adapter. The forward voltage must be limited to 500 mV at its
maximum current. The recommended Schottky diode is MBRA210ET3 from ON Semiconductor, which has a
reverse leakage current under 1 µA at room temperature and a forward voltage drop of 500 mV at the maximum
rated current (IF = 2 A).
9.2.2.4 Resistors
9.2.2.4.1 Battery Thermistor
The LP3910 battery thermistor bias provided by the TS pin is tailored to thermistors with the following
specification:
•
•
Negative temperature coefficient
100-kΩ resistance
A suitable solution is available from AVX thermistors:
AVXNB21250104 http://www.avxcorp.com/docs/Catalogs/nb21-23.pdf
9.2.2.4.2 I2C Pullup Resistors
I2C_SDA and I2C_SCL pins must have pullup resistors connected to the VDDIO pin. VDDIO must be connected
to a power supply that is less than or equal to VDD, such as BUCK2. The values of the pullup resistors (typical
approximately 1.8 kΩ) are determined by the capacitance of the bus. A resistor that is too large, combined with a
given bus capacitance, results in a rise time that would violate the maximum rise time specification. A resistor
that is too small results in a contention with the pulldown transistor on either slave(s) or master.
9.2.2.4.3 RIREF Resistor
The current through this resistor is used as a reference current that biases many analog circuits inside the
LP3910 and must have a resistance of 121 kΩ ±1%.
9.2.2.4.4 RISENSE Resistor
The current through this resistor is used as a reference current for the charge current. The accuracy of the ADC
is dependent on the tolerance of this resistor. RISENSE must have a resistance of 4.64 kΩ ±1% tolerance.
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9.2.3 Application Curves
VIN = 0 to 3.6 V
VOUT = 3.3 V
Load = 1 mA
Ch1 = Charge Current (mA)
Ch3 = CHG_DET (V)
Ch4 = USBPWR (V)
Figure 78. Enable Startup Time (LDO1)
Figure 77. Wall Adapter Removal With USBPWR Present
90
Vin = 3.6 V
Vin = 4 V
80
70
60
50
40
30
20
10
0
Vin = 5 V
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
VIN = 0 to 3.6 V
VOUT = 1.8 V
Load = 1 mA
VOUT = 1.8 V
L = 2.2 µH Forced PWM Mode
Figure 79. Enable Start-Up Time (LDO2)
Figure 80. Buck2 Efficiency vs Output Current
95
100
Vin = 3.6 V
90
Vin = 3.6 V
90
Vin = 4 V
Vin = 4 V
80
85
Vin = 5 V
70
80
75
70
65
60
55
50
Vin = 5 V
60
50
40
30
20
10
0
0.1
1.0
10
100
1000
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
VOUT = 1.8 V
L = 2.2 µH
PFM-to-PWM Mode
VOUT = 3.3 V
L = 2.2 µH Forced PWM Mode
Figure 82. Buck2 Efficiency vs Output Current
Figure 81. Buck2 Efficiency vs Output Current
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100
V
IN
= 2.7 V
90
80
70
60
50
V
= 3.6 V
IN
V
IN
= 4.2 V
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
VOUT = 3.3 V
L = 2.2 μH
PFM-to-PWM Mode
Figure 83. Buck2 Efficiency vs Output Current
10 Power Supply Recommendations
The LP3910 is designed to use a standard single-cell lithium-ion or lithium-polymer battery. Battery voltage
maximum operating voltage can be up to 4.5 V. The LP3910 can also use an AC-DC wall adapter as a charging
source up to 6 V or a USB source of at least 4.25 V. The USB charging source must supply charging currents of
100 mA, 500 mA, or 800 mA.
11 Layout
11.1 Layout Guidelines
For good performance of the circuit, it is essential to place the input and output capacitors very close to the
circuit, using wide routing for the traces to allow high currents. Sensitive components must be placed far from
those components with high pulsating current, and decoupling capacitors must be placed close to circuit VIN
pins. Digital and analog grounds must be routed separately and connected together in a star connection. It is
good practice to minimize high current and switching current paths.
11.1.1 LDO Regulators
Place the filter capacitors very close to the input and output pins. Use large trace width for high current-carrying
traces and the returns to ground.
11.1.2 Buck and Buck-Boost Regulators
Place the supply bypass, filter capacitor, and inductor close together, keeping the traces short. The traces
between these components carry relatively high switching current and act as antennas. Following these rules
reduces radiated noise. Arrange the components so that the switching current loops curl in the same direction.
Connect the buck ground and the ground of the capacitors together using generous component-side copper fill
as a pseudo-ground plane. Connect the grounds to the general board system ground plane at a single point.
Place the pseudo-ground plane below these components and then have it tied to system ground of the output
capacitor outside of the current loops. This prevents the switched current from injecting noise into the system
ground. These components, along with the inductor and output, must be placed on the same side of the circuit
board, and their connections must be made on the same layer.
Route the noise sensitive traces such as the voltage feedback path away from the inductor. This is done by
routing it on the bottom layer or by adding a grounded copper area between switching node and feedback path.
Noisy traces between the power components and keep any digital lines away from this section. Keep the
feedback node as small as possible so that the ground pin and ground traces shield the feedback node from the
SW or buck output.
Use wide traces between the power components and for power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses.
68
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Product Folder Links: LP3910
LP3910
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
11.2 Layout Example
VUSB
COPPER
POUR
VBATT
COPPER
POUR
VACDC
COPPER
POUR
TS
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VIN4
VBATT1
AGND
VBBL1
BBGND1
VBBL2
VBBOUT
3
VREFH
4
VLDO2
COPPER
POUR
LEDO2EN
5
VBBOUT
COPPER
POUR
VLDO2
VIN1
6
VBBFB
ONSTAT
7
I2C_SDA
VLDO1
8
VDDIO
COPPER
POUR
POWERACK
9
VDDIO
I2C_SCL
ISENSE
ADC2
10
11
12
ONOFF
VFB2
VLDO1
COPPER
POUR
ADC1
LEGEND
VIA to Signal Layer
VIA to VIN Layer
VIA to Power Layer
VIA to Ground Layer
VBCK1OUT
COPPER
POUR
VBCK2OUT
COPPER
POUR
Figure 84. LP3910 Layout Example
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11.3 Thermal Performance of the WQFN Package
The LP3910 is a monolithic device with integrated power FETs. For that reason, it is important to pay special
attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize
power dissipation of the WQFN package.
The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at
the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.
Compared to the traditional leaded packages where the die attach pad is embedded inside the molding
compound, the WQFN reduces one layer in the thermal path.
The thermal advantage of the WQFN package is fully realized only when the exposed die-attach pad is soldered
down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on
thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (RθJA) can be improved by a
factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land
and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer
diameter for thermal vias are 1.27 mm and 0.33 mm, respectively. Typical copper via barrel plating is 1 oz.,
although thicker copper may be used to further improve thermal performance. The LP3910 die attach pad is
connected to the substrate of the device and therefore, the thermal land and vias on the PCB board need to be
connected to ground (GND pin).
For more information on board layout techniques, refer to AN-1187 Leadless Leadframe Package (LLP)
(SNOA401). This application note also discusses package handling, solder stencil, and the assembly process.
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SNVS481M –NOVEMBER 2006–REVISED DECEMBER 2015
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For additional information, see the following:
AN1187 Leadless Leadframe Package (LLP) (SNOA401)
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2015, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP3910SQ-AK/NOPB
LP3910SQ-AN/NOPB
LP3910SQX-AA/NOPB
LP3910SQX-AN/NOPB
LP3910SQX-AP/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
NJV
NJV
NJV
NJV
NJV
48
48
48
48
48
250
250
RoHS & Green
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L3910-AK
SN
SN
SN
SN
L3910-AN
L3910-AA
L3910-AN
3910-AP
2500 RoHS & Green
2500 RoHS & Green
2500 RoHS & Green
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3910SQ-AK/NOPB
LP3910SQ-AN/NOPB
LP3910SQX-AA/NOPB
LP3910SQX-AN/NOPB
LP3910SQX-AP/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
NJV
NJV
NJV
NJV
NJV
48
48
48
48
48
250
250
178.0
178.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
2500
2500
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3910SQ-AK/NOPB
LP3910SQ-AN/NOPB
LP3910SQX-AA/NOPB
LP3910SQX-AN/NOPB
LP3910SQX-AP/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
NJV
NJV
NJV
NJV
NJV
48
48
48
48
48
250
250
208.0
208.0
367.0
367.0
367.0
191.0
191.0
367.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
2500
2500
2500
Pack Materials-Page 2
MECHANICAL DATA
NJV0048A
SQF48A (Rev A)
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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