LP3944ISQX/NOPB [TI]

RGB/白光/蓝光 8 LED 闪烁光驱动器 | RTW | 24 | -40 to 85;


型号：	LP3944ISQX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	RGB/白光/蓝光 8 LED 闪烁光驱动器 \| RTW \| 24 \| -40 to 85 驱动驱动器
文件：	总21页 (文件大小：762K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP3944

www.ti.com

SNVS264A –MAY 2004–REVISED APRIL 2013

LP3944 RGB/White/Blue 8-LED Fun Light Driver

Check for Samples: LP3944

FEATURES

DESCRIPTION

LP3944 is an integrated device capable of

independently driving 8 LEDs. This device also

contains an internal precision oscillator that provides

all the necessary timing required for driving each

LED. Two prescaler registers along with two PWM

registers provide a versatile duty cycle control. The

LP3944 contains the ability to dim LEDs in

SMBUS/I²C applications where it is required to cut

down on bus traffic.

•

Internal Power-on Reset

Active Low Reset

Internal Precision Oscillator

Variable Dim Rates (from 6.25 ms to 1.6s; 160

Hz–0.625 Hz)

APPLICATIONS

•

Customized Flashing LED Lights for Cellular

Phones

Traditionally, to dim LEDs using a serial shift register

such as 74LS594/5 would require a large amount of

traffic to be on the serial bus. LP3944 instead

requires only the setup of the frequency and duty

cycle for each output pin. From then on, only a single

command from the host is required to turn each

individual open drain output ON, OFF, or to cycle a

programmed frequency and duty cycle. Maximum

output sink current is 25 mA per pin and 200 mA per

package. Any ports not used for controlling the LEDs

can be used for general purpose input/output

expansion.

•

Portable Applications

Digital Cameras

Indicator Lamps

General Purpose I/O Expander

Toys

KEY SPECIFICATIONS

•

8 LED Driver (Multiple Programmable

States—On, Off, Input, and Dimming at a

Specified Rate)

•

8 Open Drain Outputs Capable of Driving up to

25 mA per LED

Typical Application Circuit

+5V

SMBUS

+5V

/I C

Blue LEDs

LED7

LED6

LED5

SDA

SCL

SDA

SCL

PORTx.D

RESET

LED4

LED3

LED2

LED1

LED0

Cell Phone Baseband

Controller/mController

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3944

SNVS264A –MAY 2004–REVISED APRIL 2013

www.ti.com

LP3944 Pin Out

Figure 1. (Top View)

Package Number RTW0024A

LP3944 PIN DESCRIPTION

Pin #

Name

Description

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

GND

Output of LED0 Driver

Output of LED1 Driver

Output of LED2 Driver

Output of LED3 Driver

Output of LED4 Driver

Output of LED5 Driver

Output of LED6 Driver

Output of LED7 Driver

Ground

No Connect

RST

SCL

SDA

V_DD

Active Low Reset Input

Clock Line for I²C Interface

Serial Data Line for I²C Interface

Power Supply

Address Input 0

Address Input 1

Address Input 2

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Architectural Block Diagram

A2 A1 A0

Input Register

SCL

SDA

I C

I C Bus

Bit0 of Input Reg 1

Filters

Control

LED Select Register

Bit1

Bit0

Select

LS0

LED0

Prescalar

PWM 0

Power-On Reset

RST

Oscillator

Prescalar

PWM 1

COPIES

Bit 7 of Input Register1

Bit 6 of Select Register LS1

Bit 7 of Select Register LS1

LED7

PWM0 Register

PWM1 Register

Programming Example (See end of datasheet

for complete example)

For explanation of LP3944 operation, please refer to Theory of Operation in Application Notes.

Figure 2. Block Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings^(1)(2)(3)

V_DD

−0.5V to 6V

A0, A1, A2, SCL, SDA, RST

(Collectively called digital pins)

Voltage on LED pins

Junction Temperature

Storage Temperature

Power Dissipation⁽⁴⁾

_SS−0.5V to 6V

150°C

−65°C to 150°C

1.76W

Human Body Model

Machine Model

2 kV

ESD⁽⁵⁾

150V

Charge Device Model

1 kV

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and

associated test conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) If Military/Aerospace specified devices are required, please contact Texas Instruments for availability and specifications.

(4) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formulaP =

(T_J—T_A)/θ_JA

where T_Jis the junction temperature, T_Ais the ambient temperature, and θ_JAis the junction-to-ambient thermal

resistance. The 1.76W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction

temperature, 150°C, for T_J, 85°C for T_A, and 37°C/W for θ_JA. More power can be dissipated safely at ambient temperature below 85°C.

Less power can be dissipated safely at ambient temperatures above 85°C. The Absolute Maximum power dissipation can be increased

by 27 mW for each degree below 85°C, and it must be de-rated by 27 mW for each degree above 85°C. For Operating Ratings

maximum power dissipation, T_J= 125°C and T_A= 85°C

(5) The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is 0Ω in series with 220 pF.

Operating Ratings⁽¹⁾⁽²⁾

V_DD

2.3V to 5.5V

−40°C to +125°C

−40°C to +85°C

37°C/W

Junction Temperature

Operating Ambient Temperature

Thermal Resistance (θ_JA

)

WQFN-24⁽³⁾

Power Dissipation

1.08W

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and

associated test conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pin.

(3) The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formulaP =

(T_J—T_A)/θ_JA

where T_Jis the junction temperature, T_Ais the ambient temperature, and θ_JAis the junction-to-ambient thermal

resistance. The 1.76W rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction

temperature, 150°C, for T_J, 85°C for T_A, and 37°C/W for θ_JA. More power can be dissipated safely at ambient temperature below 85°C.

Less power can be dissipated safely at ambient temperatures above 85°C. The Absolute Maximum power dissipation can be increased

by 27 mW for each degree below 85°C, and it must be de-rated by 27 mW for each degree above 85°C. For Operating Ratings

maximum power dissipation, T_J= 125°C and T_A= 85°C

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Electrical Characteristics

Unless otherwise noted, V_DD= 5.5V. Typical values and limits appearing in normal type apply for T_J= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, T_J= −40°C to +125°C.⁽¹⁾

Limit

Symbol

Parameter

Conditions

Typical

Units

Min

2.3

Max

POWER SUPPLY

V_DD

I_Q

Supply Voltage

Supply Current

5.5

No Load

Standby

350

2.0

550

µA

ΔI_Q

Additional Standby Current

V_DD= 5.5V, every LED pin at

4.3V

V_POR

t_w

Power-On Reset Voltage

Reset Pulse Width

1.8

1.96

LED

V_IL

LOW Level Input Voltage

HIGH Level Input Voltage

Low Level Output Current⁽²⁾

−0.5

2.0

0.8

5.5

V_IH

I_OL

V_OL= 0.4V, V_DD= 2.3V

V_OL= 0.4V, V_DD= 3.0V

V_OL= 0.4V, V_DD= 5.0V

V_OL= 0.7V, V_DD= 2.3V

V_OL= 0.7V, V_DD= 3.0V

V_OL= 0.7V, V_DD= 5.0V

V_DD= 3.6, V_IN= 0V or V_DD

See⁽³⁾

−1

I_LEAK

C_I/O

Input Leakage Current

µA

Input/Output Capacitance

2.6

2.3

6.5

ALL DIGITAL PINS (EXCEPT SCL AND SDA PINS)

V_IL

LOW Level Input Voltage

HIGH Level Input Voltage

Input Leakage Current

Input Capacitance

−0.5

2.0

−1

0.8

5.5

V_IH

I_LEAK

µA

C_IN

V_IN= 0V⁽³⁾

I²C INTERFACE (SCL AND SDA PINS)

V_IL

LOW Level Input Voltage

HIGH Level Input Voltage

LOW Level Output Voltage

LOW Level Output Current

Clock Frequency

-0.5

0.3V_DD

5.5

V_IH

0.7V_DD

V_OL

I_OL

0.2V_DD

V_OL= 0.4V

See⁽³⁾

kHz

F_CLK

t_HOLD

400

Hold Time Repeated START

Condition

0.6

µs

t_CLK-LP

t_CLK-HP

t_SU

CLK Low Period

CLK High Period

See⁽³⁾

1.3

0.6

µs

Set-Up Time Repeated START

Condition

0.6

µs

t_DATA-HOLDData Hold Time

t_DATA-SUData Set-Up Time

t_SU

See⁽³⁾

300

100

0.6

µs

Set-Up Time for STOP Condition See⁽³⁾

t_TRANS

Maximum Pulse Width of Spikes

that Must Be Suppressed by the

Input Filter of Both DATA & CLK

Signals

See⁽³⁾

(1) Limits are ensured. All electrical characteristics having room-temperature limits are tested during production with T_J= 25°C. All hot and

cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process

control.

(2) Each LED pin should not exceed 25 mA and the package should not exceed a total of 200 mA.

(3) Ensured by design.

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Typical Performance Characteristics

Frequency vs. Temp

(T_A= −40°C to +85°C),

V_DD= 2.3V to 3.0V

-5

-10

-40

-20

TEMPERATURE (°)

Figure 3.

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APPLICATION INFORMATION

Theory of Operation

The LP3944 takes incoming data and feed them into several registers that control the frequency and the duty

cycle of the LEDs. Two prescaler registers and two PWM registers provide two individual rates to dim or blink the

LEDs (for more information on these registers, refer to Table 1). The baseband controller/microprocessor can

program each LED to be in one of four states—on, off, DIM0 rate or DIM1 rate. One read-only registers provide

status on all 8 LEDs. The LP3944 can be used to drive RGB LEDs and/or single-color LEDs to create a colorful,

entertaining, and informative setting. This is particularly suitable for accessory functions in cellular phones and

toys. Any LED pins not used to drive LED can be used for General Purpose Parallel Input/Output (GPIO)

expansion.

The LP3944 is equipped with Power-On Reset that holds the chip in a reset state until V_DDreaches V_PORduring

power up. Once V_PORis achieved, the LP3944 comes out of reset and initializes itself to the default state.

To bring the LP3944 into reset, hold the RST pin LOW for a period of TW. This will put the chip to its default

state. The LP3944 can only be programmed after RST signal is HIGH again.

I²C Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

Figure 4. I²C Data Validity

I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits.

The I²C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I²C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 5. I²C START and STOP Conditions

Transferring Data

Every byte put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred first.

The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by

an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases

the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the

9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an

acknowledge after each byte has been received.

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After the START condition, a chip address is sent by the I²C master. This address is seven bits long followed by

an eighth bit which is a data direction bit (R/W). The LP3944 hardwires bits 7 to 4 and leaves bits 3 to 1

selectable, as shown in Figure 6. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The

LP3944 supports only a WRITE during chip addressing. The second byte selects the register to which the data

will be written. The third byte contains data to write to the selected register.

Figure 6. Chip Address Byte

ack from slave

msb Chip Address lsb

msb Register Add lsb

msb

DATA

lsb

start

ack

ack stop

SCL

SDA

address h'02

data

start

id = h'xx

w ack

addr = h'02

ack

ack stop

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

xx = 60 to 67

Figure 7. LP3944 Register Write

However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as

shown in Figure 8.

ack from slave

ack from slave repeated start

ack from slave data from slave

ack from master

msb Chip Address lsb

msb Register Add lsb

msb Chip Address lsb

msb DATA lsb

start

ack

ack rs

ack

ack stop

star

addr =

h'00

address h'00

data

ac sto

id = h'xx

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

xx = 60 to 67

Figure 8. LP3944 Register Read

Auto Increment

Auto increment is a special feature supported by the LP3944 to eliminate repeated chip and register addressing

when data are to be written to or read from registers in sequential order. The auto increment bit is inside the

disabled when it is programmed to “0”.

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Figure 9. Register Address Byte

In the READ mode, when auto increment is enabled, I²C master could receive any number of bytes from LP3944

without selecting chip address and register address again. Every time the I²C master reads a register, the

LP3944 will increment the register address and the next data register will be read. When I²C master reaches the

last register (09H register), the register address will roll over to 00H.

In the WRITE mode, when auto increment is enabled, the LP3944 will increment the register address every time

I²C master writes to register. When the last register (09H register) is reached, the register address will roll over to

02H, because the first two registers in LP3944 are read-only registers. It is possible to write to these two

registers, and the LP3944 will acknowledge, but the data will be ignored.

In the LP3944, registers 0x01, 0x08 and 0x09 are not functional. However, it is still necessary to read from 0x01

and to write to 0x08 and 0x09 in Auto Increment mode. They cannot be skipped.

If auto increment is disabled, and the I²C master does not change register address, it will continue to write data

into the same register.

Figure 10. Programming with Auto Increment Disabled (in WRITE Mode)

Figure 11. Programming with Auto Increment Enabled (in WRITE Mode)

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Table 1. LP3944 Register Table⁽¹⁾

Address (Hex)

0x00

Read/Write

LED0–7 Input Register

None

Input 1

PSC0

Read Only

R/W

0x01

0x02

Frequency Prescaler 0

PWM Register 0

Frequency Prescaler 1

PWM Register 1

LED0–3 Selector

LED4–7 Selector

None

0x03

PWM0

PSC1

R/W

0x04

R/W

0x05

PWM1

LS0

R/W

0x06

R/W

0x07

LS1

R/W

0x08

R/W

0x09

R/W

None

(1) Note: Registers 1, 8 and 9 are empty and non-functional registers. Register 1 is read-only, with all bits hard-wired to zero. Registers 8

and 9 can be written and read, but the content does ot have any effect on the operation of the LP3944.

Binary Fomat for Input Registers (Read Only)—Address 0x00 and 0x01

Table 2. Address 0x00⁽¹⁾

Bit #

Default value

LED7

LED6

LED5

LED4

LED3

LED2

LED1

LED0

(1) X = don’t care

Binary Format for Frequency Prescaler and PWM Registers — Address 0x02 to 0x05

Table 3. Address 0x02 (PSC0)⁽¹⁾

Bit #

Default value

(1) PSC0 register is used to program the period of DIM0.

DIM0 = (PSC0+1)/160

The maximum period is 1.6s when PSC0 = 255.

Table 4. Address 0x03 (PWM0)⁽¹⁾

Bit #

Default value

(1) PWM0 register determines the duty cycle of DIM0. The LED outputs are LOW (LED on) when the count is less than the value in PWM0

and HIGH (LED off) when it is greater. If PWM0 is programmed with 0x00, LED output is always HIGH (LED off).

The duty cycle of DIM0 is: PWM0/256

Default value is 50% duty cycle.

Table 5. Address 0x04 (PSC1)⁽¹⁾

Bit #

Default value

(1) PSC1 register is used to program the period of DIM1.

DIM1 = (PSC1 + 1)/160

The maximum period is 1.6s when PSC1 = 255.

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Table 6. Address 0x05 (PWM1)⁽¹⁾

Bit #

Default value

(1) PWM1 register determines the duty cycle of DIM1. The LED outputs are LOW (LED on) when the count is less than the value in PWM1

and HIGH (LED off) when it is greater. If PWM1 is programmed with 0x00, LED output is always HIGH (LED off).

The duty cycle of DIM1 is: PWM1/256

Default value is 50% duty cycle.

Binary Format for Selector Registers — Address 0x06 to 0x07Table 7

Table 7. Address 0x06 (LS0)

Bit #

Default value

LED3

LED2

LED1

LED0

Table 8. Address 0x07 (LS1)

Bit #

Default value

LED7

LED6

LED5

LED4

Table 9. LED States With Respect To Values in "B1" and "B0"

Function

Output Hi-Z

(LED off)

Output LOW

(LED on)

Output dims

(DIM0 rate)

Output dims

(DIM1 rate)

Programming Example:

Dim LEDs 0 to 7 at 1 Hz at 25% duty cycle

1. Set PSC0 to achieve DIM0 of 1s

2. Set PWM0 duty cycle to 25%

3. Set PSC1 to achieve DIM1 of 0.2s

4. Set LEDs 0 to 7 to point to DIM0

Step

Description

Set to (Hex)

Set DIM0 = 1s

1 = (PSC0 + 1)/160

PSC0 = 159

PSC0

0x09F

Set duty cycle to 25%

Duty Cycle = PWM0/256

PWM0 = 64

PWM0

PSC1

0x40

0x1F

Set DIM1 = 0.2s

0.2 = (PSC1 + 1)/160

PSC1 = 31

LEDs 0 to 7

Output = DIM0

LS0, LS1

LS0 = 0xAA

LS1 = 0xAA

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Reducing I_QWhen LEDs are Off

In many applications, the LEDs and the LP3944 share the same V_DD, as shown in Typical Application Circuit.

When the LEDs are off, the LED pins are at a lower potential than V_DD, causing extra supply current (ΔI_Q). To

minimize this current, consider keeping the LED pins at a voltage equal to or greater than V_DD

Figure 12. Methods to Reduce I_QWhen LEDs Are Off

2.7V to 5.5V

OUT

2.2 mF

LM2750-5.0

2.2 mF

LED 7

CAP+

FLY

1 mF

LP3944

CAP-

LED 0

Figure 13. Application Circuit

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REVISION HISTORY

Changes from Original (April 2013) to Revision A

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 12

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PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LP3944ISQ/NOPB

LP3944ISQX/NOPB

ACTIVE

WQFN

RTW

1000 RoHS & Green

4500 RoHS & Green

Level-3-260C-168 HR

-40 to 85

3944SQ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

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9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP3944ISQ/NOPB

LP3944ISQX/NOPB

WQFN

RTW

1000

4500

178.0

330.0

12.4

4.3

1.3

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP3944ISQ/NOPB

LP3944ISQX/NOPB

WQFN

RTW

1000

4500

208.0

356.0

191.0

356.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

PIN 1 INDEX AREA

4.1

3.9

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 2.5

(0.1) TYP

EXPOSED

THERMAL PAD

20X 0.5

2.5

2.6 0.1

0.3

24X

0.2

PIN 1 ID

(OPTIONAL)

0.1

C A B

0.05

0.5

0.3

24X

4222815/A 03/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.6)

SYMM

24X (0.6)

24X (0.25)

(1.05)

SYMM

(3.8)

20X (0.5)

(R0.05)

TYP

(

0.2) TYP

VIA

(1.05)

(3.8)

LAND PATTERN EXAMPLE

SCALE:15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222815/A 03/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RTW0024A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.15)

(0.675) TYP

(R0.05) TYP

24X (0.6)

24X (0.25)

(0.675)

TYP

SYMM

20X (0.5)

(3.8)

METAL

TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222815/A 03/2016

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LP3944ISQX/NOPB [TI]

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